2 * libqos driver framework
4 * Copyright (c) 2018 Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
19 #include "qemu/osdep.h"
21 #include "libqos/pci-pc.h"
22 #include "qemu/sockets.h"
24 #include "qemu/module.h"
25 #include "qemu/bitops.h"
26 #include "libqos/malloc.h"
27 #include "libqos/qgraph.h"
30 #define E1000E_IMS (0x00d0)
32 #define E1000E_STATUS (0x0008)
33 #define E1000E_STATUS_LU BIT(1)
34 #define E1000E_STATUS_ASDV1000 BIT(9)
36 #define E1000E_CTRL (0x0000)
37 #define E1000E_CTRL_RESET BIT(26)
39 #define E1000E_RCTL (0x0100)
40 #define E1000E_RCTL_EN BIT(1)
41 #define E1000E_RCTL_UPE BIT(3)
42 #define E1000E_RCTL_MPE BIT(4)
44 #define E1000E_RFCTL (0x5008)
45 #define E1000E_RFCTL_EXTEN BIT(15)
47 #define E1000E_TCTL (0x0400)
48 #define E1000E_TCTL_EN BIT(1)
50 #define E1000E_CTRL_EXT (0x0018)
51 #define E1000E_CTRL_EXT_DRV_LOAD BIT(28)
52 #define E1000E_CTRL_EXT_TXLSFLOW BIT(22)
54 #define E1000E_IVAR (0x00E4)
55 #define E1000E_IVAR_TEST_CFG ((E1000E_RX0_MSG_ID << 0) | BIT(3) | \
56 (E1000E_TX0_MSG_ID << 8) | BIT(11) | \
57 (E1000E_OTHER_MSG_ID << 16) | BIT(19) | \
60 #define E1000E_RING_LEN (0x1000)
62 #define E1000E_TDBAL (0x3800)
64 #define E1000E_TDBAH (0x3804)
65 #define E1000E_TDH (0x3810)
67 #define E1000E_RDBAL (0x2800)
68 #define E1000E_RDBAH (0x2804)
69 #define E1000E_RDH (0x2810)
71 #define E1000E_TXD_LEN (16)
72 #define E1000E_RXD_LEN (16)
74 static void e1000e_macreg_write(QE1000E
*d
, uint32_t reg
, uint32_t val
)
76 QE1000E_PCI
*d_pci
= container_of(d
, QE1000E_PCI
, e1000e
);
77 qpci_io_writel(&d_pci
->pci_dev
, d_pci
->mac_regs
, reg
, val
);
80 static uint32_t e1000e_macreg_read(QE1000E
*d
, uint32_t reg
)
82 QE1000E_PCI
*d_pci
= container_of(d
, QE1000E_PCI
, e1000e
);
83 return qpci_io_readl(&d_pci
->pci_dev
, d_pci
->mac_regs
, reg
);
86 void e1000e_tx_ring_push(QE1000E
*d
, void *descr
)
88 uint32_t tail
= e1000e_macreg_read(d
, E1000E_TDT
);
89 uint32_t len
= e1000e_macreg_read(d
, E1000E_TDLEN
) / E1000E_TXD_LEN
;
91 memwrite(d
->tx_ring
+ tail
* E1000E_TXD_LEN
, descr
, E1000E_TXD_LEN
);
92 e1000e_macreg_write(d
, E1000E_TDT
, (tail
+ 1) % len
);
94 /* Read WB data for the packet transmitted */
95 memread(d
->tx_ring
+ tail
* E1000E_TXD_LEN
, descr
, E1000E_TXD_LEN
);
98 void e1000e_rx_ring_push(QE1000E
*d
, void *descr
)
100 uint32_t tail
= e1000e_macreg_read(d
, E1000E_RDT
);
101 uint32_t len
= e1000e_macreg_read(d
, E1000E_RDLEN
) / E1000E_RXD_LEN
;
103 memwrite(d
->rx_ring
+ tail
* E1000E_RXD_LEN
, descr
, E1000E_RXD_LEN
);
104 e1000e_macreg_write(d
, E1000E_RDT
, (tail
+ 1) % len
);
106 /* Read WB data for the packet received */
107 memread(d
->rx_ring
+ tail
* E1000E_RXD_LEN
, descr
, E1000E_RXD_LEN
);
110 static void e1000e_foreach_callback(QPCIDevice
*dev
, int devfn
, void *data
)
112 QPCIDevice
*res
= data
;
113 memcpy(res
, dev
, sizeof(QPCIDevice
));
117 void e1000e_wait_isr(QE1000E
*d
, uint16_t msg_id
)
119 QE1000E_PCI
*d_pci
= container_of(d
, QE1000E_PCI
, e1000e
);
120 guint64 end_time
= g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND
;
123 if (qpci_msix_pending(&d_pci
->pci_dev
, msg_id
)) {
127 } while (g_get_monotonic_time() < end_time
);
129 g_error("Timeout expired");
132 static void e1000e_pci_destructor(QOSGraphObject
*obj
)
134 QE1000E_PCI
*epci
= (QE1000E_PCI
*) obj
;
135 qpci_iounmap(&epci
->pci_dev
, epci
->mac_regs
);
136 qpci_msix_disable(&epci
->pci_dev
);
139 static void e1000e_pci_start_hw(QOSGraphObject
*obj
)
141 QE1000E_PCI
*d
= (QE1000E_PCI
*) obj
;
144 /* Enable the device */
145 qpci_device_enable(&d
->pci_dev
);
147 /* Reset the device */
148 val
= e1000e_macreg_read(&d
->e1000e
, E1000E_CTRL
);
149 e1000e_macreg_write(&d
->e1000e
, E1000E_CTRL
, val
| E1000E_CTRL_RESET
);
151 /* Enable and configure MSI-X */
152 qpci_msix_enable(&d
->pci_dev
);
153 e1000e_macreg_write(&d
->e1000e
, E1000E_IVAR
, E1000E_IVAR_TEST_CFG
);
155 /* Check the device status - link and speed */
156 val
= e1000e_macreg_read(&d
->e1000e
, E1000E_STATUS
);
157 g_assert_cmphex(val
& (E1000E_STATUS_LU
| E1000E_STATUS_ASDV1000
),
158 ==, E1000E_STATUS_LU
| E1000E_STATUS_ASDV1000
);
160 /* Initialize TX/RX logic */
161 e1000e_macreg_write(&d
->e1000e
, E1000E_RCTL
, 0);
162 e1000e_macreg_write(&d
->e1000e
, E1000E_TCTL
, 0);
164 /* Notify the device that the driver is ready */
165 val
= e1000e_macreg_read(&d
->e1000e
, E1000E_CTRL_EXT
);
166 e1000e_macreg_write(&d
->e1000e
, E1000E_CTRL_EXT
,
167 val
| E1000E_CTRL_EXT_DRV_LOAD
| E1000E_CTRL_EXT_TXLSFLOW
);
169 e1000e_macreg_write(&d
->e1000e
, E1000E_TDBAL
,
170 (uint32_t) d
->e1000e
.tx_ring
);
171 e1000e_macreg_write(&d
->e1000e
, E1000E_TDBAH
,
172 (uint32_t) (d
->e1000e
.tx_ring
>> 32));
173 e1000e_macreg_write(&d
->e1000e
, E1000E_TDLEN
, E1000E_RING_LEN
);
174 e1000e_macreg_write(&d
->e1000e
, E1000E_TDT
, 0);
175 e1000e_macreg_write(&d
->e1000e
, E1000E_TDH
, 0);
177 /* Enable transmit */
178 e1000e_macreg_write(&d
->e1000e
, E1000E_TCTL
, E1000E_TCTL_EN
);
179 e1000e_macreg_write(&d
->e1000e
, E1000E_RDBAL
,
180 (uint32_t)d
->e1000e
.rx_ring
);
181 e1000e_macreg_write(&d
->e1000e
, E1000E_RDBAH
,
182 (uint32_t)(d
->e1000e
.rx_ring
>> 32));
183 e1000e_macreg_write(&d
->e1000e
, E1000E_RDLEN
, E1000E_RING_LEN
);
184 e1000e_macreg_write(&d
->e1000e
, E1000E_RDT
, 0);
185 e1000e_macreg_write(&d
->e1000e
, E1000E_RDH
, 0);
188 e1000e_macreg_write(&d
->e1000e
, E1000E_RFCTL
, E1000E_RFCTL_EXTEN
);
189 e1000e_macreg_write(&d
->e1000e
, E1000E_RCTL
, E1000E_RCTL_EN
|
193 /* Enable all interrupts */
194 e1000e_macreg_write(&d
->e1000e
, E1000E_IMS
, 0xFFFFFFFF);
198 static void *e1000e_pci_get_driver(void *obj
, const char *interface
)
200 QE1000E_PCI
*epci
= obj
;
201 if (!g_strcmp0(interface
, "e1000e-if")) {
202 return &epci
->e1000e
;
205 /* implicit contains */
206 if (!g_strcmp0(interface
, "pci-device")) {
207 return &epci
->pci_dev
;
210 fprintf(stderr
, "%s not present in e1000e\n", interface
);
211 g_assert_not_reached();
214 static void *e1000e_pci_create(void *pci_bus
, QGuestAllocator
*alloc
,
217 QE1000E_PCI
*d
= g_new0(QE1000E_PCI
, 1);
218 QPCIBus
*bus
= pci_bus
;
219 QPCIAddress
*address
= addr
;
221 qpci_device_foreach(bus
, address
->vendor_id
, address
->device_id
,
222 e1000e_foreach_callback
, &d
->pci_dev
);
224 /* Map BAR0 (mac registers) */
225 d
->mac_regs
= qpci_iomap(&d
->pci_dev
, 0, NULL
);
227 /* Allocate and setup TX ring */
228 d
->e1000e
.tx_ring
= guest_alloc(alloc
, E1000E_RING_LEN
);
229 g_assert(d
->e1000e
.tx_ring
!= 0);
231 /* Allocate and setup RX ring */
232 d
->e1000e
.rx_ring
= guest_alloc(alloc
, E1000E_RING_LEN
);
233 g_assert(d
->e1000e
.rx_ring
!= 0);
235 d
->obj
.get_driver
= e1000e_pci_get_driver
;
236 d
->obj
.start_hw
= e1000e_pci_start_hw
;
237 d
->obj
.destructor
= e1000e_pci_destructor
;
242 static void e1000e_register_nodes(void)
249 /* FIXME: every test using this node needs to setup a -netdev socket,id=hs0
250 * otherwise QEMU is not going to start */
251 QOSGraphEdgeOptions opts
= {
252 .extra_device_opts
= "netdev=hs0",
254 add_qpci_address(&opts
, &addr
);
256 qos_node_create_driver("e1000e", e1000e_pci_create
);
257 qos_node_consumes("e1000e", "pci-bus", &opts
);
260 libqos_init(e1000e_register_nodes
);