accel/tcg/user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "exec/exec-all.h"
  23 #include "tcg.h"
  24 #include "qemu/bitops.h"
  25 #include "exec/cpu_ldst.h"
  26 #include "translate-all.h"
  27 #include "exec/helper-proto.h"
  28 #include "qemu/atomic128.h"
  29
  30 #undef EAX
  31 #undef ECX
  32 #undef EDX
  33 #undef EBX
  34 #undef ESP
  35 #undef EBP
  36 #undef ESI
  37 #undef EDI
  38 #undef EIP
  39 #ifdef __linux__
  40 #include <sys/ucontext.h>
  41 #endif
  42
  43 __thread uintptr_t helper_retaddr;
  44
  45 //#define DEBUG_SIGNAL
  46
  47 /* exit the current TB from a signal handler. The host registers are
  48    restored in a state compatible with the CPU emulator
  49  */
  50 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
  51 {
  52     /* XXX: use siglongjmp ? */
  53     sigprocmask(SIG_SETMASK, old_set, NULL);
  54     cpu_loop_exit_noexc(cpu);
  55 }
  56
  57 /* 'pc' is the host PC at which the exception was raised. 'address' is
  58    the effective address of the memory exception. 'is_write' is 1 if a
  59    write caused the exception and otherwise 0'. 'old_set' is the
  60    signal set which should be restored */
  61 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
  62                                     int is_write, sigset_t *old_set)
  63 {
  64     CPUState *cpu = current_cpu;
  65     CPUClass *cc;
  66     unsigned long address = (unsigned long)info->si_addr;
  67     MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
  68
  69     switch (helper_retaddr) {
  70     default:
  71         /*
  72          * Fault during host memory operation within a helper function.
  73          * The helper's host return address, saved here, gives us a
  74          * pointer into the generated code that will unwind to the
  75          * correct guest pc.
  76          */
  77         pc = helper_retaddr;
  78         break;
  79
  80     case 0:
  81         /*
  82          * Fault during host memory operation within generated code.
  83          * (Or, a unrelated bug within qemu, but we can't tell from here).
  84          *
  85          * We take the host pc from the signal frame.  However, we cannot
  86          * use that value directly.  Within cpu_restore_state_from_tb, we
  87          * assume PC comes from GETPC(), as used by the helper functions,
  88          * so we adjust the address by -GETPC_ADJ to form an address that
  89          * is within the call insn, so that the address does not accidentially
  90          * match the beginning of the next guest insn.  However, when the
  91          * pc comes from the signal frame it points to the actual faulting
  92          * host memory insn and not the return from a call insn.
  93          *
  94          * Therefore, adjust to compensate for what will be done later
  95          * by cpu_restore_state_from_tb.
  96          */
  97         pc += GETPC_ADJ;
  98         break;
  99
 100     case 1:
 101         /*
 102          * Fault during host read for translation, or loosely, "execution".
 103          *
 104          * The guest pc is already pointing to the start of the TB for which
 105          * code is being generated.  If the guest translator manages the
 106          * page crossings correctly, this is exactly the correct address
 107          * (and if the translator doesn't handle page boundaries correctly
 108          * there's little we can do about that here).  Therefore, do not
 109          * trigger the unwinder.
 110          *
 111          * Like tb_gen_code, release the memory lock before cpu_loop_exit.
 112          */
 113         pc = 0;
 114         access_type = MMU_INST_FETCH;
 115         mmap_unlock();
 116         break;
 117     }
 118
 119     /* For synchronous signals we expect to be coming from the vCPU
 120      * thread (so current_cpu should be valid) and either from running
 121      * code or during translation which can fault as we cross pages.
 122      *
 123      * If neither is true then something has gone wrong and we should
 124      * abort rather than try and restart the vCPU execution.
 125      */
 126     if (!cpu || !cpu->running) {
 127         printf("qemu:%s received signal outside vCPU context @ pc=0x%"
 128                PRIxPTR "\n",  __func__, pc);
 129         abort();
 130     }
 131
 132 #if defined(DEBUG_SIGNAL)
 133     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 134            pc, address, is_write, *(unsigned long *)old_set);
 135 #endif
 136     /* XXX: locking issue */
 137     /* Note that it is important that we don't call page_unprotect() unless
 138      * this is really a "write to nonwriteable page" fault, because
 139      * page_unprotect() assumes that if it is called for an access to
 140      * a page that's writeable this means we had two threads racing and
 141      * another thread got there first and already made the page writeable;
 142      * so we will retry the access. If we were to call page_unprotect()
 143      * for some other kind of fault that should really be passed to the
 144      * guest, we'd end up in an infinite loop of retrying the faulting
 145      * access.
 146      */
 147     if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR &&
 148         h2g_valid(address)) {
 149         switch (page_unprotect(h2g(address), pc)) {
 150         case 0:
 151             /* Fault not caused by a page marked unwritable to protect
 152              * cached translations, must be the guest binary's problem.
 153              */
 154             break;
 155         case 1:
 156             /* Fault caused by protection of cached translation; TBs
 157              * invalidated, so resume execution.  Retain helper_retaddr
 158              * for a possible second fault.
 159              */
 160             return 1;
 161         case 2:
 162             /* Fault caused by protection of cached translation, and the
 163              * currently executing TB was modified and must be exited
 164              * immediately.  Clear helper_retaddr for next execution.
 165              */
 166             clear_helper_retaddr();
 167             cpu_exit_tb_from_sighandler(cpu, old_set);
 168             /* NORETURN */
 169
 170         default:
 171             g_assert_not_reached();
 172         }
 173     }
 174
 175     /* Convert forcefully to guest address space, invalid addresses
 176        are still valid segv ones */
 177     address = h2g_nocheck(address);
 178
 179     /*
 180      * There is no way the target can handle this other than raising
 181      * an exception.  Undo signal and retaddr state prior to longjmp.
 182      */
 183     sigprocmask(SIG_SETMASK, old_set, NULL);
 184     clear_helper_retaddr();
 185
 186     cc = CPU_GET_CLASS(cpu);
 187     cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
 188     g_assert_not_reached();
 189 }
 190
 191 #if defined(__i386__)
 192
 193 #if defined(__NetBSD__)
 194 #include <ucontext.h>
 195
 196 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 197 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 198 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 199 #define MASK_sig(context)    ((context)->uc_sigmask)
 200 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 201 #include <ucontext.h>
 202
 203 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 204 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 205 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 206 #define MASK_sig(context)    ((context)->uc_sigmask)
 207 #elif defined(__OpenBSD__)
 208 #define EIP_sig(context)     ((context)->sc_eip)
 209 #define TRAP_sig(context)    ((context)->sc_trapno)
 210 #define ERROR_sig(context)   ((context)->sc_err)
 211 #define MASK_sig(context)    ((context)->sc_mask)
 212 #else
 213 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 214 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 215 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 216 #define MASK_sig(context)    ((context)->uc_sigmask)
 217 #endif
 218
 219 int cpu_signal_handler(int host_signum, void *pinfo,
 220                        void *puc)
 221 {
 222     siginfo_t *info = pinfo;
 223 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 224     ucontext_t *uc = puc;
 225 #elif defined(__OpenBSD__)
 226     struct sigcontext *uc = puc;
 227 #else
 228     ucontext_t *uc = puc;
 229 #endif
 230     unsigned long pc;
 231     int trapno;
 232
 233 #ifndef REG_EIP
 234 /* for glibc 2.1 */
 235 #define REG_EIP    EIP
 236 #define REG_ERR    ERR
 237 #define REG_TRAPNO TRAPNO
 238 #endif
 239     pc = EIP_sig(uc);
 240     trapno = TRAP_sig(uc);
 241     return handle_cpu_signal(pc, info,
 242                              trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
 243                              &MASK_sig(uc));
 244 }
 245
 246 #elif defined(__x86_64__)
 247
 248 #ifdef __NetBSD__
 249 #define PC_sig(context)       _UC_MACHINE_PC(context)
 250 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 251 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 252 #define MASK_sig(context)     ((context)->uc_sigmask)
 253 #elif defined(__OpenBSD__)
 254 #define PC_sig(context)       ((context)->sc_rip)
 255 #define TRAP_sig(context)     ((context)->sc_trapno)
 256 #define ERROR_sig(context)    ((context)->sc_err)
 257 #define MASK_sig(context)     ((context)->sc_mask)
 258 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 259 #include <ucontext.h>
 260
 261 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 262 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 263 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 264 #define MASK_sig(context)     ((context)->uc_sigmask)
 265 #else
 266 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 267 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 268 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 269 #define MASK_sig(context)     ((context)->uc_sigmask)
 270 #endif
 271
 272 int cpu_signal_handler(int host_signum, void *pinfo,
 273                        void *puc)
 274 {
 275     siginfo_t *info = pinfo;
 276     unsigned long pc;
 277 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 278     ucontext_t *uc = puc;
 279 #elif defined(__OpenBSD__)
 280     struct sigcontext *uc = puc;
 281 #else
 282     ucontext_t *uc = puc;
 283 #endif
 284
 285     pc = PC_sig(uc);
 286     return handle_cpu_signal(pc, info,
 287                              TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
 288                              &MASK_sig(uc));
 289 }
 290
 291 #elif defined(_ARCH_PPC)
 292
 293 /***********************************************************************
 294  * signal context platform-specific definitions
 295  * From Wine
 296  */
 297 #ifdef linux
 298 /* All Registers access - only for local access */
 299 #define REG_sig(reg_name, context)              \
 300     ((context)->uc_mcontext.regs->reg_name)
 301 /* Gpr Registers access  */
 302 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 303 /* Program counter */
 304 #define IAR_sig(context)                       REG_sig(nip, context)
 305 /* Machine State Register (Supervisor) */
 306 #define MSR_sig(context)                       REG_sig(msr, context)
 307 /* Count register */
 308 #define CTR_sig(context)                       REG_sig(ctr, context)
 309 /* User's integer exception register */
 310 #define XER_sig(context)                       REG_sig(xer, context)
 311 /* Link register */
 312 #define LR_sig(context)                        REG_sig(link, context)
 313 /* Condition register */
 314 #define CR_sig(context)                        REG_sig(ccr, context)
 315
 316 /* Float Registers access  */
 317 #define FLOAT_sig(reg_num, context)                                     \
 318     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 319 #define FPSCR_sig(context) \
 320     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 321 /* Exception Registers access */
 322 #define DAR_sig(context)                       REG_sig(dar, context)
 323 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 324 #define TRAP_sig(context)                      REG_sig(trap, context)
 325 #endif /* linux */
 326
 327 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 328 #include <ucontext.h>
 329 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 330 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 331 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 332 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 333 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 334 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 335 /* Exception Registers access */
 336 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 337 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 338 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 339 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 340
 341 int cpu_signal_handler(int host_signum, void *pinfo,
 342                        void *puc)
 343 {
 344     siginfo_t *info = pinfo;
 345 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 346     ucontext_t *uc = puc;
 347 #else
 348     ucontext_t *uc = puc;
 349 #endif
 350     unsigned long pc;
 351     int is_write;
 352
 353     pc = IAR_sig(uc);
 354     is_write = 0;
 355 #if 0
 356     /* ppc 4xx case */
 357     if (DSISR_sig(uc) & 0x00800000) {
 358         is_write = 1;
 359     }
 360 #else
 361     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 362         is_write = 1;
 363     }
 364 #endif
 365     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 366 }
 367
 368 #elif defined(__alpha__)
 369
 370 int cpu_signal_handler(int host_signum, void *pinfo,
 371                            void *puc)
 372 {
 373     siginfo_t *info = pinfo;
 374     ucontext_t *uc = puc;
 375     uint32_t *pc = uc->uc_mcontext.sc_pc;
 376     uint32_t insn = *pc;
 377     int is_write = 0;
 378
 379     /* XXX: need kernel patch to get write flag faster */
 380     switch (insn >> 26) {
 381     case 0x0d: /* stw */
 382     case 0x0e: /* stb */
 383     case 0x0f: /* stq_u */
 384     case 0x24: /* stf */
 385     case 0x25: /* stg */
 386     case 0x26: /* sts */
 387     case 0x27: /* stt */
 388     case 0x2c: /* stl */
 389     case 0x2d: /* stq */
 390     case 0x2e: /* stl_c */
 391     case 0x2f: /* stq_c */
 392         is_write = 1;
 393     }
 394
 395     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 396 }
 397 #elif defined(__sparc__)
 398
 399 int cpu_signal_handler(int host_signum, void *pinfo,
 400                        void *puc)
 401 {
 402     siginfo_t *info = pinfo;
 403     int is_write;
 404     uint32_t insn;
 405 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 406     uint32_t *regs = (uint32_t *)(info + 1);
 407     void *sigmask = (regs + 20);
 408     /* XXX: is there a standard glibc define ? */
 409     unsigned long pc = regs[1];
 410 #else
 411 #ifdef __linux__
 412     struct sigcontext *sc = puc;
 413     unsigned long pc = sc->sigc_regs.tpc;
 414     void *sigmask = (void *)sc->sigc_mask;
 415 #elif defined(__OpenBSD__)
 416     struct sigcontext *uc = puc;
 417     unsigned long pc = uc->sc_pc;
 418     void *sigmask = (void *)(long)uc->sc_mask;
 419 #elif defined(__NetBSD__)
 420     ucontext_t *uc = puc;
 421     unsigned long pc = _UC_MACHINE_PC(uc);
 422     void *sigmask = (void *)&uc->uc_sigmask;
 423 #endif
 424 #endif
 425
 426     /* XXX: need kernel patch to get write flag faster */
 427     is_write = 0;
 428     insn = *(uint32_t *)pc;
 429     if ((insn >> 30) == 3) {
 430         switch ((insn >> 19) & 0x3f) {
 431         case 0x05: /* stb */
 432         case 0x15: /* stba */
 433         case 0x06: /* sth */
 434         case 0x16: /* stha */
 435         case 0x04: /* st */
 436         case 0x14: /* sta */
 437         case 0x07: /* std */
 438         case 0x17: /* stda */
 439         case 0x0e: /* stx */
 440         case 0x1e: /* stxa */
 441         case 0x24: /* stf */
 442         case 0x34: /* stfa */
 443         case 0x27: /* stdf */
 444         case 0x37: /* stdfa */
 445         case 0x26: /* stqf */
 446         case 0x36: /* stqfa */
 447         case 0x25: /* stfsr */
 448         case 0x3c: /* casa */
 449         case 0x3e: /* casxa */
 450             is_write = 1;
 451             break;
 452         }
 453     }
 454     return handle_cpu_signal(pc, info, is_write, sigmask);
 455 }
 456
 457 #elif defined(__arm__)
 458
 459 #if defined(__NetBSD__)
 460 #include <ucontext.h>
 461 #endif
 462
 463 int cpu_signal_handler(int host_signum, void *pinfo,
 464                        void *puc)
 465 {
 466     siginfo_t *info = pinfo;
 467 #if defined(__NetBSD__)
 468     ucontext_t *uc = puc;
 469 #else
 470     ucontext_t *uc = puc;
 471 #endif
 472     unsigned long pc;
 473     int is_write;
 474
 475 #if defined(__NetBSD__)
 476     pc = uc->uc_mcontext.__gregs[_REG_R15];
 477 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 478     pc = uc->uc_mcontext.gregs[R15];
 479 #else
 480     pc = uc->uc_mcontext.arm_pc;
 481 #endif
 482
 483     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 484      * later processor; on v5 we will always report this as a read).
 485      */
 486     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 487     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 488 }
 489
 490 #elif defined(__aarch64__)
 491
 492 #ifndef ESR_MAGIC
 493 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
 494 #define ESR_MAGIC 0x45535201
 495 struct esr_context {
 496     struct _aarch64_ctx head;
 497     uint64_t esr;
 498 };
 499 #endif
 500
 501 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
 502 {
 503     return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
 504 }
 505
 506 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
 507 {
 508     return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
 509 }
 510
 511 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 512 {
 513     siginfo_t *info = pinfo;
 514     ucontext_t *uc = puc;
 515     uintptr_t pc = uc->uc_mcontext.pc;
 516     bool is_write;
 517     struct _aarch64_ctx *hdr;
 518     struct esr_context const *esrctx = NULL;
 519
 520     /* Find the esr_context, which has the WnR bit in it */
 521     for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
 522         if (hdr->magic == ESR_MAGIC) {
 523             esrctx = (struct esr_context const *)hdr;
 524             break;
 525         }
 526     }
 527
 528     if (esrctx) {
 529         /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
 530         uint64_t esr = esrctx->esr;
 531         is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
 532     } else {
 533         /*
 534          * Fall back to parsing instructions; will only be needed
 535          * for really ancient (pre-3.16) kernels.
 536          */
 537         uint32_t insn = *(uint32_t *)pc;
 538
 539         is_write = ((insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */
 540                     || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */
 541                     || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */
 542                     || (insn & 0xbfc00000) == 0x0d800000   /* C3.3.4 */
 543                     || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */
 544                     || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */
 545                     || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */
 546                     /* Ignore bits 10, 11 & 21, controlling indexing.  */
 547                     || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */
 548                     || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */
 549                     /* Ignore bits 23 & 24, controlling indexing.  */
 550                     || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
 551     }
 552     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 553 }
 554
 555 #elif defined(__s390__)
 556
 557 int cpu_signal_handler(int host_signum, void *pinfo,
 558                        void *puc)
 559 {
 560     siginfo_t *info = pinfo;
 561     ucontext_t *uc = puc;
 562     unsigned long pc;
 563     uint16_t *pinsn;
 564     int is_write = 0;
 565
 566     pc = uc->uc_mcontext.psw.addr;
 567
 568     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 569        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 570        from the hardware which does in fact contain the is_write value.
 571        The rt signal handler, as far as I can tell, does not give this value
 572        at all.  Not that we could get to it from here even if it were.  */
 573     /* ??? This is not even close to complete, since it ignores all
 574        of the read-modify-write instructions.  */
 575     pinsn = (uint16_t *)pc;
 576     switch (pinsn[0] >> 8) {
 577     case 0x50: /* ST */
 578     case 0x42: /* STC */
 579     case 0x40: /* STH */
 580         is_write = 1;
 581         break;
 582     case 0xc4: /* RIL format insns */
 583         switch (pinsn[0] & 0xf) {
 584         case 0xf: /* STRL */
 585         case 0xb: /* STGRL */
 586         case 0x7: /* STHRL */
 587             is_write = 1;
 588         }
 589         break;
 590     case 0xe3: /* RXY format insns */
 591         switch (pinsn[2] & 0xff) {
 592         case 0x50: /* STY */
 593         case 0x24: /* STG */
 594         case 0x72: /* STCY */
 595         case 0x70: /* STHY */
 596         case 0x8e: /* STPQ */
 597         case 0x3f: /* STRVH */
 598         case 0x3e: /* STRV */
 599         case 0x2f: /* STRVG */
 600             is_write = 1;
 601         }
 602         break;
 603     }
 604     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 605 }
 606
 607 #elif defined(__mips__)
 608
 609 int cpu_signal_handler(int host_signum, void *pinfo,
 610                        void *puc)
 611 {
 612     siginfo_t *info = pinfo;
 613     ucontext_t *uc = puc;
 614     greg_t pc = uc->uc_mcontext.pc;
 615     int is_write;
 616
 617     /* XXX: compute is_write */
 618     is_write = 0;
 619     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 620 }
 621
 622 #elif defined(__riscv)
 623
 624 int cpu_signal_handler(int host_signum, void *pinfo,
 625                        void *puc)
 626 {
 627     siginfo_t *info = pinfo;
 628     ucontext_t *uc = puc;
 629     greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
 630     uint32_t insn = *(uint32_t *)pc;
 631     int is_write = 0;
 632
 633     /* Detect store by reading the instruction at the program
 634        counter. Note: we currently only generate 32-bit
 635        instructions so we thus only detect 32-bit stores */
 636     switch (((insn >> 0) & 0b11)) {
 637     case 3:
 638         switch (((insn >> 2) & 0b11111)) {
 639         case 8:
 640             switch (((insn >> 12) & 0b111)) {
 641             case 0: /* sb */
 642             case 1: /* sh */
 643             case 2: /* sw */
 644             case 3: /* sd */
 645             case 4: /* sq */
 646                 is_write = 1;
 647                 break;
 648             default:
 649                 break;
 650             }
 651             break;
 652         case 9:
 653             switch (((insn >> 12) & 0b111)) {
 654             case 2: /* fsw */
 655             case 3: /* fsd */
 656             case 4: /* fsq */
 657                 is_write = 1;
 658                 break;
 659             default:
 660                 break;
 661             }
 662             break;
 663         default:
 664             break;
 665         }
 666     }
 667
 668     /* Check for compressed instructions */
 669     switch (((insn >> 13) & 0b111)) {
 670     case 7:
 671         switch (insn & 0b11) {
 672         case 0: /*c.sd */
 673         case 2: /* c.sdsp */
 674             is_write = 1;
 675             break;
 676         default:
 677             break;
 678         }
 679         break;
 680     case 6:
 681         switch (insn & 0b11) {
 682         case 0: /* c.sw */
 683         case 3: /* c.swsp */
 684             is_write = 1;
 685             break;
 686         default:
 687             break;
 688         }
 689         break;
 690     default:
 691         break;
 692     }
 693
 694     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 695 }
 696
 697 #else
 698
 699 #error host CPU specific signal handler needed
 700
 701 #endif
 702
 703 /* The softmmu versions of these helpers are in cputlb.c.  */
 704
 705 /* Do not allow unaligned operations to proceed.  Return the host address.  */
 706 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
 707                                int size, uintptr_t retaddr)
 708 {
 709     /* Enforce qemu required alignment.  */
 710     if (unlikely(addr & (size - 1))) {
 711         cpu_loop_exit_atomic(env_cpu(env), retaddr);
 712     }
 713     void *ret = g2h(addr);
 714     set_helper_retaddr(retaddr);
 715     return ret;
 716 }
 717
 718 /* Macro to call the above, with local variables from the use context.  */
 719 #define ATOMIC_MMU_DECLS do {} while (0)
 720 #define ATOMIC_MMU_LOOKUP  atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
 721 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
 722
 723 #define ATOMIC_NAME(X)   HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
 724 #define EXTRA_ARGS
 725
 726 #define DATA_SIZE 1
 727 #include "atomic_template.h"
 728
 729 #define DATA_SIZE 2
 730 #include "atomic_template.h"
 731
 732 #define DATA_SIZE 4
 733 #include "atomic_template.h"
 734
 735 #ifdef CONFIG_ATOMIC64
 736 #define DATA_SIZE 8
 737 #include "atomic_template.h"
 738 #endif
 739
 740 /* The following is only callable from other helpers, and matches up
 741    with the softmmu version.  */
 742
 743 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128
 744
 745 #undef EXTRA_ARGS
 746 #undef ATOMIC_NAME
 747 #undef ATOMIC_MMU_LOOKUP
 748
 749 #define EXTRA_ARGS     , TCGMemOpIdx oi, uintptr_t retaddr
 750 #define ATOMIC_NAME(X) \
 751     HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
 752 #define ATOMIC_MMU_LOOKUP  atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
 753
 754 #define DATA_SIZE 16
 755 #include "atomic_template.h"
 756 #endif