include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef EXEC_ALL_H
  21 #define EXEC_ALL_H
  22
  23 #include "cpu.h"
  24 #include "exec/tb-context.h"
  25 #ifdef CONFIG_TCG
  26 #include "exec/cpu_ldst.h"
  27 #endif
  28 #include "sysemu/cpu-timers.h"
  29
  30 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  31 #define DEBUG_DISAS
  32
  33 /* Page tracking code uses ram addresses in system mode, and virtual
  34    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  35    type.  */
  36 #if defined(CONFIG_USER_ONLY)
  37 typedef abi_ulong tb_page_addr_t;
  38 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
  39 #else
  40 typedef ram_addr_t tb_page_addr_t;
  41 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
  42 #endif
  43
  44 #include "qemu/log.h"
  45
  46 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
  47 void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
  48                           target_ulong *data);
  49
  50 /**
  51  * cpu_restore_state:
  52  * @cpu: the vCPU state is to be restore to
  53  * @searched_pc: the host PC the fault occurred at
  54  * @will_exit: true if the TB executed will be interrupted after some
  55                cpu adjustments. Required for maintaining the correct
  56                icount valus
  57  * @return: true if state was restored, false otherwise
  58  *
  59  * Attempt to restore the state for a fault occurring in translated
  60  * code. If the searched_pc is not in translated code no state is
  61  * restored and the function returns false.
  62  */
  63 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
  64
  65 void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
  66 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  67 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  68 void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  69 void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
  70
  71 /**
  72  * cpu_loop_exit_requested:
  73  * @cpu: The CPU state to be tested
  74  *
  75  * Indicate if somebody asked for a return of the CPU to the main loop
  76  * (e.g., via cpu_exit() or cpu_interrupt()).
  77  *
  78  * This is helpful for architectures that support interruptible
  79  * instructions. After writing back all state to registers/memory, this
  80  * call can be used to check if it makes sense to return to the main loop
  81  * or to continue executing the interruptible instruction.
  82  */
  83 static inline bool cpu_loop_exit_requested(CPUState *cpu)
  84 {
  85     return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0;
  86 }
  87
  88 #if !defined(CONFIG_USER_ONLY)
  89 void cpu_reloading_memory_map(void);
  90 /**
  91  * cpu_address_space_init:
  92  * @cpu: CPU to add this address space to
  93  * @asidx: integer index of this address space
  94  * @prefix: prefix to be used as name of address space
  95  * @mr: the root memory region of address space
  96  *
  97  * Add the specified address space to the CPU's cpu_ases list.
  98  * The address space added with @asidx 0 is the one used for the
  99  * convenience pointer cpu->as.
 100  * The target-specific code which registers ASes is responsible
 101  * for defining what semantics address space 0, 1, 2, etc have.
 102  *
 103  * Before the first call to this function, the caller must set
 104  * cpu->num_ases to the total number of address spaces it needs
 105  * to support.
 106  *
 107  * Note that with KVM only one address space is supported.
 108  */
 109 void cpu_address_space_init(CPUState *cpu, int asidx,
 110                             const char *prefix, MemoryRegion *mr);
 111 #endif
 112
 113 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 114 /* cputlb.c */
 115 /**
 116  * tlb_init - initialize a CPU's TLB
 117  * @cpu: CPU whose TLB should be initialized
 118  */
 119 void tlb_init(CPUState *cpu);
 120 /**
 121  * tlb_destroy - destroy a CPU's TLB
 122  * @cpu: CPU whose TLB should be destroyed
 123  */
 124 void tlb_destroy(CPUState *cpu);
 125 /**
 126  * tlb_flush_page:
 127  * @cpu: CPU whose TLB should be flushed
 128  * @addr: virtual address of page to be flushed
 129  *
 130  * Flush one page from the TLB of the specified CPU, for all
 131  * MMU indexes.
 132  */
 133 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 134 /**
 135  * tlb_flush_page_all_cpus:
 136  * @cpu: src CPU of the flush
 137  * @addr: virtual address of page to be flushed
 138  *
 139  * Flush one page from the TLB of the specified CPU, for all
 140  * MMU indexes.
 141  */
 142 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr);
 143 /**
 144  * tlb_flush_page_all_cpus_synced:
 145  * @cpu: src CPU of the flush
 146  * @addr: virtual address of page to be flushed
 147  *
 148  * Flush one page from the TLB of the specified CPU, for all MMU
 149  * indexes like tlb_flush_page_all_cpus except the source vCPUs work
 150  * is scheduled as safe work meaning all flushes will be complete once
 151  * the source vCPUs safe work is complete. This will depend on when
 152  * the guests translation ends the TB.
 153  */
 154 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr);
 155 /**
 156  * tlb_flush:
 157  * @cpu: CPU whose TLB should be flushed
 158  *
 159  * Flush the entire TLB for the specified CPU. Most CPU architectures
 160  * allow the implementation to drop entries from the TLB at any time
 161  * so this is generally safe. If more selective flushing is required
 162  * use one of the other functions for efficiency.
 163  */
 164 void tlb_flush(CPUState *cpu);
 165 /**
 166  * tlb_flush_all_cpus:
 167  * @cpu: src CPU of the flush
 168  */
 169 void tlb_flush_all_cpus(CPUState *src_cpu);
 170 /**
 171  * tlb_flush_all_cpus_synced:
 172  * @cpu: src CPU of the flush
 173  *
 174  * Like tlb_flush_all_cpus except this except the source vCPUs work is
 175  * scheduled as safe work meaning all flushes will be complete once
 176  * the source vCPUs safe work is complete. This will depend on when
 177  * the guests translation ends the TB.
 178  */
 179 void tlb_flush_all_cpus_synced(CPUState *src_cpu);
 180 /**
 181  * tlb_flush_page_by_mmuidx:
 182  * @cpu: CPU whose TLB should be flushed
 183  * @addr: virtual address of page to be flushed
 184  * @idxmap: bitmap of MMU indexes to flush
 185  *
 186  * Flush one page from the TLB of the specified CPU, for the specified
 187  * MMU indexes.
 188  */
 189 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
 190                               uint16_t idxmap);
 191 /**
 192  * tlb_flush_page_by_mmuidx_all_cpus:
 193  * @cpu: Originating CPU of the flush
 194  * @addr: virtual address of page to be flushed
 195  * @idxmap: bitmap of MMU indexes to flush
 196  *
 197  * Flush one page from the TLB of all CPUs, for the specified
 198  * MMU indexes.
 199  */
 200 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 201                                        uint16_t idxmap);
 202 /**
 203  * tlb_flush_page_by_mmuidx_all_cpus_synced:
 204  * @cpu: Originating CPU of the flush
 205  * @addr: virtual address of page to be flushed
 206  * @idxmap: bitmap of MMU indexes to flush
 207  *
 208  * Flush one page from the TLB of all CPUs, for the specified MMU
 209  * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
 210  * vCPUs work is scheduled as safe work meaning all flushes will be
 211  * complete once  the source vCPUs safe work is complete. This will
 212  * depend on when the guests translation ends the TB.
 213  */
 214 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 215                                               uint16_t idxmap);
 216 /**
 217  * tlb_flush_by_mmuidx:
 218  * @cpu: CPU whose TLB should be flushed
 219  * @wait: If true ensure synchronisation by exiting the cpu_loop
 220  * @idxmap: bitmap of MMU indexes to flush
 221  *
 222  * Flush all entries from the TLB of the specified CPU, for the specified
 223  * MMU indexes.
 224  */
 225 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
 226 /**
 227  * tlb_flush_by_mmuidx_all_cpus:
 228  * @cpu: Originating CPU of the flush
 229  * @idxmap: bitmap of MMU indexes to flush
 230  *
 231  * Flush all entries from all TLBs of all CPUs, for the specified
 232  * MMU indexes.
 233  */
 234 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
 235 /**
 236  * tlb_flush_by_mmuidx_all_cpus_synced:
 237  * @cpu: Originating CPU of the flush
 238  * @idxmap: bitmap of MMU indexes to flush
 239  *
 240  * Flush all entries from all TLBs of all CPUs, for the specified
 241  * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
 242  * vCPUs work is scheduled as safe work meaning all flushes will be
 243  * complete once  the source vCPUs safe work is complete. This will
 244  * depend on when the guests translation ends the TB.
 245  */
 246 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
 247
 248 /**
 249  * tlb_flush_page_bits_by_mmuidx
 250  * @cpu: CPU whose TLB should be flushed
 251  * @addr: virtual address of page to be flushed
 252  * @idxmap: bitmap of mmu indexes to flush
 253  * @bits: number of significant bits in address
 254  *
 255  * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
 256  */
 257 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
 258                                    uint16_t idxmap, unsigned bits);
 259
 260 /* Similarly, with broadcast and syncing. */
 261 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
 262                                             uint16_t idxmap, unsigned bits);
 263 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
 264     (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits);
 265
 266 /**
 267  * tlb_set_page_with_attrs:
 268  * @cpu: CPU to add this TLB entry for
 269  * @vaddr: virtual address of page to add entry for
 270  * @paddr: physical address of the page
 271  * @attrs: memory transaction attributes
 272  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 273  * @mmu_idx: MMU index to insert TLB entry for
 274  * @size: size of the page in bytes
 275  *
 276  * Add an entry to this CPU's TLB (a mapping from virtual address
 277  * @vaddr to physical address @paddr) with the specified memory
 278  * transaction attributes. This is generally called by the target CPU
 279  * specific code after it has been called through the tlb_fill()
 280  * entry point and performed a successful page table walk to find
 281  * the physical address and attributes for the virtual address
 282  * which provoked the TLB miss.
 283  *
 284  * At most one entry for a given virtual address is permitted. Only a
 285  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 286  * used by tlb_flush_page.
 287  */
 288 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 289                              hwaddr paddr, MemTxAttrs attrs,
 290                              int prot, int mmu_idx, target_ulong size);
 291 /* tlb_set_page:
 292  *
 293  * This function is equivalent to calling tlb_set_page_with_attrs()
 294  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 295  * as a convenience for CPUs which don't use memory transaction attributes.
 296  */
 297 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 298                   hwaddr paddr, int prot,
 299                   int mmu_idx, target_ulong size);
 300 #else
 301 static inline void tlb_init(CPUState *cpu)
 302 {
 303 }
 304 static inline void tlb_destroy(CPUState *cpu)
 305 {
 306 }
 307 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 308 {
 309 }
 310 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
 311 {
 312 }
 313 static inline void tlb_flush_page_all_cpus_synced(CPUState *src,
 314                                                   target_ulong addr)
 315 {
 316 }
 317 static inline void tlb_flush(CPUState *cpu)
 318 {
 319 }
 320 static inline void tlb_flush_all_cpus(CPUState *src_cpu)
 321 {
 322 }
 323 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
 324 {
 325 }
 326 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 327                                             target_ulong addr, uint16_t idxmap)
 328 {
 329 }
 330
 331 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
 332 {
 333 }
 334 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
 335                                                      target_ulong addr,
 336                                                      uint16_t idxmap)
 337 {
 338 }
 339 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
 340                                                             target_ulong addr,
 341                                                             uint16_t idxmap)
 342 {
 343 }
 344 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
 345 {
 346 }
 347
 348 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
 349                                                        uint16_t idxmap)
 350 {
 351 }
 352 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
 353                                                  target_ulong addr,
 354                                                  uint16_t idxmap,
 355                                                  unsigned bits)
 356 {
 357 }
 358 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
 359                                                           target_ulong addr,
 360                                                           uint16_t idxmap,
 361                                                           unsigned bits)
 362 {
 363 }
 364 static inline void
 365 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
 366                                               uint16_t idxmap, unsigned bits)
 367 {
 368 }
 369 #endif
 370 /**
 371  * probe_access:
 372  * @env: CPUArchState
 373  * @addr: guest virtual address to look up
 374  * @size: size of the access
 375  * @access_type: read, write or execute permission
 376  * @mmu_idx: MMU index to use for lookup
 377  * @retaddr: return address for unwinding
 378  *
 379  * Look up the guest virtual address @addr.  Raise an exception if the
 380  * page does not satisfy @access_type.  Raise an exception if the
 381  * access (@addr, @size) hits a watchpoint.  For writes, mark a clean
 382  * page as dirty.
 383  *
 384  * Finally, return the host address for a page that is backed by RAM,
 385  * or NULL if the page requires I/O.
 386  */
 387 void *probe_access(CPUArchState *env, target_ulong addr, int size,
 388                    MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
 389
 390 static inline void *probe_write(CPUArchState *env, target_ulong addr, int size,
 391                                 int mmu_idx, uintptr_t retaddr)
 392 {
 393     return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
 394 }
 395
 396 static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
 397                                int mmu_idx, uintptr_t retaddr)
 398 {
 399     return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
 400 }
 401
 402 /**
 403  * probe_access_flags:
 404  * @env: CPUArchState
 405  * @addr: guest virtual address to look up
 406  * @access_type: read, write or execute permission
 407  * @mmu_idx: MMU index to use for lookup
 408  * @nonfault: suppress the fault
 409  * @phost: return value for host address
 410  * @retaddr: return address for unwinding
 411  *
 412  * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
 413  * the page, and storing the host address for RAM in @phost.
 414  *
 415  * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
 416  * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
 417  * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
 418  * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
 419  */
 420 int probe_access_flags(CPUArchState *env, target_ulong addr,
 421                        MMUAccessType access_type, int mmu_idx,
 422                        bool nonfault, void **phost, uintptr_t retaddr);
 423
 424 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 425
 426 /* Estimated block size for TB allocation.  */
 427 /* ??? The following is based on a 2015 survey of x86_64 host output.
 428    Better would seem to be some sort of dynamically sized TB array,
 429    adapting to the block sizes actually being produced.  */
 430 #if defined(CONFIG_SOFTMMU)
 431 #define CODE_GEN_AVG_BLOCK_SIZE 400
 432 #else
 433 #define CODE_GEN_AVG_BLOCK_SIZE 150
 434 #endif
 435
 436 /*
 437  * Translation Cache-related fields of a TB.
 438  * This struct exists just for convenience; we keep track of TB's in a binary
 439  * search tree, and the only fields needed to compare TB's in the tree are
 440  * @ptr and @size.
 441  * Note: the address of search data can be obtained by adding @size to @ptr.
 442  */
 443 struct tb_tc {
 444     const void *ptr;    /* pointer to the translated code */
 445     size_t size;
 446 };
 447
 448 struct TranslationBlock {
 449     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 450     target_ulong cs_base; /* CS base for this block */
 451     uint32_t flags; /* flags defining in which context the code was generated */
 452     uint16_t size;      /* size of target code for this block (1 <=
 453                            size <= TARGET_PAGE_SIZE) */
 454     uint16_t icount;
 455     uint32_t cflags;    /* compile flags */
 456 #define CF_COUNT_MASK  0x00007fff
 457 #define CF_LAST_IO     0x00008000 /* Last insn may be an IO access.  */
 458 #define CF_NOCACHE     0x00010000 /* To be freed after execution */
 459 #define CF_USE_ICOUNT  0x00020000
 460 #define CF_INVALID     0x00040000 /* TB is stale. Set with @jmp_lock held */
 461 #define CF_PARALLEL    0x00080000 /* Generate code for a parallel context */
 462 #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */
 463 #define CF_CLUSTER_SHIFT 24
 464 /* cflags' mask for hashing/comparison */
 465 #define CF_HASH_MASK   \
 466     (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL | CF_CLUSTER_MASK)
 467
 468     /* Per-vCPU dynamic tracing state used to generate this TB */
 469     uint32_t trace_vcpu_dstate;
 470
 471     struct tb_tc tc;
 472
 473     /* original tb when cflags has CF_NOCACHE */
 474     struct TranslationBlock *orig_tb;
 475     /* first and second physical page containing code. The lower bit
 476        of the pointer tells the index in page_next[].
 477        The list is protected by the TB's page('s) lock(s) */
 478     uintptr_t page_next[2];
 479     tb_page_addr_t page_addr[2];
 480
 481     /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */
 482     QemuSpin jmp_lock;
 483
 484     /* The following data are used to directly call another TB from
 485      * the code of this one. This can be done either by emitting direct or
 486      * indirect native jump instructions. These jumps are reset so that the TB
 487      * just continues its execution. The TB can be linked to another one by
 488      * setting one of the jump targets (or patching the jump instruction). Only
 489      * two of such jumps are supported.
 490      */
 491     uint16_t jmp_reset_offset[2]; /* offset of original jump target */
 492 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
 493     uintptr_t jmp_target_arg[2];  /* target address or offset */
 494
 495     /*
 496      * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps.
 497      * Each TB can have two outgoing jumps, and therefore can participate
 498      * in two lists. The list entries are kept in jmp_list_next[2]. The least
 499      * significant bit (LSB) of the pointers in these lists is used to encode
 500      * which of the two list entries is to be used in the pointed TB.
 501      *
 502      * List traversals are protected by jmp_lock. The destination TB of each
 503      * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock
 504      * can be acquired from any origin TB.
 505      *
 506      * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is
 507      * being invalidated, so that no further outgoing jumps from it can be set.
 508      *
 509      * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained
 510      * to a destination TB that has CF_INVALID set.
 511      */
 512     uintptr_t jmp_list_head;
 513     uintptr_t jmp_list_next[2];
 514     uintptr_t jmp_dest[2];
 515 };
 516
 517 extern bool parallel_cpus;
 518
 519 /* Hide the qatomic_read to make code a little easier on the eyes */
 520 static inline uint32_t tb_cflags(const TranslationBlock *tb)
 521 {
 522     return qatomic_read(&tb->cflags);
 523 }
 524
 525 /* current cflags for hashing/comparison */
 526 static inline uint32_t curr_cflags(void)
 527 {
 528     return (parallel_cpus ? CF_PARALLEL : 0)
 529          | (icount_enabled() ? CF_USE_ICOUNT : 0);
 530 }
 531
 532 /* TranslationBlock invalidate API */
 533 #if defined(CONFIG_USER_ONLY)
 534 void tb_invalidate_phys_addr(target_ulong addr);
 535 void tb_invalidate_phys_range(target_ulong start, target_ulong end);
 536 #else
 537 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 538 #endif
 539 void tb_flush(CPUState *cpu);
 540 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 541 TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
 542                                    target_ulong cs_base, uint32_t flags,
 543                                    uint32_t cf_mask);
 544 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
 545
 546 /* GETPC is the true target of the return instruction that we'll execute.  */
 547 #if defined(CONFIG_TCG_INTERPRETER)
 548 extern uintptr_t tci_tb_ptr;
 549 # define GETPC() tci_tb_ptr
 550 #else
 551 # define GETPC() \
 552     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 553 #endif
 554
 555 /* The true return address will often point to a host insn that is part of
 556    the next translated guest insn.  Adjust the address backward to point to
 557    the middle of the call insn.  Subtracting one would do the job except for
 558    several compressed mode architectures (arm, mips) which set the low bit
 559    to indicate the compressed mode; subtracting two works around that.  It
 560    is also the case that there are no host isas that contain a call insn
 561    smaller than 4 bytes, so we don't worry about special-casing this.  */
 562 #define GETPC_ADJ   2
 563
 564 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_DEBUG_TCG)
 565 void assert_no_pages_locked(void);
 566 #else
 567 static inline void assert_no_pages_locked(void)
 568 {
 569 }
 570 #endif
 571
 572 #if !defined(CONFIG_USER_ONLY)
 573
 574 /**
 575  * iotlb_to_section:
 576  * @cpu: CPU performing the access
 577  * @index: TCG CPU IOTLB entry
 578  *
 579  * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
 580  * it refers to. @index will have been initially created and returned
 581  * by memory_region_section_get_iotlb().
 582  */
 583 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
 584                                              hwaddr index, MemTxAttrs attrs);
 585 #endif
 586
 587 #if defined(CONFIG_USER_ONLY)
 588 void mmap_lock(void);
 589 void mmap_unlock(void);
 590 bool have_mmap_lock(void);
 591
 592 /**
 593  * get_page_addr_code() - user-mode version
 594  * @env: CPUArchState
 595  * @addr: guest virtual address of guest code
 596  *
 597  * Returns @addr.
 598  */
 599 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
 600                                                 target_ulong addr)
 601 {
 602     return addr;
 603 }
 604
 605 /**
 606  * get_page_addr_code_hostp() - user-mode version
 607  * @env: CPUArchState
 608  * @addr: guest virtual address of guest code
 609  *
 610  * Returns @addr.
 611  *
 612  * If @hostp is non-NULL, sets *@hostp to the host address where @addr's content
 613  * is kept.
 614  */
 615 static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env,
 616                                                       target_ulong addr,
 617                                                       void **hostp)
 618 {
 619     if (hostp) {
 620         *hostp = g2h(addr);
 621     }
 622     return addr;
 623 }
 624 #else
 625 static inline void mmap_lock(void) {}
 626 static inline void mmap_unlock(void) {}
 627
 628 /**
 629  * get_page_addr_code() - full-system version
 630  * @env: CPUArchState
 631  * @addr: guest virtual address of guest code
 632  *
 633  * If we cannot translate and execute from the entire RAM page, or if
 634  * the region is not backed by RAM, returns -1. Otherwise, returns the
 635  * ram_addr_t corresponding to the guest code at @addr.
 636  *
 637  * Note: this function can trigger an exception.
 638  */
 639 tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr);
 640
 641 /**
 642  * get_page_addr_code_hostp() - full-system version
 643  * @env: CPUArchState
 644  * @addr: guest virtual address of guest code
 645  *
 646  * See get_page_addr_code() (full-system version) for documentation on the
 647  * return value.
 648  *
 649  * Sets *@hostp (when @hostp is non-NULL) as follows.
 650  * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
 651  * to the host address where @addr's content is kept.
 652  *
 653  * Note: this function can trigger an exception.
 654  */
 655 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
 656                                         void **hostp);
 657
 658 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 659 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
 660
 661 MemoryRegionSection *
 662 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 663                                   hwaddr *xlat, hwaddr *plen,
 664                                   MemTxAttrs attrs, int *prot);
 665 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 666                                        MemoryRegionSection *section);
 667 #endif
 668
 669 #endif