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vl: fix max_cpus check
[qemu/ar7.git] / target-mips / msa_helper.c
blob6e07f6ede3b9898612680bb264cd9f3f0776be2a
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22
23 /* Data format min and max values */
24 #define DF_BITS(df) (1 << ((df) + 3))
25
26 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
27 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
28
29 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
30 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
31
32 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
33 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
34
35 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
36 #define SIGNED(x, df) \
37 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
38
39 /* Element-by-element access macros */
40 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
41
42 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
43 {
44 uint32_t i;
45
46 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
47 pwd->d[i] = pws->d[i];
48 }
49 }
50
51 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
52 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
53 uint32_t i8) \
54 { \
55 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
56 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
57 uint32_t i; \
58 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
59 DEST = OPERATION; \
60 } \
61 }
62
63 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
64 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
65 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
66 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
67
68 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
69 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
70 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
71 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
72
73 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
74 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
75 MSA_FN_IMM8(bmzi_b, pwd->b[i],
76 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
77
78 #define BIT_SELECT(dest, arg1, arg2, df) \
79 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
80 MSA_FN_IMM8(bseli_b, pwd->b[i],
81 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
82
83 #undef MSA_FN_IMM8
84
85 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
86
87 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
88 uint32_t ws, uint32_t imm)
89 {
90 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
91 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
92 wr_t wx, *pwx = &wx;
93 uint32_t i;
94
95 switch (df) {
96 case DF_BYTE:
97 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
98 pwx->b[i] = pws->b[SHF_POS(i, imm)];
99 }
100 break;
101 case DF_HALF:
102 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
103 pwx->h[i] = pws->h[SHF_POS(i, imm)];
104 }
105 break;
106 case DF_WORD:
107 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
108 pwx->w[i] = pws->w[SHF_POS(i, imm)];
109 }
110 break;
111 default:
112 assert(0);
113 }
114 msa_move_v(pwd, pwx);
115 }
116
117 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
118 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
119 uint32_t wt) \
120 { \
121 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
122 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
123 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
124 uint32_t i; \
125 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
126 DEST = OPERATION; \
127 } \
128 }
129
130 MSA_FN_VECTOR(and_v, pwd->d[i], pws->d[i] & pwt->d[i])
131 MSA_FN_VECTOR(or_v, pwd->d[i], pws->d[i] | pwt->d[i])
132 MSA_FN_VECTOR(nor_v, pwd->d[i], ~(pws->d[i] | pwt->d[i]))
133 MSA_FN_VECTOR(xor_v, pwd->d[i], pws->d[i] ^ pwt->d[i])
134 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
135 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
136 MSA_FN_VECTOR(bmz_v, pwd->d[i],
137 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
138 MSA_FN_VECTOR(bsel_v, pwd->d[i],
139 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
140 #undef BIT_MOVE_IF_NOT_ZERO
141 #undef BIT_MOVE_IF_ZERO
142 #undef BIT_SELECT
143 #undef MSA_FN_VECTOR
144
145 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
146 {
147 return arg1 + arg2;
148 }
149
150 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
151 {
152 return arg1 - arg2;
153 }
154
155 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
156 {
157 return arg1 == arg2 ? -1 : 0;
158 }
159
160 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
161 {
162 return arg1 <= arg2 ? -1 : 0;
163 }
164
165 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
166 {
167 uint64_t u_arg1 = UNSIGNED(arg1, df);
168 uint64_t u_arg2 = UNSIGNED(arg2, df);
169 return u_arg1 <= u_arg2 ? -1 : 0;
170 }
171
172 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
173 {
174 return arg1 < arg2 ? -1 : 0;
175 }
176
177 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
178 {
179 uint64_t u_arg1 = UNSIGNED(arg1, df);
180 uint64_t u_arg2 = UNSIGNED(arg2, df);
181 return u_arg1 < u_arg2 ? -1 : 0;
182 }
183
184 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
185 {
186 return arg1 > arg2 ? arg1 : arg2;
187 }
188
189 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
190 {
191 uint64_t u_arg1 = UNSIGNED(arg1, df);
192 uint64_t u_arg2 = UNSIGNED(arg2, df);
193 return u_arg1 > u_arg2 ? arg1 : arg2;
194 }
195
196 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
197 {
198 return arg1 < arg2 ? arg1 : arg2;
199 }
200
201 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
202 {
203 uint64_t u_arg1 = UNSIGNED(arg1, df);
204 uint64_t u_arg2 = UNSIGNED(arg2, df);
205 return u_arg1 < u_arg2 ? arg1 : arg2;
206 }
207
208 #define MSA_BINOP_IMM_DF(helper, func) \
209 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
210 uint32_t wd, uint32_t ws, int32_t u5) \
211 { \
212 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
213 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
214 uint32_t i; \
215 \
216 switch (df) { \
217 case DF_BYTE: \
218 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
219 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
220 } \
221 break; \
222 case DF_HALF: \
223 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
224 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
225 } \
226 break; \
227 case DF_WORD: \
228 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
229 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
230 } \
231 break; \
232 case DF_DOUBLE: \
233 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
234 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
235 } \
236 break; \
237 default: \
238 assert(0); \
239 } \
240 }
241
242 MSA_BINOP_IMM_DF(addvi, addv)
243 MSA_BINOP_IMM_DF(subvi, subv)
244 MSA_BINOP_IMM_DF(ceqi, ceq)
245 MSA_BINOP_IMM_DF(clei_s, cle_s)
246 MSA_BINOP_IMM_DF(clei_u, cle_u)
247 MSA_BINOP_IMM_DF(clti_s, clt_s)
248 MSA_BINOP_IMM_DF(clti_u, clt_u)
249 MSA_BINOP_IMM_DF(maxi_s, max_s)
250 MSA_BINOP_IMM_DF(maxi_u, max_u)
251 MSA_BINOP_IMM_DF(mini_s, min_s)
252 MSA_BINOP_IMM_DF(mini_u, min_u)
253 #undef MSA_BINOP_IMM_DF
254
255 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
256 int32_t s10)
257 {
258 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
259 uint32_t i;
260
261 switch (df) {
262 case DF_BYTE:
263 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
264 pwd->b[i] = (int8_t)s10;
265 }
266 break;
267 case DF_HALF:
268 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
269 pwd->h[i] = (int16_t)s10;
270 }
271 break;
272 case DF_WORD:
273 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
274 pwd->w[i] = (int32_t)s10;
275 }
276 break;
277 case DF_DOUBLE:
278 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
279 pwd->d[i] = (int64_t)s10;
280 }
281 break;
282 default:
283 assert(0);
284 }
285 }
286
287 /* Data format bit position and unsigned values */
288 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
289
290 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
291 {
292 int32_t b_arg2 = BIT_POSITION(arg2, df);
293 return arg1 << b_arg2;
294 }
295
296 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
297 {
298 int32_t b_arg2 = BIT_POSITION(arg2, df);
299 return arg1 >> b_arg2;
300 }
301
302 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
303 {
304 uint64_t u_arg1 = UNSIGNED(arg1, df);
305 int32_t b_arg2 = BIT_POSITION(arg2, df);
306 return u_arg1 >> b_arg2;
307 }
308
309 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
310 {
311 int32_t b_arg2 = BIT_POSITION(arg2, df);
312 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
313 }
314
315 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
316 int64_t arg2)
317 {
318 int32_t b_arg2 = BIT_POSITION(arg2, df);
319 return UNSIGNED(arg1 | (1LL << b_arg2), df);
320 }
321
322 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
323 {
324 int32_t b_arg2 = BIT_POSITION(arg2, df);
325 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
326 }
327
328 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
329 int64_t arg2)
330 {
331 uint64_t u_arg1 = UNSIGNED(arg1, df);
332 uint64_t u_dest = UNSIGNED(dest, df);
333 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
334 int32_t sh_a = DF_BITS(df) - sh_d;
335 if (sh_d == DF_BITS(df)) {
336 return u_arg1;
337 } else {
338 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
339 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
340 }
341 }
342
343 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
344 int64_t arg2)
345 {
346 uint64_t u_arg1 = UNSIGNED(arg1, df);
347 uint64_t u_dest = UNSIGNED(dest, df);
348 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
349 int32_t sh_a = DF_BITS(df) - sh_d;
350 if (sh_d == DF_BITS(df)) {
351 return u_arg1;
352 } else {
353 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
354 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
355 }
356 }
357
358 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
359 {
360 return arg < M_MIN_INT(m+1) ? M_MIN_INT(m+1) :
361 arg > M_MAX_INT(m+1) ? M_MAX_INT(m+1) :
362 arg;
363 }
364
365 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
366 {
367 uint64_t u_arg = UNSIGNED(arg, df);
368 return u_arg < M_MAX_UINT(m+1) ? u_arg :
369 M_MAX_UINT(m+1);
370 }
371
372 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
373 {
374 int32_t b_arg2 = BIT_POSITION(arg2, df);
375 if (b_arg2 == 0) {
376 return arg1;
377 } else {
378 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
379 return (arg1 >> b_arg2) + r_bit;
380 }
381 }
382
383 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
384 {
385 uint64_t u_arg1 = UNSIGNED(arg1, df);
386 int32_t b_arg2 = BIT_POSITION(arg2, df);
387 if (b_arg2 == 0) {
388 return u_arg1;
389 } else {
390 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
391 return (u_arg1 >> b_arg2) + r_bit;
392 }
393 }
394
395 #define MSA_BINOP_IMMU_DF(helper, func) \
396 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
397 uint32_t ws, uint32_t u5) \
398 { \
399 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
400 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
401 uint32_t i; \
402 \
403 switch (df) { \
404 case DF_BYTE: \
405 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
406 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
407 } \
408 break; \
409 case DF_HALF: \
410 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
411 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
412 } \
413 break; \
414 case DF_WORD: \
415 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
416 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
417 } \
418 break; \
419 case DF_DOUBLE: \
420 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
421 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
422 } \
423 break; \
424 default: \
425 assert(0); \
426 } \
427 }
428
429 MSA_BINOP_IMMU_DF(slli, sll)
430 MSA_BINOP_IMMU_DF(srai, sra)
431 MSA_BINOP_IMMU_DF(srli, srl)
432 MSA_BINOP_IMMU_DF(bclri, bclr)
433 MSA_BINOP_IMMU_DF(bseti, bset)
434 MSA_BINOP_IMMU_DF(bnegi, bneg)
435 MSA_BINOP_IMMU_DF(sat_s, sat_s)
436 MSA_BINOP_IMMU_DF(sat_u, sat_u)
437 MSA_BINOP_IMMU_DF(srari, srar)
438 MSA_BINOP_IMMU_DF(srlri, srlr)
439 #undef MSA_BINOP_IMMU_DF
440
441 #define MSA_TEROP_IMMU_DF(helper, func) \
442 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
443 uint32_t wd, uint32_t ws, uint32_t u5) \
444 { \
445 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
446 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
447 uint32_t i; \
448 \
449 switch (df) { \
450 case DF_BYTE: \
451 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
452 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
453 u5); \
454 } \
455 break; \
456 case DF_HALF: \
457 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
458 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
459 u5); \
460 } \
461 break; \
462 case DF_WORD: \
463 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
464 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
465 u5); \
466 } \
467 break; \
468 case DF_DOUBLE: \
469 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
470 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
471 u5); \
472 } \
473 break; \
474 default: \
475 assert(0); \
476 } \
477 }
478
479 MSA_TEROP_IMMU_DF(binsli, binsl)
480 MSA_TEROP_IMMU_DF(binsri, binsr)
481 #undef MSA_TEROP_IMMU_DF
482
483 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
484 {
485 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
486 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
487 return abs_arg1 > abs_arg2 ? arg1 : arg2;
488 }
489
490 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
491 {
492 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
493 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
494 return abs_arg1 < abs_arg2 ? arg1 : arg2;
495 }
496
497 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
498 {
499 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
500 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
501 return abs_arg1 + abs_arg2;
502 }
503
504 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
505 {
506 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
507 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
508 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
509 if (abs_arg1 > max_int || abs_arg2 > max_int) {
510 return (int64_t)max_int;
511 } else {
512 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
513 }
514 }
515
516 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
517 {
518 int64_t max_int = DF_MAX_INT(df);
519 int64_t min_int = DF_MIN_INT(df);
520 if (arg1 < 0) {
521 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
522 } else {
523 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
524 }
525 }
526
527 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
528 {
529 uint64_t max_uint = DF_MAX_UINT(df);
530 uint64_t u_arg1 = UNSIGNED(arg1, df);
531 uint64_t u_arg2 = UNSIGNED(arg2, df);
532 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
533 }
534
535 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
536 {
537 /* signed shift */
538 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
539 }
540
541 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
542 {
543 uint64_t u_arg1 = UNSIGNED(arg1, df);
544 uint64_t u_arg2 = UNSIGNED(arg2, df);
545 /* unsigned shift */
546 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
547 }
548
549 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
550 {
551 /* signed shift */
552 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
553 }
554
555 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
556 {
557 uint64_t u_arg1 = UNSIGNED(arg1, df);
558 uint64_t u_arg2 = UNSIGNED(arg2, df);
559 /* unsigned shift */
560 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
561 }
562
563 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
564 {
565 int64_t max_int = DF_MAX_INT(df);
566 int64_t min_int = DF_MIN_INT(df);
567 if (arg2 > 0) {
568 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
569 } else {
570 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
571 }
572 }
573
574 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
575 {
576 uint64_t u_arg1 = UNSIGNED(arg1, df);
577 uint64_t u_arg2 = UNSIGNED(arg2, df);
578 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
579 }
580
581 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
582 {
583 uint64_t u_arg1 = UNSIGNED(arg1, df);
584 uint64_t max_uint = DF_MAX_UINT(df);
585 if (arg2 >= 0) {
586 uint64_t u_arg2 = (uint64_t)arg2;
587 return (u_arg1 > u_arg2) ?
588 (int64_t)(u_arg1 - u_arg2) :
589 0;
590 } else {
591 uint64_t u_arg2 = (uint64_t)(-arg2);
592 return (u_arg1 < max_uint - u_arg2) ?
593 (int64_t)(u_arg1 + u_arg2) :
594 (int64_t)max_uint;
595 }
596 }
597
598 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
599 {
600 uint64_t u_arg1 = UNSIGNED(arg1, df);
601 uint64_t u_arg2 = UNSIGNED(arg2, df);
602 int64_t max_int = DF_MAX_INT(df);
603 int64_t min_int = DF_MIN_INT(df);
604 if (u_arg1 > u_arg2) {
605 return u_arg1 - u_arg2 < (uint64_t)max_int ?
606 (int64_t)(u_arg1 - u_arg2) :
607 max_int;
608 } else {
609 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
610 (int64_t)(u_arg1 - u_arg2) :
611 min_int;
612 }
613 }
614
615 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
616 {
617 /* signed compare */
618 return (arg1 < arg2) ?
619 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
620 }
621
622 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
623 {
624 uint64_t u_arg1 = UNSIGNED(arg1, df);
625 uint64_t u_arg2 = UNSIGNED(arg2, df);
626 /* unsigned compare */
627 return (u_arg1 < u_arg2) ?
628 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
629 }
630
631 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
632 {
633 return arg1 * arg2;
634 }
635
636 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
637 {
638 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
639 return DF_MIN_INT(df);
640 }
641 return arg2 ? arg1 / arg2 : 0;
642 }
643
644 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
645 {
646 uint64_t u_arg1 = UNSIGNED(arg1, df);
647 uint64_t u_arg2 = UNSIGNED(arg2, df);
648 return u_arg2 ? u_arg1 / u_arg2 : 0;
649 }
650
651 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
652 {
653 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
654 return 0;
655 }
656 return arg2 ? arg1 % arg2 : 0;
657 }
658
659 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
660 {
661 uint64_t u_arg1 = UNSIGNED(arg1, df);
662 uint64_t u_arg2 = UNSIGNED(arg2, df);
663 return u_arg2 ? u_arg1 % u_arg2 : 0;
664 }
665
666 #define SIGNED_EVEN(a, df) \
667 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
668
669 #define UNSIGNED_EVEN(a, df) \
670 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
671
672 #define SIGNED_ODD(a, df) \
673 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
674
675 #define UNSIGNED_ODD(a, df) \
676 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
677
678 #define SIGNED_EXTRACT(e, o, a, df) \
679 do { \
680 e = SIGNED_EVEN(a, df); \
681 o = SIGNED_ODD(a, df); \
682 } while (0);
683
684 #define UNSIGNED_EXTRACT(e, o, a, df) \
685 do { \
686 e = UNSIGNED_EVEN(a, df); \
687 o = UNSIGNED_ODD(a, df); \
688 } while (0);
689
690 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
691 {
692 int64_t even_arg1;
693 int64_t even_arg2;
694 int64_t odd_arg1;
695 int64_t odd_arg2;
696 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
697 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
698 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
699 }
700
701 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
702 {
703 int64_t even_arg1;
704 int64_t even_arg2;
705 int64_t odd_arg1;
706 int64_t odd_arg2;
707 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
708 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
709 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
710 }
711
712 #define CONCATENATE_AND_SLIDE(s, k) \
713 do { \
714 for (i = 0; i < s; i++) { \
715 v[i] = pws->b[s * k + i]; \
716 v[i + s] = pwd->b[s * k + i]; \
717 } \
718 for (i = 0; i < s; i++) { \
719 pwd->b[s * k + i] = v[i + n]; \
720 } \
721 } while (0)
722
723 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
724 wr_t *pws, target_ulong rt)
725 {
726 uint32_t n = rt % DF_ELEMENTS(df);
727 uint8_t v[64];
728 uint32_t i, k;
729
730 switch (df) {
731 case DF_BYTE:
732 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
733 break;
734 case DF_HALF:
735 for (k = 0; k < 2; k++) {
736 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
737 }
738 break;
739 case DF_WORD:
740 for (k = 0; k < 4; k++) {
741 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
742 }
743 break;
744 case DF_DOUBLE:
745 for (k = 0; k < 8; k++) {
746 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
747 }
748 break;
749 default:
750 assert(0);
751 }
752 }
753
754 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
755 {
756 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
757 }
758
759 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
760 {
761 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
762 }
763
764 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
765 {
766 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
767 }
768
769 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
770 {
771 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
772 }
773
774 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
775 {
776 int64_t q_min = DF_MIN_INT(df);
777 int64_t q_max = DF_MAX_INT(df);
778
779 if (arg1 == q_min && arg2 == q_min) {
780 return q_max;
781 }
782 return (arg1 * arg2) >> (DF_BITS(df) - 1);
783 }
784
785 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
786 {
787 int64_t q_min = DF_MIN_INT(df);
788 int64_t q_max = DF_MAX_INT(df);
789 int64_t r_bit = 1 << (DF_BITS(df) - 2);
790
791 if (arg1 == q_min && arg2 == q_min) {
792 return q_max;
793 }
794 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
795 }
796
797 #define MSA_BINOP_DF(func) \
798 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
799 uint32_t wd, uint32_t ws, uint32_t wt) \
800 { \
801 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
802 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
803 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
804 uint32_t i; \
805 \
806 switch (df) { \
807 case DF_BYTE: \
808 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
809 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
810 } \
811 break; \
812 case DF_HALF: \
813 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
814 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
815 } \
816 break; \
817 case DF_WORD: \
818 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
819 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
820 } \
821 break; \
822 case DF_DOUBLE: \
823 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
824 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
825 } \
826 break; \
827 default: \
828 assert(0); \
829 } \
830 }
831
832 MSA_BINOP_DF(sll)
833 MSA_BINOP_DF(sra)
834 MSA_BINOP_DF(srl)
835 MSA_BINOP_DF(bclr)
836 MSA_BINOP_DF(bset)
837 MSA_BINOP_DF(bneg)
838 MSA_BINOP_DF(addv)
839 MSA_BINOP_DF(subv)
840 MSA_BINOP_DF(max_s)
841 MSA_BINOP_DF(max_u)
842 MSA_BINOP_DF(min_s)
843 MSA_BINOP_DF(min_u)
844 MSA_BINOP_DF(max_a)
845 MSA_BINOP_DF(min_a)
846 MSA_BINOP_DF(ceq)
847 MSA_BINOP_DF(clt_s)
848 MSA_BINOP_DF(clt_u)
849 MSA_BINOP_DF(cle_s)
850 MSA_BINOP_DF(cle_u)
851 MSA_BINOP_DF(add_a)
852 MSA_BINOP_DF(adds_a)
853 MSA_BINOP_DF(adds_s)
854 MSA_BINOP_DF(adds_u)
855 MSA_BINOP_DF(ave_s)
856 MSA_BINOP_DF(ave_u)
857 MSA_BINOP_DF(aver_s)
858 MSA_BINOP_DF(aver_u)
859 MSA_BINOP_DF(subs_s)
860 MSA_BINOP_DF(subs_u)
861 MSA_BINOP_DF(subsus_u)
862 MSA_BINOP_DF(subsuu_s)
863 MSA_BINOP_DF(asub_s)
864 MSA_BINOP_DF(asub_u)
865 MSA_BINOP_DF(mulv)
866 MSA_BINOP_DF(div_s)
867 MSA_BINOP_DF(div_u)
868 MSA_BINOP_DF(mod_s)
869 MSA_BINOP_DF(mod_u)
870 MSA_BINOP_DF(dotp_s)
871 MSA_BINOP_DF(dotp_u)
872 MSA_BINOP_DF(srar)
873 MSA_BINOP_DF(srlr)
874 MSA_BINOP_DF(hadd_s)
875 MSA_BINOP_DF(hadd_u)
876 MSA_BINOP_DF(hsub_s)
877 MSA_BINOP_DF(hsub_u)
878
879 MSA_BINOP_DF(mul_q)
880 MSA_BINOP_DF(mulr_q)
881 #undef MSA_BINOP_DF
882
883 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
884 uint32_t ws, uint32_t rt)
885 {
886 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
887 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
888
889 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
890 }
891
892 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
893 int64_t arg2)
894 {
895 return dest + arg1 * arg2;
896 }
897
898 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
899 int64_t arg2)
900 {
901 return dest - arg1 * arg2;
902 }
903
904 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
905 int64_t arg2)
906 {
907 int64_t even_arg1;
908 int64_t even_arg2;
909 int64_t odd_arg1;
910 int64_t odd_arg2;
911 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
912 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
913 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
914 }
915
916 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
917 int64_t arg2)
918 {
919 int64_t even_arg1;
920 int64_t even_arg2;
921 int64_t odd_arg1;
922 int64_t odd_arg2;
923 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
924 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
925 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
926 }
927
928 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
929 int64_t arg2)
930 {
931 int64_t even_arg1;
932 int64_t even_arg2;
933 int64_t odd_arg1;
934 int64_t odd_arg2;
935 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
936 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
937 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
938 }
939
940 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
941 int64_t arg2)
942 {
943 int64_t even_arg1;
944 int64_t even_arg2;
945 int64_t odd_arg1;
946 int64_t odd_arg2;
947 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
948 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
949 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
950 }
951
952 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
953 int64_t arg2)
954 {
955 int64_t q_prod, q_ret;
956
957 int64_t q_max = DF_MAX_INT(df);
958 int64_t q_min = DF_MIN_INT(df);
959
960 q_prod = arg1 * arg2;
961 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
962
963 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
964 }
965
966 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
967 int64_t arg2)
968 {
969 int64_t q_prod, q_ret;
970
971 int64_t q_max = DF_MAX_INT(df);
972 int64_t q_min = DF_MIN_INT(df);
973
974 q_prod = arg1 * arg2;
975 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
976
977 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
978 }
979
980 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
981 int64_t arg2)
982 {
983 int64_t q_prod, q_ret;
984
985 int64_t q_max = DF_MAX_INT(df);
986 int64_t q_min = DF_MIN_INT(df);
987 int64_t r_bit = 1 << (DF_BITS(df) - 2);
988
989 q_prod = arg1 * arg2;
990 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
991
992 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
993 }
994
995 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
996 int64_t arg2)
997 {
998 int64_t q_prod, q_ret;
999
1000 int64_t q_max = DF_MAX_INT(df);
1001 int64_t q_min = DF_MIN_INT(df);
1002 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1003
1004 q_prod = arg1 * arg2;
1005 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1006
1007 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1008 }
1009
1010 #define MSA_TEROP_DF(func) \
1011 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1012 uint32_t ws, uint32_t wt) \
1013 { \
1014 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1015 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1016 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1017 uint32_t i; \
1018 \
1019 switch (df) { \
1020 case DF_BYTE: \
1021 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1022 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1023 pwt->b[i]); \
1024 } \
1025 break; \
1026 case DF_HALF: \
1027 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1028 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1029 pwt->h[i]); \
1030 } \
1031 break; \
1032 case DF_WORD: \
1033 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1034 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1035 pwt->w[i]); \
1036 } \
1037 break; \
1038 case DF_DOUBLE: \
1039 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1040 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1041 pwt->d[i]); \
1042 } \
1043 break; \
1044 default: \
1045 assert(0); \
1046 } \
1047 }
1048
1049 MSA_TEROP_DF(maddv)
1050 MSA_TEROP_DF(msubv)
1051 MSA_TEROP_DF(dpadd_s)
1052 MSA_TEROP_DF(dpadd_u)
1053 MSA_TEROP_DF(dpsub_s)
1054 MSA_TEROP_DF(dpsub_u)
1055 MSA_TEROP_DF(binsl)
1056 MSA_TEROP_DF(binsr)
1057 MSA_TEROP_DF(madd_q)
1058 MSA_TEROP_DF(msub_q)
1059 MSA_TEROP_DF(maddr_q)
1060 MSA_TEROP_DF(msubr_q)
1061 #undef MSA_TEROP_DF
1062
1063 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1064 wr_t *pws, target_ulong rt)
1065 {
1066 uint32_t n = rt % DF_ELEMENTS(df);
1067 uint32_t i;
1068
1069 switch (df) {
1070 case DF_BYTE:
1071 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1072 pwd->b[i] = pws->b[n];
1073 }
1074 break;
1075 case DF_HALF:
1076 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1077 pwd->h[i] = pws->h[n];
1078 }
1079 break;
1080 case DF_WORD:
1081 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1082 pwd->w[i] = pws->w[n];
1083 }
1084 break;
1085 case DF_DOUBLE:
1086 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1087 pwd->d[i] = pws->d[n];
1088 }
1089 break;
1090 default:
1091 assert(0);
1092 }
1093 }
1094
1095 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1096 uint32_t ws, uint32_t rt)
1097 {
1098 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1099 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1100
1101 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1102 }
1103
1104 #define MSA_DO_B MSA_DO(b)
1105 #define MSA_DO_H MSA_DO(h)
1106 #define MSA_DO_W MSA_DO(w)
1107 #define MSA_DO_D MSA_DO(d)
1108
1109 #define MSA_LOOP_B MSA_LOOP(B)
1110 #define MSA_LOOP_H MSA_LOOP(H)
1111 #define MSA_LOOP_W MSA_LOOP(W)
1112 #define MSA_LOOP_D MSA_LOOP(D)
1113
1114 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1115 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1116 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1117 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1118
1119 #define MSA_LOOP(DF) \
1120 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1121 MSA_DO_ ## DF \
1122 }
1123
1124 #define MSA_FN_DF(FUNC) \
1125 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1126 uint32_t ws, uint32_t wt) \
1127 { \
1128 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1129 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1130 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1131 wr_t wx, *pwx = &wx; \
1132 uint32_t i; \
1133 switch (df) { \
1134 case DF_BYTE: \
1135 MSA_LOOP_B \
1136 break; \
1137 case DF_HALF: \
1138 MSA_LOOP_H \
1139 break; \
1140 case DF_WORD: \
1141 MSA_LOOP_W \
1142 break; \
1143 case DF_DOUBLE: \
1144 MSA_LOOP_D \
1145 break; \
1146 default: \
1147 assert(0); \
1148 } \
1149 msa_move_v(pwd, pwx); \
1150 }
1151
1152 #define MSA_LOOP_COND(DF) \
1153 (DF_ELEMENTS(DF) / 2)
1154
1155 #define Rb(pwr, i) (pwr->b[i])
1156 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1157 #define Rh(pwr, i) (pwr->h[i])
1158 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1159 #define Rw(pwr, i) (pwr->w[i])
1160 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1161 #define Rd(pwr, i) (pwr->d[i])
1162 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1163
1164 #define MSA_DO(DF) \
1165 do { \
1166 R##DF(pwx, i) = pwt->DF[2*i]; \
1167 L##DF(pwx, i) = pws->DF[2*i]; \
1168 } while (0);
1169 MSA_FN_DF(pckev_df)
1170 #undef MSA_DO
1171
1172 #define MSA_DO(DF) \
1173 do { \
1174 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1175 L##DF(pwx, i) = pws->DF[2*i+1]; \
1176 } while (0);
1177 MSA_FN_DF(pckod_df)
1178 #undef MSA_DO
1179
1180 #define MSA_DO(DF) \
1181 do { \
1182 pwx->DF[2*i] = L##DF(pwt, i); \
1183 pwx->DF[2*i+1] = L##DF(pws, i); \
1184 } while (0);
1185 MSA_FN_DF(ilvl_df)
1186 #undef MSA_DO
1187
1188 #define MSA_DO(DF) \
1189 do { \
1190 pwx->DF[2*i] = R##DF(pwt, i); \
1191 pwx->DF[2*i+1] = R##DF(pws, i); \
1192 } while (0);
1193 MSA_FN_DF(ilvr_df)
1194 #undef MSA_DO
1195
1196 #define MSA_DO(DF) \
1197 do { \
1198 pwx->DF[2*i] = pwt->DF[2*i]; \
1199 pwx->DF[2*i+1] = pws->DF[2*i]; \
1200 } while (0);
1201 MSA_FN_DF(ilvev_df)
1202 #undef MSA_DO
1203
1204 #define MSA_DO(DF) \
1205 do { \
1206 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1207 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1208 } while (0);
1209 MSA_FN_DF(ilvod_df)
1210 #undef MSA_DO
1211 #undef MSA_LOOP_COND
1212
1213 #define MSA_LOOP_COND(DF) \
1214 (DF_ELEMENTS(DF))
1215
1216 #define MSA_DO(DF) \
1217 do { \
1218 uint32_t n = DF_ELEMENTS(df); \
1219 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1220 pwx->DF[i] = \
1221 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1222 } while (0);
1223 MSA_FN_DF(vshf_df)
1224 #undef MSA_DO
1225 #undef MSA_LOOP_COND
1226 #undef MSA_FN_DF
1227
1228 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1229 uint32_t ws, uint32_t n)
1230 {
1231 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1232 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1233
1234 msa_sld_df(df, pwd, pws, n);
1235 }
1236
1237 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1238 uint32_t ws, uint32_t n)
1239 {
1240 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1241 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1242
1243 msa_splat_df(df, pwd, pws, n);
1244 }
1245
1246 void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1247 uint32_t ws, uint32_t n)
1248 {
1249 n %= DF_ELEMENTS(df);
1250
1251 switch (df) {
1252 case DF_BYTE:
1253 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
1254 break;
1255 case DF_HALF:
1256 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
1257 break;
1258 case DF_WORD:
1259 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
1260 break;
1261 #ifdef TARGET_MIPS64
1262 case DF_DOUBLE:
1263 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
1264 break;
1265 #endif
1266 default:
1267 assert(0);
1268 }
1269 }
1270
1271 void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1272 uint32_t ws, uint32_t n)
1273 {
1274 n %= DF_ELEMENTS(df);
1275
1276 switch (df) {
1277 case DF_BYTE:
1278 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
1279 break;
1280 case DF_HALF:
1281 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
1282 break;
1283 case DF_WORD:
1284 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
1285 break;
1286 #ifdef TARGET_MIPS64
1287 case DF_DOUBLE:
1288 env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
1289 break;
1290 #endif
1291 default:
1292 assert(0);
1293 }
1294 }
1295
1296 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1297 uint32_t rs_num, uint32_t n)
1298 {
1299 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1300 target_ulong rs = env->active_tc.gpr[rs_num];
1301
1302 switch (df) {
1303 case DF_BYTE:
1304 pwd->b[n] = (int8_t)rs;
1305 break;
1306 case DF_HALF:
1307 pwd->h[n] = (int16_t)rs;
1308 break;
1309 case DF_WORD:
1310 pwd->w[n] = (int32_t)rs;
1311 break;
1312 case DF_DOUBLE:
1313 pwd->d[n] = (int64_t)rs;
1314 break;
1315 default:
1316 assert(0);
1317 }
1318 }
1319
1320 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1321 uint32_t ws, uint32_t n)
1322 {
1323 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1324 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1325
1326 switch (df) {
1327 case DF_BYTE:
1328 pwd->b[n] = (int8_t)pws->b[0];
1329 break;
1330 case DF_HALF:
1331 pwd->h[n] = (int16_t)pws->h[0];
1332 break;
1333 case DF_WORD:
1334 pwd->w[n] = (int32_t)pws->w[0];
1335 break;
1336 case DF_DOUBLE:
1337 pwd->d[n] = (int64_t)pws->d[0];
1338 break;
1339 default:
1340 assert(0);
1341 }
1342 }
1343
1344 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
1345 {
1346 switch (cd) {
1347 case 0:
1348 break;
1349 case 1:
1350 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
1351 /* set float_status rounding mode */
1352 set_float_rounding_mode(
1353 ieee_rm[(env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM],
1354 &env->active_tc.msa_fp_status);
1355 /* set float_status flush modes */
1356 set_flush_to_zero(
1357 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0 ? 1 : 0,
1358 &env->active_tc.msa_fp_status);
1359 set_flush_inputs_to_zero(
1360 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0 ? 1 : 0,
1361 &env->active_tc.msa_fp_status);
1362 /* check exception */
1363 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
1364 & GET_FP_CAUSE(env->active_tc.msacsr)) {
1365 helper_raise_exception(env, EXCP_MSAFPE);
1366 }
1367 break;
1368 }
1369 }
1370
1371 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
1372 {
1373 switch (cs) {
1374 case 0:
1375 return env->msair;
1376 case 1:
1377 return env->active_tc.msacsr & MSACSR_MASK;
1378 }
1379 return 0;
1380 }
1381
1382 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
1383 {
1384 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1385 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1386
1387 msa_move_v(pwd, pws);
1388 }
1389
1390 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
1391 {
1392 uint64_t x;
1393
1394 x = UNSIGNED(arg, df);
1395
1396 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
1397 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
1398 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
1399 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
1400 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
1401 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
1402
1403 return x;
1404 }
1405
1406 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
1407 {
1408 uint64_t x, y;
1409 int n, c;
1410
1411 x = UNSIGNED(arg, df);
1412 n = DF_BITS(df);
1413 c = DF_BITS(df) / 2;
1414
1415 do {
1416 y = x >> c;
1417 if (y != 0) {
1418 n = n - c;
1419 x = y;
1420 }
1421 c = c >> 1;
1422 } while (c != 0);
1423
1424 return n - x;
1425 }
1426
1427 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
1428 {
1429 return msa_nlzc_df(df, UNSIGNED((~arg), df));
1430 }
1431
1432 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1433 uint32_t rs)
1434 {
1435 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1436 uint32_t i;
1437
1438 switch (df) {
1439 case DF_BYTE:
1440 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1441 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
1442 }
1443 break;
1444 case DF_HALF:
1445 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1446 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
1447 }
1448 break;
1449 case DF_WORD:
1450 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1451 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
1452 }
1453 break;
1454 case DF_DOUBLE:
1455 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1456 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
1457 }
1458 break;
1459 default:
1460 assert(0);
1461 }
1462 }
1463
1464 #define MSA_UNOP_DF(func) \
1465 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1466 uint32_t wd, uint32_t ws) \
1467 { \
1468 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1469 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1470 uint32_t i; \
1471 \
1472 switch (df) { \
1473 case DF_BYTE: \
1474 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1475 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1476 } \
1477 break; \
1478 case DF_HALF: \
1479 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1480 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1481 } \
1482 break; \
1483 case DF_WORD: \
1484 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1485 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1486 } \
1487 break; \
1488 case DF_DOUBLE: \
1489 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1490 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1491 } \
1492 break; \
1493 default: \
1494 assert(0); \
1495 } \
1496 }
1497
1498 MSA_UNOP_DF(nlzc)
1499 MSA_UNOP_DF(nloc)
1500 MSA_UNOP_DF(pcnt)
1501 #undef MSA_UNOP_DF
1502
1503 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1504 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1505
1506 #define FLOAT_SNAN16 (float16_default_nan ^ 0x0220)
1507 /* 0x7c20 */
1508 #define FLOAT_SNAN32 (float32_default_nan ^ 0x00400020)
1509 /* 0x7f800020 */
1510 #define FLOAT_SNAN64 (float64_default_nan ^ 0x0008000000000020ULL)
1511 /* 0x7ff0000000000020 */
1512
1513 static inline void clear_msacsr_cause(CPUMIPSState *env)
1514 {
1515 SET_FP_CAUSE(env->active_tc.msacsr, 0);
1516 }
1517
1518 static inline void check_msacsr_cause(CPUMIPSState *env)
1519 {
1520 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
1521 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
1522 UPDATE_FP_FLAGS(env->active_tc.msacsr,
1523 GET_FP_CAUSE(env->active_tc.msacsr));
1524 } else {
1525 helper_raise_exception(env, EXCP_MSAFPE);
1526 }
1527 }
1528
1529 /* Flush-to-zero use cases for update_msacsr() */
1530 #define CLEAR_FS_UNDERFLOW 1
1531 #define CLEAR_IS_INEXACT 2
1532 #define RECIPROCAL_INEXACT 4
1533
1534 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
1535 {
1536 int ieee_ex;
1537
1538 int c;
1539 int cause;
1540 int enable;
1541
1542 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
1543
1544 /* QEMU softfloat does not signal all underflow cases */
1545 if (denormal) {
1546 ieee_ex |= float_flag_underflow;
1547 }
1548
1549 c = ieee_ex_to_mips(ieee_ex);
1550 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1551
1552 /* Set Inexact (I) when flushing inputs to zero */
1553 if ((ieee_ex & float_flag_input_denormal) &&
1554 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1555 if (action & CLEAR_IS_INEXACT) {
1556 c &= ~FP_INEXACT;
1557 } else {
1558 c |= FP_INEXACT;
1559 }
1560 }
1561
1562 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1563 if ((ieee_ex & float_flag_output_denormal) &&
1564 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1565 c |= FP_INEXACT;
1566 if (action & CLEAR_FS_UNDERFLOW) {
1567 c &= ~FP_UNDERFLOW;
1568 } else {
1569 c |= FP_UNDERFLOW;
1570 }
1571 }
1572
1573 /* Set Inexact (I) when Overflow (O) is not enabled */
1574 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
1575 c |= FP_INEXACT;
1576 }
1577
1578 /* Clear Exact Underflow when Underflow (U) is not enabled */
1579 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
1580 (c & FP_INEXACT) == 0) {
1581 c &= ~FP_UNDERFLOW;
1582 }
1583
1584 /* Reciprocal operations set only Inexact when valid and not
1585 divide by zero */
1586 if ((action & RECIPROCAL_INEXACT) &&
1587 (c & (FP_INVALID | FP_DIV0)) == 0) {
1588 c = FP_INEXACT;
1589 }
1590
1591 cause = c & enable; /* all current enabled exceptions */
1592
1593 if (cause == 0) {
1594 /* No enabled exception, update the MSACSR Cause
1595 with all current exceptions */
1596 SET_FP_CAUSE(env->active_tc.msacsr,
1597 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1598 } else {
1599 /* Current exceptions are enabled */
1600 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
1601 /* Exception(s) will trap, update MSACSR Cause
1602 with all enabled exceptions */
1603 SET_FP_CAUSE(env->active_tc.msacsr,
1604 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1605 }
1606 }
1607
1608 return c;
1609 }
1610
1611 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
1612 {
1613 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1614 return c & enable;
1615 }
1616
1617 static inline float16 float16_from_float32(int32 a, flag ieee STATUS_PARAM)
1618 {
1619 float16 f_val;
1620
1621 f_val = float32_to_float16((float32)a, ieee STATUS_VAR);
1622 f_val = float16_maybe_silence_nan(f_val);
1623
1624 return a < 0 ? (f_val | (1 << 15)) : f_val;
1625 }
1626
1627 static inline float32 float32_from_float64(int64 a STATUS_PARAM)
1628 {
1629 float32 f_val;
1630
1631 f_val = float64_to_float32((float64)a STATUS_VAR);
1632 f_val = float32_maybe_silence_nan(f_val);
1633
1634 return a < 0 ? (f_val | (1 << 31)) : f_val;
1635 }
1636
1637 static inline float32 float32_from_float16(int16_t a, flag ieee STATUS_PARAM)
1638 {
1639 float32 f_val;
1640
1641 f_val = float16_to_float32((float16)a, ieee STATUS_VAR);
1642 f_val = float32_maybe_silence_nan(f_val);
1643
1644 return a < 0 ? (f_val | (1 << 31)) : f_val;
1645 }
1646
1647 static inline float64 float64_from_float32(int32 a STATUS_PARAM)
1648 {
1649 float64 f_val;
1650
1651 f_val = float32_to_float64((float64)a STATUS_VAR);
1652 f_val = float64_maybe_silence_nan(f_val);
1653
1654 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
1655 }
1656
1657 static inline float32 float32_from_q16(int16_t a STATUS_PARAM)
1658 {
1659 float32 f_val;
1660
1661 /* conversion as integer and scaling */
1662 f_val = int32_to_float32(a STATUS_VAR);
1663 f_val = float32_scalbn(f_val, -15 STATUS_VAR);
1664
1665 return f_val;
1666 }
1667
1668 static inline float64 float64_from_q32(int32 a STATUS_PARAM)
1669 {
1670 float64 f_val;
1671
1672 /* conversion as integer and scaling */
1673 f_val = int32_to_float64(a STATUS_VAR);
1674 f_val = float64_scalbn(f_val, -31 STATUS_VAR);
1675
1676 return f_val;
1677 }
1678
1679 static inline int16_t float32_to_q16(float32 a STATUS_PARAM)
1680 {
1681 int32 q_val;
1682 int32 q_min = 0xffff8000;
1683 int32 q_max = 0x00007fff;
1684
1685 int ieee_ex;
1686
1687 if (float32_is_any_nan(a)) {
1688 float_raise(float_flag_invalid STATUS_VAR);
1689 return 0;
1690 }
1691
1692 /* scaling */
1693 a = float32_scalbn(a, 15 STATUS_VAR);
1694
1695 ieee_ex = get_float_exception_flags(status);
1696 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1697 STATUS_VAR);
1698
1699 if (ieee_ex & float_flag_overflow) {
1700 float_raise(float_flag_inexact STATUS_VAR);
1701 return (int32)a < 0 ? q_min : q_max;
1702 }
1703
1704 /* conversion to int */
1705 q_val = float32_to_int32(a STATUS_VAR);
1706
1707 ieee_ex = get_float_exception_flags(status);
1708 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1709 STATUS_VAR);
1710
1711 if (ieee_ex & float_flag_invalid) {
1712 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1713 STATUS_VAR);
1714 float_raise(float_flag_overflow | float_flag_inexact STATUS_VAR);
1715 return (int32)a < 0 ? q_min : q_max;
1716 }
1717
1718 if (q_val < q_min) {
1719 float_raise(float_flag_overflow | float_flag_inexact STATUS_VAR);
1720 return (int16_t)q_min;
1721 }
1722
1723 if (q_max < q_val) {
1724 float_raise(float_flag_overflow | float_flag_inexact STATUS_VAR);
1725 return (int16_t)q_max;
1726 }
1727
1728 return (int16_t)q_val;
1729 }
1730
1731 static inline int32 float64_to_q32(float64 a STATUS_PARAM)
1732 {
1733 int64 q_val;
1734 int64 q_min = 0xffffffff80000000LL;
1735 int64 q_max = 0x000000007fffffffLL;
1736
1737 int ieee_ex;
1738
1739 if (float64_is_any_nan(a)) {
1740 float_raise(float_flag_invalid STATUS_VAR);
1741 return 0;
1742 }
1743
1744 /* scaling */
1745 a = float64_scalbn(a, 31 STATUS_VAR);
1746
1747 ieee_ex = get_float_exception_flags(status);
1748 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1749 STATUS_VAR);
1750
1751 if (ieee_ex & float_flag_overflow) {
1752 float_raise(float_flag_inexact STATUS_VAR);
1753 return (int64)a < 0 ? q_min : q_max;
1754 }
1755
1756 /* conversion to integer */
1757 q_val = float64_to_int64(a STATUS_VAR);
1758
1759 ieee_ex = get_float_exception_flags(status);
1760 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1761 STATUS_VAR);
1762
1763 if (ieee_ex & float_flag_invalid) {
1764 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1765 STATUS_VAR);
1766 float_raise(float_flag_overflow | float_flag_inexact STATUS_VAR);
1767 return (int64)a < 0 ? q_min : q_max;
1768 }
1769
1770 if (q_val < q_min) {
1771 float_raise(float_flag_overflow | float_flag_inexact STATUS_VAR);
1772 return (int32)q_min;
1773 }
1774
1775 if (q_max < q_val) {
1776 float_raise(float_flag_overflow | float_flag_inexact STATUS_VAR);
1777 return (int32)q_max;
1778 }
1779
1780 return (int32)q_val;
1781 }
1782
1783 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1784 do { \
1785 float_status *status = &env->active_tc.msa_fp_status; \
1786 int c; \
1787 int64_t cond; \
1788 set_float_exception_flags(0, status); \
1789 if (!QUIET) { \
1790 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1791 } else { \
1792 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1793 } \
1794 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1795 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1796 \
1797 if (get_enabled_exceptions(env, c)) { \
1798 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
1799 } \
1800 } while (0)
1801
1802 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1803 do { \
1804 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1805 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1806 DEST = 0; \
1807 } \
1808 } while (0)
1809
1810 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1811 do { \
1812 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1813 if (DEST == 0) { \
1814 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1815 } \
1816 } while (0)
1817
1818 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1819 do { \
1820 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1821 if (DEST == 0) { \
1822 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1823 } \
1824 } while (0)
1825
1826 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1827 do { \
1828 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1829 if (DEST == 0) { \
1830 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1831 if (DEST == 0) { \
1832 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1833 } \
1834 } \
1835 } while (0)
1836
1837 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1838 do { \
1839 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1840 if (DEST == 0) { \
1841 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1842 } \
1843 } while (0)
1844
1845 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1846 do { \
1847 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1848 if (DEST == 0) { \
1849 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1850 } \
1851 } while (0)
1852
1853 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1854 do { \
1855 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1856 if (DEST == 0) { \
1857 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1858 } \
1859 } while (0)
1860
1861 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1862 wr_t *pwt, uint32_t df, int quiet)
1863 {
1864 wr_t wx, *pwx = &wx;
1865 uint32_t i;
1866
1867 clear_msacsr_cause(env);
1868
1869 switch (df) {
1870 case DF_WORD:
1871 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1872 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1873 }
1874 break;
1875 case DF_DOUBLE:
1876 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1877 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1878 }
1879 break;
1880 default:
1881 assert(0);
1882 }
1883
1884 check_msacsr_cause(env);
1885
1886 msa_move_v(pwd, pwx);
1887 }
1888
1889 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1890 wr_t *pwt, uint32_t df, int quiet)
1891 {
1892 wr_t wx, *pwx = &wx;
1893 uint32_t i;
1894
1895 clear_msacsr_cause(env);
1896
1897 switch (df) {
1898 case DF_WORD:
1899 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1900 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
1901 quiet);
1902 }
1903 break;
1904 case DF_DOUBLE:
1905 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1906 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
1907 quiet);
1908 }
1909 break;
1910 default:
1911 assert(0);
1912 }
1913
1914 check_msacsr_cause(env);
1915
1916 msa_move_v(pwd, pwx);
1917 }
1918
1919 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1920 wr_t *pwt, uint32_t df, int quiet)
1921 {
1922 wr_t wx, *pwx = &wx;
1923 uint32_t i;
1924
1925 clear_msacsr_cause(env);
1926
1927 switch (df) {
1928 case DF_WORD:
1929 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1930 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
1931 }
1932 break;
1933 case DF_DOUBLE:
1934 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1935 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
1936 }
1937 break;
1938 default:
1939 assert(0);
1940 }
1941
1942 check_msacsr_cause(env);
1943
1944 msa_move_v(pwd, pwx);
1945 }
1946
1947 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1948 wr_t *pwt, uint32_t df, int quiet)
1949 {
1950 wr_t wx, *pwx = &wx;
1951 uint32_t i;
1952
1953 clear_msacsr_cause(env);
1954
1955 switch (df) {
1956 case DF_WORD:
1957 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1958 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1959 }
1960 break;
1961 case DF_DOUBLE:
1962 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1963 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1964 }
1965 break;
1966 default:
1967 assert(0);
1968 }
1969
1970 check_msacsr_cause(env);
1971
1972 msa_move_v(pwd, pwx);
1973 }
1974
1975 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1976 wr_t *pwt, uint32_t df, int quiet)
1977 {
1978 wr_t wx, *pwx = &wx;
1979 uint32_t i;
1980
1981 clear_msacsr_cause(env);
1982
1983 switch (df) {
1984 case DF_WORD:
1985 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1986 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
1987 }
1988 break;
1989 case DF_DOUBLE:
1990 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1991 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
1992 }
1993 break;
1994 default:
1995 assert(0);
1996 }
1997
1998 check_msacsr_cause(env);
1999
2000 msa_move_v(pwd, pwx);
2001 }
2002
2003 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2004 wr_t *pwt, uint32_t df, int quiet)
2005 {
2006 wr_t wx, *pwx = &wx;
2007 uint32_t i;
2008
2009 clear_msacsr_cause(env);
2010
2011 switch (df) {
2012 case DF_WORD:
2013 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2014 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2015 }
2016 break;
2017 case DF_DOUBLE:
2018 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2019 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2020 }
2021 break;
2022 default:
2023 assert(0);
2024 }
2025
2026 check_msacsr_cause(env);
2027
2028 msa_move_v(pwd, pwx);
2029 }
2030
2031 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2032 wr_t *pwt, uint32_t df, int quiet)
2033 {
2034 wr_t wx, *pwx = &wx;
2035 uint32_t i;
2036
2037 clear_msacsr_cause(env);
2038
2039 switch (df) {
2040 case DF_WORD:
2041 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2042 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
2043 }
2044 break;
2045 case DF_DOUBLE:
2046 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2047 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
2048 }
2049 break;
2050 default:
2051 assert(0);
2052 }
2053
2054 check_msacsr_cause(env);
2055
2056 msa_move_v(pwd, pwx);
2057 }
2058
2059 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2060 wr_t *pwt, uint32_t df, int quiet)
2061 {
2062 wr_t wx, *pwx = &wx;
2063 uint32_t i;
2064
2065 clear_msacsr_cause(env);
2066
2067 switch (df) {
2068 case DF_WORD:
2069 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2070 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2071 }
2072 break;
2073 case DF_DOUBLE:
2074 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2075 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2076 }
2077 break;
2078 default:
2079 assert(0);
2080 }
2081
2082 check_msacsr_cause(env);
2083
2084 msa_move_v(pwd, pwx);
2085 }
2086
2087 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2088 wr_t *pwt, uint32_t df, int quiet)
2089 {
2090 wr_t wx, *pwx = &wx;
2091 uint32_t i;
2092
2093 clear_msacsr_cause(env);
2094
2095 switch (df) {
2096 case DF_WORD:
2097 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2098 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2099 }
2100 break;
2101 case DF_DOUBLE:
2102 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2103 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2104 }
2105 break;
2106 default:
2107 assert(0);
2108 }
2109
2110 check_msacsr_cause(env);
2111
2112 msa_move_v(pwd, pwx);
2113 }
2114
2115 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2116 wr_t *pwt, uint32_t df, int quiet)
2117 {
2118 wr_t wx, *pwx = &wx;
2119 uint32_t i;
2120
2121 clear_msacsr_cause(env);
2122
2123 switch (df) {
2124 case DF_WORD:
2125 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2126 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2127 }
2128 break;
2129 case DF_DOUBLE:
2130 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2131 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2132 }
2133 break;
2134 default:
2135 assert(0);
2136 }
2137
2138 check_msacsr_cause(env);
2139
2140 msa_move_v(pwd, pwx);
2141 }
2142
2143 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2144 wr_t *pwt, uint32_t df, int quiet) {
2145 wr_t wx, *pwx = &wx;
2146 uint32_t i;
2147
2148 clear_msacsr_cause(env);
2149
2150 switch (df) {
2151 case DF_WORD:
2152 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2153 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2154 }
2155 break;
2156 case DF_DOUBLE:
2157 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2158 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2159 }
2160 break;
2161 default:
2162 assert(0);
2163 }
2164
2165 check_msacsr_cause(env);
2166
2167 msa_move_v(pwd, pwx);
2168 }
2169
2170 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2171 uint32_t ws, uint32_t wt)
2172 {
2173 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2174 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2175 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2176 compare_af(env, pwd, pws, pwt, df, 1);
2177 }
2178
2179 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2180 uint32_t ws, uint32_t wt)
2181 {
2182 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2183 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2184 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2185 compare_un(env, pwd, pws, pwt, df, 1);
2186 }
2187
2188 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2189 uint32_t ws, uint32_t wt)
2190 {
2191 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2192 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2193 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2194 compare_eq(env, pwd, pws, pwt, df, 1);
2195 }
2196
2197 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2198 uint32_t ws, uint32_t wt)
2199 {
2200 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2201 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2202 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2203 compare_ueq(env, pwd, pws, pwt, df, 1);
2204 }
2205
2206 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2207 uint32_t ws, uint32_t wt)
2208 {
2209 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2210 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2211 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2212 compare_lt(env, pwd, pws, pwt, df, 1);
2213 }
2214
2215 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2216 uint32_t ws, uint32_t wt)
2217 {
2218 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2219 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2220 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2221 compare_ult(env, pwd, pws, pwt, df, 1);
2222 }
2223
2224 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2225 uint32_t ws, uint32_t wt)
2226 {
2227 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2228 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2229 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2230 compare_le(env, pwd, pws, pwt, df, 1);
2231 }
2232
2233 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2234 uint32_t ws, uint32_t wt)
2235 {
2236 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2237 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2238 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2239 compare_ule(env, pwd, pws, pwt, df, 1);
2240 }
2241
2242 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2243 uint32_t ws, uint32_t wt)
2244 {
2245 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2246 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2247 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2248 compare_af(env, pwd, pws, pwt, df, 0);
2249 }
2250
2251 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2252 uint32_t ws, uint32_t wt)
2253 {
2254 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2255 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2256 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2257 compare_un(env, pwd, pws, pwt, df, 0);
2258 }
2259
2260 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2261 uint32_t ws, uint32_t wt)
2262 {
2263 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2264 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2265 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2266 compare_eq(env, pwd, pws, pwt, df, 0);
2267 }
2268
2269 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2270 uint32_t ws, uint32_t wt)
2271 {
2272 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2273 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2274 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2275 compare_ueq(env, pwd, pws, pwt, df, 0);
2276 }
2277
2278 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2279 uint32_t ws, uint32_t wt)
2280 {
2281 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2282 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2283 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2284 compare_lt(env, pwd, pws, pwt, df, 0);
2285 }
2286
2287 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2288 uint32_t ws, uint32_t wt)
2289 {
2290 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2291 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2292 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2293 compare_ult(env, pwd, pws, pwt, df, 0);
2294 }
2295
2296 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2297 uint32_t ws, uint32_t wt)
2298 {
2299 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2300 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2301 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2302 compare_le(env, pwd, pws, pwt, df, 0);
2303 }
2304
2305 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2306 uint32_t ws, uint32_t wt)
2307 {
2308 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2309 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2310 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2311 compare_ule(env, pwd, pws, pwt, df, 0);
2312 }
2313
2314 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2315 uint32_t ws, uint32_t wt)
2316 {
2317 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2318 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2319 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2320 compare_or(env, pwd, pws, pwt, df, 1);
2321 }
2322
2323 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2324 uint32_t ws, uint32_t wt)
2325 {
2326 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2327 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2328 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2329 compare_une(env, pwd, pws, pwt, df, 1);
2330 }
2331
2332 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2333 uint32_t ws, uint32_t wt)
2334 {
2335 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2336 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2337 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2338 compare_ne(env, pwd, pws, pwt, df, 1);
2339 }
2340
2341 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2342 uint32_t ws, uint32_t wt)
2343 {
2344 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2345 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2346 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2347 compare_or(env, pwd, pws, pwt, df, 0);
2348 }
2349
2350 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2351 uint32_t ws, uint32_t wt)
2352 {
2353 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2354 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2355 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2356 compare_une(env, pwd, pws, pwt, df, 0);
2357 }
2358
2359 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2360 uint32_t ws, uint32_t wt)
2361 {
2362 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2363 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2364 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2365 compare_ne(env, pwd, pws, pwt, df, 0);
2366 }
2367
2368 #define float16_is_zero(ARG) 0
2369 #define float16_is_zero_or_denormal(ARG) 0
2370
2371 #define IS_DENORMAL(ARG, BITS) \
2372 (!float ## BITS ## _is_zero(ARG) \
2373 && float ## BITS ## _is_zero_or_denormal(ARG))
2374
2375 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2376 do { \
2377 float_status *status = &env->active_tc.msa_fp_status; \
2378 int c; \
2379 \
2380 set_float_exception_flags(0, status); \
2381 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2382 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2383 \
2384 if (get_enabled_exceptions(env, c)) { \
2385 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2386 } \
2387 } while (0)
2388
2389 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2390 uint32_t ws, uint32_t wt)
2391 {
2392 wr_t wx, *pwx = &wx;
2393 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2394 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2395 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2396 uint32_t i;
2397
2398 clear_msacsr_cause(env);
2399
2400 switch (df) {
2401 case DF_WORD:
2402 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2403 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
2404 }
2405 break;
2406 case DF_DOUBLE:
2407 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2408 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
2409 }
2410 break;
2411 default:
2412 assert(0);
2413 }
2414
2415 check_msacsr_cause(env);
2416 msa_move_v(pwd, pwx);
2417 }
2418
2419 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2420 uint32_t ws, uint32_t wt)
2421 {
2422 wr_t wx, *pwx = &wx;
2423 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2424 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2425 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2426 uint32_t i;
2427
2428 clear_msacsr_cause(env);
2429
2430 switch (df) {
2431 case DF_WORD:
2432 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2433 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
2434 }
2435 break;
2436 case DF_DOUBLE:
2437 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2438 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
2439 }
2440 break;
2441 default:
2442 assert(0);
2443 }
2444
2445 check_msacsr_cause(env);
2446 msa_move_v(pwd, pwx);
2447 }
2448
2449 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2450 uint32_t ws, uint32_t wt)
2451 {
2452 wr_t wx, *pwx = &wx;
2453 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2454 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2455 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2456 uint32_t i;
2457
2458 clear_msacsr_cause(env);
2459
2460 switch (df) {
2461 case DF_WORD:
2462 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2463 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
2464 }
2465 break;
2466 case DF_DOUBLE:
2467 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2468 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
2469 }
2470 break;
2471 default:
2472 assert(0);
2473 }
2474
2475 check_msacsr_cause(env);
2476
2477 msa_move_v(pwd, pwx);
2478 }
2479
2480 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2481 uint32_t ws, uint32_t wt)
2482 {
2483 wr_t wx, *pwx = &wx;
2484 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2485 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2486 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2487 uint32_t i;
2488
2489 clear_msacsr_cause(env);
2490
2491 switch (df) {
2492 case DF_WORD:
2493 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2494 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
2495 }
2496 break;
2497 case DF_DOUBLE:
2498 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2499 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
2500 }
2501 break;
2502 default:
2503 assert(0);
2504 }
2505
2506 check_msacsr_cause(env);
2507
2508 msa_move_v(pwd, pwx);
2509 }
2510
2511 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2512 do { \
2513 float_status *status = &env->active_tc.msa_fp_status; \
2514 int c; \
2515 \
2516 set_float_exception_flags(0, status); \
2517 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2518 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2519 \
2520 if (get_enabled_exceptions(env, c)) { \
2521 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2522 } \
2523 } while (0)
2524
2525 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2526 uint32_t ws, uint32_t wt)
2527 {
2528 wr_t wx, *pwx = &wx;
2529 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2530 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2531 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2532 uint32_t i;
2533
2534 clear_msacsr_cause(env);
2535
2536 switch (df) {
2537 case DF_WORD:
2538 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2539 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2540 pws->w[i], pwt->w[i], 0, 32);
2541 }
2542 break;
2543 case DF_DOUBLE:
2544 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2545 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2546 pws->d[i], pwt->d[i], 0, 64);
2547 }
2548 break;
2549 default:
2550 assert(0);
2551 }
2552
2553 check_msacsr_cause(env);
2554
2555 msa_move_v(pwd, pwx);
2556 }
2557
2558 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2559 uint32_t ws, uint32_t wt)
2560 {
2561 wr_t wx, *pwx = &wx;
2562 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2563 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2564 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2565 uint32_t i;
2566
2567 clear_msacsr_cause(env);
2568
2569 switch (df) {
2570 case DF_WORD:
2571 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2572 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2573 pws->w[i], pwt->w[i],
2574 float_muladd_negate_product, 32);
2575 }
2576 break;
2577 case DF_DOUBLE:
2578 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2579 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2580 pws->d[i], pwt->d[i],
2581 float_muladd_negate_product, 64);
2582 }
2583 break;
2584 default:
2585 assert(0);
2586 }
2587
2588 check_msacsr_cause(env);
2589
2590 msa_move_v(pwd, pwx);
2591 }
2592
2593 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2594 uint32_t ws, uint32_t wt)
2595 {
2596 wr_t wx, *pwx = &wx;
2597 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2598 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2599 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2600 uint32_t i;
2601
2602 clear_msacsr_cause(env);
2603
2604 switch (df) {
2605 case DF_WORD:
2606 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2607 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
2608 pwt->w[i] > 0x200 ? 0x200 :
2609 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
2610 32);
2611 }
2612 break;
2613 case DF_DOUBLE:
2614 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2615 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
2616 pwt->d[i] > 0x1000 ? 0x1000 :
2617 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
2618 64);
2619 }
2620 break;
2621 default:
2622 assert(0);
2623 }
2624
2625 check_msacsr_cause(env);
2626
2627 msa_move_v(pwd, pwx);
2628 }
2629
2630 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2631 do { \
2632 float_status *status = &env->active_tc.msa_fp_status; \
2633 int c; \
2634 \
2635 set_float_exception_flags(0, status); \
2636 DEST = float ## BITS ## _ ## OP(ARG, status); \
2637 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2638 \
2639 if (get_enabled_exceptions(env, c)) { \
2640 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2641 } \
2642 } while (0)
2643
2644 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2645 uint32_t ws, uint32_t wt)
2646 {
2647 wr_t wx, *pwx = &wx;
2648 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2649 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2650 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2651 uint32_t i;
2652
2653 switch (df) {
2654 case DF_WORD:
2655 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2656 /* Half precision floats come in two formats: standard
2657 IEEE and "ARM" format. The latter gains extra exponent
2658 range by omitting the NaN/Inf encodings. */
2659 flag ieee = 1;
2660
2661 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
2662 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
2663 }
2664 break;
2665 case DF_DOUBLE:
2666 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2667 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
2668 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
2669 }
2670 break;
2671 default:
2672 assert(0);
2673 }
2674
2675 check_msacsr_cause(env);
2676 msa_move_v(pwd, pwx);
2677 }
2678
2679 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2680 do { \
2681 float_status *status = &env->active_tc.msa_fp_status; \
2682 int c; \
2683 \
2684 set_float_exception_flags(0, status); \
2685 DEST = float ## BITS ## _ ## OP(ARG, status); \
2686 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2687 \
2688 if (get_enabled_exceptions(env, c)) { \
2689 DEST = ((FLOAT_SNAN ## XBITS >> 6) << 6) | c; \
2690 } \
2691 } while (0)
2692
2693 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2694 uint32_t ws, uint32_t wt)
2695 {
2696 wr_t wx, *pwx = &wx;
2697 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2698 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2699 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2700 uint32_t i;
2701
2702 clear_msacsr_cause(env);
2703
2704 switch (df) {
2705 case DF_WORD:
2706 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2707 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
2708 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
2709 }
2710 break;
2711 case DF_DOUBLE:
2712 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2713 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
2714 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
2715 }
2716 break;
2717 default:
2718 assert(0);
2719 }
2720
2721 check_msacsr_cause(env);
2722
2723 msa_move_v(pwd, pwx);
2724 }
2725
2726 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS) \
2727 !float ## BITS ## _is_any_nan(ARG1) \
2728 && float ## BITS ## _is_quiet_nan(ARG2)
2729
2730 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2731 do { \
2732 float_status *status = &env->active_tc.msa_fp_status; \
2733 int c; \
2734 \
2735 set_float_exception_flags(0, status); \
2736 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2737 c = update_msacsr(env, 0, 0); \
2738 \
2739 if (get_enabled_exceptions(env, c)) { \
2740 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2741 } \
2742 } while (0)
2743
2744 #define FMAXMIN_A(F, G, X, _S, _T, BITS) \
2745 do { \
2746 uint## BITS ##_t S = _S, T = _T; \
2747 uint## BITS ##_t as, at, xs, xt, xd; \
2748 if (NUMBER_QNAN_PAIR(S, T, BITS)) { \
2749 T = S; \
2750 } \
2751 else if (NUMBER_QNAN_PAIR(T, S, BITS)) { \
2752 S = T; \
2753 } \
2754 as = float## BITS ##_abs(S); \
2755 at = float## BITS ##_abs(T); \
2756 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2757 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2758 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2759 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2760 } while (0)
2761
2762 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2763 uint32_t ws, uint32_t wt)
2764 {
2765 wr_t wx, *pwx = &wx;
2766 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2767 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2768 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2769 uint32_t i;
2770
2771 clear_msacsr_cause(env);
2772
2773 switch (df) {
2774 case DF_WORD:
2775 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2776 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
2777 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
2778 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
2779 MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
2780 } else {
2781 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
2782 }
2783 }
2784 break;
2785 case DF_DOUBLE:
2786 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2787 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
2788 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
2789 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
2790 MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
2791 } else {
2792 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
2793 }
2794 }
2795 break;
2796 default:
2797 assert(0);
2798 }
2799
2800 check_msacsr_cause(env);
2801
2802 msa_move_v(pwd, pwx);
2803 }
2804
2805 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2806 uint32_t ws, uint32_t wt)
2807 {
2808 wr_t wx, *pwx = &wx;
2809 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2810 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2811 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2812 uint32_t i;
2813
2814 clear_msacsr_cause(env);
2815
2816 switch (df) {
2817 case DF_WORD:
2818 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2819 FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32);
2820 }
2821 break;
2822 case DF_DOUBLE:
2823 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2824 FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64);
2825 }
2826 break;
2827 default:
2828 assert(0);
2829 }
2830
2831 check_msacsr_cause(env);
2832
2833 msa_move_v(pwd, pwx);
2834 }
2835
2836 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2837 uint32_t ws, uint32_t wt)
2838 {
2839 wr_t wx, *pwx = &wx;
2840 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2841 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2842 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2843 uint32_t i;
2844
2845 clear_msacsr_cause(env);
2846
2847 switch (df) {
2848 case DF_WORD:
2849 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2850 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
2851 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
2852 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
2853 MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
2854 } else {
2855 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
2856 }
2857 }
2858 break;
2859 case DF_DOUBLE:
2860 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2861 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
2862 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
2863 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
2864 MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
2865 } else {
2866 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
2867 }
2868 }
2869 break;
2870 default:
2871 assert(0);
2872 }
2873
2874 check_msacsr_cause(env);
2875
2876 msa_move_v(pwd, pwx);
2877 }
2878
2879 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2880 uint32_t ws, uint32_t wt)
2881 {
2882 wr_t wx, *pwx = &wx;
2883 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2884 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2885 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2886 uint32_t i;
2887
2888 clear_msacsr_cause(env);
2889
2890 switch (df) {
2891 case DF_WORD:
2892 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2893 FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32);
2894 }
2895 break;
2896 case DF_DOUBLE:
2897 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2898 FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64);
2899 }
2900 break;
2901 default:
2902 assert(0);
2903 }
2904
2905 check_msacsr_cause(env);
2906
2907 msa_move_v(pwd, pwx);
2908 }
2909
2910 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
2911 uint32_t wd, uint32_t ws)
2912 {
2913 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2914 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2915 if (df == DF_WORD) {
2916 pwd->w[0] = helper_float_class_s(pws->w[0]);
2917 pwd->w[1] = helper_float_class_s(pws->w[1]);
2918 pwd->w[2] = helper_float_class_s(pws->w[2]);
2919 pwd->w[3] = helper_float_class_s(pws->w[3]);
2920 } else {
2921 pwd->d[0] = helper_float_class_d(pws->d[0]);
2922 pwd->d[1] = helper_float_class_d(pws->d[1]);
2923 }
2924 }
2925
2926 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2927 do { \
2928 float_status *status = &env->active_tc.msa_fp_status; \
2929 int c; \
2930 \
2931 set_float_exception_flags(0, status); \
2932 DEST = float ## BITS ## _ ## OP(ARG, status); \
2933 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2934 \
2935 if (get_enabled_exceptions(env, c)) { \
2936 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2937 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2938 DEST = 0; \
2939 } \
2940 } while (0)
2941
2942 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2943 uint32_t ws)
2944 {
2945 wr_t wx, *pwx = &wx;
2946 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2947 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2948 uint32_t i;
2949
2950 clear_msacsr_cause(env);
2951
2952 switch (df) {
2953 case DF_WORD:
2954 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2955 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
2956 }
2957 break;
2958 case DF_DOUBLE:
2959 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2960 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
2961 }
2962 break;
2963 default:
2964 assert(0);
2965 }
2966
2967 check_msacsr_cause(env);
2968
2969 msa_move_v(pwd, pwx);
2970 }
2971
2972 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2973 uint32_t ws)
2974 {
2975 wr_t wx, *pwx = &wx;
2976 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2977 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2978 uint32_t i;
2979
2980 clear_msacsr_cause(env);
2981
2982 switch (df) {
2983 case DF_WORD:
2984 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2985 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
2986 }
2987 break;
2988 case DF_DOUBLE:
2989 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2990 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
2991 }
2992 break;
2993 default:
2994 assert(0);
2995 }
2996
2997 check_msacsr_cause(env);
2998
2999 msa_move_v(pwd, pwx);
3000 }
3001
3002 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3003 uint32_t ws)
3004 {
3005 wr_t wx, *pwx = &wx;
3006 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3007 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3008 uint32_t i;
3009
3010 clear_msacsr_cause(env);
3011
3012 switch (df) {
3013 case DF_WORD:
3014 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3015 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
3016 }
3017 break;
3018 case DF_DOUBLE:
3019 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3020 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
3021 }
3022 break;
3023 default:
3024 assert(0);
3025 }
3026
3027 check_msacsr_cause(env);
3028
3029 msa_move_v(pwd, pwx);
3030 }
3031
3032 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3033 do { \
3034 float_status *status = &env->active_tc.msa_fp_status; \
3035 int c; \
3036 \
3037 set_float_exception_flags(0, status); \
3038 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3039 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3040 float ## BITS ## _is_quiet_nan(DEST) ? \
3041 0 : RECIPROCAL_INEXACT, \
3042 IS_DENORMAL(DEST, BITS)); \
3043 \
3044 if (get_enabled_exceptions(env, c)) { \
3045 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
3046 } \
3047 } while (0)
3048
3049 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3050 uint32_t ws)
3051 {
3052 wr_t wx, *pwx = &wx;
3053 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3054 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3055 uint32_t i;
3056
3057 clear_msacsr_cause(env);
3058
3059 switch (df) {
3060 case DF_WORD:
3061 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3062 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
3063 &env->active_tc.msa_fp_status), 32);
3064 }
3065 break;
3066 case DF_DOUBLE:
3067 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3068 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
3069 &env->active_tc.msa_fp_status), 64);
3070 }
3071 break;
3072 default:
3073 assert(0);
3074 }
3075
3076 check_msacsr_cause(env);
3077
3078 msa_move_v(pwd, pwx);
3079 }
3080
3081 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3082 uint32_t ws)
3083 {
3084 wr_t wx, *pwx = &wx;
3085 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3086 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3087 uint32_t i;
3088
3089 clear_msacsr_cause(env);
3090
3091 switch (df) {
3092 case DF_WORD:
3093 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3094 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
3095 }
3096 break;
3097 case DF_DOUBLE:
3098 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3099 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
3100 }
3101 break;
3102 default:
3103 assert(0);
3104 }
3105
3106 check_msacsr_cause(env);
3107
3108 msa_move_v(pwd, pwx);
3109 }
3110
3111 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3112 uint32_t ws)
3113 {
3114 wr_t wx, *pwx = &wx;
3115 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3116 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3117 uint32_t i;
3118
3119 clear_msacsr_cause(env);
3120
3121 switch (df) {
3122 case DF_WORD:
3123 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3124 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
3125 }
3126 break;
3127 case DF_DOUBLE:
3128 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3129 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
3130 }
3131 break;
3132 default:
3133 assert(0);
3134 }
3135
3136 check_msacsr_cause(env);
3137
3138 msa_move_v(pwd, pwx);
3139 }
3140
3141 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3142 do { \
3143 float_status *status = &env->active_tc.msa_fp_status; \
3144 int c; \
3145 \
3146 set_float_exception_flags(0, status); \
3147 set_float_rounding_mode(float_round_down, status); \
3148 DEST = float ## BITS ## _ ## log2(ARG, status); \
3149 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3150 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3151 MSACSR_RM_MASK) >> MSACSR_RM], \
3152 status); \
3153 \
3154 set_float_exception_flags(get_float_exception_flags(status) & \
3155 (~float_flag_inexact), \
3156 status); \
3157 \
3158 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3159 \
3160 if (get_enabled_exceptions(env, c)) { \
3161 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
3162 } \
3163 } while (0)
3164
3165 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3166 uint32_t ws)
3167 {
3168 wr_t wx, *pwx = &wx;
3169 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3170 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3171 uint32_t i;
3172
3173 clear_msacsr_cause(env);
3174
3175 switch (df) {
3176 case DF_WORD:
3177 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3178 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
3179 }
3180 break;
3181 case DF_DOUBLE:
3182 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3183 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
3184 }
3185 break;
3186 default:
3187 assert(0);
3188 }
3189
3190 check_msacsr_cause(env);
3191
3192 msa_move_v(pwd, pwx);
3193 }
3194
3195 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3196 uint32_t ws)
3197 {
3198 wr_t wx, *pwx = &wx;
3199 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3200 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3201 uint32_t i;
3202
3203 switch (df) {
3204 case DF_WORD:
3205 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3206 /* Half precision floats come in two formats: standard
3207 IEEE and "ARM" format. The latter gains extra exponent
3208 range by omitting the NaN/Inf encodings. */
3209 flag ieee = 1;
3210
3211 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
3212 }
3213 break;
3214 case DF_DOUBLE:
3215 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3216 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
3217 }
3218 break;
3219 default:
3220 assert(0);
3221 }
3222
3223 check_msacsr_cause(env);
3224 msa_move_v(pwd, pwx);
3225 }
3226
3227 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3228 uint32_t ws)
3229 {
3230 wr_t wx, *pwx = &wx;
3231 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3232 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3233 uint32_t i;
3234
3235 switch (df) {
3236 case DF_WORD:
3237 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3238 /* Half precision floats come in two formats: standard
3239 IEEE and "ARM" format. The latter gains extra exponent
3240 range by omitting the NaN/Inf encodings. */
3241 flag ieee = 1;
3242
3243 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
3244 }
3245 break;
3246 case DF_DOUBLE:
3247 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3248 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
3249 }
3250 break;
3251 default:
3252 assert(0);
3253 }
3254
3255 check_msacsr_cause(env);
3256 msa_move_v(pwd, pwx);
3257 }
3258
3259 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3260 uint32_t ws)
3261 {
3262 wr_t wx, *pwx = &wx;
3263 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3264 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3265 uint32_t i;
3266
3267 switch (df) {
3268 case DF_WORD:
3269 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3270 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
3271 }
3272 break;
3273 case DF_DOUBLE:
3274 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3275 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
3276 }
3277 break;
3278 default:
3279 assert(0);
3280 }
3281
3282 msa_move_v(pwd, pwx);
3283 }
3284
3285 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3286 uint32_t ws)
3287 {
3288 wr_t wx, *pwx = &wx;
3289 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3290 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3291 uint32_t i;
3292
3293 switch (df) {
3294 case DF_WORD:
3295 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3296 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
3297 }
3298 break;
3299 case DF_DOUBLE:
3300 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3301 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
3302 }
3303 break;
3304 default:
3305 assert(0);
3306 }
3307
3308 msa_move_v(pwd, pwx);
3309 }
3310
3311 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3312 uint32_t ws)
3313 {
3314 wr_t wx, *pwx = &wx;
3315 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3316 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3317 uint32_t i;
3318
3319 clear_msacsr_cause(env);
3320
3321 switch (df) {
3322 case DF_WORD:
3323 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3324 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
3325 }
3326 break;
3327 case DF_DOUBLE:
3328 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3329 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
3330 }
3331 break;
3332 default:
3333 assert(0);
3334 }
3335
3336 check_msacsr_cause(env);
3337
3338 msa_move_v(pwd, pwx);
3339 }
3340
3341 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3342 uint32_t ws)
3343 {
3344 wr_t wx, *pwx = &wx;
3345 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3346 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3347 uint32_t i;
3348
3349 clear_msacsr_cause(env);
3350
3351 switch (df) {
3352 case DF_WORD:
3353 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3354 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
3355 }
3356 break;
3357 case DF_DOUBLE:
3358 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3359 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
3360 }
3361 break;
3362 default:
3363 assert(0);
3364 }
3365
3366 check_msacsr_cause(env);
3367
3368 msa_move_v(pwd, pwx);
3369 }
3370
3371 #define float32_from_int32 int32_to_float32
3372 #define float32_from_uint32 uint32_to_float32
3373
3374 #define float64_from_int64 int64_to_float64
3375 #define float64_from_uint64 uint64_to_float64
3376
3377 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3378 uint32_t ws)
3379 {
3380 wr_t wx, *pwx = &wx;
3381 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3382 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3383 uint32_t i;
3384
3385 clear_msacsr_cause(env);
3386
3387 switch (df) {
3388 case DF_WORD:
3389 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3390 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
3391 }
3392 break;
3393 case DF_DOUBLE:
3394 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3395 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
3396 }
3397 break;
3398 default:
3399 assert(0);
3400 }
3401
3402 check_msacsr_cause(env);
3403
3404 msa_move_v(pwd, pwx);
3405 }
3406
3407 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3408 uint32_t ws)
3409 {
3410 wr_t wx, *pwx = &wx;
3411 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3412 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3413 uint32_t i;
3414
3415 clear_msacsr_cause(env);
3416
3417 switch (df) {
3418 case DF_WORD:
3419 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3420 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
3421 }
3422 break;
3423 case DF_DOUBLE:
3424 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3425 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
3426 }
3427 break;
3428 default:
3429 assert(0);
3430 }
3431
3432 check_msacsr_cause(env);
3433
3434 msa_move_v(pwd, pwx);
3435 }
AR7 emulation for QEMU