vl: fix max_cpus check
[qemu/ar7.git] / hw / pci-host / piix.c
blob1530038cb075ca35e2d8105ed484d9d5956e2294
1 /*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "hw/hw.h"
26 #include "hw/i386/pc.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "hw/isa/isa.h"
30 #include "hw/sysbus.h"
31 #include "qemu/range.h"
32 #include "hw/xen/xen.h"
33 #include "hw/pci-host/pam.h"
34 #include "sysemu/sysemu.h"
35 #include "hw/i386/ioapic.h"
36 #include "qapi/visitor.h"
39 * I440FX chipset data sheet.
40 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
43 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
44 #define I440FX_PCI_HOST_BRIDGE(obj) \
45 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
47 typedef struct I440FXState {
48 PCIHostState parent_obj;
49 PcPciInfo pci_info;
50 uint64_t pci_hole64_size;
51 uint32_t short_root_bus;
52 } I440FXState;
54 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
55 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
56 #define XEN_PIIX_NUM_PIRQS 128ULL
57 #define PIIX_PIRQC 0x60
60 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
61 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
63 #define RCR_IOPORT 0xcf9
65 typedef struct PIIX3State {
66 PCIDevice dev;
69 * bitmap to track pic levels.
70 * The pic level is the logical OR of all the PCI irqs mapped to it
71 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
73 * PIRQ is mapped to PIC pins, we track it by
74 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
75 * pic_irq * PIIX_NUM_PIRQS + pirq
77 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
78 #error "unable to encode pic state in 64bit in pic_levels."
79 #endif
80 uint64_t pic_levels;
82 qemu_irq *pic;
84 /* This member isn't used. Just for save/load compatibility */
85 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
87 /* Reset Control Register contents */
88 uint8_t rcr;
90 /* IO memory region for Reset Control Register (RCR_IOPORT) */
91 MemoryRegion rcr_mem;
92 } PIIX3State;
94 #define TYPE_I440FX_PCI_DEVICE "i440FX"
95 #define I440FX_PCI_DEVICE(obj) \
96 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
98 struct PCII440FXState {
99 /*< private >*/
100 PCIDevice parent_obj;
101 /*< public >*/
103 MemoryRegion *system_memory;
104 MemoryRegion *pci_address_space;
105 MemoryRegion *ram_memory;
106 PAMMemoryRegion pam_regions[13];
107 MemoryRegion smram_region;
108 uint8_t smm_enabled;
112 #define I440FX_PAM 0x59
113 #define I440FX_PAM_SIZE 7
114 #define I440FX_SMRAM 0x72
116 static void piix3_set_irq(void *opaque, int pirq, int level);
117 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
118 static void piix3_write_config_xen(PCIDevice *dev,
119 uint32_t address, uint32_t val, int len);
121 /* return the global irq number corresponding to a given device irq
122 pin. We could also use the bus number to have a more precise
123 mapping. */
124 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
126 int slot_addend;
127 slot_addend = (pci_dev->devfn >> 3) - 1;
128 return (pci_intx + slot_addend) & 3;
131 static void i440fx_update_memory_mappings(PCII440FXState *d)
133 int i;
134 PCIDevice *pd = PCI_DEVICE(d);
136 memory_region_transaction_begin();
137 for (i = 0; i < 13; i++) {
138 pam_update(&d->pam_regions[i], i,
139 pd->config[I440FX_PAM + ((i + 1) / 2)]);
141 smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled);
142 memory_region_transaction_commit();
145 static void i440fx_set_smm(int val, void *arg)
147 PCII440FXState *d = arg;
148 PCIDevice *pd = PCI_DEVICE(d);
150 memory_region_transaction_begin();
151 smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM],
152 &d->smram_region);
153 memory_region_transaction_commit();
157 static void i440fx_write_config(PCIDevice *dev,
158 uint32_t address, uint32_t val, int len)
160 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
162 /* XXX: implement SMRAM.D_LOCK */
163 pci_default_write_config(dev, address, val, len);
164 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
165 range_covers_byte(address, len, I440FX_SMRAM)) {
166 i440fx_update_memory_mappings(d);
170 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
172 PCII440FXState *d = opaque;
173 PCIDevice *pd = PCI_DEVICE(d);
174 int ret, i;
176 ret = pci_device_load(pd, f);
177 if (ret < 0)
178 return ret;
179 i440fx_update_memory_mappings(d);
180 qemu_get_8s(f, &d->smm_enabled);
182 if (version_id == 2) {
183 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
184 qemu_get_be32(f); /* dummy load for compatibility */
188 return 0;
191 static int i440fx_post_load(void *opaque, int version_id)
193 PCII440FXState *d = opaque;
195 i440fx_update_memory_mappings(d);
196 return 0;
199 static const VMStateDescription vmstate_i440fx = {
200 .name = "I440FX",
201 .version_id = 3,
202 .minimum_version_id = 3,
203 .minimum_version_id_old = 1,
204 .load_state_old = i440fx_load_old,
205 .post_load = i440fx_post_load,
206 .fields = (VMStateField[]) {
207 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
208 VMSTATE_UINT8(smm_enabled, PCII440FXState),
209 VMSTATE_END_OF_LIST()
213 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
214 void *opaque, const char *name,
215 Error **errp)
217 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
218 uint32_t value = s->pci_info.w32.begin;
220 visit_type_uint32(v, &value, name, errp);
223 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
224 void *opaque, const char *name,
225 Error **errp)
227 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
228 uint32_t value = s->pci_info.w32.end;
230 visit_type_uint32(v, &value, name, errp);
233 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
234 void *opaque, const char *name,
235 Error **errp)
237 PCIHostState *h = PCI_HOST_BRIDGE(obj);
238 Range w64;
240 pci_bus_get_w64_range(h->bus, &w64);
242 visit_type_uint64(v, &w64.begin, name, errp);
245 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
246 void *opaque, const char *name,
247 Error **errp)
249 PCIHostState *h = PCI_HOST_BRIDGE(obj);
250 Range w64;
252 pci_bus_get_w64_range(h->bus, &w64);
254 visit_type_uint64(v, &w64.end, name, errp);
257 static void i440fx_pcihost_initfn(Object *obj)
259 PCIHostState *s = PCI_HOST_BRIDGE(obj);
260 I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
262 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
263 "pci-conf-idx", 4);
264 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
265 "pci-conf-data", 4);
267 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
268 i440fx_pcihost_get_pci_hole_start,
269 NULL, NULL, NULL, NULL);
271 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
272 i440fx_pcihost_get_pci_hole_end,
273 NULL, NULL, NULL, NULL);
275 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
276 i440fx_pcihost_get_pci_hole64_start,
277 NULL, NULL, NULL, NULL);
279 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
280 i440fx_pcihost_get_pci_hole64_end,
281 NULL, NULL, NULL, NULL);
283 d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
286 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
288 PCIHostState *s = PCI_HOST_BRIDGE(dev);
289 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
291 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
292 sysbus_init_ioports(sbd, 0xcf8, 4);
294 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
295 sysbus_init_ioports(sbd, 0xcfc, 4);
298 static int i440fx_initfn(PCIDevice *dev)
300 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
302 dev->config[I440FX_SMRAM] = 0x02;
304 cpu_smm_register(&i440fx_set_smm, d);
305 return 0;
308 PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
309 int *piix3_devfn,
310 ISABus **isa_bus, qemu_irq *pic,
311 MemoryRegion *address_space_mem,
312 MemoryRegion *address_space_io,
313 ram_addr_t ram_size,
314 ram_addr_t below_4g_mem_size,
315 ram_addr_t above_4g_mem_size,
316 MemoryRegion *pci_address_space,
317 MemoryRegion *ram_memory)
319 DeviceState *dev;
320 PCIBus *b;
321 PCIDevice *d;
322 PCIHostState *s;
323 PIIX3State *piix3;
324 PCII440FXState *f;
325 unsigned i;
326 I440FXState *i440fx;
328 dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
329 s = PCI_HOST_BRIDGE(dev);
330 b = pci_bus_new(dev, NULL, pci_address_space,
331 address_space_io, 0, TYPE_PCI_BUS);
332 s->bus = b;
333 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
334 qdev_init_nofail(dev);
336 d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
337 *pi440fx_state = I440FX_PCI_DEVICE(d);
338 f = *pi440fx_state;
339 f->system_memory = address_space_mem;
340 f->pci_address_space = pci_address_space;
341 f->ram_memory = ram_memory;
343 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
344 i440fx->pci_info.w32.begin = below_4g_mem_size;
346 /* setup pci memory mapping */
347 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
348 f->pci_address_space);
350 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
351 f->pci_address_space, 0xa0000, 0x20000);
352 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
353 &f->smram_region, 1);
354 memory_region_set_enabled(&f->smram_region, false);
355 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
356 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
357 for (i = 0; i < 12; ++i) {
358 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
359 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
360 PAM_EXPAN_SIZE);
363 /* Xen supports additional interrupt routes from the PCI devices to
364 * the IOAPIC: the four pins of each PCI device on the bus are also
365 * connected to the IOAPIC directly.
366 * These additional routes can be discovered through ACPI. */
367 if (xen_enabled()) {
368 piix3 = DO_UPCAST(PIIX3State, dev,
369 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
370 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
371 piix3, XEN_PIIX_NUM_PIRQS);
372 } else {
373 piix3 = DO_UPCAST(PIIX3State, dev,
374 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
375 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
376 PIIX_NUM_PIRQS);
377 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
379 piix3->pic = pic;
380 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
382 *piix3_devfn = piix3->dev.devfn;
384 ram_size = ram_size / 8 / 1024 / 1024;
385 if (ram_size > 255) {
386 ram_size = 255;
388 d->config[0x57] = ram_size;
390 i440fx_update_memory_mappings(f);
392 return b;
395 PCIBus *find_i440fx(void)
397 PCIHostState *s = OBJECT_CHECK(PCIHostState,
398 object_resolve_path("/machine/i440fx", NULL),
399 TYPE_PCI_HOST_BRIDGE);
400 return s ? s->bus : NULL;
403 /* PIIX3 PCI to ISA bridge */
404 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
406 qemu_set_irq(piix3->pic[pic_irq],
407 !!(piix3->pic_levels &
408 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
409 (pic_irq * PIIX_NUM_PIRQS))));
412 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
414 int pic_irq;
415 uint64_t mask;
417 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
418 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
419 return;
422 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
423 piix3->pic_levels &= ~mask;
424 piix3->pic_levels |= mask * !!level;
427 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
429 int pic_irq;
431 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
432 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
433 return;
436 piix3_set_irq_level_internal(piix3, pirq, level);
438 piix3_set_irq_pic(piix3, pic_irq);
441 static void piix3_set_irq(void *opaque, int pirq, int level)
443 PIIX3State *piix3 = opaque;
444 piix3_set_irq_level(piix3, pirq, level);
447 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
449 PIIX3State *piix3 = opaque;
450 int irq = piix3->dev.config[PIIX_PIRQC + pin];
451 PCIINTxRoute route;
453 if (irq < PIIX_NUM_PIC_IRQS) {
454 route.mode = PCI_INTX_ENABLED;
455 route.irq = irq;
456 } else {
457 route.mode = PCI_INTX_DISABLED;
458 route.irq = -1;
460 return route;
463 /* irq routing is changed. so rebuild bitmap */
464 static void piix3_update_irq_levels(PIIX3State *piix3)
466 int pirq;
468 piix3->pic_levels = 0;
469 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
470 piix3_set_irq_level(piix3, pirq,
471 pci_bus_get_irq_level(piix3->dev.bus, pirq));
475 static void piix3_write_config(PCIDevice *dev,
476 uint32_t address, uint32_t val, int len)
478 pci_default_write_config(dev, address, val, len);
479 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
480 PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
481 int pic_irq;
483 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
484 piix3_update_irq_levels(piix3);
485 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
486 piix3_set_irq_pic(piix3, pic_irq);
491 static void piix3_write_config_xen(PCIDevice *dev,
492 uint32_t address, uint32_t val, int len)
494 xen_piix_pci_write_config_client(address, val, len);
495 piix3_write_config(dev, address, val, len);
498 static void piix3_reset(void *opaque)
500 PIIX3State *d = opaque;
501 uint8_t *pci_conf = d->dev.config;
503 pci_conf[0x04] = 0x07; /* master, memory and I/O */
504 pci_conf[0x05] = 0x00;
505 pci_conf[0x06] = 0x00;
506 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
507 pci_conf[0x4c] = 0x4d;
508 pci_conf[0x4e] = 0x03;
509 pci_conf[0x4f] = 0x00;
510 pci_conf[0x60] = 0x80;
511 pci_conf[0x61] = 0x80;
512 pci_conf[0x62] = 0x80;
513 pci_conf[0x63] = 0x80;
514 pci_conf[0x69] = 0x02;
515 pci_conf[0x70] = 0x80;
516 pci_conf[0x76] = 0x0c;
517 pci_conf[0x77] = 0x0c;
518 pci_conf[0x78] = 0x02;
519 pci_conf[0x79] = 0x00;
520 pci_conf[0x80] = 0x00;
521 pci_conf[0x82] = 0x00;
522 pci_conf[0xa0] = 0x08;
523 pci_conf[0xa2] = 0x00;
524 pci_conf[0xa3] = 0x00;
525 pci_conf[0xa4] = 0x00;
526 pci_conf[0xa5] = 0x00;
527 pci_conf[0xa6] = 0x00;
528 pci_conf[0xa7] = 0x00;
529 pci_conf[0xa8] = 0x0f;
530 pci_conf[0xaa] = 0x00;
531 pci_conf[0xab] = 0x00;
532 pci_conf[0xac] = 0x00;
533 pci_conf[0xae] = 0x00;
535 d->pic_levels = 0;
536 d->rcr = 0;
539 static int piix3_post_load(void *opaque, int version_id)
541 PIIX3State *piix3 = opaque;
542 int pirq;
544 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
545 * might bring the system to a different state than the saved one;
546 * for example, the interrupt could be masked but the i8259 would
547 * not know that yet and would trigger an interrupt in the CPU.
549 * Here, we update irq levels without raising the interrupt.
550 * Interrupt state will be deserialized separately through the i8259.
552 piix3->pic_levels = 0;
553 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
554 piix3_set_irq_level_internal(piix3, pirq,
555 pci_bus_get_irq_level(piix3->dev.bus, pirq));
557 return 0;
560 static void piix3_pre_save(void *opaque)
562 int i;
563 PIIX3State *piix3 = opaque;
565 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
566 piix3->pci_irq_levels_vmstate[i] =
567 pci_bus_get_irq_level(piix3->dev.bus, i);
571 static bool piix3_rcr_needed(void *opaque)
573 PIIX3State *piix3 = opaque;
575 return (piix3->rcr != 0);
578 static const VMStateDescription vmstate_piix3_rcr = {
579 .name = "PIIX3/rcr",
580 .version_id = 1,
581 .minimum_version_id = 1,
582 .fields = (VMStateField[]) {
583 VMSTATE_UINT8(rcr, PIIX3State),
584 VMSTATE_END_OF_LIST()
588 static const VMStateDescription vmstate_piix3 = {
589 .name = "PIIX3",
590 .version_id = 3,
591 .minimum_version_id = 2,
592 .post_load = piix3_post_load,
593 .pre_save = piix3_pre_save,
594 .fields = (VMStateField[]) {
595 VMSTATE_PCI_DEVICE(dev, PIIX3State),
596 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
597 PIIX_NUM_PIRQS, 3),
598 VMSTATE_END_OF_LIST()
600 .subsections = (VMStateSubsection[]) {
602 .vmsd = &vmstate_piix3_rcr,
603 .needed = piix3_rcr_needed,
605 { 0 }
610 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
612 PIIX3State *d = opaque;
614 if (val & 4) {
615 qemu_system_reset_request();
616 return;
618 d->rcr = val & 2; /* keep System Reset type only */
621 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
623 PIIX3State *d = opaque;
625 return d->rcr;
628 static const MemoryRegionOps rcr_ops = {
629 .read = rcr_read,
630 .write = rcr_write,
631 .endianness = DEVICE_LITTLE_ENDIAN
634 static int piix3_initfn(PCIDevice *dev)
636 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
638 isa_bus_new(DEVICE(d), pci_address_space_io(dev));
640 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
641 "piix3-reset-control", 1);
642 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
643 &d->rcr_mem, 1);
645 qemu_register_reset(piix3_reset, d);
646 return 0;
649 static void piix3_class_init(ObjectClass *klass, void *data)
651 DeviceClass *dc = DEVICE_CLASS(klass);
652 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
654 dc->desc = "ISA bridge";
655 dc->vmsd = &vmstate_piix3;
656 dc->hotpluggable = false;
657 k->init = piix3_initfn;
658 k->config_write = piix3_write_config;
659 k->vendor_id = PCI_VENDOR_ID_INTEL;
660 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
661 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
662 k->class_id = PCI_CLASS_BRIDGE_ISA;
664 * Reason: part of PIIX3 southbridge, needs to be wired up by
665 * pc_piix.c's pc_init1()
667 dc->cannot_instantiate_with_device_add_yet = true;
670 static const TypeInfo piix3_info = {
671 .name = "PIIX3",
672 .parent = TYPE_PCI_DEVICE,
673 .instance_size = sizeof(PIIX3State),
674 .class_init = piix3_class_init,
677 static void piix3_xen_class_init(ObjectClass *klass, void *data)
679 DeviceClass *dc = DEVICE_CLASS(klass);
680 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
682 dc->desc = "ISA bridge";
683 dc->vmsd = &vmstate_piix3;
684 dc->hotpluggable = false;
685 k->init = piix3_initfn;
686 k->config_write = piix3_write_config_xen;
687 k->vendor_id = PCI_VENDOR_ID_INTEL;
688 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
689 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
690 k->class_id = PCI_CLASS_BRIDGE_ISA;
692 * Reason: part of PIIX3 southbridge, needs to be wired up by
693 * pc_piix.c's pc_init1()
695 dc->cannot_instantiate_with_device_add_yet = true;
698 static const TypeInfo piix3_xen_info = {
699 .name = "PIIX3-xen",
700 .parent = TYPE_PCI_DEVICE,
701 .instance_size = sizeof(PIIX3State),
702 .class_init = piix3_xen_class_init,
705 static void i440fx_class_init(ObjectClass *klass, void *data)
707 DeviceClass *dc = DEVICE_CLASS(klass);
708 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
710 k->init = i440fx_initfn;
711 k->config_write = i440fx_write_config;
712 k->vendor_id = PCI_VENDOR_ID_INTEL;
713 k->device_id = PCI_DEVICE_ID_INTEL_82441;
714 k->revision = 0x02;
715 k->class_id = PCI_CLASS_BRIDGE_HOST;
716 dc->desc = "Host bridge";
717 dc->vmsd = &vmstate_i440fx;
719 * PCI-facing part of the host bridge, not usable without the
720 * host-facing part, which can't be device_add'ed, yet.
722 dc->cannot_instantiate_with_device_add_yet = true;
723 dc->hotpluggable = false;
726 static const TypeInfo i440fx_info = {
727 .name = TYPE_I440FX_PCI_DEVICE,
728 .parent = TYPE_PCI_DEVICE,
729 .instance_size = sizeof(PCII440FXState),
730 .class_init = i440fx_class_init,
733 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
734 PCIBus *rootbus)
736 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
738 /* For backwards compat with old device paths */
739 if (s->short_root_bus) {
740 return "0000";
742 return "0000:00";
745 static Property i440fx_props[] = {
746 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
747 pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
748 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
749 DEFINE_PROP_END_OF_LIST(),
752 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
754 DeviceClass *dc = DEVICE_CLASS(klass);
755 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
757 hc->root_bus_path = i440fx_pcihost_root_bus_path;
758 dc->realize = i440fx_pcihost_realize;
759 dc->fw_name = "pci";
760 dc->props = i440fx_props;
763 static const TypeInfo i440fx_pcihost_info = {
764 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
765 .parent = TYPE_PCI_HOST_BRIDGE,
766 .instance_size = sizeof(I440FXState),
767 .instance_init = i440fx_pcihost_initfn,
768 .class_init = i440fx_pcihost_class_init,
771 static void i440fx_register_types(void)
773 type_register_static(&i440fx_info);
774 type_register_static(&piix3_info);
775 type_register_static(&piix3_xen_info);
776 type_register_static(&i440fx_pcihost_info);
779 type_init(i440fx_register_types)