hw/char/milkymist-uart.c

   1 /*
   2  *  QEMU model of the Milkymist UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.milkymist.org/socdoc/uart.pdf
  22  */
  23
  24 #include "hw/hw.h"
  25 #include "hw/sysbus.h"
  26 #include "trace.h"
  27 #include "sysemu/char.h"
  28 #include "qemu/error-report.h"
  29
  30 enum {
  31     R_RXTX = 0,
  32     R_DIV,
  33     R_STAT,
  34     R_CTRL,
  35     R_DBG,
  36     R_MAX
  37 };
  38
  39 enum {
  40     STAT_THRE   = (1<<0),
  41     STAT_RX_EVT = (1<<1),
  42     STAT_TX_EVT = (1<<2),
  43 };
  44
  45 enum {
  46     CTRL_RX_IRQ_EN = (1<<0),
  47     CTRL_TX_IRQ_EN = (1<<1),
  48     CTRL_THRU_EN   = (1<<2),
  49 };
  50
  51 enum {
  52     DBG_BREAK_EN = (1<<0),
  53 };
  54
  55 #define TYPE_MILKYMIST_UART "milkymist-uart"
  56 #define MILKYMIST_UART(obj) \
  57     OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART)
  58
  59 struct MilkymistUartState {
  60     SysBusDevice parent_obj;
  61
  62     MemoryRegion regs_region;
  63     CharDriverState *chr;
  64     qemu_irq irq;
  65
  66     uint32_t regs[R_MAX];
  67 };
  68 typedef struct MilkymistUartState MilkymistUartState;
  69
  70 static void uart_update_irq(MilkymistUartState *s)
  71 {
  72     int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
  73     int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
  74     int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
  75     int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
  76
  77     if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
  78         trace_milkymist_uart_raise_irq();
  79         qemu_irq_raise(s->irq);
  80     } else {
  81         trace_milkymist_uart_lower_irq();
  82         qemu_irq_lower(s->irq);
  83     }
  84 }
  85
  86 static uint64_t uart_read(void *opaque, hwaddr addr,
  87                           unsigned size)
  88 {
  89     MilkymistUartState *s = opaque;
  90     uint32_t r = 0;
  91
  92     addr >>= 2;
  93     switch (addr) {
  94     case R_RXTX:
  95         r = s->regs[addr];
  96         break;
  97     case R_DIV:
  98     case R_STAT:
  99     case R_CTRL:
 100     case R_DBG:
 101         r = s->regs[addr];
 102         break;
 103
 104     default:
 105         error_report("milkymist_uart: read access to unknown register 0x"
 106                 TARGET_FMT_plx, addr << 2);
 107         break;
 108     }
 109
 110     trace_milkymist_uart_memory_read(addr << 2, r);
 111
 112     return r;
 113 }
 114
 115 static void uart_write(void *opaque, hwaddr addr, uint64_t value,
 116                        unsigned size)
 117 {
 118     MilkymistUartState *s = opaque;
 119     unsigned char ch = value;
 120
 121     trace_milkymist_uart_memory_write(addr, value);
 122
 123     addr >>= 2;
 124     switch (addr) {
 125     case R_RXTX:
 126         if (s->chr) {
 127             qemu_chr_fe_write_all(s->chr, &ch, 1);
 128         }
 129         s->regs[R_STAT] |= STAT_TX_EVT;
 130         break;
 131     case R_DIV:
 132     case R_CTRL:
 133     case R_DBG:
 134         s->regs[addr] = value;
 135         break;
 136
 137     case R_STAT:
 138         /* write one to clear bits */
 139         s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
 140         qemu_chr_accept_input(s->chr);
 141         break;
 142
 143     default:
 144         error_report("milkymist_uart: write access to unknown register 0x"
 145                 TARGET_FMT_plx, addr << 2);
 146         break;
 147     }
 148
 149     uart_update_irq(s);
 150 }
 151
 152 static const MemoryRegionOps uart_mmio_ops = {
 153     .read = uart_read,
 154     .write = uart_write,
 155     .valid = {
 156         .min_access_size = 4,
 157         .max_access_size = 4,
 158     },
 159     .endianness = DEVICE_NATIVE_ENDIAN,
 160 };
 161
 162 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 163 {
 164     MilkymistUartState *s = opaque;
 165
 166     assert(!(s->regs[R_STAT] & STAT_RX_EVT));
 167
 168     s->regs[R_STAT] |= STAT_RX_EVT;
 169     s->regs[R_RXTX] = *buf;
 170
 171     uart_update_irq(s);
 172 }
 173
 174 static int uart_can_rx(void *opaque)
 175 {
 176     MilkymistUartState *s = opaque;
 177
 178     return !(s->regs[R_STAT] & STAT_RX_EVT);
 179 }
 180
 181 static void uart_event(void *opaque, int event)
 182 {
 183 }
 184
 185 static void milkymist_uart_reset(DeviceState *d)
 186 {
 187     MilkymistUartState *s = MILKYMIST_UART(d);
 188     int i;
 189
 190     for (i = 0; i < R_MAX; i++) {
 191         s->regs[i] = 0;
 192     }
 193
 194     /* THRE is always set */
 195     s->regs[R_STAT] = STAT_THRE;
 196 }
 197
 198 static void milkymist_uart_realize(DeviceState *dev, Error **errp)
 199 {
 200     MilkymistUartState *s = MILKYMIST_UART(dev);
 201
 202     s->chr = qemu_char_get_next_serial();
 203     if (s->chr) {
 204         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 205     }
 206 }
 207
 208 static void milkymist_uart_init(Object *obj)
 209 {
 210     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 211     MilkymistUartState *s = MILKYMIST_UART(obj);
 212
 213     sysbus_init_irq(sbd, &s->irq);
 214
 215     memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
 216                           "milkymist-uart", R_MAX * 4);
 217     sysbus_init_mmio(sbd, &s->regs_region);
 218 }
 219
 220 static const VMStateDescription vmstate_milkymist_uart = {
 221     .name = "milkymist-uart",
 222     .version_id = 1,
 223     .minimum_version_id = 1,
 224     .fields = (VMStateField[]) {
 225         VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
 226         VMSTATE_END_OF_LIST()
 227     }
 228 };
 229
 230 static void milkymist_uart_class_init(ObjectClass *klass, void *data)
 231 {
 232     DeviceClass *dc = DEVICE_CLASS(klass);
 233
 234     dc->realize = milkymist_uart_realize;
 235     dc->reset = milkymist_uart_reset;
 236     dc->vmsd = &vmstate_milkymist_uart;
 237 }
 238
 239 static const TypeInfo milkymist_uart_info = {
 240     .name          = TYPE_MILKYMIST_UART,
 241     .parent        = TYPE_SYS_BUS_DEVICE,
 242     .instance_size = sizeof(MilkymistUartState),
 243     .instance_init = milkymist_uart_init,
 244     .class_init    = milkymist_uart_class_init,
 245 };
 246
 247 static void milkymist_uart_register_types(void)
 248 {
 249     type_register_static(&milkymist_uart_info);
 250 }
 251
 252 type_init(milkymist_uart_register_types)