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vl: fix max_cpus check
[qemu/ar7.git] / hw / block / fdc.c
blob739a03ed5801fab0e5f8fc6049b605a7b6a07c81
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw/hw.h"
31 #include "hw/block/fdc.h"
32 #include "qemu/error-report.h"
33 #include "qemu/timer.h"
34 #include "hw/isa/isa.h"
35 #include "hw/sysbus.h"
36 #include "sysemu/block-backend.h"
37 #include "sysemu/blockdev.h"
38 #include "sysemu/sysemu.h"
39 #include "qemu/log.h"
40
41 /********************************************************/
42 /* debug Floppy devices */
43 //#define DEBUG_FLOPPY
44
45 #ifdef DEBUG_FLOPPY
46 #define FLOPPY_DPRINTF(fmt, ...) \
47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
48 #else
49 #define FLOPPY_DPRINTF(fmt, ...)
50 #endif
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 typedef enum FDriveRate {
56 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
57 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
58 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
59 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
60 } FDriveRate;
61
62 typedef struct FDFormat {
63 FDriveType drive;
64 uint8_t last_sect;
65 uint8_t max_track;
66 uint8_t max_head;
67 FDriveRate rate;
68 } FDFormat;
69
70 static const FDFormat fd_formats[] = {
71 /* First entry is default format */
72 /* 1.44 MB 3"1/2 floppy disks */
73 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, },
74 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, },
75 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, },
76 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, },
77 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, },
78 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, },
79 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, },
80 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, },
81 /* 2.88 MB 3"1/2 floppy disks */
82 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, },
83 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, },
84 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, },
85 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, },
86 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, },
87 /* 720 kB 3"1/2 floppy disks */
88 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, },
89 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, },
90 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, },
91 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, },
92 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, },
93 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, },
94 /* 1.2 MB 5"1/4 floppy disks */
95 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, },
96 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, },
97 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, },
98 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, },
99 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, },
100 /* 720 kB 5"1/4 floppy disks */
101 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, },
102 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, },
103 /* 360 kB 5"1/4 floppy disks */
104 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, },
105 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, },
106 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, },
107 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, },
108 /* 320 kB 5"1/4 floppy disks */
109 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, },
110 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, },
111 /* 360 kB must match 5"1/4 better than 3"1/2... */
112 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, },
113 /* end */
114 { FDRIVE_DRV_NONE, -1, -1, 0, 0, },
115 };
116
117 static void pick_geometry(BlockBackend *blk, int *nb_heads,
118 int *max_track, int *last_sect,
119 FDriveType drive_in, FDriveType *drive,
120 FDriveRate *rate)
121 {
122 const FDFormat *parse;
123 uint64_t nb_sectors, size;
124 int i, first_match, match;
125
126 blk_get_geometry(blk, &nb_sectors);
127 match = -1;
128 first_match = -1;
129 for (i = 0; ; i++) {
130 parse = &fd_formats[i];
131 if (parse->drive == FDRIVE_DRV_NONE) {
132 break;
133 }
134 if (drive_in == parse->drive ||
135 drive_in == FDRIVE_DRV_NONE) {
136 size = (parse->max_head + 1) * parse->max_track *
137 parse->last_sect;
138 if (nb_sectors == size) {
139 match = i;
140 break;
141 }
142 if (first_match == -1) {
143 first_match = i;
144 }
145 }
146 }
147 if (match == -1) {
148 if (first_match == -1) {
149 match = 1;
150 } else {
151 match = first_match;
152 }
153 parse = &fd_formats[match];
154 }
155 *nb_heads = parse->max_head + 1;
156 *max_track = parse->max_track;
157 *last_sect = parse->last_sect;
158 *drive = parse->drive;
159 *rate = parse->rate;
160 }
161
162 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
163 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
164
165 /* Will always be a fixed parameter for us */
166 #define FD_SECTOR_LEN 512
167 #define FD_SECTOR_SC 2 /* Sector size code */
168 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
169
170 typedef struct FDCtrl FDCtrl;
171
172 /* Floppy disk drive emulation */
173 typedef enum FDiskFlags {
174 FDISK_DBL_SIDES = 0x01,
175 } FDiskFlags;
176
177 typedef struct FDrive {
178 FDCtrl *fdctrl;
179 BlockBackend *blk;
180 /* Drive status */
181 FDriveType drive;
182 uint8_t perpendicular; /* 2.88 MB access mode */
183 /* Position */
184 uint8_t head;
185 uint8_t track;
186 uint8_t sect;
187 /* Media */
188 FDiskFlags flags;
189 uint8_t last_sect; /* Nb sector per track */
190 uint8_t max_track; /* Nb of tracks */
191 uint16_t bps; /* Bytes per sector */
192 uint8_t ro; /* Is read-only */
193 uint8_t media_changed; /* Is media changed */
194 uint8_t media_rate; /* Data rate of medium */
195 } FDrive;
196
197 static void fd_init(FDrive *drv)
198 {
199 /* Drive */
200 drv->drive = FDRIVE_DRV_NONE;
201 drv->perpendicular = 0;
202 /* Disk */
203 drv->last_sect = 0;
204 drv->max_track = 0;
205 }
206
207 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
208
209 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
210 uint8_t last_sect, uint8_t num_sides)
211 {
212 return (((track * num_sides) + head) * last_sect) + sect - 1;
213 }
214
215 /* Returns current position, in sectors, for given drive */
216 static int fd_sector(FDrive *drv)
217 {
218 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
219 NUM_SIDES(drv));
220 }
221
222 /* Seek to a new position:
223 * returns 0 if already on right track
224 * returns 1 if track changed
225 * returns 2 if track is invalid
226 * returns 3 if sector is invalid
227 * returns 4 if seek is disabled
228 */
229 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
230 int enable_seek)
231 {
232 uint32_t sector;
233 int ret;
234
235 if (track > drv->max_track ||
236 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
237 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
238 head, track, sect, 1,
239 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
240 drv->max_track, drv->last_sect);
241 return 2;
242 }
243 if (sect > drv->last_sect) {
244 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
245 head, track, sect, 1,
246 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
247 drv->max_track, drv->last_sect);
248 return 3;
249 }
250 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
251 ret = 0;
252 if (sector != fd_sector(drv)) {
253 #if 0
254 if (!enable_seek) {
255 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
256 " (max=%d %02x %02x)\n",
257 head, track, sect, 1, drv->max_track,
258 drv->last_sect);
259 return 4;
260 }
261 #endif
262 drv->head = head;
263 if (drv->track != track) {
264 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
265 drv->media_changed = 0;
266 }
267 ret = 1;
268 }
269 drv->track = track;
270 drv->sect = sect;
271 }
272
273 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
274 ret = 2;
275 }
276
277 return ret;
278 }
279
280 /* Set drive back to track 0 */
281 static void fd_recalibrate(FDrive *drv)
282 {
283 FLOPPY_DPRINTF("recalibrate\n");
284 fd_seek(drv, 0, 0, 1, 1);
285 }
286
287 /* Revalidate a disk drive after a disk change */
288 static void fd_revalidate(FDrive *drv)
289 {
290 int nb_heads, max_track, last_sect, ro;
291 FDriveType drive;
292 FDriveRate rate;
293
294 FLOPPY_DPRINTF("revalidate\n");
295 if (drv->blk != NULL) {
296 ro = blk_is_read_only(drv->blk);
297 pick_geometry(drv->blk, &nb_heads, &max_track,
298 &last_sect, drv->drive, &drive, &rate);
299 if (!blk_is_inserted(drv->blk)) {
300 FLOPPY_DPRINTF("No disk in drive\n");
301 } else {
302 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
303 max_track, last_sect, ro ? "ro" : "rw");
304 }
305 if (nb_heads == 1) {
306 drv->flags &= ~FDISK_DBL_SIDES;
307 } else {
308 drv->flags |= FDISK_DBL_SIDES;
309 }
310 drv->max_track = max_track;
311 drv->last_sect = last_sect;
312 drv->ro = ro;
313 drv->drive = drive;
314 drv->media_rate = rate;
315 } else {
316 FLOPPY_DPRINTF("No drive connected\n");
317 drv->last_sect = 0;
318 drv->max_track = 0;
319 drv->flags &= ~FDISK_DBL_SIDES;
320 }
321 }
322
323 /********************************************************/
324 /* Intel 82078 floppy disk controller emulation */
325
326 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
327 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
328 static int fdctrl_transfer_handler (void *opaque, int nchan,
329 int dma_pos, int dma_len);
330 static void fdctrl_raise_irq(FDCtrl *fdctrl);
331 static FDrive *get_cur_drv(FDCtrl *fdctrl);
332
333 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
334 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
335 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
336 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
337 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
338 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
339 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
340 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
341 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
342 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
343 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
344 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
345
346 enum {
347 FD_DIR_WRITE = 0,
348 FD_DIR_READ = 1,
349 FD_DIR_SCANE = 2,
350 FD_DIR_SCANL = 3,
351 FD_DIR_SCANH = 4,
352 FD_DIR_VERIFY = 5,
353 };
354
355 enum {
356 FD_STATE_MULTI = 0x01, /* multi track flag */
357 FD_STATE_FORMAT = 0x02, /* format flag */
358 };
359
360 enum {
361 FD_REG_SRA = 0x00,
362 FD_REG_SRB = 0x01,
363 FD_REG_DOR = 0x02,
364 FD_REG_TDR = 0x03,
365 FD_REG_MSR = 0x04,
366 FD_REG_DSR = 0x04,
367 FD_REG_FIFO = 0x05,
368 FD_REG_DIR = 0x07,
369 FD_REG_CCR = 0x07,
370 };
371
372 enum {
373 FD_CMD_READ_TRACK = 0x02,
374 FD_CMD_SPECIFY = 0x03,
375 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
376 FD_CMD_WRITE = 0x05,
377 FD_CMD_READ = 0x06,
378 FD_CMD_RECALIBRATE = 0x07,
379 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
380 FD_CMD_WRITE_DELETED = 0x09,
381 FD_CMD_READ_ID = 0x0a,
382 FD_CMD_READ_DELETED = 0x0c,
383 FD_CMD_FORMAT_TRACK = 0x0d,
384 FD_CMD_DUMPREG = 0x0e,
385 FD_CMD_SEEK = 0x0f,
386 FD_CMD_VERSION = 0x10,
387 FD_CMD_SCAN_EQUAL = 0x11,
388 FD_CMD_PERPENDICULAR_MODE = 0x12,
389 FD_CMD_CONFIGURE = 0x13,
390 FD_CMD_LOCK = 0x14,
391 FD_CMD_VERIFY = 0x16,
392 FD_CMD_POWERDOWN_MODE = 0x17,
393 FD_CMD_PART_ID = 0x18,
394 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
395 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
396 FD_CMD_SAVE = 0x2e,
397 FD_CMD_OPTION = 0x33,
398 FD_CMD_RESTORE = 0x4e,
399 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
400 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
401 FD_CMD_FORMAT_AND_WRITE = 0xcd,
402 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
403 };
404
405 enum {
406 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
407 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
408 FD_CONFIG_POLL = 0x10, /* Poll enabled */
409 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
410 FD_CONFIG_EIS = 0x40, /* No implied seeks */
411 };
412
413 enum {
414 FD_SR0_DS0 = 0x01,
415 FD_SR0_DS1 = 0x02,
416 FD_SR0_HEAD = 0x04,
417 FD_SR0_EQPMT = 0x10,
418 FD_SR0_SEEK = 0x20,
419 FD_SR0_ABNTERM = 0x40,
420 FD_SR0_INVCMD = 0x80,
421 FD_SR0_RDYCHG = 0xc0,
422 };
423
424 enum {
425 FD_SR1_MA = 0x01, /* Missing address mark */
426 FD_SR1_NW = 0x02, /* Not writable */
427 FD_SR1_EC = 0x80, /* End of cylinder */
428 };
429
430 enum {
431 FD_SR2_SNS = 0x04, /* Scan not satisfied */
432 FD_SR2_SEH = 0x08, /* Scan equal hit */
433 };
434
435 enum {
436 FD_SRA_DIR = 0x01,
437 FD_SRA_nWP = 0x02,
438 FD_SRA_nINDX = 0x04,
439 FD_SRA_HDSEL = 0x08,
440 FD_SRA_nTRK0 = 0x10,
441 FD_SRA_STEP = 0x20,
442 FD_SRA_nDRV2 = 0x40,
443 FD_SRA_INTPEND = 0x80,
444 };
445
446 enum {
447 FD_SRB_MTR0 = 0x01,
448 FD_SRB_MTR1 = 0x02,
449 FD_SRB_WGATE = 0x04,
450 FD_SRB_RDATA = 0x08,
451 FD_SRB_WDATA = 0x10,
452 FD_SRB_DR0 = 0x20,
453 };
454
455 enum {
456 #if MAX_FD == 4
457 FD_DOR_SELMASK = 0x03,
458 #else
459 FD_DOR_SELMASK = 0x01,
460 #endif
461 FD_DOR_nRESET = 0x04,
462 FD_DOR_DMAEN = 0x08,
463 FD_DOR_MOTEN0 = 0x10,
464 FD_DOR_MOTEN1 = 0x20,
465 FD_DOR_MOTEN2 = 0x40,
466 FD_DOR_MOTEN3 = 0x80,
467 };
468
469 enum {
470 #if MAX_FD == 4
471 FD_TDR_BOOTSEL = 0x0c,
472 #else
473 FD_TDR_BOOTSEL = 0x04,
474 #endif
475 };
476
477 enum {
478 FD_DSR_DRATEMASK= 0x03,
479 FD_DSR_PWRDOWN = 0x40,
480 FD_DSR_SWRESET = 0x80,
481 };
482
483 enum {
484 FD_MSR_DRV0BUSY = 0x01,
485 FD_MSR_DRV1BUSY = 0x02,
486 FD_MSR_DRV2BUSY = 0x04,
487 FD_MSR_DRV3BUSY = 0x08,
488 FD_MSR_CMDBUSY = 0x10,
489 FD_MSR_NONDMA = 0x20,
490 FD_MSR_DIO = 0x40,
491 FD_MSR_RQM = 0x80,
492 };
493
494 enum {
495 FD_DIR_DSKCHG = 0x80,
496 };
497
498 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
499 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
500
501 struct FDCtrl {
502 MemoryRegion iomem;
503 qemu_irq irq;
504 /* Controller state */
505 QEMUTimer *result_timer;
506 int dma_chann;
507 /* Controller's identification */
508 uint8_t version;
509 /* HW */
510 uint8_t sra;
511 uint8_t srb;
512 uint8_t dor;
513 uint8_t dor_vmstate; /* only used as temp during vmstate */
514 uint8_t tdr;
515 uint8_t dsr;
516 uint8_t msr;
517 uint8_t cur_drv;
518 uint8_t status0;
519 uint8_t status1;
520 uint8_t status2;
521 /* Command FIFO */
522 uint8_t *fifo;
523 int32_t fifo_size;
524 uint32_t data_pos;
525 uint32_t data_len;
526 uint8_t data_state;
527 uint8_t data_dir;
528 uint8_t eot; /* last wanted sector */
529 /* States kept only to be returned back */
530 /* precompensation */
531 uint8_t precomp_trk;
532 uint8_t config;
533 uint8_t lock;
534 /* Power down config (also with status regB access mode */
535 uint8_t pwrd;
536 /* Floppy drives */
537 uint8_t num_floppies;
538 /* Sun4m quirks? */
539 int sun4m;
540 FDrive drives[MAX_FD];
541 int reset_sensei;
542 uint32_t check_media_rate;
543 /* Timers state */
544 uint8_t timer0;
545 uint8_t timer1;
546 };
547
548 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
549 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
550
551 typedef struct FDCtrlSysBus {
552 /*< private >*/
553 SysBusDevice parent_obj;
554 /*< public >*/
555
556 struct FDCtrl state;
557 } FDCtrlSysBus;
558
559 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
560
561 typedef struct FDCtrlISABus {
562 ISADevice parent_obj;
563
564 uint32_t iobase;
565 uint32_t irq;
566 uint32_t dma;
567 struct FDCtrl state;
568 int32_t bootindexA;
569 int32_t bootindexB;
570 } FDCtrlISABus;
571
572 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
573 {
574 FDCtrl *fdctrl = opaque;
575 uint32_t retval;
576
577 reg &= 7;
578 switch (reg) {
579 case FD_REG_SRA:
580 retval = fdctrl_read_statusA(fdctrl);
581 break;
582 case FD_REG_SRB:
583 retval = fdctrl_read_statusB(fdctrl);
584 break;
585 case FD_REG_DOR:
586 retval = fdctrl_read_dor(fdctrl);
587 break;
588 case FD_REG_TDR:
589 retval = fdctrl_read_tape(fdctrl);
590 break;
591 case FD_REG_MSR:
592 retval = fdctrl_read_main_status(fdctrl);
593 break;
594 case FD_REG_FIFO:
595 retval = fdctrl_read_data(fdctrl);
596 break;
597 case FD_REG_DIR:
598 retval = fdctrl_read_dir(fdctrl);
599 break;
600 default:
601 retval = (uint32_t)(-1);
602 break;
603 }
604 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
605
606 return retval;
607 }
608
609 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
610 {
611 FDCtrl *fdctrl = opaque;
612
613 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
614
615 reg &= 7;
616 switch (reg) {
617 case FD_REG_DOR:
618 fdctrl_write_dor(fdctrl, value);
619 break;
620 case FD_REG_TDR:
621 fdctrl_write_tape(fdctrl, value);
622 break;
623 case FD_REG_DSR:
624 fdctrl_write_rate(fdctrl, value);
625 break;
626 case FD_REG_FIFO:
627 fdctrl_write_data(fdctrl, value);
628 break;
629 case FD_REG_CCR:
630 fdctrl_write_ccr(fdctrl, value);
631 break;
632 default:
633 break;
634 }
635 }
636
637 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
638 unsigned ize)
639 {
640 return fdctrl_read(opaque, (uint32_t)reg);
641 }
642
643 static void fdctrl_write_mem (void *opaque, hwaddr reg,
644 uint64_t value, unsigned size)
645 {
646 fdctrl_write(opaque, (uint32_t)reg, value);
647 }
648
649 static const MemoryRegionOps fdctrl_mem_ops = {
650 .read = fdctrl_read_mem,
651 .write = fdctrl_write_mem,
652 .endianness = DEVICE_NATIVE_ENDIAN,
653 };
654
655 static const MemoryRegionOps fdctrl_mem_strict_ops = {
656 .read = fdctrl_read_mem,
657 .write = fdctrl_write_mem,
658 .endianness = DEVICE_NATIVE_ENDIAN,
659 .valid = {
660 .min_access_size = 1,
661 .max_access_size = 1,
662 },
663 };
664
665 static bool fdrive_media_changed_needed(void *opaque)
666 {
667 FDrive *drive = opaque;
668
669 return (drive->blk != NULL && drive->media_changed != 1);
670 }
671
672 static const VMStateDescription vmstate_fdrive_media_changed = {
673 .name = "fdrive/media_changed",
674 .version_id = 1,
675 .minimum_version_id = 1,
676 .fields = (VMStateField[]) {
677 VMSTATE_UINT8(media_changed, FDrive),
678 VMSTATE_END_OF_LIST()
679 }
680 };
681
682 static bool fdrive_media_rate_needed(void *opaque)
683 {
684 FDrive *drive = opaque;
685
686 return drive->fdctrl->check_media_rate;
687 }
688
689 static const VMStateDescription vmstate_fdrive_media_rate = {
690 .name = "fdrive/media_rate",
691 .version_id = 1,
692 .minimum_version_id = 1,
693 .fields = (VMStateField[]) {
694 VMSTATE_UINT8(media_rate, FDrive),
695 VMSTATE_END_OF_LIST()
696 }
697 };
698
699 static bool fdrive_perpendicular_needed(void *opaque)
700 {
701 FDrive *drive = opaque;
702
703 return drive->perpendicular != 0;
704 }
705
706 static const VMStateDescription vmstate_fdrive_perpendicular = {
707 .name = "fdrive/perpendicular",
708 .version_id = 1,
709 .minimum_version_id = 1,
710 .fields = (VMStateField[]) {
711 VMSTATE_UINT8(perpendicular, FDrive),
712 VMSTATE_END_OF_LIST()
713 }
714 };
715
716 static int fdrive_post_load(void *opaque, int version_id)
717 {
718 fd_revalidate(opaque);
719 return 0;
720 }
721
722 static const VMStateDescription vmstate_fdrive = {
723 .name = "fdrive",
724 .version_id = 1,
725 .minimum_version_id = 1,
726 .post_load = fdrive_post_load,
727 .fields = (VMStateField[]) {
728 VMSTATE_UINT8(head, FDrive),
729 VMSTATE_UINT8(track, FDrive),
730 VMSTATE_UINT8(sect, FDrive),
731 VMSTATE_END_OF_LIST()
732 },
733 .subsections = (VMStateSubsection[]) {
734 {
735 .vmsd = &vmstate_fdrive_media_changed,
736 .needed = &fdrive_media_changed_needed,
737 } , {
738 .vmsd = &vmstate_fdrive_media_rate,
739 .needed = &fdrive_media_rate_needed,
740 } , {
741 .vmsd = &vmstate_fdrive_perpendicular,
742 .needed = &fdrive_perpendicular_needed,
743 } , {
744 /* empty */
745 }
746 }
747 };
748
749 static void fdc_pre_save(void *opaque)
750 {
751 FDCtrl *s = opaque;
752
753 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
754 }
755
756 static int fdc_post_load(void *opaque, int version_id)
757 {
758 FDCtrl *s = opaque;
759
760 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
761 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
762 return 0;
763 }
764
765 static bool fdc_reset_sensei_needed(void *opaque)
766 {
767 FDCtrl *s = opaque;
768
769 return s->reset_sensei != 0;
770 }
771
772 static const VMStateDescription vmstate_fdc_reset_sensei = {
773 .name = "fdc/reset_sensei",
774 .version_id = 1,
775 .minimum_version_id = 1,
776 .fields = (VMStateField[]) {
777 VMSTATE_INT32(reset_sensei, FDCtrl),
778 VMSTATE_END_OF_LIST()
779 }
780 };
781
782 static bool fdc_result_timer_needed(void *opaque)
783 {
784 FDCtrl *s = opaque;
785
786 return timer_pending(s->result_timer);
787 }
788
789 static const VMStateDescription vmstate_fdc_result_timer = {
790 .name = "fdc/result_timer",
791 .version_id = 1,
792 .minimum_version_id = 1,
793 .fields = (VMStateField[]) {
794 VMSTATE_TIMER(result_timer, FDCtrl),
795 VMSTATE_END_OF_LIST()
796 }
797 };
798
799 static const VMStateDescription vmstate_fdc = {
800 .name = "fdc",
801 .version_id = 2,
802 .minimum_version_id = 2,
803 .pre_save = fdc_pre_save,
804 .post_load = fdc_post_load,
805 .fields = (VMStateField[]) {
806 /* Controller State */
807 VMSTATE_UINT8(sra, FDCtrl),
808 VMSTATE_UINT8(srb, FDCtrl),
809 VMSTATE_UINT8(dor_vmstate, FDCtrl),
810 VMSTATE_UINT8(tdr, FDCtrl),
811 VMSTATE_UINT8(dsr, FDCtrl),
812 VMSTATE_UINT8(msr, FDCtrl),
813 VMSTATE_UINT8(status0, FDCtrl),
814 VMSTATE_UINT8(status1, FDCtrl),
815 VMSTATE_UINT8(status2, FDCtrl),
816 /* Command FIFO */
817 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
818 uint8_t),
819 VMSTATE_UINT32(data_pos, FDCtrl),
820 VMSTATE_UINT32(data_len, FDCtrl),
821 VMSTATE_UINT8(data_state, FDCtrl),
822 VMSTATE_UINT8(data_dir, FDCtrl),
823 VMSTATE_UINT8(eot, FDCtrl),
824 /* States kept only to be returned back */
825 VMSTATE_UINT8(timer0, FDCtrl),
826 VMSTATE_UINT8(timer1, FDCtrl),
827 VMSTATE_UINT8(precomp_trk, FDCtrl),
828 VMSTATE_UINT8(config, FDCtrl),
829 VMSTATE_UINT8(lock, FDCtrl),
830 VMSTATE_UINT8(pwrd, FDCtrl),
831 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
832 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
833 vmstate_fdrive, FDrive),
834 VMSTATE_END_OF_LIST()
835 },
836 .subsections = (VMStateSubsection[]) {
837 {
838 .vmsd = &vmstate_fdc_reset_sensei,
839 .needed = fdc_reset_sensei_needed,
840 } , {
841 .vmsd = &vmstate_fdc_result_timer,
842 .needed = fdc_result_timer_needed,
843 } , {
844 /* empty */
845 }
846 }
847 };
848
849 static void fdctrl_external_reset_sysbus(DeviceState *d)
850 {
851 FDCtrlSysBus *sys = SYSBUS_FDC(d);
852 FDCtrl *s = &sys->state;
853
854 fdctrl_reset(s, 0);
855 }
856
857 static void fdctrl_external_reset_isa(DeviceState *d)
858 {
859 FDCtrlISABus *isa = ISA_FDC(d);
860 FDCtrl *s = &isa->state;
861
862 fdctrl_reset(s, 0);
863 }
864
865 static void fdctrl_handle_tc(void *opaque, int irq, int level)
866 {
867 //FDCtrl *s = opaque;
868
869 if (level) {
870 // XXX
871 FLOPPY_DPRINTF("TC pulsed\n");
872 }
873 }
874
875 /* Change IRQ state */
876 static void fdctrl_reset_irq(FDCtrl *fdctrl)
877 {
878 fdctrl->status0 = 0;
879 if (!(fdctrl->sra & FD_SRA_INTPEND))
880 return;
881 FLOPPY_DPRINTF("Reset interrupt\n");
882 qemu_set_irq(fdctrl->irq, 0);
883 fdctrl->sra &= ~FD_SRA_INTPEND;
884 }
885
886 static void fdctrl_raise_irq(FDCtrl *fdctrl)
887 {
888 /* Sparc mutation */
889 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
890 /* XXX: not sure */
891 fdctrl->msr &= ~FD_MSR_CMDBUSY;
892 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
893 return;
894 }
895 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
896 qemu_set_irq(fdctrl->irq, 1);
897 fdctrl->sra |= FD_SRA_INTPEND;
898 }
899
900 fdctrl->reset_sensei = 0;
901 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
902 }
903
904 /* Reset controller */
905 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
906 {
907 int i;
908
909 FLOPPY_DPRINTF("reset controller\n");
910 fdctrl_reset_irq(fdctrl);
911 /* Initialise controller */
912 fdctrl->sra = 0;
913 fdctrl->srb = 0xc0;
914 if (!fdctrl->drives[1].blk) {
915 fdctrl->sra |= FD_SRA_nDRV2;
916 }
917 fdctrl->cur_drv = 0;
918 fdctrl->dor = FD_DOR_nRESET;
919 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
920 fdctrl->msr = FD_MSR_RQM;
921 fdctrl->reset_sensei = 0;
922 timer_del(fdctrl->result_timer);
923 /* FIFO state */
924 fdctrl->data_pos = 0;
925 fdctrl->data_len = 0;
926 fdctrl->data_state = 0;
927 fdctrl->data_dir = FD_DIR_WRITE;
928 for (i = 0; i < MAX_FD; i++)
929 fd_recalibrate(&fdctrl->drives[i]);
930 fdctrl_reset_fifo(fdctrl);
931 if (do_irq) {
932 fdctrl->status0 |= FD_SR0_RDYCHG;
933 fdctrl_raise_irq(fdctrl);
934 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
935 }
936 }
937
938 static inline FDrive *drv0(FDCtrl *fdctrl)
939 {
940 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
941 }
942
943 static inline FDrive *drv1(FDCtrl *fdctrl)
944 {
945 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
946 return &fdctrl->drives[1];
947 else
948 return &fdctrl->drives[0];
949 }
950
951 #if MAX_FD == 4
952 static inline FDrive *drv2(FDCtrl *fdctrl)
953 {
954 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
955 return &fdctrl->drives[2];
956 else
957 return &fdctrl->drives[1];
958 }
959
960 static inline FDrive *drv3(FDCtrl *fdctrl)
961 {
962 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
963 return &fdctrl->drives[3];
964 else
965 return &fdctrl->drives[2];
966 }
967 #endif
968
969 static FDrive *get_cur_drv(FDCtrl *fdctrl)
970 {
971 switch (fdctrl->cur_drv) {
972 case 0: return drv0(fdctrl);
973 case 1: return drv1(fdctrl);
974 #if MAX_FD == 4
975 case 2: return drv2(fdctrl);
976 case 3: return drv3(fdctrl);
977 #endif
978 default: return NULL;
979 }
980 }
981
982 /* Status A register : 0x00 (read-only) */
983 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
984 {
985 uint32_t retval = fdctrl->sra;
986
987 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
988
989 return retval;
990 }
991
992 /* Status B register : 0x01 (read-only) */
993 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
994 {
995 uint32_t retval = fdctrl->srb;
996
997 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
998
999 return retval;
1000 }
1001
1002 /* Digital output register : 0x02 */
1003 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1004 {
1005 uint32_t retval = fdctrl->dor;
1006
1007 /* Selected drive */
1008 retval |= fdctrl->cur_drv;
1009 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1010
1011 return retval;
1012 }
1013
1014 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1015 {
1016 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1017
1018 /* Motors */
1019 if (value & FD_DOR_MOTEN0)
1020 fdctrl->srb |= FD_SRB_MTR0;
1021 else
1022 fdctrl->srb &= ~FD_SRB_MTR0;
1023 if (value & FD_DOR_MOTEN1)
1024 fdctrl->srb |= FD_SRB_MTR1;
1025 else
1026 fdctrl->srb &= ~FD_SRB_MTR1;
1027
1028 /* Drive */
1029 if (value & 1)
1030 fdctrl->srb |= FD_SRB_DR0;
1031 else
1032 fdctrl->srb &= ~FD_SRB_DR0;
1033
1034 /* Reset */
1035 if (!(value & FD_DOR_nRESET)) {
1036 if (fdctrl->dor & FD_DOR_nRESET) {
1037 FLOPPY_DPRINTF("controller enter RESET state\n");
1038 }
1039 } else {
1040 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1041 FLOPPY_DPRINTF("controller out of RESET state\n");
1042 fdctrl_reset(fdctrl, 1);
1043 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1044 }
1045 }
1046 /* Selected drive */
1047 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1048
1049 fdctrl->dor = value;
1050 }
1051
1052 /* Tape drive register : 0x03 */
1053 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1054 {
1055 uint32_t retval = fdctrl->tdr;
1056
1057 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1058
1059 return retval;
1060 }
1061
1062 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1063 {
1064 /* Reset mode */
1065 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1066 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1067 return;
1068 }
1069 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1070 /* Disk boot selection indicator */
1071 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1072 /* Tape indicators: never allow */
1073 }
1074
1075 /* Main status register : 0x04 (read) */
1076 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1077 {
1078 uint32_t retval = fdctrl->msr;
1079
1080 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1081 fdctrl->dor |= FD_DOR_nRESET;
1082
1083 /* Sparc mutation */
1084 if (fdctrl->sun4m) {
1085 retval |= FD_MSR_DIO;
1086 fdctrl_reset_irq(fdctrl);
1087 };
1088
1089 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1090
1091 return retval;
1092 }
1093
1094 /* Data select rate register : 0x04 (write) */
1095 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1096 {
1097 /* Reset mode */
1098 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1099 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1100 return;
1101 }
1102 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1103 /* Reset: autoclear */
1104 if (value & FD_DSR_SWRESET) {
1105 fdctrl->dor &= ~FD_DOR_nRESET;
1106 fdctrl_reset(fdctrl, 1);
1107 fdctrl->dor |= FD_DOR_nRESET;
1108 }
1109 if (value & FD_DSR_PWRDOWN) {
1110 fdctrl_reset(fdctrl, 1);
1111 }
1112 fdctrl->dsr = value;
1113 }
1114
1115 /* Configuration control register: 0x07 (write) */
1116 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1117 {
1118 /* Reset mode */
1119 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1120 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1121 return;
1122 }
1123 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1124
1125 /* Only the rate selection bits used in AT mode, and we
1126 * store those in the DSR.
1127 */
1128 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1129 (value & FD_DSR_DRATEMASK);
1130 }
1131
1132 static int fdctrl_media_changed(FDrive *drv)
1133 {
1134 return drv->media_changed;
1135 }
1136
1137 /* Digital input register : 0x07 (read-only) */
1138 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1139 {
1140 uint32_t retval = 0;
1141
1142 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1143 retval |= FD_DIR_DSKCHG;
1144 }
1145 if (retval != 0) {
1146 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1147 }
1148
1149 return retval;
1150 }
1151
1152 /* FIFO state control */
1153 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1154 {
1155 fdctrl->data_dir = FD_DIR_WRITE;
1156 fdctrl->data_pos = 0;
1157 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1158 }
1159
1160 /* Set FIFO status for the host to read */
1161 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len)
1162 {
1163 fdctrl->data_dir = FD_DIR_READ;
1164 fdctrl->data_len = fifo_len;
1165 fdctrl->data_pos = 0;
1166 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1167 }
1168
1169 /* Set an error: unimplemented/unknown command */
1170 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1171 {
1172 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1173 fdctrl->fifo[0]);
1174 fdctrl->fifo[0] = FD_SR0_INVCMD;
1175 fdctrl_set_fifo(fdctrl, 1);
1176 }
1177
1178 /* Seek to next sector
1179 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1180 * otherwise returns 1
1181 */
1182 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1183 {
1184 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1185 cur_drv->head, cur_drv->track, cur_drv->sect,
1186 fd_sector(cur_drv));
1187 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1188 error in fact */
1189 uint8_t new_head = cur_drv->head;
1190 uint8_t new_track = cur_drv->track;
1191 uint8_t new_sect = cur_drv->sect;
1192
1193 int ret = 1;
1194
1195 if (new_sect >= cur_drv->last_sect ||
1196 new_sect == fdctrl->eot) {
1197 new_sect = 1;
1198 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1199 if (new_head == 0 &&
1200 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1201 new_head = 1;
1202 } else {
1203 new_head = 0;
1204 new_track++;
1205 fdctrl->status0 |= FD_SR0_SEEK;
1206 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1207 ret = 0;
1208 }
1209 }
1210 } else {
1211 fdctrl->status0 |= FD_SR0_SEEK;
1212 new_track++;
1213 ret = 0;
1214 }
1215 if (ret == 1) {
1216 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1217 new_head, new_track, new_sect, fd_sector(cur_drv));
1218 }
1219 } else {
1220 new_sect++;
1221 }
1222 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1223 return ret;
1224 }
1225
1226 /* Callback for transfer end (stop or abort) */
1227 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1228 uint8_t status1, uint8_t status2)
1229 {
1230 FDrive *cur_drv;
1231 cur_drv = get_cur_drv(fdctrl);
1232
1233 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1234 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1235 if (cur_drv->head) {
1236 fdctrl->status0 |= FD_SR0_HEAD;
1237 }
1238 fdctrl->status0 |= status0;
1239
1240 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1241 status0, status1, status2, fdctrl->status0);
1242 fdctrl->fifo[0] = fdctrl->status0;
1243 fdctrl->fifo[1] = status1;
1244 fdctrl->fifo[2] = status2;
1245 fdctrl->fifo[3] = cur_drv->track;
1246 fdctrl->fifo[4] = cur_drv->head;
1247 fdctrl->fifo[5] = cur_drv->sect;
1248 fdctrl->fifo[6] = FD_SECTOR_SC;
1249 fdctrl->data_dir = FD_DIR_READ;
1250 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1251 DMA_release_DREQ(fdctrl->dma_chann);
1252 }
1253 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1254 fdctrl->msr &= ~FD_MSR_NONDMA;
1255
1256 fdctrl_set_fifo(fdctrl, 7);
1257 fdctrl_raise_irq(fdctrl);
1258 }
1259
1260 /* Prepare a data transfer (either DMA or FIFO) */
1261 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1262 {
1263 FDrive *cur_drv;
1264 uint8_t kh, kt, ks;
1265
1266 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1267 cur_drv = get_cur_drv(fdctrl);
1268 kt = fdctrl->fifo[2];
1269 kh = fdctrl->fifo[3];
1270 ks = fdctrl->fifo[4];
1271 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1272 GET_CUR_DRV(fdctrl), kh, kt, ks,
1273 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1274 NUM_SIDES(cur_drv)));
1275 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1276 case 2:
1277 /* sect too big */
1278 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1279 fdctrl->fifo[3] = kt;
1280 fdctrl->fifo[4] = kh;
1281 fdctrl->fifo[5] = ks;
1282 return;
1283 case 3:
1284 /* track too big */
1285 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1286 fdctrl->fifo[3] = kt;
1287 fdctrl->fifo[4] = kh;
1288 fdctrl->fifo[5] = ks;
1289 return;
1290 case 4:
1291 /* No seek enabled */
1292 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1293 fdctrl->fifo[3] = kt;
1294 fdctrl->fifo[4] = kh;
1295 fdctrl->fifo[5] = ks;
1296 return;
1297 case 1:
1298 fdctrl->status0 |= FD_SR0_SEEK;
1299 break;
1300 default:
1301 break;
1302 }
1303
1304 /* Check the data rate. If the programmed data rate does not match
1305 * the currently inserted medium, the operation has to fail. */
1306 if (fdctrl->check_media_rate &&
1307 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1308 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1309 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1310 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1311 fdctrl->fifo[3] = kt;
1312 fdctrl->fifo[4] = kh;
1313 fdctrl->fifo[5] = ks;
1314 return;
1315 }
1316
1317 /* Set the FIFO state */
1318 fdctrl->data_dir = direction;
1319 fdctrl->data_pos = 0;
1320 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1321 if (fdctrl->fifo[0] & 0x80)
1322 fdctrl->data_state |= FD_STATE_MULTI;
1323 else
1324 fdctrl->data_state &= ~FD_STATE_MULTI;
1325 if (fdctrl->fifo[5] == 0) {
1326 fdctrl->data_len = fdctrl->fifo[8];
1327 } else {
1328 int tmp;
1329 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1330 tmp = (fdctrl->fifo[6] - ks + 1);
1331 if (fdctrl->fifo[0] & 0x80)
1332 tmp += fdctrl->fifo[6];
1333 fdctrl->data_len *= tmp;
1334 }
1335 fdctrl->eot = fdctrl->fifo[6];
1336 if (fdctrl->dor & FD_DOR_DMAEN) {
1337 int dma_mode;
1338 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1339 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1340 dma_mode = (dma_mode >> 2) & 3;
1341 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1342 dma_mode, direction,
1343 (128 << fdctrl->fifo[5]) *
1344 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1345 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1346 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1347 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1348 (direction == FD_DIR_READ && dma_mode == 1) ||
1349 (direction == FD_DIR_VERIFY)) {
1350 /* No access is allowed until DMA transfer has completed */
1351 fdctrl->msr &= ~FD_MSR_RQM;
1352 if (direction != FD_DIR_VERIFY) {
1353 /* Now, we just have to wait for the DMA controller to
1354 * recall us...
1355 */
1356 DMA_hold_DREQ(fdctrl->dma_chann);
1357 DMA_schedule(fdctrl->dma_chann);
1358 } else {
1359 /* Start transfer */
1360 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1361 fdctrl->data_len);
1362 }
1363 return;
1364 } else {
1365 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1366 direction);
1367 }
1368 }
1369 FLOPPY_DPRINTF("start non-DMA transfer\n");
1370 fdctrl->msr |= FD_MSR_NONDMA;
1371 if (direction != FD_DIR_WRITE)
1372 fdctrl->msr |= FD_MSR_DIO;
1373 /* IO based transfer: calculate len */
1374 fdctrl_raise_irq(fdctrl);
1375 }
1376
1377 /* Prepare a transfer of deleted data */
1378 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1379 {
1380 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1381
1382 /* We don't handle deleted data,
1383 * so we don't return *ANYTHING*
1384 */
1385 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1386 }
1387
1388 /* handlers for DMA transfers */
1389 static int fdctrl_transfer_handler (void *opaque, int nchan,
1390 int dma_pos, int dma_len)
1391 {
1392 FDCtrl *fdctrl;
1393 FDrive *cur_drv;
1394 int len, start_pos, rel_pos;
1395 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1396
1397 fdctrl = opaque;
1398 if (fdctrl->msr & FD_MSR_RQM) {
1399 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1400 return 0;
1401 }
1402 cur_drv = get_cur_drv(fdctrl);
1403 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1404 fdctrl->data_dir == FD_DIR_SCANH)
1405 status2 = FD_SR2_SNS;
1406 if (dma_len > fdctrl->data_len)
1407 dma_len = fdctrl->data_len;
1408 if (cur_drv->blk == NULL) {
1409 if (fdctrl->data_dir == FD_DIR_WRITE)
1410 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1411 else
1412 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1413 len = 0;
1414 goto transfer_error;
1415 }
1416 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1417 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1418 len = dma_len - fdctrl->data_pos;
1419 if (len + rel_pos > FD_SECTOR_LEN)
1420 len = FD_SECTOR_LEN - rel_pos;
1421 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1422 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1423 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1424 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1425 fd_sector(cur_drv) * FD_SECTOR_LEN);
1426 if (fdctrl->data_dir != FD_DIR_WRITE ||
1427 len < FD_SECTOR_LEN || rel_pos != 0) {
1428 /* READ & SCAN commands and realign to a sector for WRITE */
1429 if (blk_read(cur_drv->blk, fd_sector(cur_drv),
1430 fdctrl->fifo, 1) < 0) {
1431 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1432 fd_sector(cur_drv));
1433 /* Sure, image size is too small... */
1434 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1435 }
1436 }
1437 switch (fdctrl->data_dir) {
1438 case FD_DIR_READ:
1439 /* READ commands */
1440 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1441 fdctrl->data_pos, len);
1442 break;
1443 case FD_DIR_WRITE:
1444 /* WRITE commands */
1445 if (cur_drv->ro) {
1446 /* Handle readonly medium early, no need to do DMA, touch the
1447 * LED or attempt any writes. A real floppy doesn't attempt
1448 * to write to readonly media either. */
1449 fdctrl_stop_transfer(fdctrl,
1450 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1451 0x00);
1452 goto transfer_error;
1453 }
1454
1455 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1456 fdctrl->data_pos, len);
1457 if (blk_write(cur_drv->blk, fd_sector(cur_drv),
1458 fdctrl->fifo, 1) < 0) {
1459 FLOPPY_DPRINTF("error writing sector %d\n",
1460 fd_sector(cur_drv));
1461 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1462 goto transfer_error;
1463 }
1464 break;
1465 case FD_DIR_VERIFY:
1466 /* VERIFY commands */
1467 break;
1468 default:
1469 /* SCAN commands */
1470 {
1471 uint8_t tmpbuf[FD_SECTOR_LEN];
1472 int ret;
1473 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1474 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1475 if (ret == 0) {
1476 status2 = FD_SR2_SEH;
1477 goto end_transfer;
1478 }
1479 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1480 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1481 status2 = 0x00;
1482 goto end_transfer;
1483 }
1484 }
1485 break;
1486 }
1487 fdctrl->data_pos += len;
1488 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1489 if (rel_pos == 0) {
1490 /* Seek to next sector */
1491 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1492 break;
1493 }
1494 }
1495 end_transfer:
1496 len = fdctrl->data_pos - start_pos;
1497 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1498 fdctrl->data_pos, len, fdctrl->data_len);
1499 if (fdctrl->data_dir == FD_DIR_SCANE ||
1500 fdctrl->data_dir == FD_DIR_SCANL ||
1501 fdctrl->data_dir == FD_DIR_SCANH)
1502 status2 = FD_SR2_SEH;
1503 fdctrl->data_len -= len;
1504 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1505 transfer_error:
1506
1507 return len;
1508 }
1509
1510 /* Data register : 0x05 */
1511 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1512 {
1513 FDrive *cur_drv;
1514 uint32_t retval = 0;
1515 int pos;
1516
1517 cur_drv = get_cur_drv(fdctrl);
1518 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1519 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1520 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1521 return 0;
1522 }
1523 pos = fdctrl->data_pos;
1524 if (fdctrl->msr & FD_MSR_NONDMA) {
1525 pos %= FD_SECTOR_LEN;
1526 if (pos == 0) {
1527 if (fdctrl->data_pos != 0)
1528 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1529 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1530 fd_sector(cur_drv));
1531 return 0;
1532 }
1533 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
1534 < 0) {
1535 FLOPPY_DPRINTF("error getting sector %d\n",
1536 fd_sector(cur_drv));
1537 /* Sure, image size is too small... */
1538 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1539 }
1540 }
1541 }
1542 retval = fdctrl->fifo[pos];
1543 if (++fdctrl->data_pos == fdctrl->data_len) {
1544 fdctrl->data_pos = 0;
1545 /* Switch from transfer mode to status mode
1546 * then from status mode to command mode
1547 */
1548 if (fdctrl->msr & FD_MSR_NONDMA) {
1549 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1550 } else {
1551 fdctrl_reset_fifo(fdctrl);
1552 fdctrl_reset_irq(fdctrl);
1553 }
1554 }
1555 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1556
1557 return retval;
1558 }
1559
1560 static void fdctrl_format_sector(FDCtrl *fdctrl)
1561 {
1562 FDrive *cur_drv;
1563 uint8_t kh, kt, ks;
1564
1565 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1566 cur_drv = get_cur_drv(fdctrl);
1567 kt = fdctrl->fifo[6];
1568 kh = fdctrl->fifo[7];
1569 ks = fdctrl->fifo[8];
1570 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1571 GET_CUR_DRV(fdctrl), kh, kt, ks,
1572 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1573 NUM_SIDES(cur_drv)));
1574 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1575 case 2:
1576 /* sect too big */
1577 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1578 fdctrl->fifo[3] = kt;
1579 fdctrl->fifo[4] = kh;
1580 fdctrl->fifo[5] = ks;
1581 return;
1582 case 3:
1583 /* track too big */
1584 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1585 fdctrl->fifo[3] = kt;
1586 fdctrl->fifo[4] = kh;
1587 fdctrl->fifo[5] = ks;
1588 return;
1589 case 4:
1590 /* No seek enabled */
1591 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1592 fdctrl->fifo[3] = kt;
1593 fdctrl->fifo[4] = kh;
1594 fdctrl->fifo[5] = ks;
1595 return;
1596 case 1:
1597 fdctrl->status0 |= FD_SR0_SEEK;
1598 break;
1599 default:
1600 break;
1601 }
1602 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1603 if (cur_drv->blk == NULL ||
1604 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1605 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1606 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1607 } else {
1608 if (cur_drv->sect == cur_drv->last_sect) {
1609 fdctrl->data_state &= ~FD_STATE_FORMAT;
1610 /* Last sector done */
1611 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1612 } else {
1613 /* More to do */
1614 fdctrl->data_pos = 0;
1615 fdctrl->data_len = 4;
1616 }
1617 }
1618 }
1619
1620 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1621 {
1622 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1623 fdctrl->fifo[0] = fdctrl->lock << 4;
1624 fdctrl_set_fifo(fdctrl, 1);
1625 }
1626
1627 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1628 {
1629 FDrive *cur_drv = get_cur_drv(fdctrl);
1630
1631 /* Drives position */
1632 fdctrl->fifo[0] = drv0(fdctrl)->track;
1633 fdctrl->fifo[1] = drv1(fdctrl)->track;
1634 #if MAX_FD == 4
1635 fdctrl->fifo[2] = drv2(fdctrl)->track;
1636 fdctrl->fifo[3] = drv3(fdctrl)->track;
1637 #else
1638 fdctrl->fifo[2] = 0;
1639 fdctrl->fifo[3] = 0;
1640 #endif
1641 /* timers */
1642 fdctrl->fifo[4] = fdctrl->timer0;
1643 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1644 fdctrl->fifo[6] = cur_drv->last_sect;
1645 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1646 (cur_drv->perpendicular << 2);
1647 fdctrl->fifo[8] = fdctrl->config;
1648 fdctrl->fifo[9] = fdctrl->precomp_trk;
1649 fdctrl_set_fifo(fdctrl, 10);
1650 }
1651
1652 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1653 {
1654 /* Controller's version */
1655 fdctrl->fifo[0] = fdctrl->version;
1656 fdctrl_set_fifo(fdctrl, 1);
1657 }
1658
1659 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1660 {
1661 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1662 fdctrl_set_fifo(fdctrl, 1);
1663 }
1664
1665 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1666 {
1667 FDrive *cur_drv = get_cur_drv(fdctrl);
1668
1669 /* Drives position */
1670 drv0(fdctrl)->track = fdctrl->fifo[3];
1671 drv1(fdctrl)->track = fdctrl->fifo[4];
1672 #if MAX_FD == 4
1673 drv2(fdctrl)->track = fdctrl->fifo[5];
1674 drv3(fdctrl)->track = fdctrl->fifo[6];
1675 #endif
1676 /* timers */
1677 fdctrl->timer0 = fdctrl->fifo[7];
1678 fdctrl->timer1 = fdctrl->fifo[8];
1679 cur_drv->last_sect = fdctrl->fifo[9];
1680 fdctrl->lock = fdctrl->fifo[10] >> 7;
1681 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1682 fdctrl->config = fdctrl->fifo[11];
1683 fdctrl->precomp_trk = fdctrl->fifo[12];
1684 fdctrl->pwrd = fdctrl->fifo[13];
1685 fdctrl_reset_fifo(fdctrl);
1686 }
1687
1688 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1689 {
1690 FDrive *cur_drv = get_cur_drv(fdctrl);
1691
1692 fdctrl->fifo[0] = 0;
1693 fdctrl->fifo[1] = 0;
1694 /* Drives position */
1695 fdctrl->fifo[2] = drv0(fdctrl)->track;
1696 fdctrl->fifo[3] = drv1(fdctrl)->track;
1697 #if MAX_FD == 4
1698 fdctrl->fifo[4] = drv2(fdctrl)->track;
1699 fdctrl->fifo[5] = drv3(fdctrl)->track;
1700 #else
1701 fdctrl->fifo[4] = 0;
1702 fdctrl->fifo[5] = 0;
1703 #endif
1704 /* timers */
1705 fdctrl->fifo[6] = fdctrl->timer0;
1706 fdctrl->fifo[7] = fdctrl->timer1;
1707 fdctrl->fifo[8] = cur_drv->last_sect;
1708 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1709 (cur_drv->perpendicular << 2);
1710 fdctrl->fifo[10] = fdctrl->config;
1711 fdctrl->fifo[11] = fdctrl->precomp_trk;
1712 fdctrl->fifo[12] = fdctrl->pwrd;
1713 fdctrl->fifo[13] = 0;
1714 fdctrl->fifo[14] = 0;
1715 fdctrl_set_fifo(fdctrl, 15);
1716 }
1717
1718 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1719 {
1720 FDrive *cur_drv = get_cur_drv(fdctrl);
1721
1722 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1723 timer_mod(fdctrl->result_timer,
1724 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50));
1725 }
1726
1727 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1728 {
1729 FDrive *cur_drv;
1730
1731 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1732 cur_drv = get_cur_drv(fdctrl);
1733 fdctrl->data_state |= FD_STATE_FORMAT;
1734 if (fdctrl->fifo[0] & 0x80)
1735 fdctrl->data_state |= FD_STATE_MULTI;
1736 else
1737 fdctrl->data_state &= ~FD_STATE_MULTI;
1738 cur_drv->bps =
1739 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1740 #if 0
1741 cur_drv->last_sect =
1742 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1743 fdctrl->fifo[3] / 2;
1744 #else
1745 cur_drv->last_sect = fdctrl->fifo[3];
1746 #endif
1747 /* TODO: implement format using DMA expected by the Bochs BIOS
1748 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1749 * the sector with the specified fill byte
1750 */
1751 fdctrl->data_state &= ~FD_STATE_FORMAT;
1752 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1753 }
1754
1755 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1756 {
1757 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1758 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1759 if (fdctrl->fifo[2] & 1)
1760 fdctrl->dor &= ~FD_DOR_DMAEN;
1761 else
1762 fdctrl->dor |= FD_DOR_DMAEN;
1763 /* No result back */
1764 fdctrl_reset_fifo(fdctrl);
1765 }
1766
1767 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1768 {
1769 FDrive *cur_drv;
1770
1771 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1772 cur_drv = get_cur_drv(fdctrl);
1773 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1774 /* 1 Byte status back */
1775 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1776 (cur_drv->track == 0 ? 0x10 : 0x00) |
1777 (cur_drv->head << 2) |
1778 GET_CUR_DRV(fdctrl) |
1779 0x28;
1780 fdctrl_set_fifo(fdctrl, 1);
1781 }
1782
1783 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1784 {
1785 FDrive *cur_drv;
1786
1787 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1788 cur_drv = get_cur_drv(fdctrl);
1789 fd_recalibrate(cur_drv);
1790 fdctrl_reset_fifo(fdctrl);
1791 /* Raise Interrupt */
1792 fdctrl->status0 |= FD_SR0_SEEK;
1793 fdctrl_raise_irq(fdctrl);
1794 }
1795
1796 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1797 {
1798 FDrive *cur_drv = get_cur_drv(fdctrl);
1799
1800 if (fdctrl->reset_sensei > 0) {
1801 fdctrl->fifo[0] =
1802 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1803 fdctrl->reset_sensei--;
1804 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1805 fdctrl->fifo[0] = FD_SR0_INVCMD;
1806 fdctrl_set_fifo(fdctrl, 1);
1807 return;
1808 } else {
1809 fdctrl->fifo[0] =
1810 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1811 | GET_CUR_DRV(fdctrl);
1812 }
1813
1814 fdctrl->fifo[1] = cur_drv->track;
1815 fdctrl_set_fifo(fdctrl, 2);
1816 fdctrl_reset_irq(fdctrl);
1817 fdctrl->status0 = FD_SR0_RDYCHG;
1818 }
1819
1820 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1821 {
1822 FDrive *cur_drv;
1823
1824 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1825 cur_drv = get_cur_drv(fdctrl);
1826 fdctrl_reset_fifo(fdctrl);
1827 /* The seek command just sends step pulses to the drive and doesn't care if
1828 * there is a medium inserted of if it's banging the head against the drive.
1829 */
1830 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1831 /* Raise Interrupt */
1832 fdctrl->status0 |= FD_SR0_SEEK;
1833 fdctrl_raise_irq(fdctrl);
1834 }
1835
1836 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1837 {
1838 FDrive *cur_drv = get_cur_drv(fdctrl);
1839
1840 if (fdctrl->fifo[1] & 0x80)
1841 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1842 /* No result back */
1843 fdctrl_reset_fifo(fdctrl);
1844 }
1845
1846 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1847 {
1848 fdctrl->config = fdctrl->fifo[2];
1849 fdctrl->precomp_trk = fdctrl->fifo[3];
1850 /* No result back */
1851 fdctrl_reset_fifo(fdctrl);
1852 }
1853
1854 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1855 {
1856 fdctrl->pwrd = fdctrl->fifo[1];
1857 fdctrl->fifo[0] = fdctrl->fifo[1];
1858 fdctrl_set_fifo(fdctrl, 1);
1859 }
1860
1861 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1862 {
1863 /* No result back */
1864 fdctrl_reset_fifo(fdctrl);
1865 }
1866
1867 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1868 {
1869 FDrive *cur_drv = get_cur_drv(fdctrl);
1870
1871 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1872 /* Command parameters done */
1873 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1874 fdctrl->fifo[0] = fdctrl->fifo[1];
1875 fdctrl->fifo[2] = 0;
1876 fdctrl->fifo[3] = 0;
1877 fdctrl_set_fifo(fdctrl, 4);
1878 } else {
1879 fdctrl_reset_fifo(fdctrl);
1880 }
1881 } else if (fdctrl->data_len > 7) {
1882 /* ERROR */
1883 fdctrl->fifo[0] = 0x80 |
1884 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1885 fdctrl_set_fifo(fdctrl, 1);
1886 }
1887 }
1888
1889 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1890 {
1891 FDrive *cur_drv;
1892
1893 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1894 cur_drv = get_cur_drv(fdctrl);
1895 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1896 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
1897 cur_drv->sect, 1);
1898 } else {
1899 fd_seek(cur_drv, cur_drv->head,
1900 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
1901 }
1902 fdctrl_reset_fifo(fdctrl);
1903 /* Raise Interrupt */
1904 fdctrl->status0 |= FD_SR0_SEEK;
1905 fdctrl_raise_irq(fdctrl);
1906 }
1907
1908 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1909 {
1910 FDrive *cur_drv;
1911
1912 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1913 cur_drv = get_cur_drv(fdctrl);
1914 if (fdctrl->fifo[2] > cur_drv->track) {
1915 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
1916 } else {
1917 fd_seek(cur_drv, cur_drv->head,
1918 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
1919 }
1920 fdctrl_reset_fifo(fdctrl);
1921 /* Raise Interrupt */
1922 fdctrl->status0 |= FD_SR0_SEEK;
1923 fdctrl_raise_irq(fdctrl);
1924 }
1925
1926 static const struct {
1927 uint8_t value;
1928 uint8_t mask;
1929 const char* name;
1930 int parameters;
1931 void (*handler)(FDCtrl *fdctrl, int direction);
1932 int direction;
1933 } handlers[] = {
1934 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1935 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1936 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1937 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1938 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1939 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1940 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1941 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1942 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1943 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1944 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1945 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
1946 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1947 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1948 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1949 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1950 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1951 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1952 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1953 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1954 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1955 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1956 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1957 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1958 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1959 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1960 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1961 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1962 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1963 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1964 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1965 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1966 };
1967 /* Associate command to an index in the 'handlers' array */
1968 static uint8_t command_to_handler[256];
1969
1970 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1971 {
1972 FDrive *cur_drv;
1973 int pos;
1974
1975 /* Reset mode */
1976 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1977 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1978 return;
1979 }
1980 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1981 FLOPPY_DPRINTF("error: controller not ready for writing\n");
1982 return;
1983 }
1984 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1985 /* Is it write command time ? */
1986 if (fdctrl->msr & FD_MSR_NONDMA) {
1987 /* FIFO data write */
1988 pos = fdctrl->data_pos++;
1989 pos %= FD_SECTOR_LEN;
1990 fdctrl->fifo[pos] = value;
1991 if (pos == FD_SECTOR_LEN - 1 ||
1992 fdctrl->data_pos == fdctrl->data_len) {
1993 cur_drv = get_cur_drv(fdctrl);
1994 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
1995 < 0) {
1996 FLOPPY_DPRINTF("error writing sector %d\n",
1997 fd_sector(cur_drv));
1998 return;
1999 }
2000 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2001 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2002 fd_sector(cur_drv));
2003 return;
2004 }
2005 }
2006 /* Switch from transfer mode to status mode
2007 * then from status mode to command mode
2008 */
2009 if (fdctrl->data_pos == fdctrl->data_len)
2010 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2011 return;
2012 }
2013 if (fdctrl->data_pos == 0) {
2014 /* Command */
2015 pos = command_to_handler[value & 0xff];
2016 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
2017 fdctrl->data_len = handlers[pos].parameters + 1;
2018 fdctrl->msr |= FD_MSR_CMDBUSY;
2019 }
2020
2021 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2022 fdctrl->fifo[fdctrl->data_pos++] = value;
2023 if (fdctrl->data_pos == fdctrl->data_len) {
2024 /* We now have all parameters
2025 * and will be able to treat the command
2026 */
2027 if (fdctrl->data_state & FD_STATE_FORMAT) {
2028 fdctrl_format_sector(fdctrl);
2029 return;
2030 }
2031
2032 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
2033 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
2034 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
2035 }
2036 }
2037
2038 static void fdctrl_result_timer(void *opaque)
2039 {
2040 FDCtrl *fdctrl = opaque;
2041 FDrive *cur_drv = get_cur_drv(fdctrl);
2042
2043 /* Pretend we are spinning.
2044 * This is needed for Coherent, which uses READ ID to check for
2045 * sector interleaving.
2046 */
2047 if (cur_drv->last_sect != 0) {
2048 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2049 }
2050 /* READ_ID can't automatically succeed! */
2051 if (fdctrl->check_media_rate &&
2052 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2053 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2054 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2055 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2056 } else {
2057 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2058 }
2059 }
2060
2061 static void fdctrl_change_cb(void *opaque, bool load)
2062 {
2063 FDrive *drive = opaque;
2064
2065 drive->media_changed = 1;
2066 fd_revalidate(drive);
2067 }
2068
2069 static const BlockDevOps fdctrl_block_ops = {
2070 .change_media_cb = fdctrl_change_cb,
2071 };
2072
2073 /* Init functions */
2074 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
2075 {
2076 unsigned int i;
2077 FDrive *drive;
2078
2079 for (i = 0; i < MAX_FD; i++) {
2080 drive = &fdctrl->drives[i];
2081 drive->fdctrl = fdctrl;
2082
2083 if (drive->blk) {
2084 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
2085 error_setg(errp, "fdc doesn't support drive option werror");
2086 return;
2087 }
2088 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2089 error_setg(errp, "fdc doesn't support drive option rerror");
2090 return;
2091 }
2092 }
2093
2094 fd_init(drive);
2095 fdctrl_change_cb(drive, 0);
2096 if (drive->blk) {
2097 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
2098 }
2099 }
2100 }
2101
2102 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2103 {
2104 DeviceState *dev;
2105 ISADevice *isadev;
2106
2107 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2108 if (!isadev) {
2109 return NULL;
2110 }
2111 dev = DEVICE(isadev);
2112
2113 if (fds[0]) {
2114 qdev_prop_set_drive_nofail(dev, "driveA", blk_by_legacy_dinfo(fds[0]));
2115 }
2116 if (fds[1]) {
2117 qdev_prop_set_drive_nofail(dev, "driveB", blk_by_legacy_dinfo(fds[1]));
2118 }
2119 qdev_init_nofail(dev);
2120
2121 return isadev;
2122 }
2123
2124 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2125 hwaddr mmio_base, DriveInfo **fds)
2126 {
2127 FDCtrl *fdctrl;
2128 DeviceState *dev;
2129 SysBusDevice *sbd;
2130 FDCtrlSysBus *sys;
2131
2132 dev = qdev_create(NULL, "sysbus-fdc");
2133 sys = SYSBUS_FDC(dev);
2134 fdctrl = &sys->state;
2135 fdctrl->dma_chann = dma_chann; /* FIXME */
2136 if (fds[0]) {
2137 qdev_prop_set_drive_nofail(dev, "driveA", blk_by_legacy_dinfo(fds[0]));
2138 }
2139 if (fds[1]) {
2140 qdev_prop_set_drive_nofail(dev, "driveB", blk_by_legacy_dinfo(fds[1]));
2141 }
2142 qdev_init_nofail(dev);
2143 sbd = SYS_BUS_DEVICE(dev);
2144 sysbus_connect_irq(sbd, 0, irq);
2145 sysbus_mmio_map(sbd, 0, mmio_base);
2146 }
2147
2148 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2149 DriveInfo **fds, qemu_irq *fdc_tc)
2150 {
2151 DeviceState *dev;
2152 FDCtrlSysBus *sys;
2153
2154 dev = qdev_create(NULL, "SUNW,fdtwo");
2155 if (fds[0]) {
2156 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(fds[0]));
2157 }
2158 qdev_init_nofail(dev);
2159 sys = SYSBUS_FDC(dev);
2160 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2161 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2162 *fdc_tc = qdev_get_gpio_in(dev, 0);
2163 }
2164
2165 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
2166 {
2167 int i, j;
2168 static int command_tables_inited = 0;
2169
2170 /* Fill 'command_to_handler' lookup table */
2171 if (!command_tables_inited) {
2172 command_tables_inited = 1;
2173 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2174 for (j = 0; j < sizeof(command_to_handler); j++) {
2175 if ((j & handlers[i].mask) == handlers[i].value) {
2176 command_to_handler[j] = i;
2177 }
2178 }
2179 }
2180 }
2181
2182 FLOPPY_DPRINTF("init controller\n");
2183 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2184 fdctrl->fifo_size = 512;
2185 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2186 fdctrl_result_timer, fdctrl);
2187
2188 fdctrl->version = 0x90; /* Intel 82078 controller */
2189 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2190 fdctrl->num_floppies = MAX_FD;
2191
2192 if (fdctrl->dma_chann != -1) {
2193 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
2194 }
2195 fdctrl_connect_drives(fdctrl, errp);
2196 }
2197
2198 static const MemoryRegionPortio fdc_portio_list[] = {
2199 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2200 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2201 PORTIO_END_OF_LIST(),
2202 };
2203
2204 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2205 {
2206 ISADevice *isadev = ISA_DEVICE(dev);
2207 FDCtrlISABus *isa = ISA_FDC(dev);
2208 FDCtrl *fdctrl = &isa->state;
2209 Error *err = NULL;
2210
2211 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2212 "fdc");
2213
2214 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2215 fdctrl->dma_chann = isa->dma;
2216
2217 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2218 fdctrl_realize_common(fdctrl, &err);
2219 if (err != NULL) {
2220 error_propagate(errp, err);
2221 return;
2222 }
2223 }
2224
2225 static void sysbus_fdc_initfn(Object *obj)
2226 {
2227 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2228 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2229 FDCtrl *fdctrl = &sys->state;
2230
2231 fdctrl->dma_chann = -1;
2232
2233 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2234 "fdc", 0x08);
2235 sysbus_init_mmio(sbd, &fdctrl->iomem);
2236 }
2237
2238 static void sun4m_fdc_initfn(Object *obj)
2239 {
2240 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2241 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2242 FDCtrl *fdctrl = &sys->state;
2243
2244 fdctrl->sun4m = 1;
2245
2246 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2247 fdctrl, "fdctrl", 0x08);
2248 sysbus_init_mmio(sbd, &fdctrl->iomem);
2249 }
2250
2251 static void sysbus_fdc_common_initfn(Object *obj)
2252 {
2253 DeviceState *dev = DEVICE(obj);
2254 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2255 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2256 FDCtrl *fdctrl = &sys->state;
2257
2258 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2259
2260 sysbus_init_irq(sbd, &fdctrl->irq);
2261 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2262 }
2263
2264 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2265 {
2266 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2267 FDCtrl *fdctrl = &sys->state;
2268
2269 fdctrl_realize_common(fdctrl, errp);
2270 }
2271
2272 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2273 {
2274 FDCtrlISABus *isa = ISA_FDC(fdc);
2275
2276 return isa->state.drives[i].drive;
2277 }
2278
2279 static const VMStateDescription vmstate_isa_fdc ={
2280 .name = "fdc",
2281 .version_id = 2,
2282 .minimum_version_id = 2,
2283 .fields = (VMStateField[]) {
2284 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2285 VMSTATE_END_OF_LIST()
2286 }
2287 };
2288
2289 static Property isa_fdc_properties[] = {
2290 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2291 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2292 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2293 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2294 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
2295 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2296 0, true),
2297 DEFINE_PROP_END_OF_LIST(),
2298 };
2299
2300 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2301 {
2302 DeviceClass *dc = DEVICE_CLASS(klass);
2303
2304 dc->realize = isabus_fdc_realize;
2305 dc->fw_name = "fdc";
2306 dc->reset = fdctrl_external_reset_isa;
2307 dc->vmsd = &vmstate_isa_fdc;
2308 dc->props = isa_fdc_properties;
2309 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2310 }
2311
2312 static void isabus_fdc_instance_init(Object *obj)
2313 {
2314 FDCtrlISABus *isa = ISA_FDC(obj);
2315
2316 device_add_bootindex_property(obj, &isa->bootindexA,
2317 "bootindexA", "/floppy@0",
2318 DEVICE(obj), NULL);
2319 device_add_bootindex_property(obj, &isa->bootindexB,
2320 "bootindexB", "/floppy@1",
2321 DEVICE(obj), NULL);
2322 }
2323
2324 static const TypeInfo isa_fdc_info = {
2325 .name = TYPE_ISA_FDC,
2326 .parent = TYPE_ISA_DEVICE,
2327 .instance_size = sizeof(FDCtrlISABus),
2328 .class_init = isabus_fdc_class_init,
2329 .instance_init = isabus_fdc_instance_init,
2330 };
2331
2332 static const VMStateDescription vmstate_sysbus_fdc ={
2333 .name = "fdc",
2334 .version_id = 2,
2335 .minimum_version_id = 2,
2336 .fields = (VMStateField[]) {
2337 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2338 VMSTATE_END_OF_LIST()
2339 }
2340 };
2341
2342 static Property sysbus_fdc_properties[] = {
2343 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2344 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
2345 DEFINE_PROP_END_OF_LIST(),
2346 };
2347
2348 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2349 {
2350 DeviceClass *dc = DEVICE_CLASS(klass);
2351
2352 dc->props = sysbus_fdc_properties;
2353 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2354 }
2355
2356 static const TypeInfo sysbus_fdc_info = {
2357 .name = "sysbus-fdc",
2358 .parent = TYPE_SYSBUS_FDC,
2359 .instance_init = sysbus_fdc_initfn,
2360 .class_init = sysbus_fdc_class_init,
2361 };
2362
2363 static Property sun4m_fdc_properties[] = {
2364 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
2365 DEFINE_PROP_END_OF_LIST(),
2366 };
2367
2368 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2369 {
2370 DeviceClass *dc = DEVICE_CLASS(klass);
2371
2372 dc->props = sun4m_fdc_properties;
2373 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2374 }
2375
2376 static const TypeInfo sun4m_fdc_info = {
2377 .name = "SUNW,fdtwo",
2378 .parent = TYPE_SYSBUS_FDC,
2379 .instance_init = sun4m_fdc_initfn,
2380 .class_init = sun4m_fdc_class_init,
2381 };
2382
2383 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2384 {
2385 DeviceClass *dc = DEVICE_CLASS(klass);
2386
2387 dc->realize = sysbus_fdc_common_realize;
2388 dc->reset = fdctrl_external_reset_sysbus;
2389 dc->vmsd = &vmstate_sysbus_fdc;
2390 }
2391
2392 static const TypeInfo sysbus_fdc_type_info = {
2393 .name = TYPE_SYSBUS_FDC,
2394 .parent = TYPE_SYS_BUS_DEVICE,
2395 .instance_size = sizeof(FDCtrlSysBus),
2396 .instance_init = sysbus_fdc_common_initfn,
2397 .abstract = true,
2398 .class_init = sysbus_fdc_common_class_init,
2399 };
2400
2401 static void fdc_register_types(void)
2402 {
2403 type_register_static(&isa_fdc_info);
2404 type_register_static(&sysbus_fdc_type_info);
2405 type_register_static(&sysbus_fdc_info);
2406 type_register_static(&sun4m_fdc_info);
2407 }
2408
2409 type_init(fdc_register_types)
AR7 emulation for QEMU