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target/s390x: check alignment in CDSG in the !CONFIG_ATOMIC128 case
[qemu/ar7.git] / target / ppc / translate.c
blobc0cd64d927c234dcb870090f38759cf2bb53bb07
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_env cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87 static int done_init = 0;
88
89 if (done_init)
90 return;
91
92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
93 tcg_ctx.tcg_env = cpu_env;
94
95 p = cpu_reg_names;
96 cpu_reg_names_size = sizeof(cpu_reg_names);
97
98 for (i = 0; i < 8; i++) {
99 snprintf(p, cpu_reg_names_size, "crf%d", i);
100 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
101 offsetof(CPUPPCState, crf[i]), p);
102 p += 5;
103 cpu_reg_names_size -= 5;
104 }
105
106 for (i = 0; i < 32; i++) {
107 snprintf(p, cpu_reg_names_size, "r%d", i);
108 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
109 offsetof(CPUPPCState, gpr[i]), p);
110 p += (i < 10) ? 3 : 4;
111 cpu_reg_names_size -= (i < 10) ? 3 : 4;
112 snprintf(p, cpu_reg_names_size, "r%dH", i);
113 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
114 offsetof(CPUPPCState, gprh[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "fp%d", i);
119 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
120 offsetof(CPUPPCState, fpr[i]), p);
121 p += (i < 10) ? 4 : 5;
122 cpu_reg_names_size -= (i < 10) ? 4 : 5;
123
124 snprintf(p, cpu_reg_names_size, "avr%dH", i);
125 #ifdef HOST_WORDS_BIGENDIAN
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[0]), p);
128 #else
129 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
130 offsetof(CPUPPCState, avr[i].u64[1]), p);
131 #endif
132 p += (i < 10) ? 6 : 7;
133 cpu_reg_names_size -= (i < 10) ? 6 : 7;
134
135 snprintf(p, cpu_reg_names_size, "avr%dL", i);
136 #ifdef HOST_WORDS_BIGENDIAN
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[1]), p);
139 #else
140 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
141 offsetof(CPUPPCState, avr[i].u64[0]), p);
142 #endif
143 p += (i < 10) ? 6 : 7;
144 cpu_reg_names_size -= (i < 10) ? 6 : 7;
145 snprintf(p, cpu_reg_names_size, "vsr%d", i);
146 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
147 offsetof(CPUPPCState, vsr[i]), p);
148 p += (i < 10) ? 5 : 6;
149 cpu_reg_names_size -= (i < 10) ? 5 : 6;
150 }
151
152 cpu_nip = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, nip), "nip");
154
155 cpu_msr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, msr), "msr");
157
158 cpu_ctr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, ctr), "ctr");
160
161 cpu_lr = tcg_global_mem_new(cpu_env,
162 offsetof(CPUPPCState, lr), "lr");
163
164 #if defined(TARGET_PPC64)
165 cpu_cfar = tcg_global_mem_new(cpu_env,
166 offsetof(CPUPPCState, cfar), "cfar");
167 #endif
168
169 cpu_xer = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, xer), "xer");
171 cpu_so = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, so), "SO");
173 cpu_ov = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ov), "OV");
175 cpu_ca = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, ca), "CA");
177 cpu_ov32 = tcg_global_mem_new(cpu_env,
178 offsetof(CPUPPCState, ov32), "OV32");
179 cpu_ca32 = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, ca32), "CA32");
181
182 cpu_reserve = tcg_global_mem_new(cpu_env,
183 offsetof(CPUPPCState, reserve_addr),
184 "reserve_addr");
185 cpu_reserve_val = tcg_global_mem_new(cpu_env,
186 offsetof(CPUPPCState, reserve_val),
187 "reserve_val");
188
189 cpu_fpscr = tcg_global_mem_new(cpu_env,
190 offsetof(CPUPPCState, fpscr), "fpscr");
191
192 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
193 offsetof(CPUPPCState, access_type), "access_type");
194
195 done_init = 1;
196 }
197
198 /* internal defines */
199 struct DisasContext {
200 struct TranslationBlock *tb;
201 target_ulong nip;
202 uint32_t opcode;
203 uint32_t exception;
204 /* Routine used to access memory */
205 bool pr, hv, dr, le_mode;
206 bool lazy_tlb_flush;
207 bool need_access_type;
208 int mem_idx;
209 int access_type;
210 /* Translation flags */
211 TCGMemOp default_tcg_memop_mask;
212 #if defined(TARGET_PPC64)
213 bool sf_mode;
214 bool has_cfar;
215 #endif
216 bool fpu_enabled;
217 bool altivec_enabled;
218 bool vsx_enabled;
219 bool spe_enabled;
220 bool tm_enabled;
221 bool gtse;
222 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
223 int singlestep_enabled;
224 uint64_t insns_flags;
225 uint64_t insns_flags2;
226 };
227
228 /* Return true iff byteswap is needed in a scalar memop */
229 static inline bool need_byteswap(const DisasContext *ctx)
230 {
231 #if defined(TARGET_WORDS_BIGENDIAN)
232 return ctx->le_mode;
233 #else
234 return !ctx->le_mode;
235 #endif
236 }
237
238 /* True when active word size < size of target_long. */
239 #ifdef TARGET_PPC64
240 # define NARROW_MODE(C) (!(C)->sf_mode)
241 #else
242 # define NARROW_MODE(C) 0
243 #endif
244
245 struct opc_handler_t {
246 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
247 uint32_t inval1;
248 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
249 uint32_t inval2;
250 /* instruction type */
251 uint64_t type;
252 /* extended instruction type */
253 uint64_t type2;
254 /* handler */
255 void (*handler)(DisasContext *ctx);
256 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
257 const char *oname;
258 #endif
259 #if defined(DO_PPC_STATISTICS)
260 uint64_t count;
261 #endif
262 };
263
264 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
265 {
266 if (ctx->need_access_type && ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
270 }
271
272 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
273 {
274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
278 }
279
280 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
281 {
282 TCGv_i32 t0, t1;
283
284 /* These are all synchronous exceptions, we set the PC back to
285 * the faulting instruction
286 */
287 if (ctx->exception == POWERPC_EXCP_NONE) {
288 gen_update_nip(ctx, ctx->nip - 4);
289 }
290 t0 = tcg_const_i32(excp);
291 t1 = tcg_const_i32(error);
292 gen_helper_raise_exception_err(cpu_env, t0, t1);
293 tcg_temp_free_i32(t0);
294 tcg_temp_free_i32(t1);
295 ctx->exception = (excp);
296 }
297
298 static void gen_exception(DisasContext *ctx, uint32_t excp)
299 {
300 TCGv_i32 t0;
301
302 /* These are all synchronous exceptions, we set the PC back to
303 * the faulting instruction
304 */
305 if (ctx->exception == POWERPC_EXCP_NONE) {
306 gen_update_nip(ctx, ctx->nip - 4);
307 }
308 t0 = tcg_const_i32(excp);
309 gen_helper_raise_exception(cpu_env, t0);
310 tcg_temp_free_i32(t0);
311 ctx->exception = (excp);
312 }
313
314 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
315 target_ulong nip)
316 {
317 TCGv_i32 t0;
318
319 gen_update_nip(ctx, nip);
320 t0 = tcg_const_i32(excp);
321 gen_helper_raise_exception(cpu_env, t0);
322 tcg_temp_free_i32(t0);
323 ctx->exception = (excp);
324 }
325
326 static void gen_debug_exception(DisasContext *ctx)
327 {
328 TCGv_i32 t0;
329
330 /* These are all synchronous exceptions, we set the PC back to
331 * the faulting instruction
332 */
333 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
334 (ctx->exception != POWERPC_EXCP_SYNC)) {
335 gen_update_nip(ctx, ctx->nip);
336 }
337 t0 = tcg_const_i32(EXCP_DEBUG);
338 gen_helper_raise_exception(cpu_env, t0);
339 tcg_temp_free_i32(t0);
340 }
341
342 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
343 {
344 /* Will be converted to program check if needed */
345 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
346 }
347
348 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
349 {
350 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
351 }
352
353 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
354 {
355 /* Will be converted to program check if needed */
356 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
357 }
358
359 /* Stop translation */
360 static inline void gen_stop_exception(DisasContext *ctx)
361 {
362 gen_update_nip(ctx, ctx->nip);
363 ctx->exception = POWERPC_EXCP_STOP;
364 }
365
366 #ifndef CONFIG_USER_ONLY
367 /* No need to update nip here, as execution flow will change */
368 static inline void gen_sync_exception(DisasContext *ctx)
369 {
370 ctx->exception = POWERPC_EXCP_SYNC;
371 }
372 #endif
373
374 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
375 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
376
377 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
378 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
379
380 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
381 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
382
383 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
384 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
385
386 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
387 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
388
389 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
390 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
391
392 typedef struct opcode_t {
393 unsigned char opc1, opc2, opc3, opc4;
394 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
395 unsigned char pad[4];
396 #endif
397 opc_handler_t handler;
398 const char *oname;
399 } opcode_t;
400
401 /* Helpers for priv. check */
402 #define GEN_PRIV \
403 do { \
404 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
405 } while (0)
406
407 #if defined(CONFIG_USER_ONLY)
408 #define CHK_HV GEN_PRIV
409 #define CHK_SV GEN_PRIV
410 #define CHK_HVRM GEN_PRIV
411 #else
412 #define CHK_HV \
413 do { \
414 if (unlikely(ctx->pr || !ctx->hv)) { \
415 GEN_PRIV; \
416 } \
417 } while (0)
418 #define CHK_SV \
419 do { \
420 if (unlikely(ctx->pr)) { \
421 GEN_PRIV; \
422 } \
423 } while (0)
424 #define CHK_HVRM \
425 do { \
426 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
427 GEN_PRIV; \
428 } \
429 } while (0)
430 #endif
431
432 #define CHK_NONE
433
434 /*****************************************************************************/
435 /* PowerPC instructions table */
436
437 #if defined(DO_PPC_STATISTICS)
438 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
439 { \
440 .opc1 = op1, \
441 .opc2 = op2, \
442 .opc3 = op3, \
443 .opc4 = 0xff, \
444 .handler = { \
445 .inval1 = invl, \
446 .type = _typ, \
447 .type2 = _typ2, \
448 .handler = &gen_##name, \
449 .oname = stringify(name), \
450 }, \
451 .oname = stringify(name), \
452 }
453 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
454 { \
455 .opc1 = op1, \
456 .opc2 = op2, \
457 .opc3 = op3, \
458 .opc4 = 0xff, \
459 .handler = { \
460 .inval1 = invl1, \
461 .inval2 = invl2, \
462 .type = _typ, \
463 .type2 = _typ2, \
464 .handler = &gen_##name, \
465 .oname = stringify(name), \
466 }, \
467 .oname = stringify(name), \
468 }
469 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
470 { \
471 .opc1 = op1, \
472 .opc2 = op2, \
473 .opc3 = op3, \
474 .opc4 = 0xff, \
475 .handler = { \
476 .inval1 = invl, \
477 .type = _typ, \
478 .type2 = _typ2, \
479 .handler = &gen_##name, \
480 .oname = onam, \
481 }, \
482 .oname = onam, \
483 }
484 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
485 { \
486 .opc1 = op1, \
487 .opc2 = op2, \
488 .opc3 = op3, \
489 .opc4 = op4, \
490 .handler = { \
491 .inval1 = invl, \
492 .type = _typ, \
493 .type2 = _typ2, \
494 .handler = &gen_##name, \
495 .oname = stringify(name), \
496 }, \
497 .oname = stringify(name), \
498 }
499 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
500 { \
501 .opc1 = op1, \
502 .opc2 = op2, \
503 .opc3 = op3, \
504 .opc4 = op4, \
505 .handler = { \
506 .inval1 = invl, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = onam, \
511 }, \
512 .oname = onam, \
513 }
514 #else
515 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
516 { \
517 .opc1 = op1, \
518 .opc2 = op2, \
519 .opc3 = op3, \
520 .opc4 = 0xff, \
521 .handler = { \
522 .inval1 = invl, \
523 .type = _typ, \
524 .type2 = _typ2, \
525 .handler = &gen_##name, \
526 }, \
527 .oname = stringify(name), \
528 }
529 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
530 { \
531 .opc1 = op1, \
532 .opc2 = op2, \
533 .opc3 = op3, \
534 .opc4 = 0xff, \
535 .handler = { \
536 .inval1 = invl1, \
537 .inval2 = invl2, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .opc4 = 0xff, \
550 .handler = { \
551 .inval1 = invl, \
552 .type = _typ, \
553 .type2 = _typ2, \
554 .handler = &gen_##name, \
555 }, \
556 .oname = onam, \
557 }
558 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
559 { \
560 .opc1 = op1, \
561 .opc2 = op2, \
562 .opc3 = op3, \
563 .opc4 = op4, \
564 .handler = { \
565 .inval1 = invl, \
566 .type = _typ, \
567 .type2 = _typ2, \
568 .handler = &gen_##name, \
569 }, \
570 .oname = stringify(name), \
571 }
572 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
573 { \
574 .opc1 = op1, \
575 .opc2 = op2, \
576 .opc3 = op3, \
577 .opc4 = op4, \
578 .handler = { \
579 .inval1 = invl, \
580 .type = _typ, \
581 .type2 = _typ2, \
582 .handler = &gen_##name, \
583 }, \
584 .oname = onam, \
585 }
586 #endif
587
588 /* SPR load/store helpers */
589 static inline void gen_load_spr(TCGv t, int reg)
590 {
591 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
592 }
593
594 static inline void gen_store_spr(int reg, TCGv t)
595 {
596 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
597 }
598
599 /* Invalid instruction */
600 static void gen_invalid(DisasContext *ctx)
601 {
602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
603 }
604
605 static opc_handler_t invalid_handler = {
606 .inval1 = 0xFFFFFFFF,
607 .inval2 = 0xFFFFFFFF,
608 .type = PPC_NONE,
609 .type2 = PPC_NONE,
610 .handler = gen_invalid,
611 };
612
613 /*** Integer comparison ***/
614
615 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
616 {
617 TCGv t0 = tcg_temp_new();
618 TCGv_i32 t1 = tcg_temp_new_i32();
619
620 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
621
622 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
623 tcg_gen_trunc_tl_i32(t1, t0);
624 tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
625 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
626
627 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
628 tcg_gen_trunc_tl_i32(t1, t0);
629 tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
630 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
631
632 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
633 tcg_gen_trunc_tl_i32(t1, t0);
634 tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
635 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
636
637 tcg_temp_free(t0);
638 tcg_temp_free_i32(t1);
639 }
640
641 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
642 {
643 TCGv t0 = tcg_const_tl(arg1);
644 gen_op_cmp(arg0, t0, s, crf);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
649 {
650 TCGv t0, t1;
651 t0 = tcg_temp_new();
652 t1 = tcg_temp_new();
653 if (s) {
654 tcg_gen_ext32s_tl(t0, arg0);
655 tcg_gen_ext32s_tl(t1, arg1);
656 } else {
657 tcg_gen_ext32u_tl(t0, arg0);
658 tcg_gen_ext32u_tl(t1, arg1);
659 }
660 gen_op_cmp(t0, t1, s, crf);
661 tcg_temp_free(t1);
662 tcg_temp_free(t0);
663 }
664
665 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
666 {
667 TCGv t0 = tcg_const_tl(arg1);
668 gen_op_cmp32(arg0, t0, s, crf);
669 tcg_temp_free(t0);
670 }
671
672 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
673 {
674 if (NARROW_MODE(ctx)) {
675 gen_op_cmpi32(reg, 0, 1, 0);
676 } else {
677 gen_op_cmpi(reg, 0, 1, 0);
678 }
679 }
680
681 /* cmp */
682 static void gen_cmp(DisasContext *ctx)
683 {
684 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
685 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
686 1, crfD(ctx->opcode));
687 } else {
688 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
689 1, crfD(ctx->opcode));
690 }
691 }
692
693 /* cmpi */
694 static void gen_cmpi(DisasContext *ctx)
695 {
696 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
697 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
698 1, crfD(ctx->opcode));
699 } else {
700 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
701 1, crfD(ctx->opcode));
702 }
703 }
704
705 /* cmpl */
706 static void gen_cmpl(DisasContext *ctx)
707 {
708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
709 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
710 0, crfD(ctx->opcode));
711 } else {
712 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 0, crfD(ctx->opcode));
714 }
715 }
716
717 /* cmpli */
718 static void gen_cmpli(DisasContext *ctx)
719 {
720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
721 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
722 0, crfD(ctx->opcode));
723 } else {
724 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
725 0, crfD(ctx->opcode));
726 }
727 }
728
729 /* cmprb - range comparison: isupper, isaplha, islower*/
730 static void gen_cmprb(DisasContext *ctx)
731 {
732 TCGv_i32 src1 = tcg_temp_new_i32();
733 TCGv_i32 src2 = tcg_temp_new_i32();
734 TCGv_i32 src2lo = tcg_temp_new_i32();
735 TCGv_i32 src2hi = tcg_temp_new_i32();
736 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
737
738 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
739 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
740
741 tcg_gen_andi_i32(src1, src1, 0xFF);
742 tcg_gen_ext8u_i32(src2lo, src2);
743 tcg_gen_shri_i32(src2, src2, 8);
744 tcg_gen_ext8u_i32(src2hi, src2);
745
746 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
747 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
748 tcg_gen_and_i32(crf, src2lo, src2hi);
749
750 if (ctx->opcode & 0x00200000) {
751 tcg_gen_shri_i32(src2, src2, 8);
752 tcg_gen_ext8u_i32(src2lo, src2);
753 tcg_gen_shri_i32(src2, src2, 8);
754 tcg_gen_ext8u_i32(src2hi, src2);
755 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
756 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
757 tcg_gen_and_i32(src2lo, src2lo, src2hi);
758 tcg_gen_or_i32(crf, crf, src2lo);
759 }
760 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
761 tcg_temp_free_i32(src1);
762 tcg_temp_free_i32(src2);
763 tcg_temp_free_i32(src2lo);
764 tcg_temp_free_i32(src2hi);
765 }
766
767 #if defined(TARGET_PPC64)
768 /* cmpeqb */
769 static void gen_cmpeqb(DisasContext *ctx)
770 {
771 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
772 cpu_gpr[rB(ctx->opcode)]);
773 }
774 #endif
775
776 /* isel (PowerPC 2.03 specification) */
777 static void gen_isel(DisasContext *ctx)
778 {
779 uint32_t bi = rC(ctx->opcode);
780 uint32_t mask = 0x08 >> (bi & 0x03);
781 TCGv t0 = tcg_temp_new();
782 TCGv zr;
783
784 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
785 tcg_gen_andi_tl(t0, t0, mask);
786
787 zr = tcg_const_tl(0);
788 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
789 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
790 cpu_gpr[rB(ctx->opcode)]);
791 tcg_temp_free(zr);
792 tcg_temp_free(t0);
793 }
794
795 /* cmpb: PowerPC 2.05 specification */
796 static void gen_cmpb(DisasContext *ctx)
797 {
798 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
799 cpu_gpr[rB(ctx->opcode)]);
800 }
801
802 /*** Integer arithmetic ***/
803
804 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
805 TCGv arg1, TCGv arg2, int sub)
806 {
807 TCGv t0 = tcg_temp_new();
808
809 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
810 tcg_gen_xor_tl(t0, arg1, arg2);
811 if (sub) {
812 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
813 } else {
814 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
815 }
816 tcg_temp_free(t0);
817 if (NARROW_MODE(ctx)) {
818 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
819 if (is_isa300(ctx)) {
820 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
821 }
822 } else {
823 if (is_isa300(ctx)) {
824 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
825 }
826 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
827 }
828 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
829 }
830
831 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
832 TCGv res, TCGv arg0, TCGv arg1,
833 int sub)
834 {
835 TCGv t0;
836
837 if (!is_isa300(ctx)) {
838 return;
839 }
840
841 t0 = tcg_temp_new();
842 if (sub) {
843 tcg_gen_eqv_tl(t0, arg0, arg1);
844 } else {
845 tcg_gen_xor_tl(t0, arg0, arg1);
846 }
847 tcg_gen_xor_tl(t0, t0, res);
848 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
849 tcg_temp_free(t0);
850 }
851
852 /* Common add function */
853 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
854 TCGv arg2, bool add_ca, bool compute_ca,
855 bool compute_ov, bool compute_rc0)
856 {
857 TCGv t0 = ret;
858
859 if (compute_ca || compute_ov) {
860 t0 = tcg_temp_new();
861 }
862
863 if (compute_ca) {
864 if (NARROW_MODE(ctx)) {
865 /* Caution: a non-obvious corner case of the spec is that we
866 must produce the *entire* 64-bit addition, but produce the
867 carry into bit 32. */
868 TCGv t1 = tcg_temp_new();
869 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
870 tcg_gen_add_tl(t0, arg1, arg2);
871 if (add_ca) {
872 tcg_gen_add_tl(t0, t0, cpu_ca);
873 }
874 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
875 tcg_temp_free(t1);
876 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
877 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
878 if (is_isa300(ctx)) {
879 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
880 }
881 } else {
882 TCGv zero = tcg_const_tl(0);
883 if (add_ca) {
884 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
885 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
886 } else {
887 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
888 }
889 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
890 tcg_temp_free(zero);
891 }
892 } else {
893 tcg_gen_add_tl(t0, arg1, arg2);
894 if (add_ca) {
895 tcg_gen_add_tl(t0, t0, cpu_ca);
896 }
897 }
898
899 if (compute_ov) {
900 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
901 }
902 if (unlikely(compute_rc0)) {
903 gen_set_Rc0(ctx, t0);
904 }
905
906 if (!TCGV_EQUAL(t0, ret)) {
907 tcg_gen_mov_tl(ret, t0);
908 tcg_temp_free(t0);
909 }
910 }
911 /* Add functions with two operands */
912 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
913 static void glue(gen_, name)(DisasContext *ctx) \
914 { \
915 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
916 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
917 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
918 }
919 /* Add functions with one operand and one immediate */
920 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
921 add_ca, compute_ca, compute_ov) \
922 static void glue(gen_, name)(DisasContext *ctx) \
923 { \
924 TCGv t0 = tcg_const_tl(const_val); \
925 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
926 cpu_gpr[rA(ctx->opcode)], t0, \
927 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
928 tcg_temp_free(t0); \
929 }
930
931 /* add add. addo addo. */
932 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
933 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
934 /* addc addc. addco addco. */
935 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
936 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
937 /* adde adde. addeo addeo. */
938 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
939 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
940 /* addme addme. addmeo addmeo. */
941 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
942 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
943 /* addze addze. addzeo addzeo.*/
944 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
945 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
946 /* addi */
947 static void gen_addi(DisasContext *ctx)
948 {
949 target_long simm = SIMM(ctx->opcode);
950
951 if (rA(ctx->opcode) == 0) {
952 /* li case */
953 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
954 } else {
955 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
956 cpu_gpr[rA(ctx->opcode)], simm);
957 }
958 }
959 /* addic addic.*/
960 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
961 {
962 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
963 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
964 c, 0, 1, 0, compute_rc0);
965 tcg_temp_free(c);
966 }
967
968 static void gen_addic(DisasContext *ctx)
969 {
970 gen_op_addic(ctx, 0);
971 }
972
973 static void gen_addic_(DisasContext *ctx)
974 {
975 gen_op_addic(ctx, 1);
976 }
977
978 /* addis */
979 static void gen_addis(DisasContext *ctx)
980 {
981 target_long simm = SIMM(ctx->opcode);
982
983 if (rA(ctx->opcode) == 0) {
984 /* lis case */
985 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
986 } else {
987 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
988 cpu_gpr[rA(ctx->opcode)], simm << 16);
989 }
990 }
991
992 /* addpcis */
993 static void gen_addpcis(DisasContext *ctx)
994 {
995 target_long d = DX(ctx->opcode);
996
997 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
998 }
999
1000 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1001 TCGv arg2, int sign, int compute_ov)
1002 {
1003 TCGv_i32 t0 = tcg_temp_new_i32();
1004 TCGv_i32 t1 = tcg_temp_new_i32();
1005 TCGv_i32 t2 = tcg_temp_new_i32();
1006 TCGv_i32 t3 = tcg_temp_new_i32();
1007
1008 tcg_gen_trunc_tl_i32(t0, arg1);
1009 tcg_gen_trunc_tl_i32(t1, arg2);
1010 if (sign) {
1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1012 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1013 tcg_gen_and_i32(t2, t2, t3);
1014 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1015 tcg_gen_or_i32(t2, t2, t3);
1016 tcg_gen_movi_i32(t3, 0);
1017 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1018 tcg_gen_div_i32(t3, t0, t1);
1019 tcg_gen_extu_i32_tl(ret, t3);
1020 } else {
1021 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1022 tcg_gen_movi_i32(t3, 0);
1023 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1024 tcg_gen_divu_i32(t3, t0, t1);
1025 tcg_gen_extu_i32_tl(ret, t3);
1026 }
1027 if (compute_ov) {
1028 tcg_gen_extu_i32_tl(cpu_ov, t2);
1029 if (is_isa300(ctx)) {
1030 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1031 }
1032 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1033 }
1034 tcg_temp_free_i32(t0);
1035 tcg_temp_free_i32(t1);
1036 tcg_temp_free_i32(t2);
1037 tcg_temp_free_i32(t3);
1038
1039 if (unlikely(Rc(ctx->opcode) != 0))
1040 gen_set_Rc0(ctx, ret);
1041 }
1042 /* Div functions */
1043 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1044 static void glue(gen_, name)(DisasContext *ctx) \
1045 { \
1046 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1047 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1048 sign, compute_ov); \
1049 }
1050 /* divwu divwu. divwuo divwuo. */
1051 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1052 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1053 /* divw divw. divwo divwo. */
1054 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1055 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1056
1057 /* div[wd]eu[o][.] */
1058 #define GEN_DIVE(name, hlpr, compute_ov) \
1059 static void gen_##name(DisasContext *ctx) \
1060 { \
1061 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1062 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1063 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1064 tcg_temp_free_i32(t0); \
1065 if (unlikely(Rc(ctx->opcode) != 0)) { \
1066 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1067 } \
1068 }
1069
1070 GEN_DIVE(divweu, divweu, 0);
1071 GEN_DIVE(divweuo, divweu, 1);
1072 GEN_DIVE(divwe, divwe, 0);
1073 GEN_DIVE(divweo, divwe, 1);
1074
1075 #if defined(TARGET_PPC64)
1076 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1077 TCGv arg2, int sign, int compute_ov)
1078 {
1079 TCGv_i64 t0 = tcg_temp_new_i64();
1080 TCGv_i64 t1 = tcg_temp_new_i64();
1081 TCGv_i64 t2 = tcg_temp_new_i64();
1082 TCGv_i64 t3 = tcg_temp_new_i64();
1083
1084 tcg_gen_mov_i64(t0, arg1);
1085 tcg_gen_mov_i64(t1, arg2);
1086 if (sign) {
1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1088 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1089 tcg_gen_and_i64(t2, t2, t3);
1090 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1091 tcg_gen_or_i64(t2, t2, t3);
1092 tcg_gen_movi_i64(t3, 0);
1093 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1094 tcg_gen_div_i64(ret, t0, t1);
1095 } else {
1096 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1097 tcg_gen_movi_i64(t3, 0);
1098 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1099 tcg_gen_divu_i64(ret, t0, t1);
1100 }
1101 if (compute_ov) {
1102 tcg_gen_mov_tl(cpu_ov, t2);
1103 if (is_isa300(ctx)) {
1104 tcg_gen_mov_tl(cpu_ov32, t2);
1105 }
1106 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1107 }
1108 tcg_temp_free_i64(t0);
1109 tcg_temp_free_i64(t1);
1110 tcg_temp_free_i64(t2);
1111 tcg_temp_free_i64(t3);
1112
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, ret);
1115 }
1116
1117 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1118 static void glue(gen_, name)(DisasContext *ctx) \
1119 { \
1120 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1121 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1122 sign, compute_ov); \
1123 }
1124 /* divdu divdu. divduo divduo. */
1125 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1126 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1127 /* divd divd. divdo divdo. */
1128 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1129 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1130
1131 GEN_DIVE(divdeu, divdeu, 0);
1132 GEN_DIVE(divdeuo, divdeu, 1);
1133 GEN_DIVE(divde, divde, 0);
1134 GEN_DIVE(divdeo, divde, 1);
1135 #endif
1136
1137 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1138 TCGv arg2, int sign)
1139 {
1140 TCGv_i32 t0 = tcg_temp_new_i32();
1141 TCGv_i32 t1 = tcg_temp_new_i32();
1142
1143 tcg_gen_trunc_tl_i32(t0, arg1);
1144 tcg_gen_trunc_tl_i32(t1, arg2);
1145 if (sign) {
1146 TCGv_i32 t2 = tcg_temp_new_i32();
1147 TCGv_i32 t3 = tcg_temp_new_i32();
1148 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1149 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1150 tcg_gen_and_i32(t2, t2, t3);
1151 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1152 tcg_gen_or_i32(t2, t2, t3);
1153 tcg_gen_movi_i32(t3, 0);
1154 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1155 tcg_gen_rem_i32(t3, t0, t1);
1156 tcg_gen_ext_i32_tl(ret, t3);
1157 tcg_temp_free_i32(t2);
1158 tcg_temp_free_i32(t3);
1159 } else {
1160 TCGv_i32 t2 = tcg_const_i32(1);
1161 TCGv_i32 t3 = tcg_const_i32(0);
1162 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1163 tcg_gen_remu_i32(t3, t0, t1);
1164 tcg_gen_extu_i32_tl(ret, t3);
1165 tcg_temp_free_i32(t2);
1166 tcg_temp_free_i32(t3);
1167 }
1168 tcg_temp_free_i32(t0);
1169 tcg_temp_free_i32(t1);
1170 }
1171
1172 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1173 static void glue(gen_, name)(DisasContext *ctx) \
1174 { \
1175 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1176 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1177 sign); \
1178 }
1179
1180 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1181 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1182
1183 #if defined(TARGET_PPC64)
1184 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1185 TCGv arg2, int sign)
1186 {
1187 TCGv_i64 t0 = tcg_temp_new_i64();
1188 TCGv_i64 t1 = tcg_temp_new_i64();
1189
1190 tcg_gen_mov_i64(t0, arg1);
1191 tcg_gen_mov_i64(t1, arg2);
1192 if (sign) {
1193 TCGv_i64 t2 = tcg_temp_new_i64();
1194 TCGv_i64 t3 = tcg_temp_new_i64();
1195 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1196 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1197 tcg_gen_and_i64(t2, t2, t3);
1198 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1199 tcg_gen_or_i64(t2, t2, t3);
1200 tcg_gen_movi_i64(t3, 0);
1201 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1202 tcg_gen_rem_i64(ret, t0, t1);
1203 tcg_temp_free_i64(t2);
1204 tcg_temp_free_i64(t3);
1205 } else {
1206 TCGv_i64 t2 = tcg_const_i64(1);
1207 TCGv_i64 t3 = tcg_const_i64(0);
1208 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1209 tcg_gen_remu_i64(ret, t0, t1);
1210 tcg_temp_free_i64(t2);
1211 tcg_temp_free_i64(t3);
1212 }
1213 tcg_temp_free_i64(t0);
1214 tcg_temp_free_i64(t1);
1215 }
1216
1217 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1218 static void glue(gen_, name)(DisasContext *ctx) \
1219 { \
1220 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1221 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1222 sign); \
1223 }
1224
1225 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1226 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1227 #endif
1228
1229 /* mulhw mulhw. */
1230 static void gen_mulhw(DisasContext *ctx)
1231 {
1232 TCGv_i32 t0 = tcg_temp_new_i32();
1233 TCGv_i32 t1 = tcg_temp_new_i32();
1234
1235 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1236 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1237 tcg_gen_muls2_i32(t0, t1, t0, t1);
1238 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1239 tcg_temp_free_i32(t0);
1240 tcg_temp_free_i32(t1);
1241 if (unlikely(Rc(ctx->opcode) != 0))
1242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1243 }
1244
1245 /* mulhwu mulhwu. */
1246 static void gen_mulhwu(DisasContext *ctx)
1247 {
1248 TCGv_i32 t0 = tcg_temp_new_i32();
1249 TCGv_i32 t1 = tcg_temp_new_i32();
1250
1251 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1252 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1253 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1254 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1255 tcg_temp_free_i32(t0);
1256 tcg_temp_free_i32(t1);
1257 if (unlikely(Rc(ctx->opcode) != 0))
1258 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1259 }
1260
1261 /* mullw mullw. */
1262 static void gen_mullw(DisasContext *ctx)
1263 {
1264 #if defined(TARGET_PPC64)
1265 TCGv_i64 t0, t1;
1266 t0 = tcg_temp_new_i64();
1267 t1 = tcg_temp_new_i64();
1268 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1269 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1270 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1271 tcg_temp_free(t0);
1272 tcg_temp_free(t1);
1273 #else
1274 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1275 cpu_gpr[rB(ctx->opcode)]);
1276 #endif
1277 if (unlikely(Rc(ctx->opcode) != 0))
1278 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1279 }
1280
1281 /* mullwo mullwo. */
1282 static void gen_mullwo(DisasContext *ctx)
1283 {
1284 TCGv_i32 t0 = tcg_temp_new_i32();
1285 TCGv_i32 t1 = tcg_temp_new_i32();
1286
1287 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1288 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1289 tcg_gen_muls2_i32(t0, t1, t0, t1);
1290 #if defined(TARGET_PPC64)
1291 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1292 #else
1293 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1294 #endif
1295
1296 tcg_gen_sari_i32(t0, t0, 31);
1297 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1298 tcg_gen_extu_i32_tl(cpu_ov, t0);
1299 if (is_isa300(ctx)) {
1300 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1301 }
1302 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1303
1304 tcg_temp_free_i32(t0);
1305 tcg_temp_free_i32(t1);
1306 if (unlikely(Rc(ctx->opcode) != 0))
1307 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1308 }
1309
1310 /* mulli */
1311 static void gen_mulli(DisasContext *ctx)
1312 {
1313 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1314 SIMM(ctx->opcode));
1315 }
1316
1317 #if defined(TARGET_PPC64)
1318 /* mulhd mulhd. */
1319 static void gen_mulhd(DisasContext *ctx)
1320 {
1321 TCGv lo = tcg_temp_new();
1322 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1323 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1324 tcg_temp_free(lo);
1325 if (unlikely(Rc(ctx->opcode) != 0)) {
1326 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1327 }
1328 }
1329
1330 /* mulhdu mulhdu. */
1331 static void gen_mulhdu(DisasContext *ctx)
1332 {
1333 TCGv lo = tcg_temp_new();
1334 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1335 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1336 tcg_temp_free(lo);
1337 if (unlikely(Rc(ctx->opcode) != 0)) {
1338 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1339 }
1340 }
1341
1342 /* mulld mulld. */
1343 static void gen_mulld(DisasContext *ctx)
1344 {
1345 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1346 cpu_gpr[rB(ctx->opcode)]);
1347 if (unlikely(Rc(ctx->opcode) != 0))
1348 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1349 }
1350
1351 /* mulldo mulldo. */
1352 static void gen_mulldo(DisasContext *ctx)
1353 {
1354 TCGv_i64 t0 = tcg_temp_new_i64();
1355 TCGv_i64 t1 = tcg_temp_new_i64();
1356
1357 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1358 cpu_gpr[rB(ctx->opcode)]);
1359 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1360
1361 tcg_gen_sari_i64(t0, t0, 63);
1362 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1363 if (is_isa300(ctx)) {
1364 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1365 }
1366 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1367
1368 tcg_temp_free_i64(t0);
1369 tcg_temp_free_i64(t1);
1370
1371 if (unlikely(Rc(ctx->opcode) != 0)) {
1372 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1373 }
1374 }
1375 #endif
1376
1377 /* Common subf function */
1378 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1379 TCGv arg2, bool add_ca, bool compute_ca,
1380 bool compute_ov, bool compute_rc0)
1381 {
1382 TCGv t0 = ret;
1383
1384 if (compute_ca || compute_ov) {
1385 t0 = tcg_temp_new();
1386 }
1387
1388 if (compute_ca) {
1389 /* dest = ~arg1 + arg2 [+ ca]. */
1390 if (NARROW_MODE(ctx)) {
1391 /* Caution: a non-obvious corner case of the spec is that we
1392 must produce the *entire* 64-bit addition, but produce the
1393 carry into bit 32. */
1394 TCGv inv1 = tcg_temp_new();
1395 TCGv t1 = tcg_temp_new();
1396 tcg_gen_not_tl(inv1, arg1);
1397 if (add_ca) {
1398 tcg_gen_add_tl(t0, arg2, cpu_ca);
1399 } else {
1400 tcg_gen_addi_tl(t0, arg2, 1);
1401 }
1402 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1403 tcg_gen_add_tl(t0, t0, inv1);
1404 tcg_temp_free(inv1);
1405 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1406 tcg_temp_free(t1);
1407 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1408 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1409 if (is_isa300(ctx)) {
1410 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1411 }
1412 } else if (add_ca) {
1413 TCGv zero, inv1 = tcg_temp_new();
1414 tcg_gen_not_tl(inv1, arg1);
1415 zero = tcg_const_tl(0);
1416 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1417 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1418 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1419 tcg_temp_free(zero);
1420 tcg_temp_free(inv1);
1421 } else {
1422 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1423 tcg_gen_sub_tl(t0, arg2, arg1);
1424 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1425 }
1426 } else if (add_ca) {
1427 /* Since we're ignoring carry-out, we can simplify the
1428 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1429 tcg_gen_sub_tl(t0, arg2, arg1);
1430 tcg_gen_add_tl(t0, t0, cpu_ca);
1431 tcg_gen_subi_tl(t0, t0, 1);
1432 } else {
1433 tcg_gen_sub_tl(t0, arg2, arg1);
1434 }
1435
1436 if (compute_ov) {
1437 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1438 }
1439 if (unlikely(compute_rc0)) {
1440 gen_set_Rc0(ctx, t0);
1441 }
1442
1443 if (!TCGV_EQUAL(t0, ret)) {
1444 tcg_gen_mov_tl(ret, t0);
1445 tcg_temp_free(t0);
1446 }
1447 }
1448 /* Sub functions with Two operands functions */
1449 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1450 static void glue(gen_, name)(DisasContext *ctx) \
1451 { \
1452 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1453 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1454 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1455 }
1456 /* Sub functions with one operand and one immediate */
1457 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1458 add_ca, compute_ca, compute_ov) \
1459 static void glue(gen_, name)(DisasContext *ctx) \
1460 { \
1461 TCGv t0 = tcg_const_tl(const_val); \
1462 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1463 cpu_gpr[rA(ctx->opcode)], t0, \
1464 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1465 tcg_temp_free(t0); \
1466 }
1467 /* subf subf. subfo subfo. */
1468 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1469 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1470 /* subfc subfc. subfco subfco. */
1471 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1472 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1473 /* subfe subfe. subfeo subfo. */
1474 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1475 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1476 /* subfme subfme. subfmeo subfmeo. */
1477 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1478 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1479 /* subfze subfze. subfzeo subfzeo.*/
1480 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1481 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1482
1483 /* subfic */
1484 static void gen_subfic(DisasContext *ctx)
1485 {
1486 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1487 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1488 c, 0, 1, 0, 0);
1489 tcg_temp_free(c);
1490 }
1491
1492 /* neg neg. nego nego. */
1493 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1494 {
1495 TCGv zero = tcg_const_tl(0);
1496 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1497 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1498 tcg_temp_free(zero);
1499 }
1500
1501 static void gen_neg(DisasContext *ctx)
1502 {
1503 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1504 if (unlikely(Rc(ctx->opcode))) {
1505 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1506 }
1507 }
1508
1509 static void gen_nego(DisasContext *ctx)
1510 {
1511 gen_op_arith_neg(ctx, 1);
1512 }
1513
1514 /*** Integer logical ***/
1515 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1516 static void glue(gen_, name)(DisasContext *ctx) \
1517 { \
1518 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1519 cpu_gpr[rB(ctx->opcode)]); \
1520 if (unlikely(Rc(ctx->opcode) != 0)) \
1521 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1522 }
1523
1524 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1525 static void glue(gen_, name)(DisasContext *ctx) \
1526 { \
1527 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1528 if (unlikely(Rc(ctx->opcode) != 0)) \
1529 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1530 }
1531
1532 /* and & and. */
1533 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1534 /* andc & andc. */
1535 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1536
1537 /* andi. */
1538 static void gen_andi_(DisasContext *ctx)
1539 {
1540 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1541 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1542 }
1543
1544 /* andis. */
1545 static void gen_andis_(DisasContext *ctx)
1546 {
1547 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1548 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1549 }
1550
1551 /* cntlzw */
1552 static void gen_cntlzw(DisasContext *ctx)
1553 {
1554 TCGv_i32 t = tcg_temp_new_i32();
1555
1556 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1557 tcg_gen_clzi_i32(t, t, 32);
1558 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1559 tcg_temp_free_i32(t);
1560
1561 if (unlikely(Rc(ctx->opcode) != 0))
1562 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1563 }
1564
1565 /* cnttzw */
1566 static void gen_cnttzw(DisasContext *ctx)
1567 {
1568 TCGv_i32 t = tcg_temp_new_i32();
1569
1570 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1571 tcg_gen_ctzi_i32(t, t, 32);
1572 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1573 tcg_temp_free_i32(t);
1574
1575 if (unlikely(Rc(ctx->opcode) != 0)) {
1576 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1577 }
1578 }
1579
1580 /* eqv & eqv. */
1581 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1582 /* extsb & extsb. */
1583 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1584 /* extsh & extsh. */
1585 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1586 /* nand & nand. */
1587 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1588 /* nor & nor. */
1589 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1590
1591 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1592 static void gen_pause(DisasContext *ctx)
1593 {
1594 TCGv_i32 t0 = tcg_const_i32(0);
1595 tcg_gen_st_i32(t0, cpu_env,
1596 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1597 tcg_temp_free_i32(t0);
1598
1599 /* Stop translation, this gives other CPUs a chance to run */
1600 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1601 }
1602 #endif /* defined(TARGET_PPC64) */
1603
1604 /* or & or. */
1605 static void gen_or(DisasContext *ctx)
1606 {
1607 int rs, ra, rb;
1608
1609 rs = rS(ctx->opcode);
1610 ra = rA(ctx->opcode);
1611 rb = rB(ctx->opcode);
1612 /* Optimisation for mr. ri case */
1613 if (rs != ra || rs != rb) {
1614 if (rs != rb)
1615 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1616 else
1617 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1618 if (unlikely(Rc(ctx->opcode) != 0))
1619 gen_set_Rc0(ctx, cpu_gpr[ra]);
1620 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1621 gen_set_Rc0(ctx, cpu_gpr[rs]);
1622 #if defined(TARGET_PPC64)
1623 } else if (rs != 0) { /* 0 is nop */
1624 int prio = 0;
1625
1626 switch (rs) {
1627 case 1:
1628 /* Set process priority to low */
1629 prio = 2;
1630 break;
1631 case 6:
1632 /* Set process priority to medium-low */
1633 prio = 3;
1634 break;
1635 case 2:
1636 /* Set process priority to normal */
1637 prio = 4;
1638 break;
1639 #if !defined(CONFIG_USER_ONLY)
1640 case 31:
1641 if (!ctx->pr) {
1642 /* Set process priority to very low */
1643 prio = 1;
1644 }
1645 break;
1646 case 5:
1647 if (!ctx->pr) {
1648 /* Set process priority to medium-hight */
1649 prio = 5;
1650 }
1651 break;
1652 case 3:
1653 if (!ctx->pr) {
1654 /* Set process priority to high */
1655 prio = 6;
1656 }
1657 break;
1658 case 7:
1659 if (ctx->hv && !ctx->pr) {
1660 /* Set process priority to very high */
1661 prio = 7;
1662 }
1663 break;
1664 #endif
1665 default:
1666 break;
1667 }
1668 if (prio) {
1669 TCGv t0 = tcg_temp_new();
1670 gen_load_spr(t0, SPR_PPR);
1671 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1672 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1673 gen_store_spr(SPR_PPR, t0);
1674 tcg_temp_free(t0);
1675 }
1676 #if !defined(CONFIG_USER_ONLY)
1677 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1678 * CPU and the kernel hangs. This applies to all encodings other
1679 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1680 * and all currently undefined.
1681 */
1682 gen_pause(ctx);
1683 #endif
1684 #endif
1685 }
1686 }
1687 /* orc & orc. */
1688 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1689
1690 /* xor & xor. */
1691 static void gen_xor(DisasContext *ctx)
1692 {
1693 /* Optimisation for "set to zero" case */
1694 if (rS(ctx->opcode) != rB(ctx->opcode))
1695 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1696 else
1697 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1698 if (unlikely(Rc(ctx->opcode) != 0))
1699 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1700 }
1701
1702 /* ori */
1703 static void gen_ori(DisasContext *ctx)
1704 {
1705 target_ulong uimm = UIMM(ctx->opcode);
1706
1707 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1708 return;
1709 }
1710 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1711 }
1712
1713 /* oris */
1714 static void gen_oris(DisasContext *ctx)
1715 {
1716 target_ulong uimm = UIMM(ctx->opcode);
1717
1718 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1719 /* NOP */
1720 return;
1721 }
1722 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1723 }
1724
1725 /* xori */
1726 static void gen_xori(DisasContext *ctx)
1727 {
1728 target_ulong uimm = UIMM(ctx->opcode);
1729
1730 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1731 /* NOP */
1732 return;
1733 }
1734 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1735 }
1736
1737 /* xoris */
1738 static void gen_xoris(DisasContext *ctx)
1739 {
1740 target_ulong uimm = UIMM(ctx->opcode);
1741
1742 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1743 /* NOP */
1744 return;
1745 }
1746 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1747 }
1748
1749 /* popcntb : PowerPC 2.03 specification */
1750 static void gen_popcntb(DisasContext *ctx)
1751 {
1752 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1753 }
1754
1755 static void gen_popcntw(DisasContext *ctx)
1756 {
1757 #if defined(TARGET_PPC64)
1758 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1759 #else
1760 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1761 #endif
1762 }
1763
1764 #if defined(TARGET_PPC64)
1765 /* popcntd: PowerPC 2.06 specification */
1766 static void gen_popcntd(DisasContext *ctx)
1767 {
1768 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1769 }
1770 #endif
1771
1772 /* prtyw: PowerPC 2.05 specification */
1773 static void gen_prtyw(DisasContext *ctx)
1774 {
1775 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1776 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1777 TCGv t0 = tcg_temp_new();
1778 tcg_gen_shri_tl(t0, rs, 16);
1779 tcg_gen_xor_tl(ra, rs, t0);
1780 tcg_gen_shri_tl(t0, ra, 8);
1781 tcg_gen_xor_tl(ra, ra, t0);
1782 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1783 tcg_temp_free(t0);
1784 }
1785
1786 #if defined(TARGET_PPC64)
1787 /* prtyd: PowerPC 2.05 specification */
1788 static void gen_prtyd(DisasContext *ctx)
1789 {
1790 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1791 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1792 TCGv t0 = tcg_temp_new();
1793 tcg_gen_shri_tl(t0, rs, 32);
1794 tcg_gen_xor_tl(ra, rs, t0);
1795 tcg_gen_shri_tl(t0, ra, 16);
1796 tcg_gen_xor_tl(ra, ra, t0);
1797 tcg_gen_shri_tl(t0, ra, 8);
1798 tcg_gen_xor_tl(ra, ra, t0);
1799 tcg_gen_andi_tl(ra, ra, 1);
1800 tcg_temp_free(t0);
1801 }
1802 #endif
1803
1804 #if defined(TARGET_PPC64)
1805 /* bpermd */
1806 static void gen_bpermd(DisasContext *ctx)
1807 {
1808 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1809 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1810 }
1811 #endif
1812
1813 #if defined(TARGET_PPC64)
1814 /* extsw & extsw. */
1815 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1816
1817 /* cntlzd */
1818 static void gen_cntlzd(DisasContext *ctx)
1819 {
1820 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1821 if (unlikely(Rc(ctx->opcode) != 0))
1822 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1823 }
1824
1825 /* cnttzd */
1826 static void gen_cnttzd(DisasContext *ctx)
1827 {
1828 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1829 if (unlikely(Rc(ctx->opcode) != 0)) {
1830 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1831 }
1832 }
1833
1834 /* darn */
1835 static void gen_darn(DisasContext *ctx)
1836 {
1837 int l = L(ctx->opcode);
1838
1839 if (l == 0) {
1840 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1841 } else if (l <= 2) {
1842 /* Return 64-bit random for both CRN and RRN */
1843 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1844 } else {
1845 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1846 }
1847 }
1848 #endif
1849
1850 /*** Integer rotate ***/
1851
1852 /* rlwimi & rlwimi. */
1853 static void gen_rlwimi(DisasContext *ctx)
1854 {
1855 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1856 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1857 uint32_t sh = SH(ctx->opcode);
1858 uint32_t mb = MB(ctx->opcode);
1859 uint32_t me = ME(ctx->opcode);
1860
1861 if (sh == (31-me) && mb <= me) {
1862 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1863 } else {
1864 target_ulong mask;
1865 TCGv t1;
1866
1867 #if defined(TARGET_PPC64)
1868 mb += 32;
1869 me += 32;
1870 #endif
1871 mask = MASK(mb, me);
1872
1873 t1 = tcg_temp_new();
1874 if (mask <= 0xffffffffu) {
1875 TCGv_i32 t0 = tcg_temp_new_i32();
1876 tcg_gen_trunc_tl_i32(t0, t_rs);
1877 tcg_gen_rotli_i32(t0, t0, sh);
1878 tcg_gen_extu_i32_tl(t1, t0);
1879 tcg_temp_free_i32(t0);
1880 } else {
1881 #if defined(TARGET_PPC64)
1882 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1883 tcg_gen_rotli_i64(t1, t1, sh);
1884 #else
1885 g_assert_not_reached();
1886 #endif
1887 }
1888
1889 tcg_gen_andi_tl(t1, t1, mask);
1890 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1891 tcg_gen_or_tl(t_ra, t_ra, t1);
1892 tcg_temp_free(t1);
1893 }
1894 if (unlikely(Rc(ctx->opcode) != 0)) {
1895 gen_set_Rc0(ctx, t_ra);
1896 }
1897 }
1898
1899 /* rlwinm & rlwinm. */
1900 static void gen_rlwinm(DisasContext *ctx)
1901 {
1902 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1903 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1904 int sh = SH(ctx->opcode);
1905 int mb = MB(ctx->opcode);
1906 int me = ME(ctx->opcode);
1907 int len = me - mb + 1;
1908 int rsh = (32 - sh) & 31;
1909
1910 if (sh != 0 && len > 0 && me == (31 - sh)) {
1911 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1912 } else if (me == 31 && rsh + len <= 32) {
1913 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1914 } else {
1915 target_ulong mask;
1916 #if defined(TARGET_PPC64)
1917 mb += 32;
1918 me += 32;
1919 #endif
1920 mask = MASK(mb, me);
1921 if (sh == 0) {
1922 tcg_gen_andi_tl(t_ra, t_rs, mask);
1923 } else if (mask <= 0xffffffffu) {
1924 TCGv_i32 t0 = tcg_temp_new_i32();
1925 tcg_gen_trunc_tl_i32(t0, t_rs);
1926 tcg_gen_rotli_i32(t0, t0, sh);
1927 tcg_gen_andi_i32(t0, t0, mask);
1928 tcg_gen_extu_i32_tl(t_ra, t0);
1929 tcg_temp_free_i32(t0);
1930 } else {
1931 #if defined(TARGET_PPC64)
1932 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1933 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1934 tcg_gen_andi_i64(t_ra, t_ra, mask);
1935 #else
1936 g_assert_not_reached();
1937 #endif
1938 }
1939 }
1940 if (unlikely(Rc(ctx->opcode) != 0)) {
1941 gen_set_Rc0(ctx, t_ra);
1942 }
1943 }
1944
1945 /* rlwnm & rlwnm. */
1946 static void gen_rlwnm(DisasContext *ctx)
1947 {
1948 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1949 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1950 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1951 uint32_t mb = MB(ctx->opcode);
1952 uint32_t me = ME(ctx->opcode);
1953 target_ulong mask;
1954
1955 #if defined(TARGET_PPC64)
1956 mb += 32;
1957 me += 32;
1958 #endif
1959 mask = MASK(mb, me);
1960
1961 if (mask <= 0xffffffffu) {
1962 TCGv_i32 t0 = tcg_temp_new_i32();
1963 TCGv_i32 t1 = tcg_temp_new_i32();
1964 tcg_gen_trunc_tl_i32(t0, t_rb);
1965 tcg_gen_trunc_tl_i32(t1, t_rs);
1966 tcg_gen_andi_i32(t0, t0, 0x1f);
1967 tcg_gen_rotl_i32(t1, t1, t0);
1968 tcg_gen_extu_i32_tl(t_ra, t1);
1969 tcg_temp_free_i32(t0);
1970 tcg_temp_free_i32(t1);
1971 } else {
1972 #if defined(TARGET_PPC64)
1973 TCGv_i64 t0 = tcg_temp_new_i64();
1974 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1975 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1976 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1977 tcg_temp_free_i64(t0);
1978 #else
1979 g_assert_not_reached();
1980 #endif
1981 }
1982
1983 tcg_gen_andi_tl(t_ra, t_ra, mask);
1984
1985 if (unlikely(Rc(ctx->opcode) != 0)) {
1986 gen_set_Rc0(ctx, t_ra);
1987 }
1988 }
1989
1990 #if defined(TARGET_PPC64)
1991 #define GEN_PPC64_R2(name, opc1, opc2) \
1992 static void glue(gen_, name##0)(DisasContext *ctx) \
1993 { \
1994 gen_##name(ctx, 0); \
1995 } \
1996 \
1997 static void glue(gen_, name##1)(DisasContext *ctx) \
1998 { \
1999 gen_##name(ctx, 1); \
2000 }
2001 #define GEN_PPC64_R4(name, opc1, opc2) \
2002 static void glue(gen_, name##0)(DisasContext *ctx) \
2003 { \
2004 gen_##name(ctx, 0, 0); \
2005 } \
2006 \
2007 static void glue(gen_, name##1)(DisasContext *ctx) \
2008 { \
2009 gen_##name(ctx, 0, 1); \
2010 } \
2011 \
2012 static void glue(gen_, name##2)(DisasContext *ctx) \
2013 { \
2014 gen_##name(ctx, 1, 0); \
2015 } \
2016 \
2017 static void glue(gen_, name##3)(DisasContext *ctx) \
2018 { \
2019 gen_##name(ctx, 1, 1); \
2020 }
2021
2022 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2023 {
2024 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2025 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2026 int len = me - mb + 1;
2027 int rsh = (64 - sh) & 63;
2028
2029 if (sh != 0 && len > 0 && me == (63 - sh)) {
2030 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2031 } else if (me == 63 && rsh + len <= 64) {
2032 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2033 } else {
2034 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2035 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2036 }
2037 if (unlikely(Rc(ctx->opcode) != 0)) {
2038 gen_set_Rc0(ctx, t_ra);
2039 }
2040 }
2041
2042 /* rldicl - rldicl. */
2043 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2044 {
2045 uint32_t sh, mb;
2046
2047 sh = SH(ctx->opcode) | (shn << 5);
2048 mb = MB(ctx->opcode) | (mbn << 5);
2049 gen_rldinm(ctx, mb, 63, sh);
2050 }
2051 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2052
2053 /* rldicr - rldicr. */
2054 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2055 {
2056 uint32_t sh, me;
2057
2058 sh = SH(ctx->opcode) | (shn << 5);
2059 me = MB(ctx->opcode) | (men << 5);
2060 gen_rldinm(ctx, 0, me, sh);
2061 }
2062 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2063
2064 /* rldic - rldic. */
2065 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2066 {
2067 uint32_t sh, mb;
2068
2069 sh = SH(ctx->opcode) | (shn << 5);
2070 mb = MB(ctx->opcode) | (mbn << 5);
2071 gen_rldinm(ctx, mb, 63 - sh, sh);
2072 }
2073 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2074
2075 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2076 {
2077 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2078 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2079 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2080 TCGv t0;
2081
2082 t0 = tcg_temp_new();
2083 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2084 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2085 tcg_temp_free(t0);
2086
2087 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2088 if (unlikely(Rc(ctx->opcode) != 0)) {
2089 gen_set_Rc0(ctx, t_ra);
2090 }
2091 }
2092
2093 /* rldcl - rldcl. */
2094 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2095 {
2096 uint32_t mb;
2097
2098 mb = MB(ctx->opcode) | (mbn << 5);
2099 gen_rldnm(ctx, mb, 63);
2100 }
2101 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2102
2103 /* rldcr - rldcr. */
2104 static inline void gen_rldcr(DisasContext *ctx, int men)
2105 {
2106 uint32_t me;
2107
2108 me = MB(ctx->opcode) | (men << 5);
2109 gen_rldnm(ctx, 0, me);
2110 }
2111 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2112
2113 /* rldimi - rldimi. */
2114 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2115 {
2116 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2117 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2118 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2119 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2120 uint32_t me = 63 - sh;
2121
2122 if (mb <= me) {
2123 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2124 } else {
2125 target_ulong mask = MASK(mb, me);
2126 TCGv t1 = tcg_temp_new();
2127
2128 tcg_gen_rotli_tl(t1, t_rs, sh);
2129 tcg_gen_andi_tl(t1, t1, mask);
2130 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2131 tcg_gen_or_tl(t_ra, t_ra, t1);
2132 tcg_temp_free(t1);
2133 }
2134 if (unlikely(Rc(ctx->opcode) != 0)) {
2135 gen_set_Rc0(ctx, t_ra);
2136 }
2137 }
2138 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2139 #endif
2140
2141 /*** Integer shift ***/
2142
2143 /* slw & slw. */
2144 static void gen_slw(DisasContext *ctx)
2145 {
2146 TCGv t0, t1;
2147
2148 t0 = tcg_temp_new();
2149 /* AND rS with a mask that is 0 when rB >= 0x20 */
2150 #if defined(TARGET_PPC64)
2151 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2152 tcg_gen_sari_tl(t0, t0, 0x3f);
2153 #else
2154 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2155 tcg_gen_sari_tl(t0, t0, 0x1f);
2156 #endif
2157 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2158 t1 = tcg_temp_new();
2159 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2160 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2161 tcg_temp_free(t1);
2162 tcg_temp_free(t0);
2163 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2164 if (unlikely(Rc(ctx->opcode) != 0))
2165 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2166 }
2167
2168 /* sraw & sraw. */
2169 static void gen_sraw(DisasContext *ctx)
2170 {
2171 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2172 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2173 if (unlikely(Rc(ctx->opcode) != 0))
2174 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2175 }
2176
2177 /* srawi & srawi. */
2178 static void gen_srawi(DisasContext *ctx)
2179 {
2180 int sh = SH(ctx->opcode);
2181 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2182 TCGv src = cpu_gpr[rS(ctx->opcode)];
2183 if (sh == 0) {
2184 tcg_gen_ext32s_tl(dst, src);
2185 tcg_gen_movi_tl(cpu_ca, 0);
2186 } else {
2187 TCGv t0;
2188 tcg_gen_ext32s_tl(dst, src);
2189 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2190 t0 = tcg_temp_new();
2191 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2192 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2193 tcg_temp_free(t0);
2194 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2195 tcg_gen_sari_tl(dst, dst, sh);
2196 }
2197 if (unlikely(Rc(ctx->opcode) != 0)) {
2198 gen_set_Rc0(ctx, dst);
2199 }
2200 }
2201
2202 /* srw & srw. */
2203 static void gen_srw(DisasContext *ctx)
2204 {
2205 TCGv t0, t1;
2206
2207 t0 = tcg_temp_new();
2208 /* AND rS with a mask that is 0 when rB >= 0x20 */
2209 #if defined(TARGET_PPC64)
2210 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2211 tcg_gen_sari_tl(t0, t0, 0x3f);
2212 #else
2213 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2214 tcg_gen_sari_tl(t0, t0, 0x1f);
2215 #endif
2216 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2217 tcg_gen_ext32u_tl(t0, t0);
2218 t1 = tcg_temp_new();
2219 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2220 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2221 tcg_temp_free(t1);
2222 tcg_temp_free(t0);
2223 if (unlikely(Rc(ctx->opcode) != 0))
2224 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2225 }
2226
2227 #if defined(TARGET_PPC64)
2228 /* sld & sld. */
2229 static void gen_sld(DisasContext *ctx)
2230 {
2231 TCGv t0, t1;
2232
2233 t0 = tcg_temp_new();
2234 /* AND rS with a mask that is 0 when rB >= 0x40 */
2235 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2236 tcg_gen_sari_tl(t0, t0, 0x3f);
2237 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2238 t1 = tcg_temp_new();
2239 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2240 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2241 tcg_temp_free(t1);
2242 tcg_temp_free(t0);
2243 if (unlikely(Rc(ctx->opcode) != 0))
2244 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2245 }
2246
2247 /* srad & srad. */
2248 static void gen_srad(DisasContext *ctx)
2249 {
2250 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2251 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2252 if (unlikely(Rc(ctx->opcode) != 0))
2253 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2254 }
2255 /* sradi & sradi. */
2256 static inline void gen_sradi(DisasContext *ctx, int n)
2257 {
2258 int sh = SH(ctx->opcode) + (n << 5);
2259 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2260 TCGv src = cpu_gpr[rS(ctx->opcode)];
2261 if (sh == 0) {
2262 tcg_gen_mov_tl(dst, src);
2263 tcg_gen_movi_tl(cpu_ca, 0);
2264 } else {
2265 TCGv t0;
2266 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2267 t0 = tcg_temp_new();
2268 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2269 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2270 tcg_temp_free(t0);
2271 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2272 tcg_gen_sari_tl(dst, src, sh);
2273 }
2274 if (unlikely(Rc(ctx->opcode) != 0)) {
2275 gen_set_Rc0(ctx, dst);
2276 }
2277 }
2278
2279 static void gen_sradi0(DisasContext *ctx)
2280 {
2281 gen_sradi(ctx, 0);
2282 }
2283
2284 static void gen_sradi1(DisasContext *ctx)
2285 {
2286 gen_sradi(ctx, 1);
2287 }
2288
2289 /* extswsli & extswsli. */
2290 static inline void gen_extswsli(DisasContext *ctx, int n)
2291 {
2292 int sh = SH(ctx->opcode) + (n << 5);
2293 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2294 TCGv src = cpu_gpr[rS(ctx->opcode)];
2295
2296 tcg_gen_ext32s_tl(dst, src);
2297 tcg_gen_shli_tl(dst, dst, sh);
2298 if (unlikely(Rc(ctx->opcode) != 0)) {
2299 gen_set_Rc0(ctx, dst);
2300 }
2301 }
2302
2303 static void gen_extswsli0(DisasContext *ctx)
2304 {
2305 gen_extswsli(ctx, 0);
2306 }
2307
2308 static void gen_extswsli1(DisasContext *ctx)
2309 {
2310 gen_extswsli(ctx, 1);
2311 }
2312
2313 /* srd & srd. */
2314 static void gen_srd(DisasContext *ctx)
2315 {
2316 TCGv t0, t1;
2317
2318 t0 = tcg_temp_new();
2319 /* AND rS with a mask that is 0 when rB >= 0x40 */
2320 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2321 tcg_gen_sari_tl(t0, t0, 0x3f);
2322 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2323 t1 = tcg_temp_new();
2324 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2325 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2326 tcg_temp_free(t1);
2327 tcg_temp_free(t0);
2328 if (unlikely(Rc(ctx->opcode) != 0))
2329 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2330 }
2331 #endif
2332
2333 /*** Addressing modes ***/
2334 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2335 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2336 target_long maskl)
2337 {
2338 target_long simm = SIMM(ctx->opcode);
2339
2340 simm &= ~maskl;
2341 if (rA(ctx->opcode) == 0) {
2342 if (NARROW_MODE(ctx)) {
2343 simm = (uint32_t)simm;
2344 }
2345 tcg_gen_movi_tl(EA, simm);
2346 } else if (likely(simm != 0)) {
2347 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2348 if (NARROW_MODE(ctx)) {
2349 tcg_gen_ext32u_tl(EA, EA);
2350 }
2351 } else {
2352 if (NARROW_MODE(ctx)) {
2353 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2354 } else {
2355 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2356 }
2357 }
2358 }
2359
2360 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2361 {
2362 if (rA(ctx->opcode) == 0) {
2363 if (NARROW_MODE(ctx)) {
2364 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2365 } else {
2366 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2367 }
2368 } else {
2369 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2370 if (NARROW_MODE(ctx)) {
2371 tcg_gen_ext32u_tl(EA, EA);
2372 }
2373 }
2374 }
2375
2376 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2377 {
2378 if (rA(ctx->opcode) == 0) {
2379 tcg_gen_movi_tl(EA, 0);
2380 } else if (NARROW_MODE(ctx)) {
2381 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2382 } else {
2383 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2384 }
2385 }
2386
2387 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2388 target_long val)
2389 {
2390 tcg_gen_addi_tl(ret, arg1, val);
2391 if (NARROW_MODE(ctx)) {
2392 tcg_gen_ext32u_tl(ret, ret);
2393 }
2394 }
2395
2396 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2397 {
2398 TCGLabel *l1 = gen_new_label();
2399 TCGv t0 = tcg_temp_new();
2400 TCGv_i32 t1, t2;
2401 tcg_gen_andi_tl(t0, EA, mask);
2402 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2403 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2404 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2405 gen_update_nip(ctx, ctx->nip - 4);
2406 gen_helper_raise_exception_err(cpu_env, t1, t2);
2407 tcg_temp_free_i32(t1);
2408 tcg_temp_free_i32(t2);
2409 gen_set_label(l1);
2410 tcg_temp_free(t0);
2411 }
2412
2413 static inline void gen_align_no_le(DisasContext *ctx)
2414 {
2415 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2416 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2417 }
2418
2419 /*** Integer load ***/
2420 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2421 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2422
2423 #define GEN_QEMU_LOAD_TL(ldop, op) \
2424 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2425 TCGv val, \
2426 TCGv addr) \
2427 { \
2428 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2429 }
2430
2431 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2432 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2433 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2434 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2435 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2436
2437 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2438 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2439
2440 #define GEN_QEMU_LOAD_64(ldop, op) \
2441 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2442 TCGv_i64 val, \
2443 TCGv addr) \
2444 { \
2445 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2446 }
2447
2448 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2449 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2450 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2451 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2452 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2453
2454 #if defined(TARGET_PPC64)
2455 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2456 #endif
2457
2458 #define GEN_QEMU_STORE_TL(stop, op) \
2459 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2460 TCGv val, \
2461 TCGv addr) \
2462 { \
2463 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2464 }
2465
2466 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2467 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2468 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2469
2470 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2471 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2472
2473 #define GEN_QEMU_STORE_64(stop, op) \
2474 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2475 TCGv_i64 val, \
2476 TCGv addr) \
2477 { \
2478 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2479 }
2480
2481 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2482 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2483 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2484 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2485
2486 #if defined(TARGET_PPC64)
2487 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2488 #endif
2489
2490 #define GEN_LD(name, ldop, opc, type) \
2491 static void glue(gen_, name)(DisasContext *ctx) \
2492 { \
2493 TCGv EA; \
2494 gen_set_access_type(ctx, ACCESS_INT); \
2495 EA = tcg_temp_new(); \
2496 gen_addr_imm_index(ctx, EA, 0); \
2497 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2498 tcg_temp_free(EA); \
2499 }
2500
2501 #define GEN_LDU(name, ldop, opc, type) \
2502 static void glue(gen_, name##u)(DisasContext *ctx) \
2503 { \
2504 TCGv EA; \
2505 if (unlikely(rA(ctx->opcode) == 0 || \
2506 rA(ctx->opcode) == rD(ctx->opcode))) { \
2507 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2508 return; \
2509 } \
2510 gen_set_access_type(ctx, ACCESS_INT); \
2511 EA = tcg_temp_new(); \
2512 if (type == PPC_64B) \
2513 gen_addr_imm_index(ctx, EA, 0x03); \
2514 else \
2515 gen_addr_imm_index(ctx, EA, 0); \
2516 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2517 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2518 tcg_temp_free(EA); \
2519 }
2520
2521 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2522 static void glue(gen_, name##ux)(DisasContext *ctx) \
2523 { \
2524 TCGv EA; \
2525 if (unlikely(rA(ctx->opcode) == 0 || \
2526 rA(ctx->opcode) == rD(ctx->opcode))) { \
2527 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2528 return; \
2529 } \
2530 gen_set_access_type(ctx, ACCESS_INT); \
2531 EA = tcg_temp_new(); \
2532 gen_addr_reg_index(ctx, EA); \
2533 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2534 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2535 tcg_temp_free(EA); \
2536 }
2537
2538 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2539 static void glue(gen_, name##x)(DisasContext *ctx) \
2540 { \
2541 TCGv EA; \
2542 chk; \
2543 gen_set_access_type(ctx, ACCESS_INT); \
2544 EA = tcg_temp_new(); \
2545 gen_addr_reg_index(ctx, EA); \
2546 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2547 tcg_temp_free(EA); \
2548 }
2549
2550 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2551 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2552
2553 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2554 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2555
2556 #define GEN_LDS(name, ldop, op, type) \
2557 GEN_LD(name, ldop, op | 0x20, type); \
2558 GEN_LDU(name, ldop, op | 0x21, type); \
2559 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2560 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2561
2562 /* lbz lbzu lbzux lbzx */
2563 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2564 /* lha lhau lhaux lhax */
2565 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2566 /* lhz lhzu lhzux lhzx */
2567 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2568 /* lwz lwzu lwzux lwzx */
2569 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2570 #if defined(TARGET_PPC64)
2571 /* lwaux */
2572 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2573 /* lwax */
2574 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2575 /* ldux */
2576 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2577 /* ldx */
2578 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2579
2580 /* CI load/store variants */
2581 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2582 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2583 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2584 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2585
2586 static void gen_ld(DisasContext *ctx)
2587 {
2588 TCGv EA;
2589 if (Rc(ctx->opcode)) {
2590 if (unlikely(rA(ctx->opcode) == 0 ||
2591 rA(ctx->opcode) == rD(ctx->opcode))) {
2592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2593 return;
2594 }
2595 }
2596 gen_set_access_type(ctx, ACCESS_INT);
2597 EA = tcg_temp_new();
2598 gen_addr_imm_index(ctx, EA, 0x03);
2599 if (ctx->opcode & 0x02) {
2600 /* lwa (lwau is undefined) */
2601 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2602 } else {
2603 /* ld - ldu */
2604 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2605 }
2606 if (Rc(ctx->opcode))
2607 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2608 tcg_temp_free(EA);
2609 }
2610
2611 /* lq */
2612 static void gen_lq(DisasContext *ctx)
2613 {
2614 int ra, rd;
2615 TCGv EA;
2616
2617 /* lq is a legal user mode instruction starting in ISA 2.07 */
2618 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2619 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2620
2621 if (!legal_in_user_mode && ctx->pr) {
2622 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2623 return;
2624 }
2625
2626 if (!le_is_supported && ctx->le_mode) {
2627 gen_align_no_le(ctx);
2628 return;
2629 }
2630 ra = rA(ctx->opcode);
2631 rd = rD(ctx->opcode);
2632 if (unlikely((rd & 1) || rd == ra)) {
2633 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2634 return;
2635 }
2636
2637 gen_set_access_type(ctx, ACCESS_INT);
2638 EA = tcg_temp_new();
2639 gen_addr_imm_index(ctx, EA, 0x0F);
2640
2641 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2642 necessary 64-bit byteswap already. */
2643 if (unlikely(ctx->le_mode)) {
2644 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2645 gen_addr_add(ctx, EA, EA, 8);
2646 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2647 } else {
2648 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2649 gen_addr_add(ctx, EA, EA, 8);
2650 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2651 }
2652 tcg_temp_free(EA);
2653 }
2654 #endif
2655
2656 /*** Integer store ***/
2657 #define GEN_ST(name, stop, opc, type) \
2658 static void glue(gen_, name)(DisasContext *ctx) \
2659 { \
2660 TCGv EA; \
2661 gen_set_access_type(ctx, ACCESS_INT); \
2662 EA = tcg_temp_new(); \
2663 gen_addr_imm_index(ctx, EA, 0); \
2664 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2665 tcg_temp_free(EA); \
2666 }
2667
2668 #define GEN_STU(name, stop, opc, type) \
2669 static void glue(gen_, stop##u)(DisasContext *ctx) \
2670 { \
2671 TCGv EA; \
2672 if (unlikely(rA(ctx->opcode) == 0)) { \
2673 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2674 return; \
2675 } \
2676 gen_set_access_type(ctx, ACCESS_INT); \
2677 EA = tcg_temp_new(); \
2678 if (type == PPC_64B) \
2679 gen_addr_imm_index(ctx, EA, 0x03); \
2680 else \
2681 gen_addr_imm_index(ctx, EA, 0); \
2682 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2683 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2684 tcg_temp_free(EA); \
2685 }
2686
2687 #define GEN_STUX(name, stop, opc2, opc3, type) \
2688 static void glue(gen_, name##ux)(DisasContext *ctx) \
2689 { \
2690 TCGv EA; \
2691 if (unlikely(rA(ctx->opcode) == 0)) { \
2692 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2693 return; \
2694 } \
2695 gen_set_access_type(ctx, ACCESS_INT); \
2696 EA = tcg_temp_new(); \
2697 gen_addr_reg_index(ctx, EA); \
2698 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2699 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2700 tcg_temp_free(EA); \
2701 }
2702
2703 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2704 static void glue(gen_, name##x)(DisasContext *ctx) \
2705 { \
2706 TCGv EA; \
2707 chk; \
2708 gen_set_access_type(ctx, ACCESS_INT); \
2709 EA = tcg_temp_new(); \
2710 gen_addr_reg_index(ctx, EA); \
2711 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2712 tcg_temp_free(EA); \
2713 }
2714 #define GEN_STX(name, stop, opc2, opc3, type) \
2715 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2716
2717 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2718 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2719
2720 #define GEN_STS(name, stop, op, type) \
2721 GEN_ST(name, stop, op | 0x20, type); \
2722 GEN_STU(name, stop, op | 0x21, type); \
2723 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2724 GEN_STX(name, stop, 0x17, op | 0x00, type)
2725
2726 /* stb stbu stbux stbx */
2727 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2728 /* sth sthu sthux sthx */
2729 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2730 /* stw stwu stwux stwx */
2731 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2732 #if defined(TARGET_PPC64)
2733 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2734 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2735 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2736 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2737 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2738 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2739
2740 static void gen_std(DisasContext *ctx)
2741 {
2742 int rs;
2743 TCGv EA;
2744
2745 rs = rS(ctx->opcode);
2746 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2747 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2748 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2749
2750 if (!(ctx->insns_flags & PPC_64BX)) {
2751 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2752 }
2753
2754 if (!legal_in_user_mode && ctx->pr) {
2755 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2756 return;
2757 }
2758
2759 if (!le_is_supported && ctx->le_mode) {
2760 gen_align_no_le(ctx);
2761 return;
2762 }
2763
2764 if (unlikely(rs & 1)) {
2765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2766 return;
2767 }
2768 gen_set_access_type(ctx, ACCESS_INT);
2769 EA = tcg_temp_new();
2770 gen_addr_imm_index(ctx, EA, 0x03);
2771
2772 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2773 necessary 64-bit byteswap already. */
2774 if (unlikely(ctx->le_mode)) {
2775 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2776 gen_addr_add(ctx, EA, EA, 8);
2777 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2778 } else {
2779 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2780 gen_addr_add(ctx, EA, EA, 8);
2781 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2782 }
2783 tcg_temp_free(EA);
2784 } else {
2785 /* std / stdu*/
2786 if (Rc(ctx->opcode)) {
2787 if (unlikely(rA(ctx->opcode) == 0)) {
2788 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2789 return;
2790 }
2791 }
2792 gen_set_access_type(ctx, ACCESS_INT);
2793 EA = tcg_temp_new();
2794 gen_addr_imm_index(ctx, EA, 0x03);
2795 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2796 if (Rc(ctx->opcode))
2797 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2798 tcg_temp_free(EA);
2799 }
2800 }
2801 #endif
2802 /*** Integer load and store with byte reverse ***/
2803
2804 /* lhbrx */
2805 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2806
2807 /* lwbrx */
2808 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2809
2810 #if defined(TARGET_PPC64)
2811 /* ldbrx */
2812 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2813 /* stdbrx */
2814 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2815 #endif /* TARGET_PPC64 */
2816
2817 /* sthbrx */
2818 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2819 /* stwbrx */
2820 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2821
2822 /*** Integer load and store multiple ***/
2823
2824 /* lmw */
2825 static void gen_lmw(DisasContext *ctx)
2826 {
2827 TCGv t0;
2828 TCGv_i32 t1;
2829
2830 if (ctx->le_mode) {
2831 gen_align_no_le(ctx);
2832 return;
2833 }
2834 gen_set_access_type(ctx, ACCESS_INT);
2835 t0 = tcg_temp_new();
2836 t1 = tcg_const_i32(rD(ctx->opcode));
2837 gen_addr_imm_index(ctx, t0, 0);
2838 gen_helper_lmw(cpu_env, t0, t1);
2839 tcg_temp_free(t0);
2840 tcg_temp_free_i32(t1);
2841 }
2842
2843 /* stmw */
2844 static void gen_stmw(DisasContext *ctx)
2845 {
2846 TCGv t0;
2847 TCGv_i32 t1;
2848
2849 if (ctx->le_mode) {
2850 gen_align_no_le(ctx);
2851 return;
2852 }
2853 gen_set_access_type(ctx, ACCESS_INT);
2854 t0 = tcg_temp_new();
2855 t1 = tcg_const_i32(rS(ctx->opcode));
2856 gen_addr_imm_index(ctx, t0, 0);
2857 gen_helper_stmw(cpu_env, t0, t1);
2858 tcg_temp_free(t0);
2859 tcg_temp_free_i32(t1);
2860 }
2861
2862 /*** Integer load and store strings ***/
2863
2864 /* lswi */
2865 /* PowerPC32 specification says we must generate an exception if
2866 * rA is in the range of registers to be loaded.
2867 * In an other hand, IBM says this is valid, but rA won't be loaded.
2868 * For now, I'll follow the spec...
2869 */
2870 static void gen_lswi(DisasContext *ctx)
2871 {
2872 TCGv t0;
2873 TCGv_i32 t1, t2;
2874 int nb = NB(ctx->opcode);
2875 int start = rD(ctx->opcode);
2876 int ra = rA(ctx->opcode);
2877 int nr;
2878
2879 if (ctx->le_mode) {
2880 gen_align_no_le(ctx);
2881 return;
2882 }
2883 if (nb == 0)
2884 nb = 32;
2885 nr = (nb + 3) / 4;
2886 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2887 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2888 return;
2889 }
2890 gen_set_access_type(ctx, ACCESS_INT);
2891 t0 = tcg_temp_new();
2892 gen_addr_register(ctx, t0);
2893 t1 = tcg_const_i32(nb);
2894 t2 = tcg_const_i32(start);
2895 gen_helper_lsw(cpu_env, t0, t1, t2);
2896 tcg_temp_free(t0);
2897 tcg_temp_free_i32(t1);
2898 tcg_temp_free_i32(t2);
2899 }
2900
2901 /* lswx */
2902 static void gen_lswx(DisasContext *ctx)
2903 {
2904 TCGv t0;
2905 TCGv_i32 t1, t2, t3;
2906
2907 if (ctx->le_mode) {
2908 gen_align_no_le(ctx);
2909 return;
2910 }
2911 gen_set_access_type(ctx, ACCESS_INT);
2912 t0 = tcg_temp_new();
2913 gen_addr_reg_index(ctx, t0);
2914 t1 = tcg_const_i32(rD(ctx->opcode));
2915 t2 = tcg_const_i32(rA(ctx->opcode));
2916 t3 = tcg_const_i32(rB(ctx->opcode));
2917 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2918 tcg_temp_free(t0);
2919 tcg_temp_free_i32(t1);
2920 tcg_temp_free_i32(t2);
2921 tcg_temp_free_i32(t3);
2922 }
2923
2924 /* stswi */
2925 static void gen_stswi(DisasContext *ctx)
2926 {
2927 TCGv t0;
2928 TCGv_i32 t1, t2;
2929 int nb = NB(ctx->opcode);
2930
2931 if (ctx->le_mode) {
2932 gen_align_no_le(ctx);
2933 return;
2934 }
2935 gen_set_access_type(ctx, ACCESS_INT);
2936 t0 = tcg_temp_new();
2937 gen_addr_register(ctx, t0);
2938 if (nb == 0)
2939 nb = 32;
2940 t1 = tcg_const_i32(nb);
2941 t2 = tcg_const_i32(rS(ctx->opcode));
2942 gen_helper_stsw(cpu_env, t0, t1, t2);
2943 tcg_temp_free(t0);
2944 tcg_temp_free_i32(t1);
2945 tcg_temp_free_i32(t2);
2946 }
2947
2948 /* stswx */
2949 static void gen_stswx(DisasContext *ctx)
2950 {
2951 TCGv t0;
2952 TCGv_i32 t1, t2;
2953
2954 if (ctx->le_mode) {
2955 gen_align_no_le(ctx);
2956 return;
2957 }
2958 gen_set_access_type(ctx, ACCESS_INT);
2959 t0 = tcg_temp_new();
2960 gen_addr_reg_index(ctx, t0);
2961 t1 = tcg_temp_new_i32();
2962 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2963 tcg_gen_andi_i32(t1, t1, 0x7F);
2964 t2 = tcg_const_i32(rS(ctx->opcode));
2965 gen_helper_stsw(cpu_env, t0, t1, t2);
2966 tcg_temp_free(t0);
2967 tcg_temp_free_i32(t1);
2968 tcg_temp_free_i32(t2);
2969 }
2970
2971 /*** Memory synchronisation ***/
2972 /* eieio */
2973 static void gen_eieio(DisasContext *ctx)
2974 {
2975 tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
2976 }
2977
2978 #if !defined(CONFIG_USER_ONLY)
2979 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
2980 {
2981 TCGv_i32 t;
2982 TCGLabel *l;
2983
2984 if (!ctx->lazy_tlb_flush) {
2985 return;
2986 }
2987 l = gen_new_label();
2988 t = tcg_temp_new_i32();
2989 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
2990 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
2991 if (global) {
2992 gen_helper_check_tlb_flush_global(cpu_env);
2993 } else {
2994 gen_helper_check_tlb_flush_local(cpu_env);
2995 }
2996 gen_set_label(l);
2997 tcg_temp_free_i32(t);
2998 }
2999 #else
3000 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3001 #endif
3002
3003 /* isync */
3004 static void gen_isync(DisasContext *ctx)
3005 {
3006 /*
3007 * We need to check for a pending TLB flush. This can only happen in
3008 * kernel mode however so check MSR_PR
3009 */
3010 if (!ctx->pr) {
3011 gen_check_tlb_flush(ctx, false);
3012 }
3013 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3014 gen_stop_exception(ctx);
3015 }
3016
3017 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3018
3019 #define LARX(name, memop) \
3020 static void gen_##name(DisasContext *ctx) \
3021 { \
3022 TCGv t0; \
3023 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3024 int len = MEMOP_GET_SIZE(memop); \
3025 gen_set_access_type(ctx, ACCESS_RES); \
3026 t0 = tcg_temp_local_new(); \
3027 gen_addr_reg_index(ctx, t0); \
3028 if ((len) > 1) { \
3029 gen_check_align(ctx, t0, (len)-1); \
3030 } \
3031 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3032 tcg_gen_mov_tl(cpu_reserve, t0); \
3033 tcg_gen_mov_tl(cpu_reserve_val, gpr); \
3034 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
3035 tcg_temp_free(t0); \
3036 }
3037
3038 /* lwarx */
3039 LARX(lbarx, DEF_MEMOP(MO_UB))
3040 LARX(lharx, DEF_MEMOP(MO_UW))
3041 LARX(lwarx, DEF_MEMOP(MO_UL))
3042
3043 #define LD_ATOMIC(name, memop, tp, op, eop) \
3044 static void gen_##name(DisasContext *ctx) \
3045 { \
3046 int len = MEMOP_GET_SIZE(memop); \
3047 uint32_t gpr_FC = FC(ctx->opcode); \
3048 TCGv EA = tcg_temp_local_new(); \
3049 TCGv_##tp t0, t1; \
3050 \
3051 gen_addr_register(ctx, EA); \
3052 if (len > 1) { \
3053 gen_check_align(ctx, EA, len - 1); \
3054 } \
3055 t0 = tcg_temp_new_##tp(); \
3056 t1 = tcg_temp_new_##tp(); \
3057 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3058 \
3059 switch (gpr_FC) { \
3060 case 0: /* Fetch and add */ \
3061 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3062 break; \
3063 case 1: /* Fetch and xor */ \
3064 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3065 break; \
3066 case 2: /* Fetch and or */ \
3067 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3068 break; \
3069 case 3: /* Fetch and 'and' */ \
3070 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3071 break; \
3072 case 8: /* Swap */ \
3073 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3074 break; \
3075 case 4: /* Fetch and max unsigned */ \
3076 case 5: /* Fetch and max signed */ \
3077 case 6: /* Fetch and min unsigned */ \
3078 case 7: /* Fetch and min signed */ \
3079 case 16: /* compare and swap not equal */ \
3080 case 24: /* Fetch and increment bounded */ \
3081 case 25: /* Fetch and increment equal */ \
3082 case 28: /* Fetch and decrement bounded */ \
3083 gen_invalid(ctx); \
3084 break; \
3085 default: \
3086 /* invoke data storage error handler */ \
3087 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3088 } \
3089 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3090 tcg_temp_free_##tp(t0); \
3091 tcg_temp_free_##tp(t1); \
3092 tcg_temp_free(EA); \
3093 }
3094
3095 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
3096 #if defined(TARGET_PPC64)
3097 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
3098 #endif
3099
3100 #define ST_ATOMIC(name, memop, tp, op) \
3101 static void gen_##name(DisasContext *ctx) \
3102 { \
3103 int len = MEMOP_GET_SIZE(memop); \
3104 uint32_t gpr_FC = FC(ctx->opcode); \
3105 TCGv EA = tcg_temp_local_new(); \
3106 TCGv_##tp t0, t1; \
3107 \
3108 gen_addr_register(ctx, EA); \
3109 if (len > 1) { \
3110 gen_check_align(ctx, EA, len - 1); \
3111 } \
3112 t0 = tcg_temp_new_##tp(); \
3113 t1 = tcg_temp_new_##tp(); \
3114 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3115 \
3116 switch (gpr_FC) { \
3117 case 0: /* add and Store */ \
3118 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3119 break; \
3120 case 1: /* xor and Store */ \
3121 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3122 break; \
3123 case 2: /* Or and Store */ \
3124 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3125 break; \
3126 case 3: /* 'and' and Store */ \
3127 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3128 break; \
3129 case 4: /* Store max unsigned */ \
3130 case 5: /* Store max signed */ \
3131 case 6: /* Store min unsigned */ \
3132 case 7: /* Store min signed */ \
3133 case 24: /* Store twin */ \
3134 gen_invalid(ctx); \
3135 break; \
3136 default: \
3137 /* invoke data storage error handler */ \
3138 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3139 } \
3140 tcg_temp_free_##tp(t0); \
3141 tcg_temp_free_##tp(t1); \
3142 tcg_temp_free(EA); \
3143 }
3144
3145 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
3146 #if defined(TARGET_PPC64)
3147 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
3148 #endif
3149
3150 #if defined(CONFIG_USER_ONLY)
3151 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3152 int reg, int memop)
3153 {
3154 TCGv t0 = tcg_temp_new();
3155
3156 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3157 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3158 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3159 tcg_temp_free(t0);
3160 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3161 }
3162 #else
3163 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3164 int reg, int memop)
3165 {
3166 TCGLabel *l1 = gen_new_label();
3167 TCGLabel *l2 = gen_new_label();
3168 TCGv t0;
3169
3170 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3171
3172 t0 = tcg_temp_new();
3173 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3174 cpu_gpr[reg], ctx->mem_idx,
3175 DEF_MEMOP(memop) | MO_ALIGN);
3176 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3177 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3178 tcg_gen_or_tl(t0, t0, cpu_so);
3179 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3180 tcg_temp_free(t0);
3181 tcg_gen_br(l2);
3182
3183 gen_set_label(l1);
3184
3185 /* Address mismatch implies failure. But we still need to provide the
3186 memory barrier semantics of the instruction. */
3187 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3188 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3189
3190 gen_set_label(l2);
3191 tcg_gen_movi_tl(cpu_reserve, -1);
3192 }
3193 #endif
3194
3195 #define STCX(name, memop) \
3196 static void gen_##name(DisasContext *ctx) \
3197 { \
3198 TCGv t0; \
3199 int len = MEMOP_GET_SIZE(memop); \
3200 gen_set_access_type(ctx, ACCESS_RES); \
3201 t0 = tcg_temp_local_new(); \
3202 gen_addr_reg_index(ctx, t0); \
3203 if (len > 1) { \
3204 gen_check_align(ctx, t0, (len) - 1); \
3205 } \
3206 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3207 tcg_temp_free(t0); \
3208 }
3209
3210 STCX(stbcx_, DEF_MEMOP(MO_UB))
3211 STCX(sthcx_, DEF_MEMOP(MO_UW))
3212 STCX(stwcx_, DEF_MEMOP(MO_UL))
3213
3214 #if defined(TARGET_PPC64)
3215 /* ldarx */
3216 LARX(ldarx, DEF_MEMOP(MO_Q))
3217 /* stdcx. */
3218 STCX(stdcx_, DEF_MEMOP(MO_Q))
3219
3220 /* lqarx */
3221 static void gen_lqarx(DisasContext *ctx)
3222 {
3223 TCGv EA;
3224 int rd = rD(ctx->opcode);
3225 TCGv gpr1, gpr2;
3226
3227 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3228 (rd == rB(ctx->opcode)))) {
3229 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3230 return;
3231 }
3232
3233 gen_set_access_type(ctx, ACCESS_RES);
3234 EA = tcg_temp_local_new();
3235 gen_addr_reg_index(ctx, EA);
3236 gen_check_align(ctx, EA, 15);
3237 if (unlikely(ctx->le_mode)) {
3238 gpr1 = cpu_gpr[rd+1];
3239 gpr2 = cpu_gpr[rd];
3240 } else {
3241 gpr1 = cpu_gpr[rd];
3242 gpr2 = cpu_gpr[rd+1];
3243 }
3244 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3245 tcg_gen_mov_tl(cpu_reserve, EA);
3246 gen_addr_add(ctx, EA, EA, 8);
3247 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3248
3249 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3250 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3251 tcg_temp_free(EA);
3252 }
3253
3254 /* stqcx. */
3255 static void gen_stqcx_(DisasContext *ctx)
3256 {
3257 TCGv EA;
3258 int reg = rS(ctx->opcode);
3259 int len = 16;
3260 #if !defined(CONFIG_USER_ONLY)
3261 TCGLabel *l1;
3262 TCGv gpr1, gpr2;
3263 #endif
3264
3265 if (unlikely((rD(ctx->opcode) & 1))) {
3266 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3267 return;
3268 }
3269 gen_set_access_type(ctx, ACCESS_RES);
3270 EA = tcg_temp_local_new();
3271 gen_addr_reg_index(ctx, EA);
3272 if (len > 1) {
3273 gen_check_align(ctx, EA, (len) - 1);
3274 }
3275
3276 #if defined(CONFIG_USER_ONLY)
3277 gen_conditional_store(ctx, EA, reg, 16);
3278 #else
3279 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3280 l1 = gen_new_label();
3281 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3282 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3283
3284 if (unlikely(ctx->le_mode)) {
3285 gpr1 = cpu_gpr[reg + 1];
3286 gpr2 = cpu_gpr[reg];
3287 } else {
3288 gpr1 = cpu_gpr[reg];
3289 gpr2 = cpu_gpr[reg + 1];
3290 }
3291 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3292 gen_addr_add(ctx, EA, EA, 8);
3293 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3294
3295 gen_set_label(l1);
3296 tcg_gen_movi_tl(cpu_reserve, -1);
3297 #endif
3298 tcg_temp_free(EA);
3299 }
3300
3301 #endif /* defined(TARGET_PPC64) */
3302
3303 /* sync */
3304 static void gen_sync(DisasContext *ctx)
3305 {
3306 uint32_t l = (ctx->opcode >> 21) & 3;
3307
3308 /*
3309 * We may need to check for a pending TLB flush.
3310 *
3311 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3312 *
3313 * Additionally, this can only happen in kernel mode however so
3314 * check MSR_PR as well.
3315 */
3316 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3317 gen_check_tlb_flush(ctx, true);
3318 }
3319 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3320 }
3321
3322 /* wait */
3323 static void gen_wait(DisasContext *ctx)
3324 {
3325 TCGv_i32 t0 = tcg_const_i32(1);
3326 tcg_gen_st_i32(t0, cpu_env,
3327 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3328 tcg_temp_free_i32(t0);
3329 /* Stop translation, as the CPU is supposed to sleep from now */
3330 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3331 }
3332
3333 #if defined(TARGET_PPC64)
3334 static void gen_doze(DisasContext *ctx)
3335 {
3336 #if defined(CONFIG_USER_ONLY)
3337 GEN_PRIV;
3338 #else
3339 TCGv_i32 t;
3340
3341 CHK_HV;
3342 t = tcg_const_i32(PPC_PM_DOZE);
3343 gen_helper_pminsn(cpu_env, t);
3344 tcg_temp_free_i32(t);
3345 gen_stop_exception(ctx);
3346 #endif /* defined(CONFIG_USER_ONLY) */
3347 }
3348
3349 static void gen_nap(DisasContext *ctx)
3350 {
3351 #if defined(CONFIG_USER_ONLY)
3352 GEN_PRIV;
3353 #else
3354 TCGv_i32 t;
3355
3356 CHK_HV;
3357 t = tcg_const_i32(PPC_PM_NAP);
3358 gen_helper_pminsn(cpu_env, t);
3359 tcg_temp_free_i32(t);
3360 gen_stop_exception(ctx);
3361 #endif /* defined(CONFIG_USER_ONLY) */
3362 }
3363
3364 static void gen_stop(DisasContext *ctx)
3365 {
3366 gen_nap(ctx);
3367 }
3368
3369 static void gen_sleep(DisasContext *ctx)
3370 {
3371 #if defined(CONFIG_USER_ONLY)
3372 GEN_PRIV;
3373 #else
3374 TCGv_i32 t;
3375
3376 CHK_HV;
3377 t = tcg_const_i32(PPC_PM_SLEEP);
3378 gen_helper_pminsn(cpu_env, t);
3379 tcg_temp_free_i32(t);
3380 gen_stop_exception(ctx);
3381 #endif /* defined(CONFIG_USER_ONLY) */
3382 }
3383
3384 static void gen_rvwinkle(DisasContext *ctx)
3385 {
3386 #if defined(CONFIG_USER_ONLY)
3387 GEN_PRIV;
3388 #else
3389 TCGv_i32 t;
3390
3391 CHK_HV;
3392 t = tcg_const_i32(PPC_PM_RVWINKLE);
3393 gen_helper_pminsn(cpu_env, t);
3394 tcg_temp_free_i32(t);
3395 gen_stop_exception(ctx);
3396 #endif /* defined(CONFIG_USER_ONLY) */
3397 }
3398 #endif /* #if defined(TARGET_PPC64) */
3399
3400 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3401 {
3402 #if defined(TARGET_PPC64)
3403 if (ctx->has_cfar)
3404 tcg_gen_movi_tl(cpu_cfar, nip);
3405 #endif
3406 }
3407
3408 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3409 {
3410 if (unlikely(ctx->singlestep_enabled)) {
3411 return false;
3412 }
3413
3414 #ifndef CONFIG_USER_ONLY
3415 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3416 #else
3417 return true;
3418 #endif
3419 }
3420
3421 /*** Branch ***/
3422 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3423 {
3424 if (NARROW_MODE(ctx)) {
3425 dest = (uint32_t) dest;
3426 }
3427 if (use_goto_tb(ctx, dest)) {
3428 tcg_gen_goto_tb(n);
3429 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3430 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3431 } else {
3432 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3433 if (unlikely(ctx->singlestep_enabled)) {
3434 if ((ctx->singlestep_enabled &
3435 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3436 (ctx->exception == POWERPC_EXCP_BRANCH ||
3437 ctx->exception == POWERPC_EXCP_TRACE)) {
3438 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3439 }
3440 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3441 gen_debug_exception(ctx);
3442 }
3443 }
3444 tcg_gen_exit_tb(0);
3445 }
3446 }
3447
3448 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3449 {
3450 if (NARROW_MODE(ctx)) {
3451 nip = (uint32_t)nip;
3452 }
3453 tcg_gen_movi_tl(cpu_lr, nip);
3454 }
3455
3456 /* b ba bl bla */
3457 static void gen_b(DisasContext *ctx)
3458 {
3459 target_ulong li, target;
3460
3461 ctx->exception = POWERPC_EXCP_BRANCH;
3462 /* sign extend LI */
3463 li = LI(ctx->opcode);
3464 li = (li ^ 0x02000000) - 0x02000000;
3465 if (likely(AA(ctx->opcode) == 0)) {
3466 target = ctx->nip + li - 4;
3467 } else {
3468 target = li;
3469 }
3470 if (LK(ctx->opcode)) {
3471 gen_setlr(ctx, ctx->nip);
3472 }
3473 gen_update_cfar(ctx, ctx->nip - 4);
3474 gen_goto_tb(ctx, 0, target);
3475 }
3476
3477 #define BCOND_IM 0
3478 #define BCOND_LR 1
3479 #define BCOND_CTR 2
3480 #define BCOND_TAR 3
3481
3482 static inline void gen_bcond(DisasContext *ctx, int type)
3483 {
3484 uint32_t bo = BO(ctx->opcode);
3485 TCGLabel *l1;
3486 TCGv target;
3487
3488 ctx->exception = POWERPC_EXCP_BRANCH;
3489 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3490 target = tcg_temp_local_new();
3491 if (type == BCOND_CTR)
3492 tcg_gen_mov_tl(target, cpu_ctr);
3493 else if (type == BCOND_TAR)
3494 gen_load_spr(target, SPR_TAR);
3495 else
3496 tcg_gen_mov_tl(target, cpu_lr);
3497 } else {
3498 TCGV_UNUSED(target);
3499 }
3500 if (LK(ctx->opcode))
3501 gen_setlr(ctx, ctx->nip);
3502 l1 = gen_new_label();
3503 if ((bo & 0x4) == 0) {
3504 /* Decrement and test CTR */
3505 TCGv temp = tcg_temp_new();
3506 if (unlikely(type == BCOND_CTR)) {
3507 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3508 return;
3509 }
3510 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3511 if (NARROW_MODE(ctx)) {
3512 tcg_gen_ext32u_tl(temp, cpu_ctr);
3513 } else {
3514 tcg_gen_mov_tl(temp, cpu_ctr);
3515 }
3516 if (bo & 0x2) {
3517 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3518 } else {
3519 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3520 }
3521 tcg_temp_free(temp);
3522 }
3523 if ((bo & 0x10) == 0) {
3524 /* Test CR */
3525 uint32_t bi = BI(ctx->opcode);
3526 uint32_t mask = 0x08 >> (bi & 0x03);
3527 TCGv_i32 temp = tcg_temp_new_i32();
3528
3529 if (bo & 0x8) {
3530 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3531 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3532 } else {
3533 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3534 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3535 }
3536 tcg_temp_free_i32(temp);
3537 }
3538 gen_update_cfar(ctx, ctx->nip - 4);
3539 if (type == BCOND_IM) {
3540 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3541 if (likely(AA(ctx->opcode) == 0)) {
3542 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3543 } else {
3544 gen_goto_tb(ctx, 0, li);
3545 }
3546 if ((bo & 0x14) != 0x14) {
3547 gen_set_label(l1);
3548 gen_goto_tb(ctx, 1, ctx->nip);
3549 }
3550 } else {
3551 if (NARROW_MODE(ctx)) {
3552 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3553 } else {
3554 tcg_gen_andi_tl(cpu_nip, target, ~3);
3555 }
3556 tcg_gen_exit_tb(0);
3557 if ((bo & 0x14) != 0x14) {
3558 gen_set_label(l1);
3559 gen_update_nip(ctx, ctx->nip);
3560 tcg_gen_exit_tb(0);
3561 }
3562 }
3563 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3564 tcg_temp_free(target);
3565 }
3566 }
3567
3568 static void gen_bc(DisasContext *ctx)
3569 {
3570 gen_bcond(ctx, BCOND_IM);
3571 }
3572
3573 static void gen_bcctr(DisasContext *ctx)
3574 {
3575 gen_bcond(ctx, BCOND_CTR);
3576 }
3577
3578 static void gen_bclr(DisasContext *ctx)
3579 {
3580 gen_bcond(ctx, BCOND_LR);
3581 }
3582
3583 static void gen_bctar(DisasContext *ctx)
3584 {
3585 gen_bcond(ctx, BCOND_TAR);
3586 }
3587
3588 /*** Condition register logical ***/
3589 #define GEN_CRLOGIC(name, tcg_op, opc) \
3590 static void glue(gen_, name)(DisasContext *ctx) \
3591 { \
3592 uint8_t bitmask; \
3593 int sh; \
3594 TCGv_i32 t0, t1; \
3595 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3596 t0 = tcg_temp_new_i32(); \
3597 if (sh > 0) \
3598 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3599 else if (sh < 0) \
3600 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3601 else \
3602 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3603 t1 = tcg_temp_new_i32(); \
3604 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3605 if (sh > 0) \
3606 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3607 else if (sh < 0) \
3608 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3609 else \
3610 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3611 tcg_op(t0, t0, t1); \
3612 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3613 tcg_gen_andi_i32(t0, t0, bitmask); \
3614 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3615 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3616 tcg_temp_free_i32(t0); \
3617 tcg_temp_free_i32(t1); \
3618 }
3619
3620 /* crand */
3621 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3622 /* crandc */
3623 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3624 /* creqv */
3625 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3626 /* crnand */
3627 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3628 /* crnor */
3629 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3630 /* cror */
3631 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3632 /* crorc */
3633 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3634 /* crxor */
3635 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3636
3637 /* mcrf */
3638 static void gen_mcrf(DisasContext *ctx)
3639 {
3640 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3641 }
3642
3643 /*** System linkage ***/
3644
3645 /* rfi (supervisor only) */
3646 static void gen_rfi(DisasContext *ctx)
3647 {
3648 #if defined(CONFIG_USER_ONLY)
3649 GEN_PRIV;
3650 #else
3651 /* This instruction doesn't exist anymore on 64-bit server
3652 * processors compliant with arch 2.x
3653 */
3654 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3655 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3656 return;
3657 }
3658 /* Restore CPU state */
3659 CHK_SV;
3660 gen_update_cfar(ctx, ctx->nip - 4);
3661 gen_helper_rfi(cpu_env);
3662 gen_sync_exception(ctx);
3663 #endif
3664 }
3665
3666 #if defined(TARGET_PPC64)
3667 static void gen_rfid(DisasContext *ctx)
3668 {
3669 #if defined(CONFIG_USER_ONLY)
3670 GEN_PRIV;
3671 #else
3672 /* Restore CPU state */
3673 CHK_SV;
3674 gen_update_cfar(ctx, ctx->nip - 4);
3675 gen_helper_rfid(cpu_env);
3676 gen_sync_exception(ctx);
3677 #endif
3678 }
3679
3680 static void gen_hrfid(DisasContext *ctx)
3681 {
3682 #if defined(CONFIG_USER_ONLY)
3683 GEN_PRIV;
3684 #else
3685 /* Restore CPU state */
3686 CHK_HV;
3687 gen_helper_hrfid(cpu_env);
3688 gen_sync_exception(ctx);
3689 #endif
3690 }
3691 #endif
3692
3693 /* sc */
3694 #if defined(CONFIG_USER_ONLY)
3695 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3696 #else
3697 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3698 #endif
3699 static void gen_sc(DisasContext *ctx)
3700 {
3701 uint32_t lev;
3702
3703 lev = (ctx->opcode >> 5) & 0x7F;
3704 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3705 }
3706
3707 /*** Trap ***/
3708
3709 /* Check for unconditional traps (always or never) */
3710 static bool check_unconditional_trap(DisasContext *ctx)
3711 {
3712 /* Trap never */
3713 if (TO(ctx->opcode) == 0) {
3714 return true;
3715 }
3716 /* Trap always */
3717 if (TO(ctx->opcode) == 31) {
3718 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3719 return true;
3720 }
3721 return false;
3722 }
3723
3724 /* tw */
3725 static void gen_tw(DisasContext *ctx)
3726 {
3727 TCGv_i32 t0;
3728
3729 if (check_unconditional_trap(ctx)) {
3730 return;
3731 }
3732 t0 = tcg_const_i32(TO(ctx->opcode));
3733 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3734 t0);
3735 tcg_temp_free_i32(t0);
3736 }
3737
3738 /* twi */
3739 static void gen_twi(DisasContext *ctx)
3740 {
3741 TCGv t0;
3742 TCGv_i32 t1;
3743
3744 if (check_unconditional_trap(ctx)) {
3745 return;
3746 }
3747 t0 = tcg_const_tl(SIMM(ctx->opcode));
3748 t1 = tcg_const_i32(TO(ctx->opcode));
3749 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3750 tcg_temp_free(t0);
3751 tcg_temp_free_i32(t1);
3752 }
3753
3754 #if defined(TARGET_PPC64)
3755 /* td */
3756 static void gen_td(DisasContext *ctx)
3757 {
3758 TCGv_i32 t0;
3759
3760 if (check_unconditional_trap(ctx)) {
3761 return;
3762 }
3763 t0 = tcg_const_i32(TO(ctx->opcode));
3764 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3765 t0);
3766 tcg_temp_free_i32(t0);
3767 }
3768
3769 /* tdi */
3770 static void gen_tdi(DisasContext *ctx)
3771 {
3772 TCGv t0;
3773 TCGv_i32 t1;
3774
3775 if (check_unconditional_trap(ctx)) {
3776 return;
3777 }
3778 t0 = tcg_const_tl(SIMM(ctx->opcode));
3779 t1 = tcg_const_i32(TO(ctx->opcode));
3780 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3781 tcg_temp_free(t0);
3782 tcg_temp_free_i32(t1);
3783 }
3784 #endif
3785
3786 /*** Processor control ***/
3787
3788 static void gen_read_xer(DisasContext *ctx, TCGv dst)
3789 {
3790 TCGv t0 = tcg_temp_new();
3791 TCGv t1 = tcg_temp_new();
3792 TCGv t2 = tcg_temp_new();
3793 tcg_gen_mov_tl(dst, cpu_xer);
3794 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3795 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3796 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3797 tcg_gen_or_tl(t0, t0, t1);
3798 tcg_gen_or_tl(dst, dst, t2);
3799 tcg_gen_or_tl(dst, dst, t0);
3800 if (is_isa300(ctx)) {
3801 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
3802 tcg_gen_or_tl(dst, dst, t0);
3803 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
3804 tcg_gen_or_tl(dst, dst, t0);
3805 }
3806 tcg_temp_free(t0);
3807 tcg_temp_free(t1);
3808 tcg_temp_free(t2);
3809 }
3810
3811 static void gen_write_xer(TCGv src)
3812 {
3813 /* Write all flags, while reading back check for isa300 */
3814 tcg_gen_andi_tl(cpu_xer, src,
3815 ~((1u << XER_SO) |
3816 (1u << XER_OV) | (1u << XER_OV32) |
3817 (1u << XER_CA) | (1u << XER_CA32)));
3818 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
3819 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
3820 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3821 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3822 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
3823 }
3824
3825 /* mcrxr */
3826 static void gen_mcrxr(DisasContext *ctx)
3827 {
3828 TCGv_i32 t0 = tcg_temp_new_i32();
3829 TCGv_i32 t1 = tcg_temp_new_i32();
3830 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3831
3832 tcg_gen_trunc_tl_i32(t0, cpu_so);
3833 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3834 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3835 tcg_gen_shli_i32(t0, t0, 3);
3836 tcg_gen_shli_i32(t1, t1, 2);
3837 tcg_gen_shli_i32(dst, dst, 1);
3838 tcg_gen_or_i32(dst, dst, t0);
3839 tcg_gen_or_i32(dst, dst, t1);
3840 tcg_temp_free_i32(t0);
3841 tcg_temp_free_i32(t1);
3842
3843 tcg_gen_movi_tl(cpu_so, 0);
3844 tcg_gen_movi_tl(cpu_ov, 0);
3845 tcg_gen_movi_tl(cpu_ca, 0);
3846 }
3847
3848 #ifdef TARGET_PPC64
3849 /* mcrxrx */
3850 static void gen_mcrxrx(DisasContext *ctx)
3851 {
3852 TCGv t0 = tcg_temp_new();
3853 TCGv t1 = tcg_temp_new();
3854 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3855
3856 /* copy OV and OV32 */
3857 tcg_gen_shli_tl(t0, cpu_ov, 1);
3858 tcg_gen_or_tl(t0, t0, cpu_ov32);
3859 tcg_gen_shli_tl(t0, t0, 2);
3860 /* copy CA and CA32 */
3861 tcg_gen_shli_tl(t1, cpu_ca, 1);
3862 tcg_gen_or_tl(t1, t1, cpu_ca32);
3863 tcg_gen_or_tl(t0, t0, t1);
3864 tcg_gen_trunc_tl_i32(dst, t0);
3865 tcg_temp_free(t0);
3866 tcg_temp_free(t1);
3867 }
3868 #endif
3869
3870 /* mfcr mfocrf */
3871 static void gen_mfcr(DisasContext *ctx)
3872 {
3873 uint32_t crm, crn;
3874
3875 if (likely(ctx->opcode & 0x00100000)) {
3876 crm = CRM(ctx->opcode);
3877 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3878 crn = ctz32 (crm);
3879 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3880 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3881 cpu_gpr[rD(ctx->opcode)], crn * 4);
3882 }
3883 } else {
3884 TCGv_i32 t0 = tcg_temp_new_i32();
3885 tcg_gen_mov_i32(t0, cpu_crf[0]);
3886 tcg_gen_shli_i32(t0, t0, 4);
3887 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3888 tcg_gen_shli_i32(t0, t0, 4);
3889 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3890 tcg_gen_shli_i32(t0, t0, 4);
3891 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3892 tcg_gen_shli_i32(t0, t0, 4);
3893 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3894 tcg_gen_shli_i32(t0, t0, 4);
3895 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3896 tcg_gen_shli_i32(t0, t0, 4);
3897 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3898 tcg_gen_shli_i32(t0, t0, 4);
3899 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3900 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3901 tcg_temp_free_i32(t0);
3902 }
3903 }
3904
3905 /* mfmsr */
3906 static void gen_mfmsr(DisasContext *ctx)
3907 {
3908 CHK_SV;
3909 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3910 }
3911
3912 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3913 {
3914 #if 0
3915 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3916 printf("ERROR: try to access SPR %d !\n", sprn);
3917 #endif
3918 }
3919 #define SPR_NOACCESS (&spr_noaccess)
3920
3921 /* mfspr */
3922 static inline void gen_op_mfspr(DisasContext *ctx)
3923 {
3924 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3925 uint32_t sprn = SPR(ctx->opcode);
3926
3927 #if defined(CONFIG_USER_ONLY)
3928 read_cb = ctx->spr_cb[sprn].uea_read;
3929 #else
3930 if (ctx->pr) {
3931 read_cb = ctx->spr_cb[sprn].uea_read;
3932 } else if (ctx->hv) {
3933 read_cb = ctx->spr_cb[sprn].hea_read;
3934 } else {
3935 read_cb = ctx->spr_cb[sprn].oea_read;
3936 }
3937 #endif
3938 if (likely(read_cb != NULL)) {
3939 if (likely(read_cb != SPR_NOACCESS)) {
3940 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3941 } else {
3942 /* Privilege exception */
3943 /* This is a hack to avoid warnings when running Linux:
3944 * this OS breaks the PowerPC virtualisation model,
3945 * allowing userland application to read the PVR
3946 */
3947 if (sprn != SPR_PVR) {
3948 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3949 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3950 if (qemu_log_separate()) {
3951 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3952 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3953 }
3954 }
3955 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3956 }
3957 } else {
3958 /* ISA 2.07 defines these as no-ops */
3959 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3960 (sprn >= 808 && sprn <= 811)) {
3961 /* This is a nop */
3962 return;
3963 }
3964 /* Not defined */
3965 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3966 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3967 if (qemu_log_separate()) {
3968 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3969 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3970 }
3971
3972 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3973 * it can generate a priv, a hv emu or a no-op
3974 */
3975 if (sprn & 0x10) {
3976 if (ctx->pr) {
3977 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3978 }
3979 } else {
3980 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3981 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3982 }
3983 }
3984 }
3985 }
3986
3987 static void gen_mfspr(DisasContext *ctx)
3988 {
3989 gen_op_mfspr(ctx);
3990 }
3991
3992 /* mftb */
3993 static void gen_mftb(DisasContext *ctx)
3994 {
3995 gen_op_mfspr(ctx);
3996 }
3997
3998 /* mtcrf mtocrf*/
3999 static void gen_mtcrf(DisasContext *ctx)
4000 {
4001 uint32_t crm, crn;
4002
4003 crm = CRM(ctx->opcode);
4004 if (likely((ctx->opcode & 0x00100000))) {
4005 if (crm && ((crm & (crm - 1)) == 0)) {
4006 TCGv_i32 temp = tcg_temp_new_i32();
4007 crn = ctz32 (crm);
4008 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4009 tcg_gen_shri_i32(temp, temp, crn * 4);
4010 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4011 tcg_temp_free_i32(temp);
4012 }
4013 } else {
4014 TCGv_i32 temp = tcg_temp_new_i32();
4015 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4016 for (crn = 0 ; crn < 8 ; crn++) {
4017 if (crm & (1 << crn)) {
4018 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4019 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4020 }
4021 }
4022 tcg_temp_free_i32(temp);
4023 }
4024 }
4025
4026 /* mtmsr */
4027 #if defined(TARGET_PPC64)
4028 static void gen_mtmsrd(DisasContext *ctx)
4029 {
4030 CHK_SV;
4031
4032 #if !defined(CONFIG_USER_ONLY)
4033 if (ctx->opcode & 0x00010000) {
4034 /* Special form that does not need any synchronisation */
4035 TCGv t0 = tcg_temp_new();
4036 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4037 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4038 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4039 tcg_temp_free(t0);
4040 } else {
4041 /* XXX: we need to update nip before the store
4042 * if we enter power saving mode, we will exit the loop
4043 * directly from ppc_store_msr
4044 */
4045 gen_update_nip(ctx, ctx->nip);
4046 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4047 /* Must stop the translation as machine state (may have) changed */
4048 /* Note that mtmsr is not always defined as context-synchronizing */
4049 gen_stop_exception(ctx);
4050 }
4051 #endif /* !defined(CONFIG_USER_ONLY) */
4052 }
4053 #endif /* defined(TARGET_PPC64) */
4054
4055 static void gen_mtmsr(DisasContext *ctx)
4056 {
4057 CHK_SV;
4058
4059 #if !defined(CONFIG_USER_ONLY)
4060 if (ctx->opcode & 0x00010000) {
4061 /* Special form that does not need any synchronisation */
4062 TCGv t0 = tcg_temp_new();
4063 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4064 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4065 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4066 tcg_temp_free(t0);
4067 } else {
4068 TCGv msr = tcg_temp_new();
4069
4070 /* XXX: we need to update nip before the store
4071 * if we enter power saving mode, we will exit the loop
4072 * directly from ppc_store_msr
4073 */
4074 gen_update_nip(ctx, ctx->nip);
4075 #if defined(TARGET_PPC64)
4076 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4077 #else
4078 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4079 #endif
4080 gen_helper_store_msr(cpu_env, msr);
4081 tcg_temp_free(msr);
4082 /* Must stop the translation as machine state (may have) changed */
4083 /* Note that mtmsr is not always defined as context-synchronizing */
4084 gen_stop_exception(ctx);
4085 }
4086 #endif
4087 }
4088
4089 /* mtspr */
4090 static void gen_mtspr(DisasContext *ctx)
4091 {
4092 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4093 uint32_t sprn = SPR(ctx->opcode);
4094
4095 #if defined(CONFIG_USER_ONLY)
4096 write_cb = ctx->spr_cb[sprn].uea_write;
4097 #else
4098 if (ctx->pr) {
4099 write_cb = ctx->spr_cb[sprn].uea_write;
4100 } else if (ctx->hv) {
4101 write_cb = ctx->spr_cb[sprn].hea_write;
4102 } else {
4103 write_cb = ctx->spr_cb[sprn].oea_write;
4104 }
4105 #endif
4106 if (likely(write_cb != NULL)) {
4107 if (likely(write_cb != SPR_NOACCESS)) {
4108 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4109 } else {
4110 /* Privilege exception */
4111 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4112 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4113 if (qemu_log_separate()) {
4114 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4115 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4116 }
4117 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4118 }
4119 } else {
4120 /* ISA 2.07 defines these as no-ops */
4121 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4122 (sprn >= 808 && sprn <= 811)) {
4123 /* This is a nop */
4124 return;
4125 }
4126
4127 /* Not defined */
4128 if (qemu_log_separate()) {
4129 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4130 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4131 }
4132 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4133 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4134
4135
4136 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4137 * it can generate a priv, a hv emu or a no-op
4138 */
4139 if (sprn & 0x10) {
4140 if (ctx->pr) {
4141 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4142 }
4143 } else {
4144 if (ctx->pr || sprn == 0) {
4145 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4146 }
4147 }
4148 }
4149 }
4150
4151 #if defined(TARGET_PPC64)
4152 /* setb */
4153 static void gen_setb(DisasContext *ctx)
4154 {
4155 TCGv_i32 t0 = tcg_temp_new_i32();
4156 TCGv_i32 t8 = tcg_temp_new_i32();
4157 TCGv_i32 tm1 = tcg_temp_new_i32();
4158 int crf = crfS(ctx->opcode);
4159
4160 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4161 tcg_gen_movi_i32(t8, 8);
4162 tcg_gen_movi_i32(tm1, -1);
4163 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4164 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4165
4166 tcg_temp_free_i32(t0);
4167 tcg_temp_free_i32(t8);
4168 tcg_temp_free_i32(tm1);
4169 }
4170 #endif
4171
4172 /*** Cache management ***/
4173
4174 /* dcbf */
4175 static void gen_dcbf(DisasContext *ctx)
4176 {
4177 /* XXX: specification says this is treated as a load by the MMU */
4178 TCGv t0;
4179 gen_set_access_type(ctx, ACCESS_CACHE);
4180 t0 = tcg_temp_new();
4181 gen_addr_reg_index(ctx, t0);
4182 gen_qemu_ld8u(ctx, t0, t0);
4183 tcg_temp_free(t0);
4184 }
4185
4186 /* dcbi (Supervisor only) */
4187 static void gen_dcbi(DisasContext *ctx)
4188 {
4189 #if defined(CONFIG_USER_ONLY)
4190 GEN_PRIV;
4191 #else
4192 TCGv EA, val;
4193
4194 CHK_SV;
4195 EA = tcg_temp_new();
4196 gen_set_access_type(ctx, ACCESS_CACHE);
4197 gen_addr_reg_index(ctx, EA);
4198 val = tcg_temp_new();
4199 /* XXX: specification says this should be treated as a store by the MMU */
4200 gen_qemu_ld8u(ctx, val, EA);
4201 gen_qemu_st8(ctx, val, EA);
4202 tcg_temp_free(val);
4203 tcg_temp_free(EA);
4204 #endif /* defined(CONFIG_USER_ONLY) */
4205 }
4206
4207 /* dcdst */
4208 static void gen_dcbst(DisasContext *ctx)
4209 {
4210 /* XXX: specification say this is treated as a load by the MMU */
4211 TCGv t0;
4212 gen_set_access_type(ctx, ACCESS_CACHE);
4213 t0 = tcg_temp_new();
4214 gen_addr_reg_index(ctx, t0);
4215 gen_qemu_ld8u(ctx, t0, t0);
4216 tcg_temp_free(t0);
4217 }
4218
4219 /* dcbt */
4220 static void gen_dcbt(DisasContext *ctx)
4221 {
4222 /* interpreted as no-op */
4223 /* XXX: specification say this is treated as a load by the MMU
4224 * but does not generate any exception
4225 */
4226 }
4227
4228 /* dcbtst */
4229 static void gen_dcbtst(DisasContext *ctx)
4230 {
4231 /* interpreted as no-op */
4232 /* XXX: specification say this is treated as a load by the MMU
4233 * but does not generate any exception
4234 */
4235 }
4236
4237 /* dcbtls */
4238 static void gen_dcbtls(DisasContext *ctx)
4239 {
4240 /* Always fails locking the cache */
4241 TCGv t0 = tcg_temp_new();
4242 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4243 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4244 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4245 tcg_temp_free(t0);
4246 }
4247
4248 /* dcbz */
4249 static void gen_dcbz(DisasContext *ctx)
4250 {
4251 TCGv tcgv_addr;
4252 TCGv_i32 tcgv_op;
4253
4254 gen_set_access_type(ctx, ACCESS_CACHE);
4255 tcgv_addr = tcg_temp_new();
4256 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4257 gen_addr_reg_index(ctx, tcgv_addr);
4258 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4259 tcg_temp_free(tcgv_addr);
4260 tcg_temp_free_i32(tcgv_op);
4261 }
4262
4263 /* dst / dstt */
4264 static void gen_dst(DisasContext *ctx)
4265 {
4266 if (rA(ctx->opcode) == 0) {
4267 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4268 } else {
4269 /* interpreted as no-op */
4270 }
4271 }
4272
4273 /* dstst /dststt */
4274 static void gen_dstst(DisasContext *ctx)
4275 {
4276 if (rA(ctx->opcode) == 0) {
4277 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4278 } else {
4279 /* interpreted as no-op */
4280 }
4281
4282 }
4283
4284 /* dss / dssall */
4285 static void gen_dss(DisasContext *ctx)
4286 {
4287 /* interpreted as no-op */
4288 }
4289
4290 /* icbi */
4291 static void gen_icbi(DisasContext *ctx)
4292 {
4293 TCGv t0;
4294 gen_set_access_type(ctx, ACCESS_CACHE);
4295 t0 = tcg_temp_new();
4296 gen_addr_reg_index(ctx, t0);
4297 gen_helper_icbi(cpu_env, t0);
4298 tcg_temp_free(t0);
4299 }
4300
4301 /* Optional: */
4302 /* dcba */
4303 static void gen_dcba(DisasContext *ctx)
4304 {
4305 /* interpreted as no-op */
4306 /* XXX: specification say this is treated as a store by the MMU
4307 * but does not generate any exception
4308 */
4309 }
4310
4311 /*** Segment register manipulation ***/
4312 /* Supervisor only: */
4313
4314 /* mfsr */
4315 static void gen_mfsr(DisasContext *ctx)
4316 {
4317 #if defined(CONFIG_USER_ONLY)
4318 GEN_PRIV;
4319 #else
4320 TCGv t0;
4321
4322 CHK_SV;
4323 t0 = tcg_const_tl(SR(ctx->opcode));
4324 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4325 tcg_temp_free(t0);
4326 #endif /* defined(CONFIG_USER_ONLY) */
4327 }
4328
4329 /* mfsrin */
4330 static void gen_mfsrin(DisasContext *ctx)
4331 {
4332 #if defined(CONFIG_USER_ONLY)
4333 GEN_PRIV;
4334 #else
4335 TCGv t0;
4336
4337 CHK_SV;
4338 t0 = tcg_temp_new();
4339 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4340 tcg_gen_andi_tl(t0, t0, 0xF);
4341 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4342 tcg_temp_free(t0);
4343 #endif /* defined(CONFIG_USER_ONLY) */
4344 }
4345
4346 /* mtsr */
4347 static void gen_mtsr(DisasContext *ctx)
4348 {
4349 #if defined(CONFIG_USER_ONLY)
4350 GEN_PRIV;
4351 #else
4352 TCGv t0;
4353
4354 CHK_SV;
4355 t0 = tcg_const_tl(SR(ctx->opcode));
4356 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4357 tcg_temp_free(t0);
4358 #endif /* defined(CONFIG_USER_ONLY) */
4359 }
4360
4361 /* mtsrin */
4362 static void gen_mtsrin(DisasContext *ctx)
4363 {
4364 #if defined(CONFIG_USER_ONLY)
4365 GEN_PRIV;
4366 #else
4367 TCGv t0;
4368 CHK_SV;
4369
4370 t0 = tcg_temp_new();
4371 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4372 tcg_gen_andi_tl(t0, t0, 0xF);
4373 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4374 tcg_temp_free(t0);
4375 #endif /* defined(CONFIG_USER_ONLY) */
4376 }
4377
4378 #if defined(TARGET_PPC64)
4379 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4380
4381 /* mfsr */
4382 static void gen_mfsr_64b(DisasContext *ctx)
4383 {
4384 #if defined(CONFIG_USER_ONLY)
4385 GEN_PRIV;
4386 #else
4387 TCGv t0;
4388
4389 CHK_SV;
4390 t0 = tcg_const_tl(SR(ctx->opcode));
4391 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4392 tcg_temp_free(t0);
4393 #endif /* defined(CONFIG_USER_ONLY) */
4394 }
4395
4396 /* mfsrin */
4397 static void gen_mfsrin_64b(DisasContext *ctx)
4398 {
4399 #if defined(CONFIG_USER_ONLY)
4400 GEN_PRIV;
4401 #else
4402 TCGv t0;
4403
4404 CHK_SV;
4405 t0 = tcg_temp_new();
4406 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4407 tcg_gen_andi_tl(t0, t0, 0xF);
4408 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4409 tcg_temp_free(t0);
4410 #endif /* defined(CONFIG_USER_ONLY) */
4411 }
4412
4413 /* mtsr */
4414 static void gen_mtsr_64b(DisasContext *ctx)
4415 {
4416 #if defined(CONFIG_USER_ONLY)
4417 GEN_PRIV;
4418 #else
4419 TCGv t0;
4420
4421 CHK_SV;
4422 t0 = tcg_const_tl(SR(ctx->opcode));
4423 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4424 tcg_temp_free(t0);
4425 #endif /* defined(CONFIG_USER_ONLY) */
4426 }
4427
4428 /* mtsrin */
4429 static void gen_mtsrin_64b(DisasContext *ctx)
4430 {
4431 #if defined(CONFIG_USER_ONLY)
4432 GEN_PRIV;
4433 #else
4434 TCGv t0;
4435
4436 CHK_SV;
4437 t0 = tcg_temp_new();
4438 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4439 tcg_gen_andi_tl(t0, t0, 0xF);
4440 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4441 tcg_temp_free(t0);
4442 #endif /* defined(CONFIG_USER_ONLY) */
4443 }
4444
4445 /* slbmte */
4446 static void gen_slbmte(DisasContext *ctx)
4447 {
4448 #if defined(CONFIG_USER_ONLY)
4449 GEN_PRIV;
4450 #else
4451 CHK_SV;
4452
4453 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4454 cpu_gpr[rS(ctx->opcode)]);
4455 #endif /* defined(CONFIG_USER_ONLY) */
4456 }
4457
4458 static void gen_slbmfee(DisasContext *ctx)
4459 {
4460 #if defined(CONFIG_USER_ONLY)
4461 GEN_PRIV;
4462 #else
4463 CHK_SV;
4464
4465 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4466 cpu_gpr[rB(ctx->opcode)]);
4467 #endif /* defined(CONFIG_USER_ONLY) */
4468 }
4469
4470 static void gen_slbmfev(DisasContext *ctx)
4471 {
4472 #if defined(CONFIG_USER_ONLY)
4473 GEN_PRIV;
4474 #else
4475 CHK_SV;
4476
4477 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4478 cpu_gpr[rB(ctx->opcode)]);
4479 #endif /* defined(CONFIG_USER_ONLY) */
4480 }
4481
4482 static void gen_slbfee_(DisasContext *ctx)
4483 {
4484 #if defined(CONFIG_USER_ONLY)
4485 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4486 #else
4487 TCGLabel *l1, *l2;
4488
4489 if (unlikely(ctx->pr)) {
4490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4491 return;
4492 }
4493 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4494 cpu_gpr[rB(ctx->opcode)]);
4495 l1 = gen_new_label();
4496 l2 = gen_new_label();
4497 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4498 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4499 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4500 tcg_gen_br(l2);
4501 gen_set_label(l1);
4502 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4503 gen_set_label(l2);
4504 #endif
4505 }
4506 #endif /* defined(TARGET_PPC64) */
4507
4508 /*** Lookaside buffer management ***/
4509 /* Optional & supervisor only: */
4510
4511 /* tlbia */
4512 static void gen_tlbia(DisasContext *ctx)
4513 {
4514 #if defined(CONFIG_USER_ONLY)
4515 GEN_PRIV;
4516 #else
4517 CHK_HV;
4518
4519 gen_helper_tlbia(cpu_env);
4520 #endif /* defined(CONFIG_USER_ONLY) */
4521 }
4522
4523 /* tlbiel */
4524 static void gen_tlbiel(DisasContext *ctx)
4525 {
4526 #if defined(CONFIG_USER_ONLY)
4527 GEN_PRIV;
4528 #else
4529 CHK_SV;
4530
4531 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4532 #endif /* defined(CONFIG_USER_ONLY) */
4533 }
4534
4535 /* tlbie */
4536 static void gen_tlbie(DisasContext *ctx)
4537 {
4538 #if defined(CONFIG_USER_ONLY)
4539 GEN_PRIV;
4540 #else
4541 TCGv_i32 t1;
4542
4543 if (ctx->gtse) {
4544 CHK_SV; /* If gtse is set then tblie is supervisor privileged */
4545 } else {
4546 CHK_HV; /* Else hypervisor privileged */
4547 }
4548
4549 if (NARROW_MODE(ctx)) {
4550 TCGv t0 = tcg_temp_new();
4551 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4552 gen_helper_tlbie(cpu_env, t0);
4553 tcg_temp_free(t0);
4554 } else {
4555 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4556 }
4557 t1 = tcg_temp_new_i32();
4558 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4559 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4560 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4561 tcg_temp_free_i32(t1);
4562 #endif /* defined(CONFIG_USER_ONLY) */
4563 }
4564
4565 /* tlbsync */
4566 static void gen_tlbsync(DisasContext *ctx)
4567 {
4568 #if defined(CONFIG_USER_ONLY)
4569 GEN_PRIV;
4570 #else
4571 CHK_HV;
4572
4573 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4574 if (ctx->insns_flags & PPC_BOOKE) {
4575 gen_check_tlb_flush(ctx, true);
4576 }
4577 #endif /* defined(CONFIG_USER_ONLY) */
4578 }
4579
4580 #if defined(TARGET_PPC64)
4581 /* slbia */
4582 static void gen_slbia(DisasContext *ctx)
4583 {
4584 #if defined(CONFIG_USER_ONLY)
4585 GEN_PRIV;
4586 #else
4587 CHK_SV;
4588
4589 gen_helper_slbia(cpu_env);
4590 #endif /* defined(CONFIG_USER_ONLY) */
4591 }
4592
4593 /* slbie */
4594 static void gen_slbie(DisasContext *ctx)
4595 {
4596 #if defined(CONFIG_USER_ONLY)
4597 GEN_PRIV;
4598 #else
4599 CHK_SV;
4600
4601 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4602 #endif /* defined(CONFIG_USER_ONLY) */
4603 }
4604
4605 /* slbieg */
4606 static void gen_slbieg(DisasContext *ctx)
4607 {
4608 #if defined(CONFIG_USER_ONLY)
4609 GEN_PRIV;
4610 #else
4611 CHK_SV;
4612
4613 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4614 #endif /* defined(CONFIG_USER_ONLY) */
4615 }
4616
4617 /* slbsync */
4618 static void gen_slbsync(DisasContext *ctx)
4619 {
4620 #if defined(CONFIG_USER_ONLY)
4621 GEN_PRIV;
4622 #else
4623 CHK_SV;
4624 gen_check_tlb_flush(ctx, true);
4625 #endif /* defined(CONFIG_USER_ONLY) */
4626 }
4627
4628 #endif /* defined(TARGET_PPC64) */
4629
4630 /*** External control ***/
4631 /* Optional: */
4632
4633 /* eciwx */
4634 static void gen_eciwx(DisasContext *ctx)
4635 {
4636 TCGv t0;
4637 /* Should check EAR[E] ! */
4638 gen_set_access_type(ctx, ACCESS_EXT);
4639 t0 = tcg_temp_new();
4640 gen_addr_reg_index(ctx, t0);
4641 gen_check_align(ctx, t0, 0x03);
4642 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4643 tcg_temp_free(t0);
4644 }
4645
4646 /* ecowx */
4647 static void gen_ecowx(DisasContext *ctx)
4648 {
4649 TCGv t0;
4650 /* Should check EAR[E] ! */
4651 gen_set_access_type(ctx, ACCESS_EXT);
4652 t0 = tcg_temp_new();
4653 gen_addr_reg_index(ctx, t0);
4654 gen_check_align(ctx, t0, 0x03);
4655 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4656 tcg_temp_free(t0);
4657 }
4658
4659 /* PowerPC 601 specific instructions */
4660
4661 /* abs - abs. */
4662 static void gen_abs(DisasContext *ctx)
4663 {
4664 TCGLabel *l1 = gen_new_label();
4665 TCGLabel *l2 = gen_new_label();
4666 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4667 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4668 tcg_gen_br(l2);
4669 gen_set_label(l1);
4670 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4671 gen_set_label(l2);
4672 if (unlikely(Rc(ctx->opcode) != 0))
4673 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4674 }
4675
4676 /* abso - abso. */
4677 static void gen_abso(DisasContext *ctx)
4678 {
4679 TCGLabel *l1 = gen_new_label();
4680 TCGLabel *l2 = gen_new_label();
4681 TCGLabel *l3 = gen_new_label();
4682 /* Start with XER OV disabled, the most likely case */
4683 tcg_gen_movi_tl(cpu_ov, 0);
4684 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4685 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4686 tcg_gen_movi_tl(cpu_ov, 1);
4687 tcg_gen_movi_tl(cpu_so, 1);
4688 tcg_gen_br(l2);
4689 gen_set_label(l1);
4690 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4691 tcg_gen_br(l3);
4692 gen_set_label(l2);
4693 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4694 gen_set_label(l3);
4695 if (unlikely(Rc(ctx->opcode) != 0))
4696 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4697 }
4698
4699 /* clcs */
4700 static void gen_clcs(DisasContext *ctx)
4701 {
4702 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4703 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4704 tcg_temp_free_i32(t0);
4705 /* Rc=1 sets CR0 to an undefined state */
4706 }
4707
4708 /* div - div. */
4709 static void gen_div(DisasContext *ctx)
4710 {
4711 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4712 cpu_gpr[rB(ctx->opcode)]);
4713 if (unlikely(Rc(ctx->opcode) != 0))
4714 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4715 }
4716
4717 /* divo - divo. */
4718 static void gen_divo(DisasContext *ctx)
4719 {
4720 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4721 cpu_gpr[rB(ctx->opcode)]);
4722 if (unlikely(Rc(ctx->opcode) != 0))
4723 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4724 }
4725
4726 /* divs - divs. */
4727 static void gen_divs(DisasContext *ctx)
4728 {
4729 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4730 cpu_gpr[rB(ctx->opcode)]);
4731 if (unlikely(Rc(ctx->opcode) != 0))
4732 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4733 }
4734
4735 /* divso - divso. */
4736 static void gen_divso(DisasContext *ctx)
4737 {
4738 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4739 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4740 if (unlikely(Rc(ctx->opcode) != 0))
4741 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4742 }
4743
4744 /* doz - doz. */
4745 static void gen_doz(DisasContext *ctx)
4746 {
4747 TCGLabel *l1 = gen_new_label();
4748 TCGLabel *l2 = gen_new_label();
4749 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4750 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4751 tcg_gen_br(l2);
4752 gen_set_label(l1);
4753 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4754 gen_set_label(l2);
4755 if (unlikely(Rc(ctx->opcode) != 0))
4756 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4757 }
4758
4759 /* dozo - dozo. */
4760 static void gen_dozo(DisasContext *ctx)
4761 {
4762 TCGLabel *l1 = gen_new_label();
4763 TCGLabel *l2 = gen_new_label();
4764 TCGv t0 = tcg_temp_new();
4765 TCGv t1 = tcg_temp_new();
4766 TCGv t2 = tcg_temp_new();
4767 /* Start with XER OV disabled, the most likely case */
4768 tcg_gen_movi_tl(cpu_ov, 0);
4769 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4770 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4771 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4772 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4773 tcg_gen_andc_tl(t1, t1, t2);
4774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4775 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4776 tcg_gen_movi_tl(cpu_ov, 1);
4777 tcg_gen_movi_tl(cpu_so, 1);
4778 tcg_gen_br(l2);
4779 gen_set_label(l1);
4780 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4781 gen_set_label(l2);
4782 tcg_temp_free(t0);
4783 tcg_temp_free(t1);
4784 tcg_temp_free(t2);
4785 if (unlikely(Rc(ctx->opcode) != 0))
4786 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4787 }
4788
4789 /* dozi */
4790 static void gen_dozi(DisasContext *ctx)
4791 {
4792 target_long simm = SIMM(ctx->opcode);
4793 TCGLabel *l1 = gen_new_label();
4794 TCGLabel *l2 = gen_new_label();
4795 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4796 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4797 tcg_gen_br(l2);
4798 gen_set_label(l1);
4799 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4800 gen_set_label(l2);
4801 if (unlikely(Rc(ctx->opcode) != 0))
4802 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4803 }
4804
4805 /* lscbx - lscbx. */
4806 static void gen_lscbx(DisasContext *ctx)
4807 {
4808 TCGv t0 = tcg_temp_new();
4809 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4810 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4811 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4812
4813 gen_addr_reg_index(ctx, t0);
4814 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4815 tcg_temp_free_i32(t1);
4816 tcg_temp_free_i32(t2);
4817 tcg_temp_free_i32(t3);
4818 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4819 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4820 if (unlikely(Rc(ctx->opcode) != 0))
4821 gen_set_Rc0(ctx, t0);
4822 tcg_temp_free(t0);
4823 }
4824
4825 /* maskg - maskg. */
4826 static void gen_maskg(DisasContext *ctx)
4827 {
4828 TCGLabel *l1 = gen_new_label();
4829 TCGv t0 = tcg_temp_new();
4830 TCGv t1 = tcg_temp_new();
4831 TCGv t2 = tcg_temp_new();
4832 TCGv t3 = tcg_temp_new();
4833 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4834 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4835 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4836 tcg_gen_addi_tl(t2, t0, 1);
4837 tcg_gen_shr_tl(t2, t3, t2);
4838 tcg_gen_shr_tl(t3, t3, t1);
4839 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4840 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4841 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4842 gen_set_label(l1);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
4845 tcg_temp_free(t2);
4846 tcg_temp_free(t3);
4847 if (unlikely(Rc(ctx->opcode) != 0))
4848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4849 }
4850
4851 /* maskir - maskir. */
4852 static void gen_maskir(DisasContext *ctx)
4853 {
4854 TCGv t0 = tcg_temp_new();
4855 TCGv t1 = tcg_temp_new();
4856 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4857 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4858 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4859 tcg_temp_free(t0);
4860 tcg_temp_free(t1);
4861 if (unlikely(Rc(ctx->opcode) != 0))
4862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4863 }
4864
4865 /* mul - mul. */
4866 static void gen_mul(DisasContext *ctx)
4867 {
4868 TCGv_i64 t0 = tcg_temp_new_i64();
4869 TCGv_i64 t1 = tcg_temp_new_i64();
4870 TCGv t2 = tcg_temp_new();
4871 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4872 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4873 tcg_gen_mul_i64(t0, t0, t1);
4874 tcg_gen_trunc_i64_tl(t2, t0);
4875 gen_store_spr(SPR_MQ, t2);
4876 tcg_gen_shri_i64(t1, t0, 32);
4877 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4878 tcg_temp_free_i64(t0);
4879 tcg_temp_free_i64(t1);
4880 tcg_temp_free(t2);
4881 if (unlikely(Rc(ctx->opcode) != 0))
4882 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4883 }
4884
4885 /* mulo - mulo. */
4886 static void gen_mulo(DisasContext *ctx)
4887 {
4888 TCGLabel *l1 = gen_new_label();
4889 TCGv_i64 t0 = tcg_temp_new_i64();
4890 TCGv_i64 t1 = tcg_temp_new_i64();
4891 TCGv t2 = tcg_temp_new();
4892 /* Start with XER OV disabled, the most likely case */
4893 tcg_gen_movi_tl(cpu_ov, 0);
4894 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4895 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4896 tcg_gen_mul_i64(t0, t0, t1);
4897 tcg_gen_trunc_i64_tl(t2, t0);
4898 gen_store_spr(SPR_MQ, t2);
4899 tcg_gen_shri_i64(t1, t0, 32);
4900 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4901 tcg_gen_ext32s_i64(t1, t0);
4902 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4903 tcg_gen_movi_tl(cpu_ov, 1);
4904 tcg_gen_movi_tl(cpu_so, 1);
4905 gen_set_label(l1);
4906 tcg_temp_free_i64(t0);
4907 tcg_temp_free_i64(t1);
4908 tcg_temp_free(t2);
4909 if (unlikely(Rc(ctx->opcode) != 0))
4910 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4911 }
4912
4913 /* nabs - nabs. */
4914 static void gen_nabs(DisasContext *ctx)
4915 {
4916 TCGLabel *l1 = gen_new_label();
4917 TCGLabel *l2 = gen_new_label();
4918 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4919 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4920 tcg_gen_br(l2);
4921 gen_set_label(l1);
4922 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4923 gen_set_label(l2);
4924 if (unlikely(Rc(ctx->opcode) != 0))
4925 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4926 }
4927
4928 /* nabso - nabso. */
4929 static void gen_nabso(DisasContext *ctx)
4930 {
4931 TCGLabel *l1 = gen_new_label();
4932 TCGLabel *l2 = gen_new_label();
4933 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4934 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4935 tcg_gen_br(l2);
4936 gen_set_label(l1);
4937 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4938 gen_set_label(l2);
4939 /* nabs never overflows */
4940 tcg_gen_movi_tl(cpu_ov, 0);
4941 if (unlikely(Rc(ctx->opcode) != 0))
4942 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4943 }
4944
4945 /* rlmi - rlmi. */
4946 static void gen_rlmi(DisasContext *ctx)
4947 {
4948 uint32_t mb = MB(ctx->opcode);
4949 uint32_t me = ME(ctx->opcode);
4950 TCGv t0 = tcg_temp_new();
4951 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4952 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4953 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4954 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4955 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4956 tcg_temp_free(t0);
4957 if (unlikely(Rc(ctx->opcode) != 0))
4958 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4959 }
4960
4961 /* rrib - rrib. */
4962 static void gen_rrib(DisasContext *ctx)
4963 {
4964 TCGv t0 = tcg_temp_new();
4965 TCGv t1 = tcg_temp_new();
4966 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4967 tcg_gen_movi_tl(t1, 0x80000000);
4968 tcg_gen_shr_tl(t1, t1, t0);
4969 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4970 tcg_gen_and_tl(t0, t0, t1);
4971 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4972 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4973 tcg_temp_free(t0);
4974 tcg_temp_free(t1);
4975 if (unlikely(Rc(ctx->opcode) != 0))
4976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4977 }
4978
4979 /* sle - sle. */
4980 static void gen_sle(DisasContext *ctx)
4981 {
4982 TCGv t0 = tcg_temp_new();
4983 TCGv t1 = tcg_temp_new();
4984 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4985 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4986 tcg_gen_subfi_tl(t1, 32, t1);
4987 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4988 tcg_gen_or_tl(t1, t0, t1);
4989 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4990 gen_store_spr(SPR_MQ, t1);
4991 tcg_temp_free(t0);
4992 tcg_temp_free(t1);
4993 if (unlikely(Rc(ctx->opcode) != 0))
4994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4995 }
4996
4997 /* sleq - sleq. */
4998 static void gen_sleq(DisasContext *ctx)
4999 {
5000 TCGv t0 = tcg_temp_new();
5001 TCGv t1 = tcg_temp_new();
5002 TCGv t2 = tcg_temp_new();
5003 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5004 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5005 tcg_gen_shl_tl(t2, t2, t0);
5006 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5007 gen_load_spr(t1, SPR_MQ);
5008 gen_store_spr(SPR_MQ, t0);
5009 tcg_gen_and_tl(t0, t0, t2);
5010 tcg_gen_andc_tl(t1, t1, t2);
5011 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5012 tcg_temp_free(t0);
5013 tcg_temp_free(t1);
5014 tcg_temp_free(t2);
5015 if (unlikely(Rc(ctx->opcode) != 0))
5016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5017 }
5018
5019 /* sliq - sliq. */
5020 static void gen_sliq(DisasContext *ctx)
5021 {
5022 int sh = SH(ctx->opcode);
5023 TCGv t0 = tcg_temp_new();
5024 TCGv t1 = tcg_temp_new();
5025 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5026 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5027 tcg_gen_or_tl(t1, t0, t1);
5028 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5029 gen_store_spr(SPR_MQ, t1);
5030 tcg_temp_free(t0);
5031 tcg_temp_free(t1);
5032 if (unlikely(Rc(ctx->opcode) != 0))
5033 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5034 }
5035
5036 /* slliq - slliq. */
5037 static void gen_slliq(DisasContext *ctx)
5038 {
5039 int sh = SH(ctx->opcode);
5040 TCGv t0 = tcg_temp_new();
5041 TCGv t1 = tcg_temp_new();
5042 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5043 gen_load_spr(t1, SPR_MQ);
5044 gen_store_spr(SPR_MQ, t0);
5045 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5046 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5047 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5048 tcg_temp_free(t0);
5049 tcg_temp_free(t1);
5050 if (unlikely(Rc(ctx->opcode) != 0))
5051 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5052 }
5053
5054 /* sllq - sllq. */
5055 static void gen_sllq(DisasContext *ctx)
5056 {
5057 TCGLabel *l1 = gen_new_label();
5058 TCGLabel *l2 = gen_new_label();
5059 TCGv t0 = tcg_temp_local_new();
5060 TCGv t1 = tcg_temp_local_new();
5061 TCGv t2 = tcg_temp_local_new();
5062 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5063 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5064 tcg_gen_shl_tl(t1, t1, t2);
5065 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5066 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5067 gen_load_spr(t0, SPR_MQ);
5068 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5069 tcg_gen_br(l2);
5070 gen_set_label(l1);
5071 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5072 gen_load_spr(t2, SPR_MQ);
5073 tcg_gen_andc_tl(t1, t2, t1);
5074 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5075 gen_set_label(l2);
5076 tcg_temp_free(t0);
5077 tcg_temp_free(t1);
5078 tcg_temp_free(t2);
5079 if (unlikely(Rc(ctx->opcode) != 0))
5080 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5081 }
5082
5083 /* slq - slq. */
5084 static void gen_slq(DisasContext *ctx)
5085 {
5086 TCGLabel *l1 = gen_new_label();
5087 TCGv t0 = tcg_temp_new();
5088 TCGv t1 = tcg_temp_new();
5089 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5090 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5091 tcg_gen_subfi_tl(t1, 32, t1);
5092 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5093 tcg_gen_or_tl(t1, t0, t1);
5094 gen_store_spr(SPR_MQ, t1);
5095 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5097 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5098 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5099 gen_set_label(l1);
5100 tcg_temp_free(t0);
5101 tcg_temp_free(t1);
5102 if (unlikely(Rc(ctx->opcode) != 0))
5103 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5104 }
5105
5106 /* sraiq - sraiq. */
5107 static void gen_sraiq(DisasContext *ctx)
5108 {
5109 int sh = SH(ctx->opcode);
5110 TCGLabel *l1 = gen_new_label();
5111 TCGv t0 = tcg_temp_new();
5112 TCGv t1 = tcg_temp_new();
5113 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5114 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5115 tcg_gen_or_tl(t0, t0, t1);
5116 gen_store_spr(SPR_MQ, t0);
5117 tcg_gen_movi_tl(cpu_ca, 0);
5118 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5119 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5120 tcg_gen_movi_tl(cpu_ca, 1);
5121 gen_set_label(l1);
5122 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5123 tcg_temp_free(t0);
5124 tcg_temp_free(t1);
5125 if (unlikely(Rc(ctx->opcode) != 0))
5126 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5127 }
5128
5129 /* sraq - sraq. */
5130 static void gen_sraq(DisasContext *ctx)
5131 {
5132 TCGLabel *l1 = gen_new_label();
5133 TCGLabel *l2 = gen_new_label();
5134 TCGv t0 = tcg_temp_new();
5135 TCGv t1 = tcg_temp_local_new();
5136 TCGv t2 = tcg_temp_local_new();
5137 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5138 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5139 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5140 tcg_gen_subfi_tl(t2, 32, t2);
5141 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5142 tcg_gen_or_tl(t0, t0, t2);
5143 gen_store_spr(SPR_MQ, t0);
5144 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5145 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5146 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5147 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5148 gen_set_label(l1);
5149 tcg_temp_free(t0);
5150 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5151 tcg_gen_movi_tl(cpu_ca, 0);
5152 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5153 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5154 tcg_gen_movi_tl(cpu_ca, 1);
5155 gen_set_label(l2);
5156 tcg_temp_free(t1);
5157 tcg_temp_free(t2);
5158 if (unlikely(Rc(ctx->opcode) != 0))
5159 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5160 }
5161
5162 /* sre - sre. */
5163 static void gen_sre(DisasContext *ctx)
5164 {
5165 TCGv t0 = tcg_temp_new();
5166 TCGv t1 = tcg_temp_new();
5167 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5168 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5169 tcg_gen_subfi_tl(t1, 32, t1);
5170 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5171 tcg_gen_or_tl(t1, t0, t1);
5172 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5173 gen_store_spr(SPR_MQ, t1);
5174 tcg_temp_free(t0);
5175 tcg_temp_free(t1);
5176 if (unlikely(Rc(ctx->opcode) != 0))
5177 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5178 }
5179
5180 /* srea - srea. */
5181 static void gen_srea(DisasContext *ctx)
5182 {
5183 TCGv t0 = tcg_temp_new();
5184 TCGv t1 = tcg_temp_new();
5185 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5186 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5187 gen_store_spr(SPR_MQ, t0);
5188 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5189 tcg_temp_free(t0);
5190 tcg_temp_free(t1);
5191 if (unlikely(Rc(ctx->opcode) != 0))
5192 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5193 }
5194
5195 /* sreq */
5196 static void gen_sreq(DisasContext *ctx)
5197 {
5198 TCGv t0 = tcg_temp_new();
5199 TCGv t1 = tcg_temp_new();
5200 TCGv t2 = tcg_temp_new();
5201 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5202 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5203 tcg_gen_shr_tl(t1, t1, t0);
5204 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5205 gen_load_spr(t2, SPR_MQ);
5206 gen_store_spr(SPR_MQ, t0);
5207 tcg_gen_and_tl(t0, t0, t1);
5208 tcg_gen_andc_tl(t2, t2, t1);
5209 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5210 tcg_temp_free(t0);
5211 tcg_temp_free(t1);
5212 tcg_temp_free(t2);
5213 if (unlikely(Rc(ctx->opcode) != 0))
5214 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5215 }
5216
5217 /* sriq */
5218 static void gen_sriq(DisasContext *ctx)
5219 {
5220 int sh = SH(ctx->opcode);
5221 TCGv t0 = tcg_temp_new();
5222 TCGv t1 = tcg_temp_new();
5223 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5224 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5225 tcg_gen_or_tl(t1, t0, t1);
5226 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5227 gen_store_spr(SPR_MQ, t1);
5228 tcg_temp_free(t0);
5229 tcg_temp_free(t1);
5230 if (unlikely(Rc(ctx->opcode) != 0))
5231 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5232 }
5233
5234 /* srliq */
5235 static void gen_srliq(DisasContext *ctx)
5236 {
5237 int sh = SH(ctx->opcode);
5238 TCGv t0 = tcg_temp_new();
5239 TCGv t1 = tcg_temp_new();
5240 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5241 gen_load_spr(t1, SPR_MQ);
5242 gen_store_spr(SPR_MQ, t0);
5243 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5244 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5245 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5246 tcg_temp_free(t0);
5247 tcg_temp_free(t1);
5248 if (unlikely(Rc(ctx->opcode) != 0))
5249 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5250 }
5251
5252 /* srlq */
5253 static void gen_srlq(DisasContext *ctx)
5254 {
5255 TCGLabel *l1 = gen_new_label();
5256 TCGLabel *l2 = gen_new_label();
5257 TCGv t0 = tcg_temp_local_new();
5258 TCGv t1 = tcg_temp_local_new();
5259 TCGv t2 = tcg_temp_local_new();
5260 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5261 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5262 tcg_gen_shr_tl(t2, t1, t2);
5263 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5264 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5265 gen_load_spr(t0, SPR_MQ);
5266 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5267 tcg_gen_br(l2);
5268 gen_set_label(l1);
5269 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5270 tcg_gen_and_tl(t0, t0, t2);
5271 gen_load_spr(t1, SPR_MQ);
5272 tcg_gen_andc_tl(t1, t1, t2);
5273 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5274 gen_set_label(l2);
5275 tcg_temp_free(t0);
5276 tcg_temp_free(t1);
5277 tcg_temp_free(t2);
5278 if (unlikely(Rc(ctx->opcode) != 0))
5279 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5280 }
5281
5282 /* srq */
5283 static void gen_srq(DisasContext *ctx)
5284 {
5285 TCGLabel *l1 = gen_new_label();
5286 TCGv t0 = tcg_temp_new();
5287 TCGv t1 = tcg_temp_new();
5288 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5289 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5290 tcg_gen_subfi_tl(t1, 32, t1);
5291 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5292 tcg_gen_or_tl(t1, t0, t1);
5293 gen_store_spr(SPR_MQ, t1);
5294 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5295 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5296 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5297 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5298 gen_set_label(l1);
5299 tcg_temp_free(t0);
5300 tcg_temp_free(t1);
5301 if (unlikely(Rc(ctx->opcode) != 0))
5302 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5303 }
5304
5305 /* PowerPC 602 specific instructions */
5306
5307 /* dsa */
5308 static void gen_dsa(DisasContext *ctx)
5309 {
5310 /* XXX: TODO */
5311 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5312 }
5313
5314 /* esa */
5315 static void gen_esa(DisasContext *ctx)
5316 {
5317 /* XXX: TODO */
5318 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5319 }
5320
5321 /* mfrom */
5322 static void gen_mfrom(DisasContext *ctx)
5323 {
5324 #if defined(CONFIG_USER_ONLY)
5325 GEN_PRIV;
5326 #else
5327 CHK_SV;
5328 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5329 #endif /* defined(CONFIG_USER_ONLY) */
5330 }
5331
5332 /* 602 - 603 - G2 TLB management */
5333
5334 /* tlbld */
5335 static void gen_tlbld_6xx(DisasContext *ctx)
5336 {
5337 #if defined(CONFIG_USER_ONLY)
5338 GEN_PRIV;
5339 #else
5340 CHK_SV;
5341 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5342 #endif /* defined(CONFIG_USER_ONLY) */
5343 }
5344
5345 /* tlbli */
5346 static void gen_tlbli_6xx(DisasContext *ctx)
5347 {
5348 #if defined(CONFIG_USER_ONLY)
5349 GEN_PRIV;
5350 #else
5351 CHK_SV;
5352 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5353 #endif /* defined(CONFIG_USER_ONLY) */
5354 }
5355
5356 /* 74xx TLB management */
5357
5358 /* tlbld */
5359 static void gen_tlbld_74xx(DisasContext *ctx)
5360 {
5361 #if defined(CONFIG_USER_ONLY)
5362 GEN_PRIV;
5363 #else
5364 CHK_SV;
5365 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5366 #endif /* defined(CONFIG_USER_ONLY) */
5367 }
5368
5369 /* tlbli */
5370 static void gen_tlbli_74xx(DisasContext *ctx)
5371 {
5372 #if defined(CONFIG_USER_ONLY)
5373 GEN_PRIV;
5374 #else
5375 CHK_SV;
5376 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5377 #endif /* defined(CONFIG_USER_ONLY) */
5378 }
5379
5380 /* POWER instructions not in PowerPC 601 */
5381
5382 /* clf */
5383 static void gen_clf(DisasContext *ctx)
5384 {
5385 /* Cache line flush: implemented as no-op */
5386 }
5387
5388 /* cli */
5389 static void gen_cli(DisasContext *ctx)
5390 {
5391 #if defined(CONFIG_USER_ONLY)
5392 GEN_PRIV;
5393 #else
5394 /* Cache line invalidate: privileged and treated as no-op */
5395 CHK_SV;
5396 #endif /* defined(CONFIG_USER_ONLY) */
5397 }
5398
5399 /* dclst */
5400 static void gen_dclst(DisasContext *ctx)
5401 {
5402 /* Data cache line store: treated as no-op */
5403 }
5404
5405 static void gen_mfsri(DisasContext *ctx)
5406 {
5407 #if defined(CONFIG_USER_ONLY)
5408 GEN_PRIV;
5409 #else
5410 int ra = rA(ctx->opcode);
5411 int rd = rD(ctx->opcode);
5412 TCGv t0;
5413
5414 CHK_SV;
5415 t0 = tcg_temp_new();
5416 gen_addr_reg_index(ctx, t0);
5417 tcg_gen_shri_tl(t0, t0, 28);
5418 tcg_gen_andi_tl(t0, t0, 0xF);
5419 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5420 tcg_temp_free(t0);
5421 if (ra != 0 && ra != rd)
5422 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5423 #endif /* defined(CONFIG_USER_ONLY) */
5424 }
5425
5426 static void gen_rac(DisasContext *ctx)
5427 {
5428 #if defined(CONFIG_USER_ONLY)
5429 GEN_PRIV;
5430 #else
5431 TCGv t0;
5432
5433 CHK_SV;
5434 t0 = tcg_temp_new();
5435 gen_addr_reg_index(ctx, t0);
5436 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5437 tcg_temp_free(t0);
5438 #endif /* defined(CONFIG_USER_ONLY) */
5439 }
5440
5441 static void gen_rfsvc(DisasContext *ctx)
5442 {
5443 #if defined(CONFIG_USER_ONLY)
5444 GEN_PRIV;
5445 #else
5446 CHK_SV;
5447
5448 gen_helper_rfsvc(cpu_env);
5449 gen_sync_exception(ctx);
5450 #endif /* defined(CONFIG_USER_ONLY) */
5451 }
5452
5453 /* svc is not implemented for now */
5454
5455 /* BookE specific instructions */
5456
5457 /* XXX: not implemented on 440 ? */
5458 static void gen_mfapidi(DisasContext *ctx)
5459 {
5460 /* XXX: TODO */
5461 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5462 }
5463
5464 /* XXX: not implemented on 440 ? */
5465 static void gen_tlbiva(DisasContext *ctx)
5466 {
5467 #if defined(CONFIG_USER_ONLY)
5468 GEN_PRIV;
5469 #else
5470 TCGv t0;
5471
5472 CHK_SV;
5473 t0 = tcg_temp_new();
5474 gen_addr_reg_index(ctx, t0);
5475 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5476 tcg_temp_free(t0);
5477 #endif /* defined(CONFIG_USER_ONLY) */
5478 }
5479
5480 /* All 405 MAC instructions are translated here */
5481 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5482 int ra, int rb, int rt, int Rc)
5483 {
5484 TCGv t0, t1;
5485
5486 t0 = tcg_temp_local_new();
5487 t1 = tcg_temp_local_new();
5488
5489 switch (opc3 & 0x0D) {
5490 case 0x05:
5491 /* macchw - macchw. - macchwo - macchwo. */
5492 /* macchws - macchws. - macchwso - macchwso. */
5493 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5494 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5495 /* mulchw - mulchw. */
5496 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5497 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5498 tcg_gen_ext16s_tl(t1, t1);
5499 break;
5500 case 0x04:
5501 /* macchwu - macchwu. - macchwuo - macchwuo. */
5502 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5503 /* mulchwu - mulchwu. */
5504 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5505 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5506 tcg_gen_ext16u_tl(t1, t1);
5507 break;
5508 case 0x01:
5509 /* machhw - machhw. - machhwo - machhwo. */
5510 /* machhws - machhws. - machhwso - machhwso. */
5511 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5512 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5513 /* mulhhw - mulhhw. */
5514 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5515 tcg_gen_ext16s_tl(t0, t0);
5516 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5517 tcg_gen_ext16s_tl(t1, t1);
5518 break;
5519 case 0x00:
5520 /* machhwu - machhwu. - machhwuo - machhwuo. */
5521 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5522 /* mulhhwu - mulhhwu. */
5523 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5524 tcg_gen_ext16u_tl(t0, t0);
5525 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5526 tcg_gen_ext16u_tl(t1, t1);
5527 break;
5528 case 0x0D:
5529 /* maclhw - maclhw. - maclhwo - maclhwo. */
5530 /* maclhws - maclhws. - maclhwso - maclhwso. */
5531 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5532 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5533 /* mullhw - mullhw. */
5534 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5535 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5536 break;
5537 case 0x0C:
5538 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5539 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5540 /* mullhwu - mullhwu. */
5541 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5542 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5543 break;
5544 }
5545 if (opc2 & 0x04) {
5546 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5547 tcg_gen_mul_tl(t1, t0, t1);
5548 if (opc2 & 0x02) {
5549 /* nmultiply-and-accumulate (0x0E) */
5550 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5551 } else {
5552 /* multiply-and-accumulate (0x0C) */
5553 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5554 }
5555
5556 if (opc3 & 0x12) {
5557 /* Check overflow and/or saturate */
5558 TCGLabel *l1 = gen_new_label();
5559
5560 if (opc3 & 0x10) {
5561 /* Start with XER OV disabled, the most likely case */
5562 tcg_gen_movi_tl(cpu_ov, 0);
5563 }
5564 if (opc3 & 0x01) {
5565 /* Signed */
5566 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5567 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5568 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5569 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5570 if (opc3 & 0x02) {
5571 /* Saturate */
5572 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5573 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5574 }
5575 } else {
5576 /* Unsigned */
5577 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5578 if (opc3 & 0x02) {
5579 /* Saturate */
5580 tcg_gen_movi_tl(t0, UINT32_MAX);
5581 }
5582 }
5583 if (opc3 & 0x10) {
5584 /* Check overflow */
5585 tcg_gen_movi_tl(cpu_ov, 1);
5586 tcg_gen_movi_tl(cpu_so, 1);
5587 }
5588 gen_set_label(l1);
5589 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5590 }
5591 } else {
5592 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5593 }
5594 tcg_temp_free(t0);
5595 tcg_temp_free(t1);
5596 if (unlikely(Rc) != 0) {
5597 /* Update Rc0 */
5598 gen_set_Rc0(ctx, cpu_gpr[rt]);
5599 }
5600 }
5601
5602 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5603 static void glue(gen_, name)(DisasContext *ctx) \
5604 { \
5605 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5606 rD(ctx->opcode), Rc(ctx->opcode)); \
5607 }
5608
5609 /* macchw - macchw. */
5610 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5611 /* macchwo - macchwo. */
5612 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5613 /* macchws - macchws. */
5614 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5615 /* macchwso - macchwso. */
5616 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5617 /* macchwsu - macchwsu. */
5618 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5619 /* macchwsuo - macchwsuo. */
5620 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5621 /* macchwu - macchwu. */
5622 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5623 /* macchwuo - macchwuo. */
5624 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5625 /* machhw - machhw. */
5626 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5627 /* machhwo - machhwo. */
5628 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5629 /* machhws - machhws. */
5630 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5631 /* machhwso - machhwso. */
5632 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5633 /* machhwsu - machhwsu. */
5634 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5635 /* machhwsuo - machhwsuo. */
5636 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5637 /* machhwu - machhwu. */
5638 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5639 /* machhwuo - machhwuo. */
5640 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5641 /* maclhw - maclhw. */
5642 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5643 /* maclhwo - maclhwo. */
5644 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5645 /* maclhws - maclhws. */
5646 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5647 /* maclhwso - maclhwso. */
5648 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5649 /* maclhwu - maclhwu. */
5650 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5651 /* maclhwuo - maclhwuo. */
5652 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5653 /* maclhwsu - maclhwsu. */
5654 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5655 /* maclhwsuo - maclhwsuo. */
5656 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5657 /* nmacchw - nmacchw. */
5658 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5659 /* nmacchwo - nmacchwo. */
5660 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5661 /* nmacchws - nmacchws. */
5662 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5663 /* nmacchwso - nmacchwso. */
5664 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5665 /* nmachhw - nmachhw. */
5666 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5667 /* nmachhwo - nmachhwo. */
5668 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5669 /* nmachhws - nmachhws. */
5670 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5671 /* nmachhwso - nmachhwso. */
5672 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5673 /* nmaclhw - nmaclhw. */
5674 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5675 /* nmaclhwo - nmaclhwo. */
5676 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5677 /* nmaclhws - nmaclhws. */
5678 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5679 /* nmaclhwso - nmaclhwso. */
5680 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5681
5682 /* mulchw - mulchw. */
5683 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5684 /* mulchwu - mulchwu. */
5685 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5686 /* mulhhw - mulhhw. */
5687 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5688 /* mulhhwu - mulhhwu. */
5689 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5690 /* mullhw - mullhw. */
5691 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5692 /* mullhwu - mullhwu. */
5693 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5694
5695 /* mfdcr */
5696 static void gen_mfdcr(DisasContext *ctx)
5697 {
5698 #if defined(CONFIG_USER_ONLY)
5699 GEN_PRIV;
5700 #else
5701 TCGv dcrn;
5702
5703 CHK_SV;
5704 dcrn = tcg_const_tl(SPR(ctx->opcode));
5705 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5706 tcg_temp_free(dcrn);
5707 #endif /* defined(CONFIG_USER_ONLY) */
5708 }
5709
5710 /* mtdcr */
5711 static void gen_mtdcr(DisasContext *ctx)
5712 {
5713 #if defined(CONFIG_USER_ONLY)
5714 GEN_PRIV;
5715 #else
5716 TCGv dcrn;
5717
5718 CHK_SV;
5719 dcrn = tcg_const_tl(SPR(ctx->opcode));
5720 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5721 tcg_temp_free(dcrn);
5722 #endif /* defined(CONFIG_USER_ONLY) */
5723 }
5724
5725 /* mfdcrx */
5726 /* XXX: not implemented on 440 ? */
5727 static void gen_mfdcrx(DisasContext *ctx)
5728 {
5729 #if defined(CONFIG_USER_ONLY)
5730 GEN_PRIV;
5731 #else
5732 CHK_SV;
5733 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5734 cpu_gpr[rA(ctx->opcode)]);
5735 /* Note: Rc update flag set leads to undefined state of Rc0 */
5736 #endif /* defined(CONFIG_USER_ONLY) */
5737 }
5738
5739 /* mtdcrx */
5740 /* XXX: not implemented on 440 ? */
5741 static void gen_mtdcrx(DisasContext *ctx)
5742 {
5743 #if defined(CONFIG_USER_ONLY)
5744 GEN_PRIV;
5745 #else
5746 CHK_SV;
5747 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5748 cpu_gpr[rS(ctx->opcode)]);
5749 /* Note: Rc update flag set leads to undefined state of Rc0 */
5750 #endif /* defined(CONFIG_USER_ONLY) */
5751 }
5752
5753 /* mfdcrux (PPC 460) : user-mode access to DCR */
5754 static void gen_mfdcrux(DisasContext *ctx)
5755 {
5756 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5757 cpu_gpr[rA(ctx->opcode)]);
5758 /* Note: Rc update flag set leads to undefined state of Rc0 */
5759 }
5760
5761 /* mtdcrux (PPC 460) : user-mode access to DCR */
5762 static void gen_mtdcrux(DisasContext *ctx)
5763 {
5764 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5765 cpu_gpr[rS(ctx->opcode)]);
5766 /* Note: Rc update flag set leads to undefined state of Rc0 */
5767 }
5768
5769 /* dccci */
5770 static void gen_dccci(DisasContext *ctx)
5771 {
5772 CHK_SV;
5773 /* interpreted as no-op */
5774 }
5775
5776 /* dcread */
5777 static void gen_dcread(DisasContext *ctx)
5778 {
5779 #if defined(CONFIG_USER_ONLY)
5780 GEN_PRIV;
5781 #else
5782 TCGv EA, val;
5783
5784 CHK_SV;
5785 gen_set_access_type(ctx, ACCESS_CACHE);
5786 EA = tcg_temp_new();
5787 gen_addr_reg_index(ctx, EA);
5788 val = tcg_temp_new();
5789 gen_qemu_ld32u(ctx, val, EA);
5790 tcg_temp_free(val);
5791 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5792 tcg_temp_free(EA);
5793 #endif /* defined(CONFIG_USER_ONLY) */
5794 }
5795
5796 /* icbt */
5797 static void gen_icbt_40x(DisasContext *ctx)
5798 {
5799 /* interpreted as no-op */
5800 /* XXX: specification say this is treated as a load by the MMU
5801 * but does not generate any exception
5802 */
5803 }
5804
5805 /* iccci */
5806 static void gen_iccci(DisasContext *ctx)
5807 {
5808 CHK_SV;
5809 /* interpreted as no-op */
5810 }
5811
5812 /* icread */
5813 static void gen_icread(DisasContext *ctx)
5814 {
5815 CHK_SV;
5816 /* interpreted as no-op */
5817 }
5818
5819 /* rfci (supervisor only) */
5820 static void gen_rfci_40x(DisasContext *ctx)
5821 {
5822 #if defined(CONFIG_USER_ONLY)
5823 GEN_PRIV;
5824 #else
5825 CHK_SV;
5826 /* Restore CPU state */
5827 gen_helper_40x_rfci(cpu_env);
5828 gen_sync_exception(ctx);
5829 #endif /* defined(CONFIG_USER_ONLY) */
5830 }
5831
5832 static void gen_rfci(DisasContext *ctx)
5833 {
5834 #if defined(CONFIG_USER_ONLY)
5835 GEN_PRIV;
5836 #else
5837 CHK_SV;
5838 /* Restore CPU state */
5839 gen_helper_rfci(cpu_env);
5840 gen_sync_exception(ctx);
5841 #endif /* defined(CONFIG_USER_ONLY) */
5842 }
5843
5844 /* BookE specific */
5845
5846 /* XXX: not implemented on 440 ? */
5847 static void gen_rfdi(DisasContext *ctx)
5848 {
5849 #if defined(CONFIG_USER_ONLY)
5850 GEN_PRIV;
5851 #else
5852 CHK_SV;
5853 /* Restore CPU state */
5854 gen_helper_rfdi(cpu_env);
5855 gen_sync_exception(ctx);
5856 #endif /* defined(CONFIG_USER_ONLY) */
5857 }
5858
5859 /* XXX: not implemented on 440 ? */
5860 static void gen_rfmci(DisasContext *ctx)
5861 {
5862 #if defined(CONFIG_USER_ONLY)
5863 GEN_PRIV;
5864 #else
5865 CHK_SV;
5866 /* Restore CPU state */
5867 gen_helper_rfmci(cpu_env);
5868 gen_sync_exception(ctx);
5869 #endif /* defined(CONFIG_USER_ONLY) */
5870 }
5871
5872 /* TLB management - PowerPC 405 implementation */
5873
5874 /* tlbre */
5875 static void gen_tlbre_40x(DisasContext *ctx)
5876 {
5877 #if defined(CONFIG_USER_ONLY)
5878 GEN_PRIV;
5879 #else
5880 CHK_SV;
5881 switch (rB(ctx->opcode)) {
5882 case 0:
5883 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5884 cpu_gpr[rA(ctx->opcode)]);
5885 break;
5886 case 1:
5887 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5888 cpu_gpr[rA(ctx->opcode)]);
5889 break;
5890 default:
5891 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5892 break;
5893 }
5894 #endif /* defined(CONFIG_USER_ONLY) */
5895 }
5896
5897 /* tlbsx - tlbsx. */
5898 static void gen_tlbsx_40x(DisasContext *ctx)
5899 {
5900 #if defined(CONFIG_USER_ONLY)
5901 GEN_PRIV;
5902 #else
5903 TCGv t0;
5904
5905 CHK_SV;
5906 t0 = tcg_temp_new();
5907 gen_addr_reg_index(ctx, t0);
5908 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5909 tcg_temp_free(t0);
5910 if (Rc(ctx->opcode)) {
5911 TCGLabel *l1 = gen_new_label();
5912 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5913 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5914 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5915 gen_set_label(l1);
5916 }
5917 #endif /* defined(CONFIG_USER_ONLY) */
5918 }
5919
5920 /* tlbwe */
5921 static void gen_tlbwe_40x(DisasContext *ctx)
5922 {
5923 #if defined(CONFIG_USER_ONLY)
5924 GEN_PRIV;
5925 #else
5926 CHK_SV;
5927
5928 switch (rB(ctx->opcode)) {
5929 case 0:
5930 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5931 cpu_gpr[rS(ctx->opcode)]);
5932 break;
5933 case 1:
5934 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5935 cpu_gpr[rS(ctx->opcode)]);
5936 break;
5937 default:
5938 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5939 break;
5940 }
5941 #endif /* defined(CONFIG_USER_ONLY) */
5942 }
5943
5944 /* TLB management - PowerPC 440 implementation */
5945
5946 /* tlbre */
5947 static void gen_tlbre_440(DisasContext *ctx)
5948 {
5949 #if defined(CONFIG_USER_ONLY)
5950 GEN_PRIV;
5951 #else
5952 CHK_SV;
5953
5954 switch (rB(ctx->opcode)) {
5955 case 0:
5956 case 1:
5957 case 2:
5958 {
5959 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5960 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5961 t0, cpu_gpr[rA(ctx->opcode)]);
5962 tcg_temp_free_i32(t0);
5963 }
5964 break;
5965 default:
5966 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5967 break;
5968 }
5969 #endif /* defined(CONFIG_USER_ONLY) */
5970 }
5971
5972 /* tlbsx - tlbsx. */
5973 static void gen_tlbsx_440(DisasContext *ctx)
5974 {
5975 #if defined(CONFIG_USER_ONLY)
5976 GEN_PRIV;
5977 #else
5978 TCGv t0;
5979
5980 CHK_SV;
5981 t0 = tcg_temp_new();
5982 gen_addr_reg_index(ctx, t0);
5983 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5984 tcg_temp_free(t0);
5985 if (Rc(ctx->opcode)) {
5986 TCGLabel *l1 = gen_new_label();
5987 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5988 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5989 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5990 gen_set_label(l1);
5991 }
5992 #endif /* defined(CONFIG_USER_ONLY) */
5993 }
5994
5995 /* tlbwe */
5996 static void gen_tlbwe_440(DisasContext *ctx)
5997 {
5998 #if defined(CONFIG_USER_ONLY)
5999 GEN_PRIV;
6000 #else
6001 CHK_SV;
6002 switch (rB(ctx->opcode)) {
6003 case 0:
6004 case 1:
6005 case 2:
6006 {
6007 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6008 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6009 cpu_gpr[rS(ctx->opcode)]);
6010 tcg_temp_free_i32(t0);
6011 }
6012 break;
6013 default:
6014 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6015 break;
6016 }
6017 #endif /* defined(CONFIG_USER_ONLY) */
6018 }
6019
6020 /* TLB management - PowerPC BookE 2.06 implementation */
6021
6022 /* tlbre */
6023 static void gen_tlbre_booke206(DisasContext *ctx)
6024 {
6025 #if defined(CONFIG_USER_ONLY)
6026 GEN_PRIV;
6027 #else
6028 CHK_SV;
6029 gen_helper_booke206_tlbre(cpu_env);
6030 #endif /* defined(CONFIG_USER_ONLY) */
6031 }
6032
6033 /* tlbsx - tlbsx. */
6034 static void gen_tlbsx_booke206(DisasContext *ctx)
6035 {
6036 #if defined(CONFIG_USER_ONLY)
6037 GEN_PRIV;
6038 #else
6039 TCGv t0;
6040
6041 CHK_SV;
6042 if (rA(ctx->opcode)) {
6043 t0 = tcg_temp_new();
6044 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6045 } else {
6046 t0 = tcg_const_tl(0);
6047 }
6048
6049 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6050 gen_helper_booke206_tlbsx(cpu_env, t0);
6051 tcg_temp_free(t0);
6052 #endif /* defined(CONFIG_USER_ONLY) */
6053 }
6054
6055 /* tlbwe */
6056 static void gen_tlbwe_booke206(DisasContext *ctx)
6057 {
6058 #if defined(CONFIG_USER_ONLY)
6059 GEN_PRIV;
6060 #else
6061 CHK_SV;
6062 gen_helper_booke206_tlbwe(cpu_env);
6063 #endif /* defined(CONFIG_USER_ONLY) */
6064 }
6065
6066 static void gen_tlbivax_booke206(DisasContext *ctx)
6067 {
6068 #if defined(CONFIG_USER_ONLY)
6069 GEN_PRIV;
6070 #else
6071 TCGv t0;
6072
6073 CHK_SV;
6074 t0 = tcg_temp_new();
6075 gen_addr_reg_index(ctx, t0);
6076 gen_helper_booke206_tlbivax(cpu_env, t0);
6077 tcg_temp_free(t0);
6078 #endif /* defined(CONFIG_USER_ONLY) */
6079 }
6080
6081 static void gen_tlbilx_booke206(DisasContext *ctx)
6082 {
6083 #if defined(CONFIG_USER_ONLY)
6084 GEN_PRIV;
6085 #else
6086 TCGv t0;
6087
6088 CHK_SV;
6089 t0 = tcg_temp_new();
6090 gen_addr_reg_index(ctx, t0);
6091
6092 switch((ctx->opcode >> 21) & 0x3) {
6093 case 0:
6094 gen_helper_booke206_tlbilx0(cpu_env, t0);
6095 break;
6096 case 1:
6097 gen_helper_booke206_tlbilx1(cpu_env, t0);
6098 break;
6099 case 3:
6100 gen_helper_booke206_tlbilx3(cpu_env, t0);
6101 break;
6102 default:
6103 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6104 break;
6105 }
6106
6107 tcg_temp_free(t0);
6108 #endif /* defined(CONFIG_USER_ONLY) */
6109 }
6110
6111
6112 /* wrtee */
6113 static void gen_wrtee(DisasContext *ctx)
6114 {
6115 #if defined(CONFIG_USER_ONLY)
6116 GEN_PRIV;
6117 #else
6118 TCGv t0;
6119
6120 CHK_SV;
6121 t0 = tcg_temp_new();
6122 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6123 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6124 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6125 tcg_temp_free(t0);
6126 /* Stop translation to have a chance to raise an exception
6127 * if we just set msr_ee to 1
6128 */
6129 gen_stop_exception(ctx);
6130 #endif /* defined(CONFIG_USER_ONLY) */
6131 }
6132
6133 /* wrteei */
6134 static void gen_wrteei(DisasContext *ctx)
6135 {
6136 #if defined(CONFIG_USER_ONLY)
6137 GEN_PRIV;
6138 #else
6139 CHK_SV;
6140 if (ctx->opcode & 0x00008000) {
6141 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6142 /* Stop translation to have a chance to raise an exception */
6143 gen_stop_exception(ctx);
6144 } else {
6145 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6146 }
6147 #endif /* defined(CONFIG_USER_ONLY) */
6148 }
6149
6150 /* PowerPC 440 specific instructions */
6151
6152 /* dlmzb */
6153 static void gen_dlmzb(DisasContext *ctx)
6154 {
6155 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6156 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6157 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6158 tcg_temp_free_i32(t0);
6159 }
6160
6161 /* mbar replaces eieio on 440 */
6162 static void gen_mbar(DisasContext *ctx)
6163 {
6164 /* interpreted as no-op */
6165 }
6166
6167 /* msync replaces sync on 440 */
6168 static void gen_msync_4xx(DisasContext *ctx)
6169 {
6170 /* interpreted as no-op */
6171 }
6172
6173 /* icbt */
6174 static void gen_icbt_440(DisasContext *ctx)
6175 {
6176 /* interpreted as no-op */
6177 /* XXX: specification say this is treated as a load by the MMU
6178 * but does not generate any exception
6179 */
6180 }
6181
6182 /* Embedded.Processor Control */
6183
6184 static void gen_msgclr(DisasContext *ctx)
6185 {
6186 #if defined(CONFIG_USER_ONLY)
6187 GEN_PRIV;
6188 #else
6189 CHK_SV;
6190 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6191 #endif /* defined(CONFIG_USER_ONLY) */
6192 }
6193
6194 static void gen_msgsnd(DisasContext *ctx)
6195 {
6196 #if defined(CONFIG_USER_ONLY)
6197 GEN_PRIV;
6198 #else
6199 CHK_SV;
6200 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6201 #endif /* defined(CONFIG_USER_ONLY) */
6202 }
6203
6204
6205 #if defined(TARGET_PPC64)
6206 static void gen_maddld(DisasContext *ctx)
6207 {
6208 TCGv_i64 t1 = tcg_temp_new_i64();
6209
6210 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6211 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6212 tcg_temp_free_i64(t1);
6213 }
6214
6215 /* maddhd maddhdu */
6216 static void gen_maddhd_maddhdu(DisasContext *ctx)
6217 {
6218 TCGv_i64 lo = tcg_temp_new_i64();
6219 TCGv_i64 hi = tcg_temp_new_i64();
6220 TCGv_i64 t1 = tcg_temp_new_i64();
6221
6222 if (Rc(ctx->opcode)) {
6223 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6224 cpu_gpr[rB(ctx->opcode)]);
6225 tcg_gen_movi_i64(t1, 0);
6226 } else {
6227 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6228 cpu_gpr[rB(ctx->opcode)]);
6229 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6230 }
6231 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6232 cpu_gpr[rC(ctx->opcode)], t1);
6233 tcg_temp_free_i64(lo);
6234 tcg_temp_free_i64(hi);
6235 tcg_temp_free_i64(t1);
6236 }
6237 #endif /* defined(TARGET_PPC64) */
6238
6239 static void gen_tbegin(DisasContext *ctx)
6240 {
6241 if (unlikely(!ctx->tm_enabled)) {
6242 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6243 return;
6244 }
6245 gen_helper_tbegin(cpu_env);
6246 }
6247
6248 #define GEN_TM_NOOP(name) \
6249 static inline void gen_##name(DisasContext *ctx) \
6250 { \
6251 if (unlikely(!ctx->tm_enabled)) { \
6252 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6253 return; \
6254 } \
6255 /* Because tbegin always fails in QEMU, these user \
6256 * space instructions all have a simple implementation: \
6257 * \
6258 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6259 * = 0b0 || 0b00 || 0b0 \
6260 */ \
6261 tcg_gen_movi_i32(cpu_crf[0], 0); \
6262 }
6263
6264 GEN_TM_NOOP(tend);
6265 GEN_TM_NOOP(tabort);
6266 GEN_TM_NOOP(tabortwc);
6267 GEN_TM_NOOP(tabortwci);
6268 GEN_TM_NOOP(tabortdc);
6269 GEN_TM_NOOP(tabortdci);
6270 GEN_TM_NOOP(tsr);
6271 static inline void gen_cp_abort(DisasContext *ctx)
6272 {
6273 // Do Nothing
6274 }
6275
6276 #define GEN_CP_PASTE_NOOP(name) \
6277 static inline void gen_##name(DisasContext *ctx) \
6278 { \
6279 /* Generate invalid exception until \
6280 * we have an implementation of the copy \
6281 * paste facility \
6282 */ \
6283 gen_invalid(ctx); \
6284 }
6285
6286 GEN_CP_PASTE_NOOP(copy)
6287 GEN_CP_PASTE_NOOP(paste)
6288
6289 static void gen_tcheck(DisasContext *ctx)
6290 {
6291 if (unlikely(!ctx->tm_enabled)) {
6292 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6293 return;
6294 }
6295 /* Because tbegin always fails, the tcheck implementation
6296 * is simple:
6297 *
6298 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6299 * = 0b1 || 0b00 || 0b0
6300 */
6301 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6302 }
6303
6304 #if defined(CONFIG_USER_ONLY)
6305 #define GEN_TM_PRIV_NOOP(name) \
6306 static inline void gen_##name(DisasContext *ctx) \
6307 { \
6308 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6309 }
6310
6311 #else
6312
6313 #define GEN_TM_PRIV_NOOP(name) \
6314 static inline void gen_##name(DisasContext *ctx) \
6315 { \
6316 CHK_SV; \
6317 if (unlikely(!ctx->tm_enabled)) { \
6318 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6319 return; \
6320 } \
6321 /* Because tbegin always fails, the implementation is \
6322 * simple: \
6323 * \
6324 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6325 * = 0b0 || 0b00 | 0b0 \
6326 */ \
6327 tcg_gen_movi_i32(cpu_crf[0], 0); \
6328 }
6329
6330 #endif
6331
6332 GEN_TM_PRIV_NOOP(treclaim);
6333 GEN_TM_PRIV_NOOP(trechkpt);
6334
6335 #include "translate/fp-impl.inc.c"
6336
6337 #include "translate/vmx-impl.inc.c"
6338
6339 #include "translate/vsx-impl.inc.c"
6340
6341 #include "translate/dfp-impl.inc.c"
6342
6343 #include "translate/spe-impl.inc.c"
6344
6345 /* Handles lfdp, lxsd, lxssp */
6346 static void gen_dform39(DisasContext *ctx)
6347 {
6348 switch (ctx->opcode & 0x3) {
6349 case 0: /* lfdp */
6350 if (ctx->insns_flags2 & PPC2_ISA205) {
6351 return gen_lfdp(ctx);
6352 }
6353 break;
6354 case 2: /* lxsd */
6355 if (ctx->insns_flags2 & PPC2_ISA300) {
6356 return gen_lxsd(ctx);
6357 }
6358 break;
6359 case 3: /* lxssp */
6360 if (ctx->insns_flags2 & PPC2_ISA300) {
6361 return gen_lxssp(ctx);
6362 }
6363 break;
6364 }
6365 return gen_invalid(ctx);
6366 }
6367
6368 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6369 static void gen_dform3D(DisasContext *ctx)
6370 {
6371 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6372 switch (ctx->opcode & 0x7) {
6373 case 1: /* lxv */
6374 if (ctx->insns_flags2 & PPC2_ISA300) {
6375 return gen_lxv(ctx);
6376 }
6377 break;
6378 case 5: /* stxv */
6379 if (ctx->insns_flags2 & PPC2_ISA300) {
6380 return gen_stxv(ctx);
6381 }
6382 break;
6383 }
6384 } else { /* DS-FORM */
6385 switch (ctx->opcode & 0x3) {
6386 case 0: /* stfdp */
6387 if (ctx->insns_flags2 & PPC2_ISA205) {
6388 return gen_stfdp(ctx);
6389 }
6390 break;
6391 case 2: /* stxsd */
6392 if (ctx->insns_flags2 & PPC2_ISA300) {
6393 return gen_stxsd(ctx);
6394 }
6395 break;
6396 case 3: /* stxssp */
6397 if (ctx->insns_flags2 & PPC2_ISA300) {
6398 return gen_stxssp(ctx);
6399 }
6400 break;
6401 }
6402 }
6403 return gen_invalid(ctx);
6404 }
6405
6406 static opcode_t opcodes[] = {
6407 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6408 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6409 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6410 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6411 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6412 #if defined(TARGET_PPC64)
6413 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6414 #endif
6415 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6416 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6417 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6418 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6419 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6420 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6421 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6422 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6423 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6424 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6425 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6426 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6427 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6428 #if defined(TARGET_PPC64)
6429 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6430 #endif
6431 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6432 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6433 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6434 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6435 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6436 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6437 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6438 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6439 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6440 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6441 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6442 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6443 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6444 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6445 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6446 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6447 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6448 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6449 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6450 #if defined(TARGET_PPC64)
6451 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6452 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6453 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6454 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6455 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6456 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6457 #endif
6458 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6459 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6460 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6461 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6462 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6463 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6464 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6465 #if defined(TARGET_PPC64)
6466 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6467 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6468 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6469 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6470 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6471 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6472 PPC_NONE, PPC2_ISA300),
6473 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6474 PPC_NONE, PPC2_ISA300),
6475 #endif
6476 #if defined(TARGET_PPC64)
6477 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6478 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6479 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6480 #endif
6481 /* handles lfdp, lxsd, lxssp */
6482 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6483 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6484 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6485 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6486 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6487 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6488 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6489 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6490 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6491 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6492 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6493 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6494 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6495 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6496 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6497 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6498 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6499 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6500 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6501 #if defined(TARGET_PPC64)
6502 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6503 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6504 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6505 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6506 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6507 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6508 #endif
6509 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6510 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6511 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6512 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6513 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6514 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6515 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6516 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6517 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6518 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6519 #if defined(TARGET_PPC64)
6520 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6521 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6522 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6523 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6524 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6525 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6526 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6527 #endif
6528 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6529 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6530 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6531 #if defined(TARGET_PPC64)
6532 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6533 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6534 #endif
6535 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6536 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6537 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6538 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6539 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6540 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6541 #if defined(TARGET_PPC64)
6542 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6543 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6544 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6545 #endif
6546 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6547 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6548 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6549 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6550 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6551 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6552 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6553 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6554 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6555 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6556 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6557 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6558 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6559 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6560 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6561 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6562 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6563 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6564 #if defined(TARGET_PPC64)
6565 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6566 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6567 PPC_SEGMENT_64B),
6568 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6569 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6570 PPC_SEGMENT_64B),
6571 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6572 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6573 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6574 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6575 #endif
6576 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6577 /* XXX Those instructions will need to be handled differently for
6578 * different ISA versions */
6579 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6580 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6581 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6582 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
6583 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6584 #if defined(TARGET_PPC64)
6585 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6586 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6587 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6588 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6589 #endif
6590 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6591 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6592 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6593 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6594 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6595 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6596 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6597 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6598 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6599 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6600 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6601 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6602 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6603 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6604 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6605 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6606 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6607 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6608 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6609 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6610 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6611 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6612 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6613 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6614 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6615 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6616 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6617 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6618 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6619 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6620 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6621 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6622 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6623 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6624 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6625 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6626 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6627 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6628 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6629 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6630 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6631 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6632 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6633 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6634 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6635 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6636 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6637 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6638 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6639 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6640 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6641 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6642 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6643 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6644 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6645 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6646 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6647 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6648 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6649 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6650 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6651 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6652 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6653 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6654 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6655 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6656 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6657 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6658 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6659 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6660 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6661 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6662 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6663 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6664 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6665 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6666 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6667 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6668 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6669 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6670 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6671 PPC_NONE, PPC2_BOOKE206),
6672 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6673 PPC_NONE, PPC2_BOOKE206),
6674 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6675 PPC_NONE, PPC2_BOOKE206),
6676 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6677 PPC_NONE, PPC2_BOOKE206),
6678 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6679 PPC_NONE, PPC2_BOOKE206),
6680 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6681 PPC_NONE, PPC2_PRCNTL),
6682 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6683 PPC_NONE, PPC2_PRCNTL),
6684 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6685 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6686 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6687 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6688 PPC_BOOKE, PPC2_BOOKE206),
6689 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6690 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6691 PPC_BOOKE, PPC2_BOOKE206),
6692 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6693 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6694 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6695 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6696 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6697 #if defined(TARGET_PPC64)
6698 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6699 PPC2_ISA300),
6700 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6701 #endif
6702
6703 #undef GEN_INT_ARITH_ADD
6704 #undef GEN_INT_ARITH_ADD_CONST
6705 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6706 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6707 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6708 add_ca, compute_ca, compute_ov) \
6709 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6710 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6711 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6712 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6713 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6714 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6715 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6716 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6717 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6718 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6719 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6720
6721 #undef GEN_INT_ARITH_DIVW
6722 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6723 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6724 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6725 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6726 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6727 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6728 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6729 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6730 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6731 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6732 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6733 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6734
6735 #if defined(TARGET_PPC64)
6736 #undef GEN_INT_ARITH_DIVD
6737 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6738 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6739 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6740 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6741 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6742 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6743
6744 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6745 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6746 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6747 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6748 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6749 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6750
6751 #undef GEN_INT_ARITH_MUL_HELPER
6752 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6753 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6754 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6755 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6756 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6757 #endif
6758
6759 #undef GEN_INT_ARITH_SUBF
6760 #undef GEN_INT_ARITH_SUBF_CONST
6761 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6762 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6763 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6764 add_ca, compute_ca, compute_ov) \
6765 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6766 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6767 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6768 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6769 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6770 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6771 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6772 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6773 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6774 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6775 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6776
6777 #undef GEN_LOGICAL1
6778 #undef GEN_LOGICAL2
6779 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6780 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6781 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6782 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6783 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6784 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6785 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6786 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6787 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6788 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6789 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6790 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6791 #if defined(TARGET_PPC64)
6792 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6793 #endif
6794
6795 #if defined(TARGET_PPC64)
6796 #undef GEN_PPC64_R2
6797 #undef GEN_PPC64_R4
6798 #define GEN_PPC64_R2(name, opc1, opc2) \
6799 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6800 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6801 PPC_64B)
6802 #define GEN_PPC64_R4(name, opc1, opc2) \
6803 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6804 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6805 PPC_64B), \
6806 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6807 PPC_64B), \
6808 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6809 PPC_64B)
6810 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6811 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6812 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6813 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6814 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6815 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6816 #endif
6817
6818 #undef GEN_LD
6819 #undef GEN_LDU
6820 #undef GEN_LDUX
6821 #undef GEN_LDX_E
6822 #undef GEN_LDS
6823 #define GEN_LD(name, ldop, opc, type) \
6824 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6825 #define GEN_LDU(name, ldop, opc, type) \
6826 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6827 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6828 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6829 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6830 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6831 #define GEN_LDS(name, ldop, op, type) \
6832 GEN_LD(name, ldop, op | 0x20, type) \
6833 GEN_LDU(name, ldop, op | 0x21, type) \
6834 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6835 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6836
6837 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6838 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6839 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6840 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6841 #if defined(TARGET_PPC64)
6842 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6843 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6844 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6845 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6846 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6847
6848 /* HV/P7 and later only */
6849 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6850 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6851 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6852 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6853 #endif
6854 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6855 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6856
6857 #undef GEN_ST
6858 #undef GEN_STU
6859 #undef GEN_STUX
6860 #undef GEN_STX_E
6861 #undef GEN_STS
6862 #define GEN_ST(name, stop, opc, type) \
6863 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6864 #define GEN_STU(name, stop, opc, type) \
6865 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6866 #define GEN_STUX(name, stop, opc2, opc3, type) \
6867 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6868 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6869 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6870 #define GEN_STS(name, stop, op, type) \
6871 GEN_ST(name, stop, op | 0x20, type) \
6872 GEN_STU(name, stop, op | 0x21, type) \
6873 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6874 GEN_STX(name, stop, 0x17, op | 0x00, type)
6875
6876 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6877 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6878 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6879 #if defined(TARGET_PPC64)
6880 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6881 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6882 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6883 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6884 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6885 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6886 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6887 #endif
6888 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6889 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6890
6891 #undef GEN_CRLOGIC
6892 #define GEN_CRLOGIC(name, tcg_op, opc) \
6893 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6894 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6895 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6896 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6897 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6898 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6899 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6900 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6901 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6902
6903 #undef GEN_MAC_HANDLER
6904 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6905 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6906 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6907 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6908 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6909 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6910 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6911 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6912 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6913 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6914 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6915 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6916 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6917 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6918 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6919 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6920 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6921 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6922 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6923 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6924 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6925 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6926 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6927 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6928 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6929 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6930 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6931 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6932 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6933 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6934 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6935 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6936 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6937 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6938 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6939 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6940 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6941 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6942 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6943 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6944 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6945 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6946 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6947 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6948
6949 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6950 PPC_NONE, PPC2_TM),
6951 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6952 PPC_NONE, PPC2_TM),
6953 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6954 PPC_NONE, PPC2_TM),
6955 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6956 PPC_NONE, PPC2_TM),
6957 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6958 PPC_NONE, PPC2_TM),
6959 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6960 PPC_NONE, PPC2_TM),
6961 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6962 PPC_NONE, PPC2_TM),
6963 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6964 PPC_NONE, PPC2_TM),
6965 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6966 PPC_NONE, PPC2_TM),
6967 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6968 PPC_NONE, PPC2_TM),
6969 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6970 PPC_NONE, PPC2_TM),
6971
6972 #include "translate/fp-ops.inc.c"
6973
6974 #include "translate/vmx-ops.inc.c"
6975
6976 #include "translate/vsx-ops.inc.c"
6977
6978 #include "translate/dfp-ops.inc.c"
6979
6980 #include "translate/spe-ops.inc.c"
6981 };
6982
6983 #include "helper_regs.h"
6984 #include "translate_init.c"
6985
6986 /*****************************************************************************/
6987 /* Misc PowerPC helpers */
6988 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6989 int flags)
6990 {
6991 #define RGPL 4
6992 #define RFPL 4
6993
6994 PowerPCCPU *cpu = POWERPC_CPU(cs);
6995 CPUPPCState *env = &cpu->env;
6996 int i;
6997
6998 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6999 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7000 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7001 cs->cpu_index);
7002 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7003 TARGET_FMT_lx " iidx %d didx %d\n",
7004 env->msr, env->spr[SPR_HID0],
7005 env->hflags, env->immu_idx, env->dmmu_idx);
7006 #if !defined(NO_TIMER_DUMP)
7007 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7008 #if !defined(CONFIG_USER_ONLY)
7009 " DECR %08" PRIu32
7010 #endif
7011 "\n",
7012 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7013 #if !defined(CONFIG_USER_ONLY)
7014 , cpu_ppc_load_decr(env)
7015 #endif
7016 );
7017 #endif
7018 for (i = 0; i < 32; i++) {
7019 if ((i & (RGPL - 1)) == 0)
7020 cpu_fprintf(f, "GPR%02d", i);
7021 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7022 if ((i & (RGPL - 1)) == (RGPL - 1))
7023 cpu_fprintf(f, "\n");
7024 }
7025 cpu_fprintf(f, "CR ");
7026 for (i = 0; i < 8; i++)
7027 cpu_fprintf(f, "%01x", env->crf[i]);
7028 cpu_fprintf(f, " [");
7029 for (i = 0; i < 8; i++) {
7030 char a = '-';
7031 if (env->crf[i] & 0x08)
7032 a = 'L';
7033 else if (env->crf[i] & 0x04)
7034 a = 'G';
7035 else if (env->crf[i] & 0x02)
7036 a = 'E';
7037 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7038 }
7039 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7040 env->reserve_addr);
7041 for (i = 0; i < 32; i++) {
7042 if ((i & (RFPL - 1)) == 0)
7043 cpu_fprintf(f, "FPR%02d", i);
7044 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7045 if ((i & (RFPL - 1)) == (RFPL - 1))
7046 cpu_fprintf(f, "\n");
7047 }
7048 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7049 #if !defined(CONFIG_USER_ONLY)
7050 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7051 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7052 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7053 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7054
7055 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7056 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7057 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7058 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7059
7060 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7061 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7062 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7063 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7064
7065 #if defined(TARGET_PPC64)
7066 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7067 env->excp_model == POWERPC_EXCP_POWER8) {
7068 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7069 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7070 }
7071 #endif
7072 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7073 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7074 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7075 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7076 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7077
7078 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7079 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7080 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7081 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7082
7083 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7084 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7085 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7086 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7087
7088 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7089 " EPR " TARGET_FMT_lx "\n",
7090 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7091 env->spr[SPR_BOOKE_EPR]);
7092
7093 /* FSL-specific */
7094 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7095 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7096 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7097 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7098
7099 /*
7100 * IVORs are left out as they are large and do not change often --
7101 * they can be read with "p $ivor0", "p $ivor1", etc.
7102 */
7103 }
7104
7105 #if defined(TARGET_PPC64)
7106 if (env->flags & POWERPC_FLAG_CFAR) {
7107 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7108 }
7109 #endif
7110
7111 if (env->spr_cb[SPR_LPCR].name)
7112 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7113
7114 switch (POWERPC_MMU_VER(env->mmu_model)) {
7115 case POWERPC_MMU_32B:
7116 case POWERPC_MMU_601:
7117 case POWERPC_MMU_SOFT_6xx:
7118 case POWERPC_MMU_SOFT_74xx:
7119 #if defined(TARGET_PPC64)
7120 case POWERPC_MMU_VER_64B:
7121 case POWERPC_MMU_VER_2_03:
7122 case POWERPC_MMU_VER_2_06:
7123 case POWERPC_MMU_VER_2_07:
7124 case POWERPC_MMU_VER_3_00:
7125 #endif
7126 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7127 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7128 }
7129 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7130 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7131 break;
7132 case POWERPC_MMU_BOOKE206:
7133 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7134 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7135 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7136 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7137
7138 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7139 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7140 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7141 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7142
7143 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7144 " TLB1CFG " TARGET_FMT_lx "\n",
7145 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7146 env->spr[SPR_BOOKE_TLB1CFG]);
7147 break;
7148 default:
7149 break;
7150 }
7151 #endif
7152
7153 #undef RGPL
7154 #undef RFPL
7155 }
7156
7157 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7158 fprintf_function cpu_fprintf, int flags)
7159 {
7160 #if defined(DO_PPC_STATISTICS)
7161 PowerPCCPU *cpu = POWERPC_CPU(cs);
7162 opc_handler_t **t1, **t2, **t3, *handler;
7163 int op1, op2, op3;
7164
7165 t1 = cpu->env.opcodes;
7166 for (op1 = 0; op1 < 64; op1++) {
7167 handler = t1[op1];
7168 if (is_indirect_opcode(handler)) {
7169 t2 = ind_table(handler);
7170 for (op2 = 0; op2 < 32; op2++) {
7171 handler = t2[op2];
7172 if (is_indirect_opcode(handler)) {
7173 t3 = ind_table(handler);
7174 for (op3 = 0; op3 < 32; op3++) {
7175 handler = t3[op3];
7176 if (handler->count == 0)
7177 continue;
7178 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7179 "%016" PRIx64 " %" PRId64 "\n",
7180 op1, op2, op3, op1, (op3 << 5) | op2,
7181 handler->oname,
7182 handler->count, handler->count);
7183 }
7184 } else {
7185 if (handler->count == 0)
7186 continue;
7187 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7188 "%016" PRIx64 " %" PRId64 "\n",
7189 op1, op2, op1, op2, handler->oname,
7190 handler->count, handler->count);
7191 }
7192 }
7193 } else {
7194 if (handler->count == 0)
7195 continue;
7196 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7197 " %" PRId64 "\n",
7198 op1, op1, handler->oname,
7199 handler->count, handler->count);
7200 }
7201 }
7202 #endif
7203 }
7204
7205 /*****************************************************************************/
7206 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
7207 {
7208 PowerPCCPU *cpu = ppc_env_get_cpu(env);
7209 CPUState *cs = CPU(cpu);
7210 DisasContext ctx, *ctxp = &ctx;
7211 opc_handler_t **table, *handler;
7212 target_ulong pc_start;
7213 int num_insns;
7214 int max_insns;
7215
7216 pc_start = tb->pc;
7217 ctx.nip = pc_start;
7218 ctx.tb = tb;
7219 ctx.exception = POWERPC_EXCP_NONE;
7220 ctx.spr_cb = env->spr_cb;
7221 ctx.pr = msr_pr;
7222 ctx.mem_idx = env->dmmu_idx;
7223 ctx.dr = msr_dr;
7224 #if !defined(CONFIG_USER_ONLY)
7225 ctx.hv = msr_hv || !env->has_hv_mode;
7226 #endif
7227 ctx.insns_flags = env->insns_flags;
7228 ctx.insns_flags2 = env->insns_flags2;
7229 ctx.access_type = -1;
7230 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7231 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
7232 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
7233 #if defined(TARGET_PPC64)
7234 ctx.sf_mode = msr_is_64bit(env, env->msr);
7235 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7236 #endif
7237 if (env->mmu_model == POWERPC_MMU_32B ||
7238 env->mmu_model == POWERPC_MMU_601 ||
7239 (env->mmu_model & POWERPC_MMU_64B))
7240 ctx.lazy_tlb_flush = true;
7241
7242 ctx.fpu_enabled = !!msr_fp;
7243 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7244 ctx.spe_enabled = !!msr_spe;
7245 else
7246 ctx.spe_enabled = false;
7247 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7248 ctx.altivec_enabled = !!msr_vr;
7249 else
7250 ctx.altivec_enabled = false;
7251 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7252 ctx.vsx_enabled = !!msr_vsx;
7253 } else {
7254 ctx.vsx_enabled = false;
7255 }
7256 #if defined(TARGET_PPC64)
7257 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7258 ctx.tm_enabled = !!msr_tm;
7259 } else {
7260 ctx.tm_enabled = false;
7261 }
7262 #endif
7263 ctx.gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7264 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7265 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7266 else
7267 ctx.singlestep_enabled = 0;
7268 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7269 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7270 if (unlikely(cs->singlestep_enabled)) {
7271 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7272 }
7273 #if defined (DO_SINGLE_STEP) && 0
7274 /* Single step trace mode */
7275 msr_se = 1;
7276 #endif
7277 num_insns = 0;
7278 max_insns = tb->cflags & CF_COUNT_MASK;
7279 if (max_insns == 0) {
7280 max_insns = CF_COUNT_MASK;
7281 }
7282 if (max_insns > TCG_MAX_INSNS) {
7283 max_insns = TCG_MAX_INSNS;
7284 }
7285
7286 gen_tb_start(tb);
7287 tcg_clear_temp_count();
7288 /* Set env in case of segfault during code fetch */
7289 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7290 tcg_gen_insn_start(ctx.nip);
7291 num_insns++;
7292
7293 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7294 gen_debug_exception(ctxp);
7295 /* The address covered by the breakpoint must be included in
7296 [tb->pc, tb->pc + tb->size) in order to for it to be
7297 properly cleared -- thus we increment the PC here so that
7298 the logic setting tb->size below does the right thing. */
7299 ctx.nip += 4;
7300 break;
7301 }
7302
7303 LOG_DISAS("----------------\n");
7304 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7305 ctx.nip, ctx.mem_idx, (int)msr_ir);
7306 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7307 gen_io_start();
7308 if (unlikely(need_byteswap(&ctx))) {
7309 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7310 } else {
7311 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7312 }
7313 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7314 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7315 opc3(ctx.opcode), opc4(ctx.opcode),
7316 ctx.le_mode ? "little" : "big");
7317 ctx.nip += 4;
7318 table = env->opcodes;
7319 handler = table[opc1(ctx.opcode)];
7320 if (is_indirect_opcode(handler)) {
7321 table = ind_table(handler);
7322 handler = table[opc2(ctx.opcode)];
7323 if (is_indirect_opcode(handler)) {
7324 table = ind_table(handler);
7325 handler = table[opc3(ctx.opcode)];
7326 if (is_indirect_opcode(handler)) {
7327 table = ind_table(handler);
7328 handler = table[opc4(ctx.opcode)];
7329 }
7330 }
7331 }
7332 /* Is opcode *REALLY* valid ? */
7333 if (unlikely(handler->handler == &gen_invalid)) {
7334 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7335 "%02x - %02x - %02x - %02x (%08x) "
7336 TARGET_FMT_lx " %d\n",
7337 opc1(ctx.opcode), opc2(ctx.opcode),
7338 opc3(ctx.opcode), opc4(ctx.opcode),
7339 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7340 } else {
7341 uint32_t inval;
7342
7343 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7344 inval = handler->inval2;
7345 } else {
7346 inval = handler->inval1;
7347 }
7348
7349 if (unlikely((ctx.opcode & inval) != 0)) {
7350 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7351 "%02x - %02x - %02x - %02x (%08x) "
7352 TARGET_FMT_lx "\n", ctx.opcode & inval,
7353 opc1(ctx.opcode), opc2(ctx.opcode),
7354 opc3(ctx.opcode), opc4(ctx.opcode),
7355 ctx.opcode, ctx.nip - 4);
7356 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7357 break;
7358 }
7359 }
7360 (*(handler->handler))(&ctx);
7361 #if defined(DO_PPC_STATISTICS)
7362 handler->count++;
7363 #endif
7364 /* Check trace mode exceptions */
7365 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7366 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7367 ctx.exception != POWERPC_SYSCALL &&
7368 ctx.exception != POWERPC_EXCP_TRAP &&
7369 ctx.exception != POWERPC_EXCP_BRANCH)) {
7370 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7371 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7372 (cs->singlestep_enabled) ||
7373 singlestep ||
7374 num_insns >= max_insns)) {
7375 /* if we reach a page boundary or are single stepping, stop
7376 * generation
7377 */
7378 break;
7379 }
7380 if (tcg_check_temp_count()) {
7381 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7382 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7383 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7384 exit(1);
7385 }
7386 }
7387 if (tb->cflags & CF_LAST_IO)
7388 gen_io_end();
7389 if (ctx.exception == POWERPC_EXCP_NONE) {
7390 gen_goto_tb(&ctx, 0, ctx.nip);
7391 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7392 if (unlikely(cs->singlestep_enabled)) {
7393 gen_debug_exception(ctxp);
7394 }
7395 /* Generate the return instruction */
7396 tcg_gen_exit_tb(0);
7397 }
7398 gen_tb_end(tb, num_insns);
7399
7400 tb->size = ctx.nip - pc_start;
7401 tb->icount = num_insns;
7402
7403 #if defined(DEBUG_DISAS)
7404 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7405 && qemu_log_in_addr_range(pc_start)) {
7406 int flags;
7407 flags = env->bfd_mach;
7408 flags |= ctx.le_mode << 16;
7409 qemu_log_lock();
7410 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7411 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7412 qemu_log("\n");
7413 qemu_log_unlock();
7414 }
7415 #endif
7416 }
7417
7418 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7419 target_ulong *data)
7420 {
7421 env->nip = data[0];
7422 }
AR7 emulation for QEMU