block: Minimize raw use of bds->total_sectors
[qemu/ar7.git] / exec.c
bloba083ff89ad23ce3facced797e23a95806bb46a95
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #ifndef _WIN32
22 #endif
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg.h"
29 #include "hw/qdev-core.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/boards.h"
32 #include "hw/xen/xen.h"
33 #endif
34 #include "sysemu/kvm.h"
35 #include "sysemu/sysemu.h"
36 #include "qemu/timer.h"
37 #include "qemu/config-file.h"
38 #include "qemu/error-report.h"
39 #if defined(CONFIG_USER_ONLY)
40 #include "qemu.h"
41 #else /* !CONFIG_USER_ONLY */
42 #include "hw/hw.h"
43 #include "exec/memory.h"
44 #include "exec/ioport.h"
45 #include "sysemu/dma.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/hw_accel.h"
48 #include "exec/address-spaces.h"
49 #include "sysemu/xen-mapcache.h"
50 #include "trace-root.h"
52 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
53 #include <fcntl.h>
54 #include <linux/falloc.h>
55 #endif
57 #endif
58 #include "exec/cpu-all.h"
59 #include "qemu/rcu_queue.h"
60 #include "qemu/main-loop.h"
61 #include "translate-all.h"
62 #include "sysemu/replay.h"
64 #include "exec/memory-internal.h"
65 #include "exec/ram_addr.h"
66 #include "exec/log.h"
68 #include "migration/vmstate.h"
70 #include "qemu/range.h"
71 #ifndef _WIN32
72 #include "qemu/mmap-alloc.h"
73 #endif
75 #include "monitor/monitor.h"
77 //#define DEBUG_SUBPAGE
79 #if !defined(CONFIG_USER_ONLY)
80 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
81 * are protected by the ramlist lock.
83 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
85 static MemoryRegion *system_memory;
86 static MemoryRegion *system_io;
88 AddressSpace address_space_io;
89 AddressSpace address_space_memory;
91 MemoryRegion io_mem_rom, io_mem_notdirty;
92 static MemoryRegion io_mem_unassigned;
94 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
95 #define RAM_PREALLOC (1 << 0)
97 /* RAM is mmap-ed with MAP_SHARED */
98 #define RAM_SHARED (1 << 1)
100 /* Only a portion of RAM (used_length) is actually used, and migrated.
101 * This used_length size can change across reboots.
103 #define RAM_RESIZEABLE (1 << 2)
105 #endif
107 #ifdef TARGET_PAGE_BITS_VARY
108 int target_page_bits;
109 bool target_page_bits_decided;
110 #endif
112 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
113 /* current CPU in the current thread. It is only valid inside
114 cpu_exec() */
115 __thread CPUState *current_cpu;
116 /* 0 = Do not count executed instructions.
117 1 = Precise instruction counting.
118 2 = Adaptive rate instruction counting. */
119 int use_icount;
121 uintptr_t qemu_host_page_size;
122 intptr_t qemu_host_page_mask;
123 uintptr_t qemu_real_host_page_size;
124 intptr_t qemu_real_host_page_mask;
126 bool set_preferred_target_page_bits(int bits)
128 /* The target page size is the lowest common denominator for all
129 * the CPUs in the system, so we can only make it smaller, never
130 * larger. And we can't make it smaller once we've committed to
131 * a particular size.
133 #ifdef TARGET_PAGE_BITS_VARY
134 assert(bits >= TARGET_PAGE_BITS_MIN);
135 if (target_page_bits == 0 || target_page_bits > bits) {
136 if (target_page_bits_decided) {
137 return false;
139 target_page_bits = bits;
141 #endif
142 return true;
145 #if !defined(CONFIG_USER_ONLY)
147 static void finalize_target_page_bits(void)
149 #ifdef TARGET_PAGE_BITS_VARY
150 if (target_page_bits == 0) {
151 target_page_bits = TARGET_PAGE_BITS_MIN;
153 target_page_bits_decided = true;
154 #endif
157 typedef struct PhysPageEntry PhysPageEntry;
159 struct PhysPageEntry {
160 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
161 uint32_t skip : 6;
162 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
163 uint32_t ptr : 26;
166 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
168 /* Size of the L2 (and L3, etc) page tables. */
169 #define ADDR_SPACE_BITS 64
171 #define P_L2_BITS 9
172 #define P_L2_SIZE (1 << P_L2_BITS)
174 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
176 typedef PhysPageEntry Node[P_L2_SIZE];
178 typedef struct PhysPageMap {
179 struct rcu_head rcu;
181 unsigned sections_nb;
182 unsigned sections_nb_alloc;
183 unsigned nodes_nb;
184 unsigned nodes_nb_alloc;
185 Node *nodes;
186 MemoryRegionSection *sections;
187 } PhysPageMap;
189 struct AddressSpaceDispatch {
190 struct rcu_head rcu;
192 MemoryRegionSection *mru_section;
193 /* This is a multi-level map on the physical address space.
194 * The bottom level has pointers to MemoryRegionSections.
196 PhysPageEntry phys_map;
197 PhysPageMap map;
198 AddressSpace *as;
201 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
202 typedef struct subpage_t {
203 MemoryRegion iomem;
204 AddressSpace *as;
205 hwaddr base;
206 uint16_t sub_section[];
207 } subpage_t;
209 #define PHYS_SECTION_UNASSIGNED 0
210 #define PHYS_SECTION_NOTDIRTY 1
211 #define PHYS_SECTION_ROM 2
212 #define PHYS_SECTION_WATCH 3
214 static void io_mem_init(void);
215 static void memory_map_init(void);
216 static void tcg_commit(MemoryListener *listener);
218 static MemoryRegion io_mem_watch;
221 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
222 * @cpu: the CPU whose AddressSpace this is
223 * @as: the AddressSpace itself
224 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
225 * @tcg_as_listener: listener for tracking changes to the AddressSpace
227 struct CPUAddressSpace {
228 CPUState *cpu;
229 AddressSpace *as;
230 struct AddressSpaceDispatch *memory_dispatch;
231 MemoryListener tcg_as_listener;
234 struct DirtyBitmapSnapshot {
235 ram_addr_t start;
236 ram_addr_t end;
237 unsigned long dirty[];
240 #endif
242 #if !defined(CONFIG_USER_ONLY)
244 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
246 static unsigned alloc_hint = 16;
247 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
248 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
249 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
250 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
251 alloc_hint = map->nodes_nb_alloc;
255 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
257 unsigned i;
258 uint32_t ret;
259 PhysPageEntry e;
260 PhysPageEntry *p;
262 ret = map->nodes_nb++;
263 p = map->nodes[ret];
264 assert(ret != PHYS_MAP_NODE_NIL);
265 assert(ret != map->nodes_nb_alloc);
267 e.skip = leaf ? 0 : 1;
268 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
269 for (i = 0; i < P_L2_SIZE; ++i) {
270 memcpy(&p[i], &e, sizeof(e));
272 return ret;
275 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
276 hwaddr *index, hwaddr *nb, uint16_t leaf,
277 int level)
279 PhysPageEntry *p;
280 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
282 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
283 lp->ptr = phys_map_node_alloc(map, level == 0);
285 p = map->nodes[lp->ptr];
286 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
288 while (*nb && lp < &p[P_L2_SIZE]) {
289 if ((*index & (step - 1)) == 0 && *nb >= step) {
290 lp->skip = 0;
291 lp->ptr = leaf;
292 *index += step;
293 *nb -= step;
294 } else {
295 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
297 ++lp;
301 static void phys_page_set(AddressSpaceDispatch *d,
302 hwaddr index, hwaddr nb,
303 uint16_t leaf)
305 /* Wildly overreserve - it doesn't matter much. */
306 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
308 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
311 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
312 * and update our entry so we can skip it and go directly to the destination.
314 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
316 unsigned valid_ptr = P_L2_SIZE;
317 int valid = 0;
318 PhysPageEntry *p;
319 int i;
321 if (lp->ptr == PHYS_MAP_NODE_NIL) {
322 return;
325 p = nodes[lp->ptr];
326 for (i = 0; i < P_L2_SIZE; i++) {
327 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
328 continue;
331 valid_ptr = i;
332 valid++;
333 if (p[i].skip) {
334 phys_page_compact(&p[i], nodes);
338 /* We can only compress if there's only one child. */
339 if (valid != 1) {
340 return;
343 assert(valid_ptr < P_L2_SIZE);
345 /* Don't compress if it won't fit in the # of bits we have. */
346 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
347 return;
350 lp->ptr = p[valid_ptr].ptr;
351 if (!p[valid_ptr].skip) {
352 /* If our only child is a leaf, make this a leaf. */
353 /* By design, we should have made this node a leaf to begin with so we
354 * should never reach here.
355 * But since it's so simple to handle this, let's do it just in case we
356 * change this rule.
358 lp->skip = 0;
359 } else {
360 lp->skip += p[valid_ptr].skip;
364 static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb)
366 if (d->phys_map.skip) {
367 phys_page_compact(&d->phys_map, d->map.nodes);
371 static inline bool section_covers_addr(const MemoryRegionSection *section,
372 hwaddr addr)
374 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
375 * the section must cover the entire address space.
377 return int128_gethi(section->size) ||
378 range_covers_byte(section->offset_within_address_space,
379 int128_getlo(section->size), addr);
382 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
384 PhysPageEntry lp = d->phys_map, *p;
385 Node *nodes = d->map.nodes;
386 MemoryRegionSection *sections = d->map.sections;
387 hwaddr index = addr >> TARGET_PAGE_BITS;
388 int i;
390 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
391 if (lp.ptr == PHYS_MAP_NODE_NIL) {
392 return &sections[PHYS_SECTION_UNASSIGNED];
394 p = nodes[lp.ptr];
395 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
398 if (section_covers_addr(&sections[lp.ptr], addr)) {
399 return &sections[lp.ptr];
400 } else {
401 return &sections[PHYS_SECTION_UNASSIGNED];
405 bool memory_region_is_unassigned(MemoryRegion *mr)
407 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
408 && mr != &io_mem_watch;
411 /* Called from RCU critical section */
412 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
413 hwaddr addr,
414 bool resolve_subpage)
416 MemoryRegionSection *section = atomic_read(&d->mru_section);
417 subpage_t *subpage;
418 bool update;
420 if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&
421 section_covers_addr(section, addr)) {
422 update = false;
423 } else {
424 section = phys_page_find(d, addr);
425 update = true;
427 if (resolve_subpage && section->mr->subpage) {
428 subpage = container_of(section->mr, subpage_t, iomem);
429 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
431 if (update) {
432 atomic_set(&d->mru_section, section);
434 return section;
437 /* Called from RCU critical section */
438 static MemoryRegionSection *
439 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
440 hwaddr *plen, bool resolve_subpage)
442 MemoryRegionSection *section;
443 MemoryRegion *mr;
444 Int128 diff;
446 section = address_space_lookup_region(d, addr, resolve_subpage);
447 /* Compute offset within MemoryRegionSection */
448 addr -= section->offset_within_address_space;
450 /* Compute offset within MemoryRegion */
451 *xlat = addr + section->offset_within_region;
453 mr = section->mr;
455 /* MMIO registers can be expected to perform full-width accesses based only
456 * on their address, without considering adjacent registers that could
457 * decode to completely different MemoryRegions. When such registers
458 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
459 * regions overlap wildly. For this reason we cannot clamp the accesses
460 * here.
462 * If the length is small (as is the case for address_space_ldl/stl),
463 * everything works fine. If the incoming length is large, however,
464 * the caller really has to do the clamping through memory_access_size.
466 if (memory_region_is_ram(mr)) {
467 diff = int128_sub(section->size, int128_make64(addr));
468 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
470 return section;
473 /* Called from RCU critical section */
474 static MemoryRegionSection address_space_do_translate(AddressSpace *as,
475 hwaddr addr,
476 hwaddr *xlat,
477 hwaddr *plen,
478 bool is_write,
479 bool is_mmio)
481 IOMMUTLBEntry iotlb;
482 MemoryRegionSection *section;
483 MemoryRegion *mr;
485 for (;;) {
486 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
487 section = address_space_translate_internal(d, addr, &addr, plen, is_mmio);
488 mr = section->mr;
490 if (!mr->iommu_ops) {
491 break;
494 iotlb = mr->iommu_ops->translate(mr, addr, is_write ?
495 IOMMU_WO : IOMMU_RO);
496 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
497 | (addr & iotlb.addr_mask));
498 *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1);
499 if (!(iotlb.perm & (1 << is_write))) {
500 goto translate_fail;
503 as = iotlb.target_as;
506 *xlat = addr;
508 return *section;
510 translate_fail:
511 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
514 /* Called from RCU critical section */
515 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
516 bool is_write)
518 MemoryRegionSection section;
519 hwaddr xlat, plen;
521 /* Try to get maximum page mask during translation. */
522 plen = (hwaddr)-1;
524 /* This can never be MMIO. */
525 section = address_space_do_translate(as, addr, &xlat, &plen,
526 is_write, false);
528 /* Illegal translation */
529 if (section.mr == &io_mem_unassigned) {
530 goto iotlb_fail;
533 /* Convert memory region offset into address space offset */
534 xlat += section.offset_within_address_space -
535 section.offset_within_region;
537 if (plen == (hwaddr)-1) {
539 * We use default page size here. Logically it only happens
540 * for identity mappings.
542 plen = TARGET_PAGE_SIZE;
545 /* Convert to address mask */
546 plen -= 1;
548 return (IOMMUTLBEntry) {
549 .target_as = section.address_space,
550 .iova = addr & ~plen,
551 .translated_addr = xlat & ~plen,
552 .addr_mask = plen,
553 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
554 .perm = IOMMU_RW,
557 iotlb_fail:
558 return (IOMMUTLBEntry) {0};
561 /* Called from RCU critical section */
562 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
563 hwaddr *xlat, hwaddr *plen,
564 bool is_write)
566 MemoryRegion *mr;
567 MemoryRegionSection section;
569 /* This can be MMIO, so setup MMIO bit. */
570 section = address_space_do_translate(as, addr, xlat, plen, is_write, true);
571 mr = section.mr;
573 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
574 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
575 *plen = MIN(page, *plen);
578 return mr;
581 /* Called from RCU critical section */
582 MemoryRegionSection *
583 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
584 hwaddr *xlat, hwaddr *plen)
586 MemoryRegionSection *section;
587 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
589 section = address_space_translate_internal(d, addr, xlat, plen, false);
591 assert(!section->mr->iommu_ops);
592 return section;
594 #endif
596 #if !defined(CONFIG_USER_ONLY)
598 static int cpu_common_post_load(void *opaque, int version_id)
600 CPUState *cpu = opaque;
602 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
603 version_id is increased. */
604 cpu->interrupt_request &= ~0x01;
605 tlb_flush(cpu);
607 return 0;
610 static int cpu_common_pre_load(void *opaque)
612 CPUState *cpu = opaque;
614 cpu->exception_index = -1;
616 return 0;
619 static bool cpu_common_exception_index_needed(void *opaque)
621 CPUState *cpu = opaque;
623 return tcg_enabled() && cpu->exception_index != -1;
626 static const VMStateDescription vmstate_cpu_common_exception_index = {
627 .name = "cpu_common/exception_index",
628 .version_id = 1,
629 .minimum_version_id = 1,
630 .needed = cpu_common_exception_index_needed,
631 .fields = (VMStateField[]) {
632 VMSTATE_INT32(exception_index, CPUState),
633 VMSTATE_END_OF_LIST()
637 static bool cpu_common_crash_occurred_needed(void *opaque)
639 CPUState *cpu = opaque;
641 return cpu->crash_occurred;
644 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
645 .name = "cpu_common/crash_occurred",
646 .version_id = 1,
647 .minimum_version_id = 1,
648 .needed = cpu_common_crash_occurred_needed,
649 .fields = (VMStateField[]) {
650 VMSTATE_BOOL(crash_occurred, CPUState),
651 VMSTATE_END_OF_LIST()
655 const VMStateDescription vmstate_cpu_common = {
656 .name = "cpu_common",
657 .version_id = 1,
658 .minimum_version_id = 1,
659 .pre_load = cpu_common_pre_load,
660 .post_load = cpu_common_post_load,
661 .fields = (VMStateField[]) {
662 VMSTATE_UINT32(halted, CPUState),
663 VMSTATE_UINT32(interrupt_request, CPUState),
664 VMSTATE_END_OF_LIST()
666 .subsections = (const VMStateDescription*[]) {
667 &vmstate_cpu_common_exception_index,
668 &vmstate_cpu_common_crash_occurred,
669 NULL
673 #endif
675 CPUState *qemu_get_cpu(int index)
677 CPUState *cpu;
679 CPU_FOREACH(cpu) {
680 if (cpu->cpu_index == index) {
681 return cpu;
685 return NULL;
688 #if !defined(CONFIG_USER_ONLY)
689 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx)
691 CPUAddressSpace *newas;
693 /* Target code should have set num_ases before calling us */
694 assert(asidx < cpu->num_ases);
696 if (asidx == 0) {
697 /* address space 0 gets the convenience alias */
698 cpu->as = as;
701 /* KVM cannot currently support multiple address spaces. */
702 assert(asidx == 0 || !kvm_enabled());
704 if (!cpu->cpu_ases) {
705 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
708 newas = &cpu->cpu_ases[asidx];
709 newas->cpu = cpu;
710 newas->as = as;
711 if (tcg_enabled()) {
712 newas->tcg_as_listener.commit = tcg_commit;
713 memory_listener_register(&newas->tcg_as_listener, as);
717 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
719 /* Return the AddressSpace corresponding to the specified index */
720 return cpu->cpu_ases[asidx].as;
722 #endif
724 void cpu_exec_unrealizefn(CPUState *cpu)
726 CPUClass *cc = CPU_GET_CLASS(cpu);
728 cpu_list_remove(cpu);
730 if (cc->vmsd != NULL) {
731 vmstate_unregister(NULL, cc->vmsd, cpu);
733 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
734 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
738 void cpu_exec_initfn(CPUState *cpu)
740 cpu->as = NULL;
741 cpu->num_ases = 0;
743 #ifndef CONFIG_USER_ONLY
744 cpu->thread_id = qemu_get_thread_id();
746 /* This is a softmmu CPU object, so create a property for it
747 * so users can wire up its memory. (This can't go in qom/cpu.c
748 * because that file is compiled only once for both user-mode
749 * and system builds.) The default if no link is set up is to use
750 * the system address space.
752 object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION,
753 (Object **)&cpu->memory,
754 qdev_prop_allow_set_link_before_realize,
755 OBJ_PROP_LINK_UNREF_ON_RELEASE,
756 &error_abort);
757 cpu->memory = system_memory;
758 object_ref(OBJECT(cpu->memory));
759 #endif
762 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
764 CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu);
766 cpu_list_add(cpu);
768 #ifndef CONFIG_USER_ONLY
769 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
770 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
772 if (cc->vmsd != NULL) {
773 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
775 #endif
778 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
780 /* Flush the whole TB as this will not have race conditions
781 * even if we don't have proper locking yet.
782 * Ideally we would just invalidate the TBs for the
783 * specified PC.
785 tb_flush(cpu);
788 #if defined(CONFIG_USER_ONLY)
789 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
794 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
795 int flags)
797 return -ENOSYS;
800 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
804 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
805 int flags, CPUWatchpoint **watchpoint)
807 return -ENOSYS;
809 #else
810 /* Add a watchpoint. */
811 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
812 int flags, CPUWatchpoint **watchpoint)
814 CPUWatchpoint *wp;
816 /* forbid ranges which are empty or run off the end of the address space */
817 if (len == 0 || (addr + len - 1) < addr) {
818 error_report("tried to set invalid watchpoint at %"
819 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
820 return -EINVAL;
822 wp = g_malloc(sizeof(*wp));
824 wp->vaddr = addr;
825 wp->len = len;
826 wp->flags = flags;
828 /* keep all GDB-injected watchpoints in front */
829 if (flags & BP_GDB) {
830 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
831 } else {
832 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
835 tlb_flush_page(cpu, addr);
837 if (watchpoint)
838 *watchpoint = wp;
839 return 0;
842 /* Remove a specific watchpoint. */
843 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
844 int flags)
846 CPUWatchpoint *wp;
848 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
849 if (addr == wp->vaddr && len == wp->len
850 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
851 cpu_watchpoint_remove_by_ref(cpu, wp);
852 return 0;
855 return -ENOENT;
858 /* Remove a specific watchpoint by reference. */
859 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
861 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
863 tlb_flush_page(cpu, watchpoint->vaddr);
865 g_free(watchpoint);
868 /* Remove all matching watchpoints. */
869 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
871 CPUWatchpoint *wp, *next;
873 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
874 if (wp->flags & mask) {
875 cpu_watchpoint_remove_by_ref(cpu, wp);
880 /* Return true if this watchpoint address matches the specified
881 * access (ie the address range covered by the watchpoint overlaps
882 * partially or completely with the address range covered by the
883 * access).
885 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
886 vaddr addr,
887 vaddr len)
889 /* We know the lengths are non-zero, but a little caution is
890 * required to avoid errors in the case where the range ends
891 * exactly at the top of the address space and so addr + len
892 * wraps round to zero.
894 vaddr wpend = wp->vaddr + wp->len - 1;
895 vaddr addrend = addr + len - 1;
897 return !(addr > wpend || wp->vaddr > addrend);
900 #endif
902 /* Add a breakpoint. */
903 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
904 CPUBreakpoint **breakpoint)
906 CPUBreakpoint *bp;
908 bp = g_malloc(sizeof(*bp));
910 bp->pc = pc;
911 bp->flags = flags;
913 /* keep all GDB-injected breakpoints in front */
914 if (flags & BP_GDB) {
915 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
916 } else {
917 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
920 breakpoint_invalidate(cpu, pc);
922 if (breakpoint) {
923 *breakpoint = bp;
925 return 0;
928 /* Remove a specific breakpoint. */
929 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
931 CPUBreakpoint *bp;
933 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
934 if (bp->pc == pc && bp->flags == flags) {
935 cpu_breakpoint_remove_by_ref(cpu, bp);
936 return 0;
939 return -ENOENT;
942 /* Remove a specific breakpoint by reference. */
943 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
945 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
947 breakpoint_invalidate(cpu, breakpoint->pc);
949 g_free(breakpoint);
952 /* Remove all matching breakpoints. */
953 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
955 CPUBreakpoint *bp, *next;
957 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
958 if (bp->flags & mask) {
959 cpu_breakpoint_remove_by_ref(cpu, bp);
964 /* enable or disable single step mode. EXCP_DEBUG is returned by the
965 CPU loop after each instruction */
966 void cpu_single_step(CPUState *cpu, int enabled)
968 if (cpu->singlestep_enabled != enabled) {
969 cpu->singlestep_enabled = enabled;
970 if (kvm_enabled()) {
971 kvm_update_guest_debug(cpu, 0);
972 } else {
973 /* must flush all the translated code to avoid inconsistencies */
974 /* XXX: only flush what is necessary */
975 tb_flush(cpu);
980 void cpu_abort(CPUState *cpu, const char *fmt, ...)
982 va_list ap;
983 va_list ap2;
985 va_start(ap, fmt);
986 va_copy(ap2, ap);
987 fprintf(stderr, "qemu: fatal: ");
988 vfprintf(stderr, fmt, ap);
989 fprintf(stderr, "\n");
990 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
991 if (qemu_log_separate()) {
992 qemu_log_lock();
993 qemu_log("qemu: fatal: ");
994 qemu_log_vprintf(fmt, ap2);
995 qemu_log("\n");
996 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
997 qemu_log_flush();
998 qemu_log_unlock();
999 qemu_log_close();
1001 va_end(ap2);
1002 va_end(ap);
1003 replay_finish();
1004 #if defined(CONFIG_USER_ONLY)
1006 struct sigaction act;
1007 sigfillset(&act.sa_mask);
1008 act.sa_handler = SIG_DFL;
1009 sigaction(SIGABRT, &act, NULL);
1011 #endif
1012 abort();
1015 #if !defined(CONFIG_USER_ONLY)
1016 /* Called from RCU critical section */
1017 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1019 RAMBlock *block;
1021 block = atomic_rcu_read(&ram_list.mru_block);
1022 if (block && addr - block->offset < block->max_length) {
1023 return block;
1025 RAMBLOCK_FOREACH(block) {
1026 if (addr - block->offset < block->max_length) {
1027 goto found;
1031 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1032 abort();
1034 found:
1035 /* It is safe to write mru_block outside the iothread lock. This
1036 * is what happens:
1038 * mru_block = xxx
1039 * rcu_read_unlock()
1040 * xxx removed from list
1041 * rcu_read_lock()
1042 * read mru_block
1043 * mru_block = NULL;
1044 * call_rcu(reclaim_ramblock, xxx);
1045 * rcu_read_unlock()
1047 * atomic_rcu_set is not needed here. The block was already published
1048 * when it was placed into the list. Here we're just making an extra
1049 * copy of the pointer.
1051 ram_list.mru_block = block;
1052 return block;
1055 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1057 CPUState *cpu;
1058 ram_addr_t start1;
1059 RAMBlock *block;
1060 ram_addr_t end;
1062 end = TARGET_PAGE_ALIGN(start + length);
1063 start &= TARGET_PAGE_MASK;
1065 rcu_read_lock();
1066 block = qemu_get_ram_block(start);
1067 assert(block == qemu_get_ram_block(end - 1));
1068 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1069 CPU_FOREACH(cpu) {
1070 tlb_reset_dirty(cpu, start1, length);
1072 rcu_read_unlock();
1075 /* Note: start and end must be within the same ram block. */
1076 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1077 ram_addr_t length,
1078 unsigned client)
1080 DirtyMemoryBlocks *blocks;
1081 unsigned long end, page;
1082 bool dirty = false;
1084 if (length == 0) {
1085 return false;
1088 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1089 page = start >> TARGET_PAGE_BITS;
1091 rcu_read_lock();
1093 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1095 while (page < end) {
1096 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1097 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1098 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1100 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1101 offset, num);
1102 page += num;
1105 rcu_read_unlock();
1107 if (dirty && tcg_enabled()) {
1108 tlb_reset_dirty_range_all(start, length);
1111 return dirty;
1114 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1115 (ram_addr_t start, ram_addr_t length, unsigned client)
1117 DirtyMemoryBlocks *blocks;
1118 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1119 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1120 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1121 DirtyBitmapSnapshot *snap;
1122 unsigned long page, end, dest;
1124 snap = g_malloc0(sizeof(*snap) +
1125 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1126 snap->start = first;
1127 snap->end = last;
1129 page = first >> TARGET_PAGE_BITS;
1130 end = last >> TARGET_PAGE_BITS;
1131 dest = 0;
1133 rcu_read_lock();
1135 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1137 while (page < end) {
1138 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1139 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1140 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1142 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1143 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1144 offset >>= BITS_PER_LEVEL;
1146 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1147 blocks->blocks[idx] + offset,
1148 num);
1149 page += num;
1150 dest += num >> BITS_PER_LEVEL;
1153 rcu_read_unlock();
1155 if (tcg_enabled()) {
1156 tlb_reset_dirty_range_all(start, length);
1159 return snap;
1162 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1163 ram_addr_t start,
1164 ram_addr_t length)
1166 unsigned long page, end;
1168 assert(start >= snap->start);
1169 assert(start + length <= snap->end);
1171 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1172 page = (start - snap->start) >> TARGET_PAGE_BITS;
1174 while (page < end) {
1175 if (test_bit(page, snap->dirty)) {
1176 return true;
1178 page++;
1180 return false;
1183 /* Called from RCU critical section */
1184 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1185 MemoryRegionSection *section,
1186 target_ulong vaddr,
1187 hwaddr paddr, hwaddr xlat,
1188 int prot,
1189 target_ulong *address)
1191 hwaddr iotlb;
1192 CPUWatchpoint *wp;
1194 if (memory_region_is_ram(section->mr)) {
1195 /* Normal RAM. */
1196 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1197 if (!section->readonly) {
1198 iotlb |= PHYS_SECTION_NOTDIRTY;
1199 } else {
1200 iotlb |= PHYS_SECTION_ROM;
1202 } else {
1203 AddressSpaceDispatch *d;
1205 d = atomic_rcu_read(&section->address_space->dispatch);
1206 iotlb = section - d->map.sections;
1207 iotlb += xlat;
1210 /* Make accesses to pages with watchpoints go via the
1211 watchpoint trap routines. */
1212 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1213 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1214 /* Avoid trapping reads of pages with a write breakpoint. */
1215 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1216 iotlb = PHYS_SECTION_WATCH + paddr;
1217 *address |= TLB_MMIO;
1218 break;
1223 return iotlb;
1225 #endif /* defined(CONFIG_USER_ONLY) */
1227 #if !defined(CONFIG_USER_ONLY)
1229 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1230 uint16_t section);
1231 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
1233 static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
1234 qemu_anon_ram_alloc;
1237 * Set a custom physical guest memory alloator.
1238 * Accelerators with unusual needs may need this. Hopefully, we can
1239 * get rid of it eventually.
1241 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
1243 phys_mem_alloc = alloc;
1246 static uint16_t phys_section_add(PhysPageMap *map,
1247 MemoryRegionSection *section)
1249 /* The physical section number is ORed with a page-aligned
1250 * pointer to produce the iotlb entries. Thus it should
1251 * never overflow into the page-aligned value.
1253 assert(map->sections_nb < TARGET_PAGE_SIZE);
1255 if (map->sections_nb == map->sections_nb_alloc) {
1256 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1257 map->sections = g_renew(MemoryRegionSection, map->sections,
1258 map->sections_nb_alloc);
1260 map->sections[map->sections_nb] = *section;
1261 memory_region_ref(section->mr);
1262 return map->sections_nb++;
1265 static void phys_section_destroy(MemoryRegion *mr)
1267 bool have_sub_page = mr->subpage;
1269 memory_region_unref(mr);
1271 if (have_sub_page) {
1272 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1273 object_unref(OBJECT(&subpage->iomem));
1274 g_free(subpage);
1278 static void phys_sections_free(PhysPageMap *map)
1280 while (map->sections_nb > 0) {
1281 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1282 phys_section_destroy(section->mr);
1284 g_free(map->sections);
1285 g_free(map->nodes);
1288 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
1290 subpage_t *subpage;
1291 hwaddr base = section->offset_within_address_space
1292 & TARGET_PAGE_MASK;
1293 MemoryRegionSection *existing = phys_page_find(d, base);
1294 MemoryRegionSection subsection = {
1295 .offset_within_address_space = base,
1296 .size = int128_make64(TARGET_PAGE_SIZE),
1298 hwaddr start, end;
1300 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1302 if (!(existing->mr->subpage)) {
1303 subpage = subpage_init(d->as, base);
1304 subsection.address_space = d->as;
1305 subsection.mr = &subpage->iomem;
1306 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1307 phys_section_add(&d->map, &subsection));
1308 } else {
1309 subpage = container_of(existing->mr, subpage_t, iomem);
1311 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1312 end = start + int128_get64(section->size) - 1;
1313 subpage_register(subpage, start, end,
1314 phys_section_add(&d->map, section));
1318 static void register_multipage(AddressSpaceDispatch *d,
1319 MemoryRegionSection *section)
1321 hwaddr start_addr = section->offset_within_address_space;
1322 uint16_t section_index = phys_section_add(&d->map, section);
1323 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1324 TARGET_PAGE_BITS));
1326 assert(num_pages);
1327 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1330 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
1332 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1333 AddressSpaceDispatch *d = as->next_dispatch;
1334 MemoryRegionSection now = *section, remain = *section;
1335 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1337 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1338 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1339 - now.offset_within_address_space;
1341 now.size = int128_min(int128_make64(left), now.size);
1342 register_subpage(d, &now);
1343 } else {
1344 now.size = int128_zero();
1346 while (int128_ne(remain.size, now.size)) {
1347 remain.size = int128_sub(remain.size, now.size);
1348 remain.offset_within_address_space += int128_get64(now.size);
1349 remain.offset_within_region += int128_get64(now.size);
1350 now = remain;
1351 if (int128_lt(remain.size, page_size)) {
1352 register_subpage(d, &now);
1353 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1354 now.size = page_size;
1355 register_subpage(d, &now);
1356 } else {
1357 now.size = int128_and(now.size, int128_neg(page_size));
1358 register_multipage(d, &now);
1363 void qemu_flush_coalesced_mmio_buffer(void)
1365 if (kvm_enabled())
1366 kvm_flush_coalesced_mmio_buffer();
1369 void qemu_mutex_lock_ramlist(void)
1371 qemu_mutex_lock(&ram_list.mutex);
1374 void qemu_mutex_unlock_ramlist(void)
1376 qemu_mutex_unlock(&ram_list.mutex);
1379 void ram_block_dump(Monitor *mon)
1381 RAMBlock *block;
1382 char *psize;
1384 rcu_read_lock();
1385 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1386 "Block Name", "PSize", "Offset", "Used", "Total");
1387 RAMBLOCK_FOREACH(block) {
1388 psize = size_to_str(block->page_size);
1389 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1390 " 0x%016" PRIx64 "\n", block->idstr, psize,
1391 (uint64_t)block->offset,
1392 (uint64_t)block->used_length,
1393 (uint64_t)block->max_length);
1394 g_free(psize);
1396 rcu_read_unlock();
1399 #ifdef __linux__
1401 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1402 * may or may not name the same files / on the same filesystem now as
1403 * when we actually open and map them. Iterate over the file
1404 * descriptors instead, and use qemu_fd_getpagesize().
1406 static int find_max_supported_pagesize(Object *obj, void *opaque)
1408 char *mem_path;
1409 long *hpsize_min = opaque;
1411 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1412 mem_path = object_property_get_str(obj, "mem-path", NULL);
1413 if (mem_path) {
1414 long hpsize = qemu_mempath_getpagesize(mem_path);
1415 if (hpsize < *hpsize_min) {
1416 *hpsize_min = hpsize;
1418 } else {
1419 *hpsize_min = getpagesize();
1423 return 0;
1426 long qemu_getrampagesize(void)
1428 long hpsize = LONG_MAX;
1429 long mainrampagesize;
1430 Object *memdev_root;
1432 if (mem_path) {
1433 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1434 } else {
1435 mainrampagesize = getpagesize();
1438 /* it's possible we have memory-backend objects with
1439 * hugepage-backed RAM. these may get mapped into system
1440 * address space via -numa parameters or memory hotplug
1441 * hooks. we want to take these into account, but we
1442 * also want to make sure these supported hugepage
1443 * sizes are applicable across the entire range of memory
1444 * we may boot from, so we take the min across all
1445 * backends, and assume normal pages in cases where a
1446 * backend isn't backed by hugepages.
1448 memdev_root = object_resolve_path("/objects", NULL);
1449 if (memdev_root) {
1450 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1452 if (hpsize == LONG_MAX) {
1453 /* No additional memory regions found ==> Report main RAM page size */
1454 return mainrampagesize;
1457 /* If NUMA is disabled or the NUMA nodes are not backed with a
1458 * memory-backend, then there is at least one node using "normal" RAM,
1459 * so if its page size is smaller we have got to report that size instead.
1461 if (hpsize > mainrampagesize &&
1462 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1463 static bool warned;
1464 if (!warned) {
1465 error_report("Huge page support disabled (n/a for main memory).");
1466 warned = true;
1468 return mainrampagesize;
1471 return hpsize;
1473 #else
1474 long qemu_getrampagesize(void)
1476 return getpagesize();
1478 #endif
1480 #ifdef __linux__
1481 static int64_t get_file_size(int fd)
1483 int64_t size = lseek(fd, 0, SEEK_END);
1484 if (size < 0) {
1485 return -errno;
1487 return size;
1490 static int file_ram_open(const char *path,
1491 const char *region_name,
1492 bool *created,
1493 Error **errp)
1495 char *filename;
1496 char *sanitized_name;
1497 char *c;
1498 int fd = -1;
1500 *created = false;
1501 for (;;) {
1502 fd = open(path, O_RDWR);
1503 if (fd >= 0) {
1504 /* @path names an existing file, use it */
1505 break;
1507 if (errno == ENOENT) {
1508 /* @path names a file that doesn't exist, create it */
1509 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1510 if (fd >= 0) {
1511 *created = true;
1512 break;
1514 } else if (errno == EISDIR) {
1515 /* @path names a directory, create a file there */
1516 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1517 sanitized_name = g_strdup(region_name);
1518 for (c = sanitized_name; *c != '\0'; c++) {
1519 if (*c == '/') {
1520 *c = '_';
1524 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1525 sanitized_name);
1526 g_free(sanitized_name);
1528 fd = mkstemp(filename);
1529 if (fd >= 0) {
1530 unlink(filename);
1531 g_free(filename);
1532 break;
1534 g_free(filename);
1536 if (errno != EEXIST && errno != EINTR) {
1537 error_setg_errno(errp, errno,
1538 "can't open backing store %s for guest RAM",
1539 path);
1540 return -1;
1543 * Try again on EINTR and EEXIST. The latter happens when
1544 * something else creates the file between our two open().
1548 return fd;
1551 static void *file_ram_alloc(RAMBlock *block,
1552 ram_addr_t memory,
1553 int fd,
1554 bool truncate,
1555 Error **errp)
1557 void *area;
1559 block->page_size = qemu_fd_getpagesize(fd);
1560 block->mr->align = block->page_size;
1561 #if defined(__s390x__)
1562 if (kvm_enabled()) {
1563 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1565 #endif
1567 if (memory < block->page_size) {
1568 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1569 "or larger than page size 0x%zx",
1570 memory, block->page_size);
1571 return NULL;
1574 memory = ROUND_UP(memory, block->page_size);
1577 * ftruncate is not supported by hugetlbfs in older
1578 * hosts, so don't bother bailing out on errors.
1579 * If anything goes wrong with it under other filesystems,
1580 * mmap will fail.
1582 * Do not truncate the non-empty backend file to avoid corrupting
1583 * the existing data in the file. Disabling shrinking is not
1584 * enough. For example, the current vNVDIMM implementation stores
1585 * the guest NVDIMM labels at the end of the backend file. If the
1586 * backend file is later extended, QEMU will not be able to find
1587 * those labels. Therefore, extending the non-empty backend file
1588 * is disabled as well.
1590 if (truncate && ftruncate(fd, memory)) {
1591 perror("ftruncate");
1594 area = qemu_ram_mmap(fd, memory, block->mr->align,
1595 block->flags & RAM_SHARED);
1596 if (area == MAP_FAILED) {
1597 error_setg_errno(errp, errno,
1598 "unable to map backing store for guest RAM");
1599 return NULL;
1602 if (mem_prealloc) {
1603 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1604 if (errp && *errp) {
1605 qemu_ram_munmap(area, memory);
1606 return NULL;
1610 block->fd = fd;
1611 return area;
1613 #endif
1615 /* Called with the ramlist lock held. */
1616 static ram_addr_t find_ram_offset(ram_addr_t size)
1618 RAMBlock *block, *next_block;
1619 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1621 assert(size != 0); /* it would hand out same offset multiple times */
1623 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1624 return 0;
1627 RAMBLOCK_FOREACH(block) {
1628 ram_addr_t end, next = RAM_ADDR_MAX;
1630 end = block->offset + block->max_length;
1632 RAMBLOCK_FOREACH(next_block) {
1633 if (next_block->offset >= end) {
1634 next = MIN(next, next_block->offset);
1637 if (next - end >= size && next - end < mingap) {
1638 offset = end;
1639 mingap = next - end;
1643 if (offset == RAM_ADDR_MAX) {
1644 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1645 (uint64_t)size);
1646 abort();
1649 return offset;
1652 unsigned long last_ram_page(void)
1654 RAMBlock *block;
1655 ram_addr_t last = 0;
1657 rcu_read_lock();
1658 RAMBLOCK_FOREACH(block) {
1659 last = MAX(last, block->offset + block->max_length);
1661 rcu_read_unlock();
1662 return last >> TARGET_PAGE_BITS;
1665 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1667 int ret;
1669 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1670 if (!machine_dump_guest_core(current_machine)) {
1671 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1672 if (ret) {
1673 perror("qemu_madvise");
1674 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1675 "but dump_guest_core=off specified\n");
1680 const char *qemu_ram_get_idstr(RAMBlock *rb)
1682 return rb->idstr;
1685 bool qemu_ram_is_shared(RAMBlock *rb)
1687 return rb->flags & RAM_SHARED;
1690 /* Called with iothread lock held. */
1691 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1693 RAMBlock *block;
1695 assert(new_block);
1696 assert(!new_block->idstr[0]);
1698 if (dev) {
1699 char *id = qdev_get_dev_path(dev);
1700 if (id) {
1701 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1702 g_free(id);
1705 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1707 rcu_read_lock();
1708 RAMBLOCK_FOREACH(block) {
1709 if (block != new_block &&
1710 !strcmp(block->idstr, new_block->idstr)) {
1711 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1712 new_block->idstr);
1713 abort();
1716 rcu_read_unlock();
1719 /* Called with iothread lock held. */
1720 void qemu_ram_unset_idstr(RAMBlock *block)
1722 /* FIXME: arch_init.c assumes that this is not called throughout
1723 * migration. Ignore the problem since hot-unplug during migration
1724 * does not work anyway.
1726 if (block) {
1727 memset(block->idstr, 0, sizeof(block->idstr));
1731 size_t qemu_ram_pagesize(RAMBlock *rb)
1733 return rb->page_size;
1736 /* Returns the largest size of page in use */
1737 size_t qemu_ram_pagesize_largest(void)
1739 RAMBlock *block;
1740 size_t largest = 0;
1742 RAMBLOCK_FOREACH(block) {
1743 largest = MAX(largest, qemu_ram_pagesize(block));
1746 return largest;
1749 static int memory_try_enable_merging(void *addr, size_t len)
1751 if (!machine_mem_merge(current_machine)) {
1752 /* disabled by the user */
1753 return 0;
1756 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1759 /* Only legal before guest might have detected the memory size: e.g. on
1760 * incoming migration, or right after reset.
1762 * As memory core doesn't know how is memory accessed, it is up to
1763 * resize callback to update device state and/or add assertions to detect
1764 * misuse, if necessary.
1766 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1768 assert(block);
1770 newsize = HOST_PAGE_ALIGN(newsize);
1772 if (block->used_length == newsize) {
1773 return 0;
1776 if (!(block->flags & RAM_RESIZEABLE)) {
1777 error_setg_errno(errp, EINVAL,
1778 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1779 " in != 0x" RAM_ADDR_FMT, block->idstr,
1780 newsize, block->used_length);
1781 return -EINVAL;
1784 if (block->max_length < newsize) {
1785 error_setg_errno(errp, EINVAL,
1786 "Length too large: %s: 0x" RAM_ADDR_FMT
1787 " > 0x" RAM_ADDR_FMT, block->idstr,
1788 newsize, block->max_length);
1789 return -EINVAL;
1792 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1793 block->used_length = newsize;
1794 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1795 DIRTY_CLIENTS_ALL);
1796 memory_region_set_size(block->mr, newsize);
1797 if (block->resized) {
1798 block->resized(block->idstr, newsize, block->host);
1800 return 0;
1803 /* Called with ram_list.mutex held */
1804 static void dirty_memory_extend(ram_addr_t old_ram_size,
1805 ram_addr_t new_ram_size)
1807 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1808 DIRTY_MEMORY_BLOCK_SIZE);
1809 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1810 DIRTY_MEMORY_BLOCK_SIZE);
1811 int i;
1813 /* Only need to extend if block count increased */
1814 if (new_num_blocks <= old_num_blocks) {
1815 return;
1818 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1819 DirtyMemoryBlocks *old_blocks;
1820 DirtyMemoryBlocks *new_blocks;
1821 int j;
1823 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1824 new_blocks = g_malloc(sizeof(*new_blocks) +
1825 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1827 if (old_num_blocks) {
1828 memcpy(new_blocks->blocks, old_blocks->blocks,
1829 old_num_blocks * sizeof(old_blocks->blocks[0]));
1832 for (j = old_num_blocks; j < new_num_blocks; j++) {
1833 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1836 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1838 if (old_blocks) {
1839 g_free_rcu(old_blocks, rcu);
1844 static void ram_block_add(RAMBlock *new_block, Error **errp)
1846 RAMBlock *block;
1847 RAMBlock *last_block = NULL;
1848 ram_addr_t old_ram_size, new_ram_size;
1849 Error *err = NULL;
1851 old_ram_size = last_ram_page();
1853 qemu_mutex_lock_ramlist();
1854 new_block->offset = find_ram_offset(new_block->max_length);
1856 if (!new_block->host) {
1857 if (xen_enabled()) {
1858 xen_ram_alloc(new_block->offset, new_block->max_length,
1859 new_block->mr, &err);
1860 if (err) {
1861 error_propagate(errp, err);
1862 qemu_mutex_unlock_ramlist();
1863 return;
1865 } else {
1866 new_block->host = phys_mem_alloc(new_block->max_length,
1867 &new_block->mr->align);
1868 if (!new_block->host) {
1869 error_setg_errno(errp, errno,
1870 "cannot set up guest memory '%s'",
1871 memory_region_name(new_block->mr));
1872 qemu_mutex_unlock_ramlist();
1873 return;
1875 memory_try_enable_merging(new_block->host, new_block->max_length);
1879 new_ram_size = MAX(old_ram_size,
1880 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1881 if (new_ram_size > old_ram_size) {
1882 dirty_memory_extend(old_ram_size, new_ram_size);
1884 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1885 * QLIST (which has an RCU-friendly variant) does not have insertion at
1886 * tail, so save the last element in last_block.
1888 RAMBLOCK_FOREACH(block) {
1889 last_block = block;
1890 if (block->max_length < new_block->max_length) {
1891 break;
1894 if (block) {
1895 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1896 } else if (last_block) {
1897 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1898 } else { /* list is empty */
1899 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1901 ram_list.mru_block = NULL;
1903 /* Write list before version */
1904 smp_wmb();
1905 ram_list.version++;
1906 qemu_mutex_unlock_ramlist();
1908 cpu_physical_memory_set_dirty_range(new_block->offset,
1909 new_block->used_length,
1910 DIRTY_CLIENTS_ALL);
1912 if (new_block->host) {
1913 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1914 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1915 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1916 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1917 ram_block_notify_add(new_block->host, new_block->max_length);
1921 #ifdef __linux__
1922 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
1923 bool share, int fd,
1924 Error **errp)
1926 RAMBlock *new_block;
1927 Error *local_err = NULL;
1928 int64_t file_size;
1930 if (xen_enabled()) {
1931 error_setg(errp, "-mem-path not supported with Xen");
1932 return NULL;
1935 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1936 error_setg(errp,
1937 "host lacks kvm mmu notifiers, -mem-path unsupported");
1938 return NULL;
1941 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1943 * file_ram_alloc() needs to allocate just like
1944 * phys_mem_alloc, but we haven't bothered to provide
1945 * a hook there.
1947 error_setg(errp,
1948 "-mem-path not supported with this accelerator");
1949 return NULL;
1952 size = HOST_PAGE_ALIGN(size);
1953 file_size = get_file_size(fd);
1954 if (file_size > 0 && file_size < size) {
1955 error_setg(errp, "backing store %s size 0x%" PRIx64
1956 " does not match 'size' option 0x" RAM_ADDR_FMT,
1957 mem_path, file_size, size);
1958 return NULL;
1961 new_block = g_malloc0(sizeof(*new_block));
1962 new_block->mr = mr;
1963 new_block->used_length = size;
1964 new_block->max_length = size;
1965 new_block->flags = share ? RAM_SHARED : 0;
1966 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
1967 if (!new_block->host) {
1968 g_free(new_block);
1969 return NULL;
1972 ram_block_add(new_block, &local_err);
1973 if (local_err) {
1974 g_free(new_block);
1975 error_propagate(errp, local_err);
1976 return NULL;
1978 return new_block;
1983 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
1984 bool share, const char *mem_path,
1985 Error **errp)
1987 int fd;
1988 bool created;
1989 RAMBlock *block;
1991 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
1992 if (fd < 0) {
1993 return NULL;
1996 block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1997 if (!block) {
1998 if (created) {
1999 unlink(mem_path);
2001 close(fd);
2002 return NULL;
2005 return block;
2007 #endif
2009 static
2010 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2011 void (*resized)(const char*,
2012 uint64_t length,
2013 void *host),
2014 void *host, bool resizeable,
2015 MemoryRegion *mr, Error **errp)
2017 RAMBlock *new_block;
2018 Error *local_err = NULL;
2020 size = HOST_PAGE_ALIGN(size);
2021 max_size = HOST_PAGE_ALIGN(max_size);
2022 new_block = g_malloc0(sizeof(*new_block));
2023 new_block->mr = mr;
2024 new_block->resized = resized;
2025 new_block->used_length = size;
2026 new_block->max_length = max_size;
2027 assert(max_size >= size);
2028 new_block->fd = -1;
2029 new_block->page_size = getpagesize();
2030 new_block->host = host;
2031 if (host) {
2032 new_block->flags |= RAM_PREALLOC;
2034 if (resizeable) {
2035 new_block->flags |= RAM_RESIZEABLE;
2037 ram_block_add(new_block, &local_err);
2038 if (local_err) {
2039 g_free(new_block);
2040 error_propagate(errp, local_err);
2041 return NULL;
2043 return new_block;
2046 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2047 MemoryRegion *mr, Error **errp)
2049 return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp);
2052 RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
2054 return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp);
2057 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2058 void (*resized)(const char*,
2059 uint64_t length,
2060 void *host),
2061 MemoryRegion *mr, Error **errp)
2063 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp);
2066 static void reclaim_ramblock(RAMBlock *block)
2068 if (block->flags & RAM_PREALLOC) {
2070 } else if (xen_enabled()) {
2071 xen_invalidate_map_cache_entry(block->host);
2072 #ifndef _WIN32
2073 } else if (block->fd >= 0) {
2074 qemu_ram_munmap(block->host, block->max_length);
2075 close(block->fd);
2076 #endif
2077 } else {
2078 qemu_anon_ram_free(block->host, block->max_length);
2080 g_free(block);
2083 void qemu_ram_free(RAMBlock *block)
2085 if (!block) {
2086 return;
2089 if (block->host) {
2090 ram_block_notify_remove(block->host, block->max_length);
2093 qemu_mutex_lock_ramlist();
2094 QLIST_REMOVE_RCU(block, next);
2095 ram_list.mru_block = NULL;
2096 /* Write list before version */
2097 smp_wmb();
2098 ram_list.version++;
2099 call_rcu(block, reclaim_ramblock, rcu);
2100 qemu_mutex_unlock_ramlist();
2103 #ifndef _WIN32
2104 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2106 RAMBlock *block;
2107 ram_addr_t offset;
2108 int flags;
2109 void *area, *vaddr;
2111 RAMBLOCK_FOREACH(block) {
2112 offset = addr - block->offset;
2113 if (offset < block->max_length) {
2114 vaddr = ramblock_ptr(block, offset);
2115 if (block->flags & RAM_PREALLOC) {
2117 } else if (xen_enabled()) {
2118 abort();
2119 } else {
2120 flags = MAP_FIXED;
2121 if (block->fd >= 0) {
2122 flags |= (block->flags & RAM_SHARED ?
2123 MAP_SHARED : MAP_PRIVATE);
2124 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2125 flags, block->fd, offset);
2126 } else {
2128 * Remap needs to match alloc. Accelerators that
2129 * set phys_mem_alloc never remap. If they did,
2130 * we'd need a remap hook here.
2132 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2134 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2135 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2136 flags, -1, 0);
2138 if (area != vaddr) {
2139 fprintf(stderr, "Could not remap addr: "
2140 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
2141 length, addr);
2142 exit(1);
2144 memory_try_enable_merging(vaddr, length);
2145 qemu_ram_setup_dump(vaddr, length);
2150 #endif /* !_WIN32 */
2152 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2153 * This should not be used for general purpose DMA. Use address_space_map
2154 * or address_space_rw instead. For local memory (e.g. video ram) that the
2155 * device owns, use memory_region_get_ram_ptr.
2157 * Called within RCU critical section.
2159 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2161 RAMBlock *block = ram_block;
2163 if (block == NULL) {
2164 block = qemu_get_ram_block(addr);
2165 addr -= block->offset;
2168 if (xen_enabled() && block->host == NULL) {
2169 /* We need to check if the requested address is in the RAM
2170 * because we don't want to map the entire memory in QEMU.
2171 * In that case just map until the end of the page.
2173 if (block->offset == 0) {
2174 return xen_map_cache(addr, 0, 0, false);
2177 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2179 return ramblock_ptr(block, addr);
2182 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2183 * but takes a size argument.
2185 * Called within RCU critical section.
2187 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2188 hwaddr *size)
2190 RAMBlock *block = ram_block;
2191 if (*size == 0) {
2192 return NULL;
2195 if (block == NULL) {
2196 block = qemu_get_ram_block(addr);
2197 addr -= block->offset;
2199 *size = MIN(*size, block->max_length - addr);
2201 if (xen_enabled() && block->host == NULL) {
2202 /* We need to check if the requested address is in the RAM
2203 * because we don't want to map the entire memory in QEMU.
2204 * In that case just map the requested area.
2206 if (block->offset == 0) {
2207 return xen_map_cache(addr, *size, 1, true);
2210 block->host = xen_map_cache(block->offset, block->max_length, 1, true);
2213 return ramblock_ptr(block, addr);
2217 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2218 * in that RAMBlock.
2220 * ptr: Host pointer to look up
2221 * round_offset: If true round the result offset down to a page boundary
2222 * *ram_addr: set to result ram_addr
2223 * *offset: set to result offset within the RAMBlock
2225 * Returns: RAMBlock (or NULL if not found)
2227 * By the time this function returns, the returned pointer is not protected
2228 * by RCU anymore. If the caller is not within an RCU critical section and
2229 * does not hold the iothread lock, it must have other means of protecting the
2230 * pointer, such as a reference to the region that includes the incoming
2231 * ram_addr_t.
2233 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2234 ram_addr_t *offset)
2236 RAMBlock *block;
2237 uint8_t *host = ptr;
2239 if (xen_enabled()) {
2240 ram_addr_t ram_addr;
2241 rcu_read_lock();
2242 ram_addr = xen_ram_addr_from_mapcache(ptr);
2243 block = qemu_get_ram_block(ram_addr);
2244 if (block) {
2245 *offset = ram_addr - block->offset;
2247 rcu_read_unlock();
2248 return block;
2251 rcu_read_lock();
2252 block = atomic_rcu_read(&ram_list.mru_block);
2253 if (block && block->host && host - block->host < block->max_length) {
2254 goto found;
2257 RAMBLOCK_FOREACH(block) {
2258 /* This case append when the block is not mapped. */
2259 if (block->host == NULL) {
2260 continue;
2262 if (host - block->host < block->max_length) {
2263 goto found;
2267 rcu_read_unlock();
2268 return NULL;
2270 found:
2271 *offset = (host - block->host);
2272 if (round_offset) {
2273 *offset &= TARGET_PAGE_MASK;
2275 rcu_read_unlock();
2276 return block;
2280 * Finds the named RAMBlock
2282 * name: The name of RAMBlock to find
2284 * Returns: RAMBlock (or NULL if not found)
2286 RAMBlock *qemu_ram_block_by_name(const char *name)
2288 RAMBlock *block;
2290 RAMBLOCK_FOREACH(block) {
2291 if (!strcmp(name, block->idstr)) {
2292 return block;
2296 return NULL;
2299 /* Some of the softmmu routines need to translate from a host pointer
2300 (typically a TLB entry) back to a ram offset. */
2301 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2303 RAMBlock *block;
2304 ram_addr_t offset;
2306 block = qemu_ram_block_from_host(ptr, false, &offset);
2307 if (!block) {
2308 return RAM_ADDR_INVALID;
2311 return block->offset + offset;
2314 /* Called within RCU critical section. */
2315 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2316 uint64_t val, unsigned size)
2318 bool locked = false;
2320 assert(tcg_enabled());
2321 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2322 locked = true;
2323 tb_lock();
2324 tb_invalidate_phys_page_fast(ram_addr, size);
2326 switch (size) {
2327 case 1:
2328 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2329 break;
2330 case 2:
2331 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2332 break;
2333 case 4:
2334 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2335 break;
2336 default:
2337 abort();
2340 if (locked) {
2341 tb_unlock();
2344 /* Set both VGA and migration bits for simplicity and to remove
2345 * the notdirty callback faster.
2347 cpu_physical_memory_set_dirty_range(ram_addr, size,
2348 DIRTY_CLIENTS_NOCODE);
2349 /* we remove the notdirty callback only if the code has been
2350 flushed */
2351 if (!cpu_physical_memory_is_clean(ram_addr)) {
2352 tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr);
2356 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2357 unsigned size, bool is_write)
2359 return is_write;
2362 static const MemoryRegionOps notdirty_mem_ops = {
2363 .write = notdirty_mem_write,
2364 .valid.accepts = notdirty_mem_accepts,
2365 .endianness = DEVICE_NATIVE_ENDIAN,
2368 /* Generate a debug exception if a watchpoint has been hit. */
2369 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2371 CPUState *cpu = current_cpu;
2372 CPUClass *cc = CPU_GET_CLASS(cpu);
2373 CPUArchState *env = cpu->env_ptr;
2374 target_ulong pc, cs_base;
2375 target_ulong vaddr;
2376 CPUWatchpoint *wp;
2377 uint32_t cpu_flags;
2379 assert(tcg_enabled());
2380 if (cpu->watchpoint_hit) {
2381 /* We re-entered the check after replacing the TB. Now raise
2382 * the debug interrupt so that is will trigger after the
2383 * current instruction. */
2384 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2385 return;
2387 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2388 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2389 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2390 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2391 && (wp->flags & flags)) {
2392 if (flags == BP_MEM_READ) {
2393 wp->flags |= BP_WATCHPOINT_HIT_READ;
2394 } else {
2395 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2397 wp->hitaddr = vaddr;
2398 wp->hitattrs = attrs;
2399 if (!cpu->watchpoint_hit) {
2400 if (wp->flags & BP_CPU &&
2401 !cc->debug_check_watchpoint(cpu, wp)) {
2402 wp->flags &= ~BP_WATCHPOINT_HIT;
2403 continue;
2405 cpu->watchpoint_hit = wp;
2407 /* Both tb_lock and iothread_mutex will be reset when
2408 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2409 * back into the cpu_exec main loop.
2411 tb_lock();
2412 tb_check_watchpoint(cpu);
2413 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2414 cpu->exception_index = EXCP_DEBUG;
2415 cpu_loop_exit(cpu);
2416 } else {
2417 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2418 tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
2419 cpu_loop_exit_noexc(cpu);
2422 } else {
2423 wp->flags &= ~BP_WATCHPOINT_HIT;
2428 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2429 so these check for a hit then pass through to the normal out-of-line
2430 phys routines. */
2431 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2432 unsigned size, MemTxAttrs attrs)
2434 MemTxResult res;
2435 uint64_t data;
2436 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2437 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2439 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2440 switch (size) {
2441 case 1:
2442 data = address_space_ldub(as, addr, attrs, &res);
2443 break;
2444 case 2:
2445 data = address_space_lduw(as, addr, attrs, &res);
2446 break;
2447 case 4:
2448 data = address_space_ldl(as, addr, attrs, &res);
2449 break;
2450 default: abort();
2452 *pdata = data;
2453 return res;
2456 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2457 uint64_t val, unsigned size,
2458 MemTxAttrs attrs)
2460 MemTxResult res;
2461 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2462 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2464 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2465 switch (size) {
2466 case 1:
2467 address_space_stb(as, addr, val, attrs, &res);
2468 break;
2469 case 2:
2470 address_space_stw(as, addr, val, attrs, &res);
2471 break;
2472 case 4:
2473 address_space_stl(as, addr, val, attrs, &res);
2474 break;
2475 default: abort();
2477 return res;
2480 static const MemoryRegionOps watch_mem_ops = {
2481 .read_with_attrs = watch_mem_read,
2482 .write_with_attrs = watch_mem_write,
2483 .endianness = DEVICE_NATIVE_ENDIAN,
2486 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2487 unsigned len, MemTxAttrs attrs)
2489 subpage_t *subpage = opaque;
2490 uint8_t buf[8];
2491 MemTxResult res;
2493 #if defined(DEBUG_SUBPAGE)
2494 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2495 subpage, len, addr);
2496 #endif
2497 res = address_space_read(subpage->as, addr + subpage->base,
2498 attrs, buf, len);
2499 if (res) {
2500 return res;
2502 switch (len) {
2503 case 1:
2504 *data = ldub_p(buf);
2505 return MEMTX_OK;
2506 case 2:
2507 *data = lduw_p(buf);
2508 return MEMTX_OK;
2509 case 4:
2510 *data = ldl_p(buf);
2511 return MEMTX_OK;
2512 case 8:
2513 *data = ldq_p(buf);
2514 return MEMTX_OK;
2515 default:
2516 abort();
2520 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2521 uint64_t value, unsigned len, MemTxAttrs attrs)
2523 subpage_t *subpage = opaque;
2524 uint8_t buf[8];
2526 #if defined(DEBUG_SUBPAGE)
2527 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2528 " value %"PRIx64"\n",
2529 __func__, subpage, len, addr, value);
2530 #endif
2531 switch (len) {
2532 case 1:
2533 stb_p(buf, value);
2534 break;
2535 case 2:
2536 stw_p(buf, value);
2537 break;
2538 case 4:
2539 stl_p(buf, value);
2540 break;
2541 case 8:
2542 stq_p(buf, value);
2543 break;
2544 default:
2545 abort();
2547 return address_space_write(subpage->as, addr + subpage->base,
2548 attrs, buf, len);
2551 static bool subpage_accepts(void *opaque, hwaddr addr,
2552 unsigned len, bool is_write)
2554 subpage_t *subpage = opaque;
2555 #if defined(DEBUG_SUBPAGE)
2556 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2557 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2558 #endif
2560 return address_space_access_valid(subpage->as, addr + subpage->base,
2561 len, is_write);
2564 static const MemoryRegionOps subpage_ops = {
2565 .read_with_attrs = subpage_read,
2566 .write_with_attrs = subpage_write,
2567 .impl.min_access_size = 1,
2568 .impl.max_access_size = 8,
2569 .valid.min_access_size = 1,
2570 .valid.max_access_size = 8,
2571 .valid.accepts = subpage_accepts,
2572 .endianness = DEVICE_NATIVE_ENDIAN,
2575 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2576 uint16_t section)
2578 int idx, eidx;
2580 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2581 return -1;
2582 idx = SUBPAGE_IDX(start);
2583 eidx = SUBPAGE_IDX(end);
2584 #if defined(DEBUG_SUBPAGE)
2585 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2586 __func__, mmio, start, end, idx, eidx, section);
2587 #endif
2588 for (; idx <= eidx; idx++) {
2589 mmio->sub_section[idx] = section;
2592 return 0;
2595 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
2597 subpage_t *mmio;
2599 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2600 mmio->as = as;
2601 mmio->base = base;
2602 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2603 NULL, TARGET_PAGE_SIZE);
2604 mmio->iomem.subpage = true;
2605 #if defined(DEBUG_SUBPAGE)
2606 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2607 mmio, base, TARGET_PAGE_SIZE);
2608 #endif
2609 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2611 return mmio;
2614 static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
2615 MemoryRegion *mr)
2617 assert(as);
2618 MemoryRegionSection section = {
2619 .address_space = as,
2620 .mr = mr,
2621 .offset_within_address_space = 0,
2622 .offset_within_region = 0,
2623 .size = int128_2_64(),
2626 return phys_section_add(map, &section);
2629 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2631 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2632 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2633 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2634 MemoryRegionSection *sections = d->map.sections;
2636 return sections[index & ~TARGET_PAGE_MASK].mr;
2639 static void io_mem_init(void)
2641 memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
2642 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2643 NULL, UINT64_MAX);
2645 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2646 * which can be called without the iothread mutex.
2648 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2649 NULL, UINT64_MAX);
2650 memory_region_clear_global_locking(&io_mem_notdirty);
2652 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2653 NULL, UINT64_MAX);
2656 static void mem_begin(MemoryListener *listener)
2658 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2659 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2660 uint16_t n;
2662 n = dummy_section(&d->map, as, &io_mem_unassigned);
2663 assert(n == PHYS_SECTION_UNASSIGNED);
2664 n = dummy_section(&d->map, as, &io_mem_notdirty);
2665 assert(n == PHYS_SECTION_NOTDIRTY);
2666 n = dummy_section(&d->map, as, &io_mem_rom);
2667 assert(n == PHYS_SECTION_ROM);
2668 n = dummy_section(&d->map, as, &io_mem_watch);
2669 assert(n == PHYS_SECTION_WATCH);
2671 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2672 d->as = as;
2673 as->next_dispatch = d;
2676 static void address_space_dispatch_free(AddressSpaceDispatch *d)
2678 phys_sections_free(&d->map);
2679 g_free(d);
2682 static void mem_commit(MemoryListener *listener)
2684 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2685 AddressSpaceDispatch *cur = as->dispatch;
2686 AddressSpaceDispatch *next = as->next_dispatch;
2688 phys_page_compact_all(next, next->map.nodes_nb);
2690 atomic_rcu_set(&as->dispatch, next);
2691 if (cur) {
2692 call_rcu(cur, address_space_dispatch_free, rcu);
2696 static void tcg_commit(MemoryListener *listener)
2698 CPUAddressSpace *cpuas;
2699 AddressSpaceDispatch *d;
2701 /* since each CPU stores ram addresses in its TLB cache, we must
2702 reset the modified entries */
2703 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2704 cpu_reloading_memory_map();
2705 /* The CPU and TLB are protected by the iothread lock.
2706 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2707 * may have split the RCU critical section.
2709 d = atomic_rcu_read(&cpuas->as->dispatch);
2710 atomic_rcu_set(&cpuas->memory_dispatch, d);
2711 tlb_flush(cpuas->cpu);
2714 void address_space_init_dispatch(AddressSpace *as)
2716 as->dispatch = NULL;
2717 as->dispatch_listener = (MemoryListener) {
2718 .begin = mem_begin,
2719 .commit = mem_commit,
2720 .region_add = mem_add,
2721 .region_nop = mem_add,
2722 .priority = 0,
2724 memory_listener_register(&as->dispatch_listener, as);
2727 void address_space_unregister(AddressSpace *as)
2729 memory_listener_unregister(&as->dispatch_listener);
2732 void address_space_destroy_dispatch(AddressSpace *as)
2734 AddressSpaceDispatch *d = as->dispatch;
2736 atomic_rcu_set(&as->dispatch, NULL);
2737 if (d) {
2738 call_rcu(d, address_space_dispatch_free, rcu);
2742 static void memory_map_init(void)
2744 system_memory = g_malloc(sizeof(*system_memory));
2746 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2747 address_space_init(&address_space_memory, system_memory, "memory");
2749 system_io = g_malloc(sizeof(*system_io));
2750 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2751 65536);
2752 address_space_init(&address_space_io, system_io, "I/O");
2755 MemoryRegion *get_system_memory(void)
2757 return system_memory;
2760 MemoryRegion *get_system_io(void)
2762 return system_io;
2765 #endif /* !defined(CONFIG_USER_ONLY) */
2767 /* physical memory access (slow version, mainly for debug) */
2768 #if defined(CONFIG_USER_ONLY)
2769 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2770 uint8_t *buf, int len, int is_write)
2772 int l, flags;
2773 target_ulong page;
2774 void * p;
2776 while (len > 0) {
2777 page = addr & TARGET_PAGE_MASK;
2778 l = (page + TARGET_PAGE_SIZE) - addr;
2779 if (l > len)
2780 l = len;
2781 flags = page_get_flags(page);
2782 if (!(flags & PAGE_VALID))
2783 return -1;
2784 if (is_write) {
2785 if (!(flags & PAGE_WRITE))
2786 return -1;
2787 /* XXX: this code should not depend on lock_user */
2788 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2789 return -1;
2790 memcpy(p, buf, l);
2791 unlock_user(p, addr, l);
2792 } else {
2793 if (!(flags & PAGE_READ))
2794 return -1;
2795 /* XXX: this code should not depend on lock_user */
2796 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2797 return -1;
2798 memcpy(buf, p, l);
2799 unlock_user(p, addr, 0);
2801 len -= l;
2802 buf += l;
2803 addr += l;
2805 return 0;
2808 #else
2810 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2811 hwaddr length)
2813 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2814 addr += memory_region_get_ram_addr(mr);
2816 /* No early return if dirty_log_mask is or becomes 0, because
2817 * cpu_physical_memory_set_dirty_range will still call
2818 * xen_modified_memory.
2820 if (dirty_log_mask) {
2821 dirty_log_mask =
2822 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2824 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2825 assert(tcg_enabled());
2826 tb_lock();
2827 tb_invalidate_phys_range(addr, addr + length);
2828 tb_unlock();
2829 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2831 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2834 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2836 unsigned access_size_max = mr->ops->valid.max_access_size;
2838 /* Regions are assumed to support 1-4 byte accesses unless
2839 otherwise specified. */
2840 if (access_size_max == 0) {
2841 access_size_max = 4;
2844 /* Bound the maximum access by the alignment of the address. */
2845 if (!mr->ops->impl.unaligned) {
2846 unsigned align_size_max = addr & -addr;
2847 if (align_size_max != 0 && align_size_max < access_size_max) {
2848 access_size_max = align_size_max;
2852 /* Don't attempt accesses larger than the maximum. */
2853 if (l > access_size_max) {
2854 l = access_size_max;
2856 l = pow2floor(l);
2858 return l;
2861 static bool prepare_mmio_access(MemoryRegion *mr)
2863 bool unlocked = !qemu_mutex_iothread_locked();
2864 bool release_lock = false;
2866 if (unlocked && mr->global_locking) {
2867 qemu_mutex_lock_iothread();
2868 unlocked = false;
2869 release_lock = true;
2871 if (mr->flush_coalesced_mmio) {
2872 if (unlocked) {
2873 qemu_mutex_lock_iothread();
2875 qemu_flush_coalesced_mmio_buffer();
2876 if (unlocked) {
2877 qemu_mutex_unlock_iothread();
2881 return release_lock;
2884 /* Called within RCU critical section. */
2885 static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
2886 MemTxAttrs attrs,
2887 const uint8_t *buf,
2888 int len, hwaddr addr1,
2889 hwaddr l, MemoryRegion *mr)
2891 uint8_t *ptr;
2892 uint64_t val;
2893 MemTxResult result = MEMTX_OK;
2894 bool release_lock = false;
2896 for (;;) {
2897 if (!memory_access_is_direct(mr, true)) {
2898 release_lock |= prepare_mmio_access(mr);
2899 l = memory_access_size(mr, l, addr1);
2900 /* XXX: could force current_cpu to NULL to avoid
2901 potential bugs */
2902 switch (l) {
2903 case 8:
2904 /* 64 bit write access */
2905 val = ldq_p(buf);
2906 result |= memory_region_dispatch_write(mr, addr1, val, 8,
2907 attrs);
2908 break;
2909 case 4:
2910 /* 32 bit write access */
2911 val = (uint32_t)ldl_p(buf);
2912 result |= memory_region_dispatch_write(mr, addr1, val, 4,
2913 attrs);
2914 break;
2915 case 2:
2916 /* 16 bit write access */
2917 val = lduw_p(buf);
2918 result |= memory_region_dispatch_write(mr, addr1, val, 2,
2919 attrs);
2920 break;
2921 case 1:
2922 /* 8 bit write access */
2923 val = ldub_p(buf);
2924 result |= memory_region_dispatch_write(mr, addr1, val, 1,
2925 attrs);
2926 break;
2927 default:
2928 abort();
2930 } else {
2931 /* RAM case */
2932 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2933 memcpy(ptr, buf, l);
2934 invalidate_and_set_dirty(mr, addr1, l);
2937 if (release_lock) {
2938 qemu_mutex_unlock_iothread();
2939 release_lock = false;
2942 len -= l;
2943 buf += l;
2944 addr += l;
2946 if (!len) {
2947 break;
2950 l = len;
2951 mr = address_space_translate(as, addr, &addr1, &l, true);
2954 return result;
2957 MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2958 const uint8_t *buf, int len)
2960 hwaddr l;
2961 hwaddr addr1;
2962 MemoryRegion *mr;
2963 MemTxResult result = MEMTX_OK;
2965 if (len > 0) {
2966 rcu_read_lock();
2967 l = len;
2968 mr = address_space_translate(as, addr, &addr1, &l, true);
2969 result = address_space_write_continue(as, addr, attrs, buf, len,
2970 addr1, l, mr);
2971 rcu_read_unlock();
2974 return result;
2977 /* Called within RCU critical section. */
2978 MemTxResult address_space_read_continue(AddressSpace *as, hwaddr addr,
2979 MemTxAttrs attrs, uint8_t *buf,
2980 int len, hwaddr addr1, hwaddr l,
2981 MemoryRegion *mr)
2983 uint8_t *ptr;
2984 uint64_t val;
2985 MemTxResult result = MEMTX_OK;
2986 bool release_lock = false;
2988 for (;;) {
2989 if (!memory_access_is_direct(mr, false)) {
2990 /* I/O case */
2991 release_lock |= prepare_mmio_access(mr);
2992 l = memory_access_size(mr, l, addr1);
2993 switch (l) {
2994 case 8:
2995 /* 64 bit read access */
2996 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
2997 attrs);
2998 stq_p(buf, val);
2999 break;
3000 case 4:
3001 /* 32 bit read access */
3002 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
3003 attrs);
3004 stl_p(buf, val);
3005 break;
3006 case 2:
3007 /* 16 bit read access */
3008 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
3009 attrs);
3010 stw_p(buf, val);
3011 break;
3012 case 1:
3013 /* 8 bit read access */
3014 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
3015 attrs);
3016 stb_p(buf, val);
3017 break;
3018 default:
3019 abort();
3021 } else {
3022 /* RAM case */
3023 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3024 memcpy(buf, ptr, l);
3027 if (release_lock) {
3028 qemu_mutex_unlock_iothread();
3029 release_lock = false;
3032 len -= l;
3033 buf += l;
3034 addr += l;
3036 if (!len) {
3037 break;
3040 l = len;
3041 mr = address_space_translate(as, addr, &addr1, &l, false);
3044 return result;
3047 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3048 MemTxAttrs attrs, uint8_t *buf, int len)
3050 hwaddr l;
3051 hwaddr addr1;
3052 MemoryRegion *mr;
3053 MemTxResult result = MEMTX_OK;
3055 if (len > 0) {
3056 rcu_read_lock();
3057 l = len;
3058 mr = address_space_translate(as, addr, &addr1, &l, false);
3059 result = address_space_read_continue(as, addr, attrs, buf, len,
3060 addr1, l, mr);
3061 rcu_read_unlock();
3064 return result;
3067 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3068 uint8_t *buf, int len, bool is_write)
3070 if (is_write) {
3071 return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
3072 } else {
3073 return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
3077 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3078 int len, int is_write)
3080 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3081 buf, len, is_write);
3084 enum write_rom_type {
3085 WRITE_DATA,
3086 FLUSH_CACHE,
3089 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3090 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3092 hwaddr l;
3093 uint8_t *ptr;
3094 hwaddr addr1;
3095 MemoryRegion *mr;
3097 rcu_read_lock();
3098 while (len > 0) {
3099 l = len;
3100 mr = address_space_translate(as, addr, &addr1, &l, true);
3102 if (!(memory_region_is_ram(mr) ||
3103 memory_region_is_romd(mr))) {
3104 l = memory_access_size(mr, l, addr1);
3105 } else {
3106 /* ROM/RAM case */
3107 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3108 switch (type) {
3109 case WRITE_DATA:
3110 memcpy(ptr, buf, l);
3111 invalidate_and_set_dirty(mr, addr1, l);
3112 break;
3113 case FLUSH_CACHE:
3114 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3115 break;
3118 len -= l;
3119 buf += l;
3120 addr += l;
3122 rcu_read_unlock();
3125 /* used for ROM loading : can write in RAM and ROM */
3126 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3127 const uint8_t *buf, int len)
3129 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3132 void cpu_flush_icache_range(hwaddr start, int len)
3135 * This function should do the same thing as an icache flush that was
3136 * triggered from within the guest. For TCG we are always cache coherent,
3137 * so there is no need to flush anything. For KVM / Xen we need to flush
3138 * the host's instruction cache at least.
3140 if (tcg_enabled()) {
3141 return;
3144 cpu_physical_memory_write_rom_internal(&address_space_memory,
3145 start, NULL, len, FLUSH_CACHE);
3148 typedef struct {
3149 MemoryRegion *mr;
3150 void *buffer;
3151 hwaddr addr;
3152 hwaddr len;
3153 bool in_use;
3154 } BounceBuffer;
3156 static BounceBuffer bounce;
3158 typedef struct MapClient {
3159 QEMUBH *bh;
3160 QLIST_ENTRY(MapClient) link;
3161 } MapClient;
3163 QemuMutex map_client_list_lock;
3164 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3165 = QLIST_HEAD_INITIALIZER(map_client_list);
3167 static void cpu_unregister_map_client_do(MapClient *client)
3169 QLIST_REMOVE(client, link);
3170 g_free(client);
3173 static void cpu_notify_map_clients_locked(void)
3175 MapClient *client;
3177 while (!QLIST_EMPTY(&map_client_list)) {
3178 client = QLIST_FIRST(&map_client_list);
3179 qemu_bh_schedule(client->bh);
3180 cpu_unregister_map_client_do(client);
3184 void cpu_register_map_client(QEMUBH *bh)
3186 MapClient *client = g_malloc(sizeof(*client));
3188 qemu_mutex_lock(&map_client_list_lock);
3189 client->bh = bh;
3190 QLIST_INSERT_HEAD(&map_client_list, client, link);
3191 if (!atomic_read(&bounce.in_use)) {
3192 cpu_notify_map_clients_locked();
3194 qemu_mutex_unlock(&map_client_list_lock);
3197 void cpu_exec_init_all(void)
3199 qemu_mutex_init(&ram_list.mutex);
3200 /* The data structures we set up here depend on knowing the page size,
3201 * so no more changes can be made after this point.
3202 * In an ideal world, nothing we did before we had finished the
3203 * machine setup would care about the target page size, and we could
3204 * do this much later, rather than requiring board models to state
3205 * up front what their requirements are.
3207 finalize_target_page_bits();
3208 io_mem_init();
3209 memory_map_init();
3210 qemu_mutex_init(&map_client_list_lock);
3213 void cpu_unregister_map_client(QEMUBH *bh)
3215 MapClient *client;
3217 qemu_mutex_lock(&map_client_list_lock);
3218 QLIST_FOREACH(client, &map_client_list, link) {
3219 if (client->bh == bh) {
3220 cpu_unregister_map_client_do(client);
3221 break;
3224 qemu_mutex_unlock(&map_client_list_lock);
3227 static void cpu_notify_map_clients(void)
3229 qemu_mutex_lock(&map_client_list_lock);
3230 cpu_notify_map_clients_locked();
3231 qemu_mutex_unlock(&map_client_list_lock);
3234 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
3236 MemoryRegion *mr;
3237 hwaddr l, xlat;
3239 rcu_read_lock();
3240 while (len > 0) {
3241 l = len;
3242 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3243 if (!memory_access_is_direct(mr, is_write)) {
3244 l = memory_access_size(mr, l, addr);
3245 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
3246 rcu_read_unlock();
3247 return false;
3251 len -= l;
3252 addr += l;
3254 rcu_read_unlock();
3255 return true;
3258 static hwaddr
3259 address_space_extend_translation(AddressSpace *as, hwaddr addr, hwaddr target_len,
3260 MemoryRegion *mr, hwaddr base, hwaddr len,
3261 bool is_write)
3263 hwaddr done = 0;
3264 hwaddr xlat;
3265 MemoryRegion *this_mr;
3267 for (;;) {
3268 target_len -= len;
3269 addr += len;
3270 done += len;
3271 if (target_len == 0) {
3272 return done;
3275 len = target_len;
3276 this_mr = address_space_translate(as, addr, &xlat, &len, is_write);
3277 if (this_mr != mr || xlat != base + done) {
3278 return done;
3283 /* Map a physical memory region into a host virtual address.
3284 * May map a subset of the requested range, given by and returned in *plen.
3285 * May return NULL if resources needed to perform the mapping are exhausted.
3286 * Use only for reads OR writes - not for read-modify-write operations.
3287 * Use cpu_register_map_client() to know when retrying the map operation is
3288 * likely to succeed.
3290 void *address_space_map(AddressSpace *as,
3291 hwaddr addr,
3292 hwaddr *plen,
3293 bool is_write)
3295 hwaddr len = *plen;
3296 hwaddr l, xlat;
3297 MemoryRegion *mr;
3298 void *ptr;
3300 if (len == 0) {
3301 return NULL;
3304 l = len;
3305 rcu_read_lock();
3306 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3308 if (!memory_access_is_direct(mr, is_write)) {
3309 if (atomic_xchg(&bounce.in_use, true)) {
3310 rcu_read_unlock();
3311 return NULL;
3313 /* Avoid unbounded allocations */
3314 l = MIN(l, TARGET_PAGE_SIZE);
3315 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3316 bounce.addr = addr;
3317 bounce.len = l;
3319 memory_region_ref(mr);
3320 bounce.mr = mr;
3321 if (!is_write) {
3322 address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED,
3323 bounce.buffer, l);
3326 rcu_read_unlock();
3327 *plen = l;
3328 return bounce.buffer;
3332 memory_region_ref(mr);
3333 *plen = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3334 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen);
3335 rcu_read_unlock();
3337 return ptr;
3340 /* Unmaps a memory region previously mapped by address_space_map().
3341 * Will also mark the memory as dirty if is_write == 1. access_len gives
3342 * the amount of memory that was actually read or written by the caller.
3344 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3345 int is_write, hwaddr access_len)
3347 if (buffer != bounce.buffer) {
3348 MemoryRegion *mr;
3349 ram_addr_t addr1;
3351 mr = memory_region_from_host(buffer, &addr1);
3352 assert(mr != NULL);
3353 if (is_write) {
3354 invalidate_and_set_dirty(mr, addr1, access_len);
3356 if (xen_enabled()) {
3357 xen_invalidate_map_cache_entry(buffer);
3359 memory_region_unref(mr);
3360 return;
3362 if (is_write) {
3363 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3364 bounce.buffer, access_len);
3366 qemu_vfree(bounce.buffer);
3367 bounce.buffer = NULL;
3368 memory_region_unref(bounce.mr);
3369 atomic_mb_set(&bounce.in_use, false);
3370 cpu_notify_map_clients();
3373 void *cpu_physical_memory_map(hwaddr addr,
3374 hwaddr *plen,
3375 int is_write)
3377 return address_space_map(&address_space_memory, addr, plen, is_write);
3380 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3381 int is_write, hwaddr access_len)
3383 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3386 #define ARG1_DECL AddressSpace *as
3387 #define ARG1 as
3388 #define SUFFIX
3389 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3390 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3391 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3392 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3393 #define RCU_READ_LOCK(...) rcu_read_lock()
3394 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3395 #include "memory_ldst.inc.c"
3397 int64_t address_space_cache_init(MemoryRegionCache *cache,
3398 AddressSpace *as,
3399 hwaddr addr,
3400 hwaddr len,
3401 bool is_write)
3403 cache->len = len;
3404 cache->as = as;
3405 cache->xlat = addr;
3406 return len;
3409 void address_space_cache_invalidate(MemoryRegionCache *cache,
3410 hwaddr addr,
3411 hwaddr access_len)
3415 void address_space_cache_destroy(MemoryRegionCache *cache)
3417 cache->as = NULL;
3420 #define ARG1_DECL MemoryRegionCache *cache
3421 #define ARG1 cache
3422 #define SUFFIX _cached
3423 #define TRANSLATE(addr, ...) \
3424 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3425 #define IS_DIRECT(mr, is_write) true
3426 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3427 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3428 #define RCU_READ_LOCK() rcu_read_lock()
3429 #define RCU_READ_UNLOCK() rcu_read_unlock()
3430 #include "memory_ldst.inc.c"
3432 /* virtual memory access for debug (includes writing to ROM) */
3433 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3434 uint8_t *buf, int len, int is_write)
3436 int l;
3437 hwaddr phys_addr;
3438 target_ulong page;
3440 cpu_synchronize_state(cpu);
3441 while (len > 0) {
3442 int asidx;
3443 MemTxAttrs attrs;
3445 page = addr & TARGET_PAGE_MASK;
3446 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3447 asidx = cpu_asidx_from_attrs(cpu, attrs);
3448 /* if no physical page mapped, return an error */
3449 if (phys_addr == -1)
3450 return -1;
3451 l = (page + TARGET_PAGE_SIZE) - addr;
3452 if (l > len)
3453 l = len;
3454 phys_addr += (addr & ~TARGET_PAGE_MASK);
3455 if (is_write) {
3456 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3457 phys_addr, buf, l);
3458 } else {
3459 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3460 MEMTXATTRS_UNSPECIFIED,
3461 buf, l, 0);
3463 len -= l;
3464 buf += l;
3465 addr += l;
3467 return 0;
3471 * Allows code that needs to deal with migration bitmaps etc to still be built
3472 * target independent.
3474 size_t qemu_target_page_size(void)
3476 return TARGET_PAGE_SIZE;
3479 int qemu_target_page_bits(void)
3481 return TARGET_PAGE_BITS;
3484 int qemu_target_page_bits_min(void)
3486 return TARGET_PAGE_BITS_MIN;
3488 #endif
3491 * A helper function for the _utterly broken_ virtio device model to find out if
3492 * it's running on a big endian machine. Don't do this at home kids!
3494 bool target_words_bigendian(void);
3495 bool target_words_bigendian(void)
3497 #if defined(TARGET_WORDS_BIGENDIAN)
3498 return true;
3499 #else
3500 return false;
3501 #endif
3504 #ifndef CONFIG_USER_ONLY
3505 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3507 MemoryRegion*mr;
3508 hwaddr l = 1;
3509 bool res;
3511 rcu_read_lock();
3512 mr = address_space_translate(&address_space_memory,
3513 phys_addr, &phys_addr, &l, false);
3515 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3516 rcu_read_unlock();
3517 return res;
3520 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3522 RAMBlock *block;
3523 int ret = 0;
3525 rcu_read_lock();
3526 RAMBLOCK_FOREACH(block) {
3527 ret = func(block->idstr, block->host, block->offset,
3528 block->used_length, opaque);
3529 if (ret) {
3530 break;
3533 rcu_read_unlock();
3534 return ret;
3538 * Unmap pages of memory from start to start+length such that
3539 * they a) read as 0, b) Trigger whatever fault mechanism
3540 * the OS provides for postcopy.
3541 * The pages must be unmapped by the end of the function.
3542 * Returns: 0 on success, none-0 on failure
3545 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3547 int ret = -1;
3549 uint8_t *host_startaddr = rb->host + start;
3551 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3552 error_report("ram_block_discard_range: Unaligned start address: %p",
3553 host_startaddr);
3554 goto err;
3557 if ((start + length) <= rb->used_length) {
3558 uint8_t *host_endaddr = host_startaddr + length;
3559 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3560 error_report("ram_block_discard_range: Unaligned end address: %p",
3561 host_endaddr);
3562 goto err;
3565 errno = ENOTSUP; /* If we are missing MADVISE etc */
3567 if (rb->page_size == qemu_host_page_size) {
3568 #if defined(CONFIG_MADVISE)
3569 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3570 * freeing the page.
3572 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3573 #endif
3574 } else {
3575 /* Huge page case - unfortunately it can't do DONTNEED, but
3576 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3577 * huge page file.
3579 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3580 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3581 start, length);
3582 #endif
3584 if (ret) {
3585 ret = -errno;
3586 error_report("ram_block_discard_range: Failed to discard range "
3587 "%s:%" PRIx64 " +%zx (%d)",
3588 rb->idstr, start, length, ret);
3590 } else {
3591 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3592 "/%zx/" RAM_ADDR_FMT")",
3593 rb->idstr, start, length, rb->used_length);
3596 err:
3597 return ret;
3600 #endif
3602 void page_size_init(void)
3604 /* NOTE: we can always suppose that qemu_host_page_size >=
3605 TARGET_PAGE_SIZE */
3606 qemu_real_host_page_size = getpagesize();
3607 qemu_real_host_page_mask = -(intptr_t)qemu_real_host_page_size;
3608 if (qemu_host_page_size == 0) {
3609 qemu_host_page_size = qemu_real_host_page_size;
3611 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
3612 qemu_host_page_size = TARGET_PAGE_SIZE;
3614 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;