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migration/tls: extract migration_tls_client_create for common-use
[qemu/ar7.git] / target / i386 / cpu.c
blob3ffd877dd51f14576d9fb04605b777ce22e7a53b
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/hvf.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/xen.h"
33 #include "kvm_i386.h"
34 #include "sev_i386.h"
35
36 #include "qemu/error-report.h"
37 #include "qemu/module.h"
38 #include "qemu/option.h"
39 #include "qemu/config-file.h"
40 #include "qapi/error.h"
41 #include "qapi/qapi-visit-machine.h"
42 #include "qapi/qapi-visit-run-state.h"
43 #include "qapi/qmp/qdict.h"
44 #include "qapi/qmp/qerror.h"
45 #include "qapi/visitor.h"
46 #include "qom/qom-qobject.h"
47 #include "sysemu/arch_init.h"
48 #include "qapi/qapi-commands-machine-target.h"
49
50 #include "standard-headers/asm-x86/kvm_para.h"
51
52 #include "sysemu/sysemu.h"
53 #include "sysemu/tcg.h"
54 #include "hw/qdev-properties.h"
55 #include "hw/i386/topology.h"
56 #ifndef CONFIG_USER_ONLY
57 #include "exec/address-spaces.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
60 #endif
61
62 #include "disas/capstone.h"
63
64 /* Helpers for building CPUID[2] descriptors: */
65
66 struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72 };
73
74 /*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82 .associativity = 4, .line_size = 32, },
83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84 .associativity = 4, .line_size = 64, },
85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86 .associativity = 2, .line_size = 32, },
87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 32, },
89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90 .associativity = 4, .line_size = 64, },
91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92 .associativity = 6, .line_size = 64, },
93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94 .associativity = 2, .line_size = 64, },
95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
108 .associativity = 8, .line_size = 64, },
109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
114 .associativity = 4, .line_size = 32, },
115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
118 .associativity = 4, .line_size = 32, },
119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
120 .associativity = 4, .line_size = 64, },
121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
122 .associativity = 8, .line_size = 64, },
123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
131 .associativity = 12, .line_size = 64, },
132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
133 .associativity = 16, .line_size = 64, },
134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
135 .associativity = 24, .line_size = 64, },
136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 8, .line_size = 64, },
138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
143 .associativity = 4, .line_size = 64, },
144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
150 .associativity = 8, .line_size = 64, },
151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 2, .line_size = 64, },
153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 64, },
155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 .associativity = 8, .line_size = 32, },
159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 .associativity = 8, .line_size = 32, },
163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 8, .line_size = 64, },
167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 4, .line_size = 64, },
173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 .associativity = 8, .line_size = 64, },
179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
184 .associativity = 12, .line_size = 64, },
185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
190 .associativity = 16, .line_size = 64, },
191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
194 .associativity = 24, .line_size = 64, },
195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
196 .associativity = 24, .line_size = 64, },
197 };
198
199 /*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
204
205 /*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 {
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
225
226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227 }
228
229 /* CPUID Leaf 4 constants: */
230
231 /* EAX: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
235
236 #define CACHE_LEVEL(l) (l << 5)
237
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
239
240 /* EDX: */
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
244
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
250
251
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257 {
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283 }
284
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287 {
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294 }
295
296 #define ASSOC_FULL 0xFF
297
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
312 /*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319 {
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339 }
340
341 /* Encode cache info for CPUID[8000001D] */
342 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
343 X86CPUTopoInfo *topo_info,
344 uint32_t *eax, uint32_t *ebx,
345 uint32_t *ecx, uint32_t *edx)
346 {
347 uint32_t l3_threads;
348 assert(cache->size == cache->line_size * cache->associativity *
349 cache->partitions * cache->sets);
350
351 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
352 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
353
354 /* L3 is shared among multiple cores */
355 if (cache->level == 3) {
356 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
357 *eax |= (l3_threads - 1) << 14;
358 } else {
359 *eax |= ((topo_info->threads_per_core - 1) << 14);
360 }
361
362 assert(cache->line_size > 0);
363 assert(cache->partitions > 0);
364 assert(cache->associativity > 0);
365 /* We don't implement fully-associative caches */
366 assert(cache->associativity < cache->sets);
367 *ebx = (cache->line_size - 1) |
368 ((cache->partitions - 1) << 12) |
369 ((cache->associativity - 1) << 22);
370
371 assert(cache->sets > 0);
372 *ecx = cache->sets - 1;
373
374 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
375 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
376 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
377 }
378
379 /* Encode cache info for CPUID[8000001E] */
380 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
381 uint32_t *eax, uint32_t *ebx,
382 uint32_t *ecx, uint32_t *edx)
383 {
384 X86CPUTopoIDs topo_ids;
385
386 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
387
388 *eax = cpu->apic_id;
389
390 /*
391 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
392 * Read-only. Reset: 0000_XXXXh.
393 * See Core::X86::Cpuid::ExtApicId.
394 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
395 * Bits Description
396 * 31:16 Reserved.
397 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
398 * The number of threads per core is ThreadsPerCore+1.
399 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
400 *
401 * NOTE: CoreId is already part of apic_id. Just use it. We can
402 * use all the 8 bits to represent the core_id here.
403 */
404 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
405
406 /*
407 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
408 * Read-only. Reset: 0000_0XXXh.
409 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
410 * Bits Description
411 * 31:11 Reserved.
412 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
413 * ValidValues:
414 * Value Description
415 * 000b 1 node per processor.
416 * 001b 2 nodes per processor.
417 * 010b Reserved.
418 * 011b 4 nodes per processor.
419 * 111b-100b Reserved.
420 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
421 *
422 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
423 * But users can create more nodes than the actual hardware can
424 * support. To genaralize we can use all the upper 8 bits for nodes.
425 * NodeId is combination of node and socket_id which is already decoded
426 * in apic_id. Just use it by shifting.
427 */
428 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
429 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
430
431 *edx = 0;
432 }
433
434 /*
435 * Definitions of the hardcoded cache entries we expose:
436 * These are legacy cache values. If there is a need to change any
437 * of these values please use builtin_x86_defs
438 */
439
440 /* L1 data cache: */
441 static CPUCacheInfo legacy_l1d_cache = {
442 .type = DATA_CACHE,
443 .level = 1,
444 .size = 32 * KiB,
445 .self_init = 1,
446 .line_size = 64,
447 .associativity = 8,
448 .sets = 64,
449 .partitions = 1,
450 .no_invd_sharing = true,
451 };
452
453 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
454 static CPUCacheInfo legacy_l1d_cache_amd = {
455 .type = DATA_CACHE,
456 .level = 1,
457 .size = 64 * KiB,
458 .self_init = 1,
459 .line_size = 64,
460 .associativity = 2,
461 .sets = 512,
462 .partitions = 1,
463 .lines_per_tag = 1,
464 .no_invd_sharing = true,
465 };
466
467 /* L1 instruction cache: */
468 static CPUCacheInfo legacy_l1i_cache = {
469 .type = INSTRUCTION_CACHE,
470 .level = 1,
471 .size = 32 * KiB,
472 .self_init = 1,
473 .line_size = 64,
474 .associativity = 8,
475 .sets = 64,
476 .partitions = 1,
477 .no_invd_sharing = true,
478 };
479
480 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
481 static CPUCacheInfo legacy_l1i_cache_amd = {
482 .type = INSTRUCTION_CACHE,
483 .level = 1,
484 .size = 64 * KiB,
485 .self_init = 1,
486 .line_size = 64,
487 .associativity = 2,
488 .sets = 512,
489 .partitions = 1,
490 .lines_per_tag = 1,
491 .no_invd_sharing = true,
492 };
493
494 /* Level 2 unified cache: */
495 static CPUCacheInfo legacy_l2_cache = {
496 .type = UNIFIED_CACHE,
497 .level = 2,
498 .size = 4 * MiB,
499 .self_init = 1,
500 .line_size = 64,
501 .associativity = 16,
502 .sets = 4096,
503 .partitions = 1,
504 .no_invd_sharing = true,
505 };
506
507 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
508 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
509 .type = UNIFIED_CACHE,
510 .level = 2,
511 .size = 2 * MiB,
512 .line_size = 64,
513 .associativity = 8,
514 };
515
516
517 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
518 static CPUCacheInfo legacy_l2_cache_amd = {
519 .type = UNIFIED_CACHE,
520 .level = 2,
521 .size = 512 * KiB,
522 .line_size = 64,
523 .lines_per_tag = 1,
524 .associativity = 16,
525 .sets = 512,
526 .partitions = 1,
527 };
528
529 /* Level 3 unified cache: */
530 static CPUCacheInfo legacy_l3_cache = {
531 .type = UNIFIED_CACHE,
532 .level = 3,
533 .size = 16 * MiB,
534 .line_size = 64,
535 .associativity = 16,
536 .sets = 16384,
537 .partitions = 1,
538 .lines_per_tag = 1,
539 .self_init = true,
540 .inclusive = true,
541 .complex_indexing = true,
542 };
543
544 /* TLB definitions: */
545
546 #define L1_DTLB_2M_ASSOC 1
547 #define L1_DTLB_2M_ENTRIES 255
548 #define L1_DTLB_4K_ASSOC 1
549 #define L1_DTLB_4K_ENTRIES 255
550
551 #define L1_ITLB_2M_ASSOC 1
552 #define L1_ITLB_2M_ENTRIES 255
553 #define L1_ITLB_4K_ASSOC 1
554 #define L1_ITLB_4K_ENTRIES 255
555
556 #define L2_DTLB_2M_ASSOC 0 /* disabled */
557 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
558 #define L2_DTLB_4K_ASSOC 4
559 #define L2_DTLB_4K_ENTRIES 512
560
561 #define L2_ITLB_2M_ASSOC 0 /* disabled */
562 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
563 #define L2_ITLB_4K_ASSOC 4
564 #define L2_ITLB_4K_ENTRIES 512
565
566 /* CPUID Leaf 0x14 constants: */
567 #define INTEL_PT_MAX_SUBLEAF 0x1
568 /*
569 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
570 * MSR can be accessed;
571 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
572 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
573 * of Intel PT MSRs across warm reset;
574 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
575 */
576 #define INTEL_PT_MINIMAL_EBX 0xf
577 /*
578 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
579 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
580 * accessed;
581 * bit[01]: ToPA tables can hold any number of output entries, up to the
582 * maximum allowed by the MaskOrTableOffset field of
583 * IA32_RTIT_OUTPUT_MASK_PTRS;
584 * bit[02]: Support Single-Range Output scheme;
585 */
586 #define INTEL_PT_MINIMAL_ECX 0x7
587 /* generated packets which contain IP payloads have LIP values */
588 #define INTEL_PT_IP_LIP (1 << 31)
589 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
590 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
591 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
592 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
593 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
594
595 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
596 uint32_t vendor2, uint32_t vendor3)
597 {
598 int i;
599 for (i = 0; i < 4; i++) {
600 dst[i] = vendor1 >> (8 * i);
601 dst[i + 4] = vendor2 >> (8 * i);
602 dst[i + 8] = vendor3 >> (8 * i);
603 }
604 dst[CPUID_VENDOR_SZ] = '\0';
605 }
606
607 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
608 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
609 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
610 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
611 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
612 CPUID_PSE36 | CPUID_FXSR)
613 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
614 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
615 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
616 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
617 CPUID_PAE | CPUID_SEP | CPUID_APIC)
618
619 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
620 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
621 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
622 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
623 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
624 /* partly implemented:
625 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
626 /* missing:
627 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
628 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
629 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
630 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
631 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
632 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
633 CPUID_EXT_RDRAND)
634 /* missing:
635 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
636 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
637 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
638 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
639 CPUID_EXT_F16C */
640
641 #ifdef TARGET_X86_64
642 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
643 #else
644 #define TCG_EXT2_X86_64_FEATURES 0
645 #endif
646
647 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
648 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
649 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
650 TCG_EXT2_X86_64_FEATURES)
651 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
652 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
653 #define TCG_EXT4_FEATURES 0
654 #define TCG_SVM_FEATURES CPUID_SVM_NPT
655 #define TCG_KVM_FEATURES 0
656 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
657 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
658 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
659 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
660 CPUID_7_0_EBX_ERMS)
661 /* missing:
662 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
663 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
664 CPUID_7_0_EBX_RDSEED */
665 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
666 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
667 CPUID_7_0_ECX_LA57)
668 #define TCG_7_0_EDX_FEATURES 0
669 #define TCG_7_1_EAX_FEATURES 0
670 #define TCG_APM_FEATURES 0
671 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
672 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
673 /* missing:
674 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
675
676 typedef enum FeatureWordType {
677 CPUID_FEATURE_WORD,
678 MSR_FEATURE_WORD,
679 } FeatureWordType;
680
681 typedef struct FeatureWordInfo {
682 FeatureWordType type;
683 /* feature flags names are taken from "Intel Processor Identification and
684 * the CPUID Instruction" and AMD's "CPUID Specification".
685 * In cases of disagreement between feature naming conventions,
686 * aliases may be added.
687 */
688 const char *feat_names[64];
689 union {
690 /* If type==CPUID_FEATURE_WORD */
691 struct {
692 uint32_t eax; /* Input EAX for CPUID */
693 bool needs_ecx; /* CPUID instruction uses ECX as input */
694 uint32_t ecx; /* Input ECX value for CPUID */
695 int reg; /* output register (R_* constant) */
696 } cpuid;
697 /* If type==MSR_FEATURE_WORD */
698 struct {
699 uint32_t index;
700 } msr;
701 };
702 uint64_t tcg_features; /* Feature flags supported by TCG */
703 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
704 uint64_t migratable_flags; /* Feature flags known to be migratable */
705 /* Features that shouldn't be auto-enabled by "-cpu host" */
706 uint64_t no_autoenable_flags;
707 } FeatureWordInfo;
708
709 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
710 [FEAT_1_EDX] = {
711 .type = CPUID_FEATURE_WORD,
712 .feat_names = {
713 "fpu", "vme", "de", "pse",
714 "tsc", "msr", "pae", "mce",
715 "cx8", "apic", NULL, "sep",
716 "mtrr", "pge", "mca", "cmov",
717 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
718 NULL, "ds" /* Intel dts */, "acpi", "mmx",
719 "fxsr", "sse", "sse2", "ss",
720 "ht" /* Intel htt */, "tm", "ia64", "pbe",
721 },
722 .cpuid = {.eax = 1, .reg = R_EDX, },
723 .tcg_features = TCG_FEATURES,
724 },
725 [FEAT_1_ECX] = {
726 .type = CPUID_FEATURE_WORD,
727 .feat_names = {
728 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
729 "ds-cpl", "vmx", "smx", "est",
730 "tm2", "ssse3", "cid", NULL,
731 "fma", "cx16", "xtpr", "pdcm",
732 NULL, "pcid", "dca", "sse4.1",
733 "sse4.2", "x2apic", "movbe", "popcnt",
734 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
735 "avx", "f16c", "rdrand", "hypervisor",
736 },
737 .cpuid = { .eax = 1, .reg = R_ECX, },
738 .tcg_features = TCG_EXT_FEATURES,
739 },
740 /* Feature names that are already defined on feature_name[] but
741 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
742 * names on feat_names below. They are copied automatically
743 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
744 */
745 [FEAT_8000_0001_EDX] = {
746 .type = CPUID_FEATURE_WORD,
747 .feat_names = {
748 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
749 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
750 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
751 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
752 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
753 "nx", NULL, "mmxext", NULL /* mmx */,
754 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
755 NULL, "lm", "3dnowext", "3dnow",
756 },
757 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
758 .tcg_features = TCG_EXT2_FEATURES,
759 },
760 [FEAT_8000_0001_ECX] = {
761 .type = CPUID_FEATURE_WORD,
762 .feat_names = {
763 "lahf-lm", "cmp-legacy", "svm", "extapic",
764 "cr8legacy", "abm", "sse4a", "misalignsse",
765 "3dnowprefetch", "osvw", "ibs", "xop",
766 "skinit", "wdt", NULL, "lwp",
767 "fma4", "tce", NULL, "nodeid-msr",
768 NULL, "tbm", "topoext", "perfctr-core",
769 "perfctr-nb", NULL, NULL, NULL,
770 NULL, NULL, NULL, NULL,
771 },
772 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
773 .tcg_features = TCG_EXT3_FEATURES,
774 /*
775 * TOPOEXT is always allowed but can't be enabled blindly by
776 * "-cpu host", as it requires consistent cache topology info
777 * to be provided so it doesn't confuse guests.
778 */
779 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
780 },
781 [FEAT_C000_0001_EDX] = {
782 .type = CPUID_FEATURE_WORD,
783 .feat_names = {
784 NULL, NULL, "xstore", "xstore-en",
785 NULL, NULL, "xcrypt", "xcrypt-en",
786 "ace2", "ace2-en", "phe", "phe-en",
787 "pmm", "pmm-en", NULL, NULL,
788 NULL, NULL, NULL, NULL,
789 NULL, NULL, NULL, NULL,
790 NULL, NULL, NULL, NULL,
791 NULL, NULL, NULL, NULL,
792 },
793 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
794 .tcg_features = TCG_EXT4_FEATURES,
795 },
796 [FEAT_KVM] = {
797 .type = CPUID_FEATURE_WORD,
798 .feat_names = {
799 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
800 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
801 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
802 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL,
803 NULL, NULL, NULL, NULL,
804 NULL, NULL, NULL, NULL,
805 "kvmclock-stable-bit", NULL, NULL, NULL,
806 NULL, NULL, NULL, NULL,
807 },
808 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
809 .tcg_features = TCG_KVM_FEATURES,
810 },
811 [FEAT_KVM_HINTS] = {
812 .type = CPUID_FEATURE_WORD,
813 .feat_names = {
814 "kvm-hint-dedicated", NULL, NULL, NULL,
815 NULL, NULL, NULL, NULL,
816 NULL, NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 NULL, NULL, NULL, NULL,
819 NULL, NULL, NULL, NULL,
820 NULL, NULL, NULL, NULL,
821 NULL, NULL, NULL, NULL,
822 },
823 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
824 .tcg_features = TCG_KVM_FEATURES,
825 /*
826 * KVM hints aren't auto-enabled by -cpu host, they need to be
827 * explicitly enabled in the command-line.
828 */
829 .no_autoenable_flags = ~0U,
830 },
831 /*
832 * .feat_names are commented out for Hyper-V enlightenments because we
833 * don't want to have two different ways for enabling them on QEMU command
834 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
835 * enabling several feature bits simultaneously, exposing these bits
836 * individually may just confuse guests.
837 */
838 [FEAT_HYPERV_EAX] = {
839 .type = CPUID_FEATURE_WORD,
840 .feat_names = {
841 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
842 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
843 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
844 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
845 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
846 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
847 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
848 NULL, NULL,
849 NULL, NULL, NULL, NULL,
850 NULL, NULL, NULL, NULL,
851 NULL, NULL, NULL, NULL,
852 NULL, NULL, NULL, NULL,
853 },
854 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
855 },
856 [FEAT_HYPERV_EBX] = {
857 .type = CPUID_FEATURE_WORD,
858 .feat_names = {
859 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
860 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
861 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
862 NULL /* hv_create_port */, NULL /* hv_connect_port */,
863 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
864 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
865 NULL, NULL,
866 NULL, NULL, NULL, NULL,
867 NULL, NULL, NULL, NULL,
868 NULL, NULL, NULL, NULL,
869 NULL, NULL, NULL, NULL,
870 },
871 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
872 },
873 [FEAT_HYPERV_EDX] = {
874 .type = CPUID_FEATURE_WORD,
875 .feat_names = {
876 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
877 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
878 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
879 NULL, NULL,
880 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
881 NULL, NULL, NULL, NULL,
882 NULL, NULL, NULL, NULL,
883 NULL, NULL, NULL, NULL,
884 NULL, NULL, NULL, NULL,
885 NULL, NULL, NULL, NULL,
886 },
887 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
888 },
889 [FEAT_HV_RECOMM_EAX] = {
890 .type = CPUID_FEATURE_WORD,
891 .feat_names = {
892 NULL /* hv_recommend_pv_as_switch */,
893 NULL /* hv_recommend_pv_tlbflush_local */,
894 NULL /* hv_recommend_pv_tlbflush_remote */,
895 NULL /* hv_recommend_msr_apic_access */,
896 NULL /* hv_recommend_msr_reset */,
897 NULL /* hv_recommend_relaxed_timing */,
898 NULL /* hv_recommend_dma_remapping */,
899 NULL /* hv_recommend_int_remapping */,
900 NULL /* hv_recommend_x2apic_msrs */,
901 NULL /* hv_recommend_autoeoi_deprecation */,
902 NULL /* hv_recommend_pv_ipi */,
903 NULL /* hv_recommend_ex_hypercalls */,
904 NULL /* hv_hypervisor_is_nested */,
905 NULL /* hv_recommend_int_mbec */,
906 NULL /* hv_recommend_evmcs */,
907 NULL,
908 NULL, NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 NULL, NULL, NULL, NULL,
912 },
913 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
914 },
915 [FEAT_HV_NESTED_EAX] = {
916 .type = CPUID_FEATURE_WORD,
917 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
918 },
919 [FEAT_SVM] = {
920 .type = CPUID_FEATURE_WORD,
921 .feat_names = {
922 "npt", "lbrv", "svm-lock", "nrip-save",
923 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
924 NULL, NULL, "pause-filter", NULL,
925 "pfthreshold", NULL, NULL, NULL,
926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 NULL, NULL, NULL, NULL,
930 },
931 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
932 .tcg_features = TCG_SVM_FEATURES,
933 },
934 [FEAT_7_0_EBX] = {
935 .type = CPUID_FEATURE_WORD,
936 .feat_names = {
937 "fsgsbase", "tsc-adjust", NULL, "bmi1",
938 "hle", "avx2", NULL, "smep",
939 "bmi2", "erms", "invpcid", "rtm",
940 NULL, NULL, "mpx", NULL,
941 "avx512f", "avx512dq", "rdseed", "adx",
942 "smap", "avx512ifma", "pcommit", "clflushopt",
943 "clwb", "intel-pt", "avx512pf", "avx512er",
944 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
945 },
946 .cpuid = {
947 .eax = 7,
948 .needs_ecx = true, .ecx = 0,
949 .reg = R_EBX,
950 },
951 .tcg_features = TCG_7_0_EBX_FEATURES,
952 },
953 [FEAT_7_0_ECX] = {
954 .type = CPUID_FEATURE_WORD,
955 .feat_names = {
956 NULL, "avx512vbmi", "umip", "pku",
957 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
958 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
959 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
960 "la57", NULL, NULL, NULL,
961 NULL, NULL, "rdpid", NULL,
962 NULL, "cldemote", NULL, "movdiri",
963 "movdir64b", NULL, NULL, NULL,
964 },
965 .cpuid = {
966 .eax = 7,
967 .needs_ecx = true, .ecx = 0,
968 .reg = R_ECX,
969 },
970 .tcg_features = TCG_7_0_ECX_FEATURES,
971 },
972 [FEAT_7_0_EDX] = {
973 .type = CPUID_FEATURE_WORD,
974 .feat_names = {
975 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
976 "fsrm", NULL, NULL, NULL,
977 "avx512-vp2intersect", NULL, "md-clear", NULL,
978 NULL, NULL, "serialize", NULL,
979 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
980 NULL, NULL, NULL, NULL,
981 NULL, NULL, "spec-ctrl", "stibp",
982 NULL, "arch-capabilities", "core-capability", "ssbd",
983 },
984 .cpuid = {
985 .eax = 7,
986 .needs_ecx = true, .ecx = 0,
987 .reg = R_EDX,
988 },
989 .tcg_features = TCG_7_0_EDX_FEATURES,
990 },
991 [FEAT_7_1_EAX] = {
992 .type = CPUID_FEATURE_WORD,
993 .feat_names = {
994 NULL, NULL, NULL, NULL,
995 NULL, "avx512-bf16", NULL, NULL,
996 NULL, NULL, NULL, NULL,
997 NULL, NULL, NULL, NULL,
998 NULL, NULL, NULL, NULL,
999 NULL, NULL, NULL, NULL,
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 },
1003 .cpuid = {
1004 .eax = 7,
1005 .needs_ecx = true, .ecx = 1,
1006 .reg = R_EAX,
1007 },
1008 .tcg_features = TCG_7_1_EAX_FEATURES,
1009 },
1010 [FEAT_8000_0007_EDX] = {
1011 .type = CPUID_FEATURE_WORD,
1012 .feat_names = {
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 "invtsc", NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL,
1017 NULL, NULL, NULL, NULL,
1018 NULL, NULL, NULL, NULL,
1019 NULL, NULL, NULL, NULL,
1020 NULL, NULL, NULL, NULL,
1021 },
1022 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1023 .tcg_features = TCG_APM_FEATURES,
1024 .unmigratable_flags = CPUID_APM_INVTSC,
1025 },
1026 [FEAT_8000_0008_EBX] = {
1027 .type = CPUID_FEATURE_WORD,
1028 .feat_names = {
1029 "clzero", NULL, "xsaveerptr", NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, "wbnoinvd", NULL, NULL,
1032 "ibpb", NULL, NULL, "amd-stibp",
1033 NULL, NULL, NULL, NULL,
1034 NULL, NULL, NULL, NULL,
1035 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1036 NULL, NULL, NULL, NULL,
1037 },
1038 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1039 .tcg_features = 0,
1040 .unmigratable_flags = 0,
1041 },
1042 [FEAT_XSAVE] = {
1043 .type = CPUID_FEATURE_WORD,
1044 .feat_names = {
1045 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1046 NULL, NULL, NULL, NULL,
1047 NULL, NULL, NULL, NULL,
1048 NULL, NULL, NULL, NULL,
1049 NULL, NULL, NULL, NULL,
1050 NULL, NULL, NULL, NULL,
1051 NULL, NULL, NULL, NULL,
1052 NULL, NULL, NULL, NULL,
1053 },
1054 .cpuid = {
1055 .eax = 0xd,
1056 .needs_ecx = true, .ecx = 1,
1057 .reg = R_EAX,
1058 },
1059 .tcg_features = TCG_XSAVE_FEATURES,
1060 },
1061 [FEAT_6_EAX] = {
1062 .type = CPUID_FEATURE_WORD,
1063 .feat_names = {
1064 NULL, NULL, "arat", NULL,
1065 NULL, NULL, NULL, NULL,
1066 NULL, NULL, NULL, NULL,
1067 NULL, NULL, NULL, NULL,
1068 NULL, NULL, NULL, NULL,
1069 NULL, NULL, NULL, NULL,
1070 NULL, NULL, NULL, NULL,
1071 NULL, NULL, NULL, NULL,
1072 },
1073 .cpuid = { .eax = 6, .reg = R_EAX, },
1074 .tcg_features = TCG_6_EAX_FEATURES,
1075 },
1076 [FEAT_XSAVE_COMP_LO] = {
1077 .type = CPUID_FEATURE_WORD,
1078 .cpuid = {
1079 .eax = 0xD,
1080 .needs_ecx = true, .ecx = 0,
1081 .reg = R_EAX,
1082 },
1083 .tcg_features = ~0U,
1084 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1085 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1086 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1087 XSTATE_PKRU_MASK,
1088 },
1089 [FEAT_XSAVE_COMP_HI] = {
1090 .type = CPUID_FEATURE_WORD,
1091 .cpuid = {
1092 .eax = 0xD,
1093 .needs_ecx = true, .ecx = 0,
1094 .reg = R_EDX,
1095 },
1096 .tcg_features = ~0U,
1097 },
1098 /*Below are MSR exposed features*/
1099 [FEAT_ARCH_CAPABILITIES] = {
1100 .type = MSR_FEATURE_WORD,
1101 .feat_names = {
1102 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1103 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1104 "taa-no", NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL,
1108 NULL, NULL, NULL, NULL,
1109 NULL, NULL, NULL, NULL,
1110 },
1111 .msr = {
1112 .index = MSR_IA32_ARCH_CAPABILITIES,
1113 },
1114 },
1115 [FEAT_CORE_CAPABILITY] = {
1116 .type = MSR_FEATURE_WORD,
1117 .feat_names = {
1118 NULL, NULL, NULL, NULL,
1119 NULL, "split-lock-detect", NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 NULL, NULL, NULL, NULL,
1126 },
1127 .msr = {
1128 .index = MSR_IA32_CORE_CAPABILITY,
1129 },
1130 },
1131 [FEAT_PERF_CAPABILITIES] = {
1132 .type = MSR_FEATURE_WORD,
1133 .feat_names = {
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, "full-width-write", NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL,
1141 NULL, NULL, NULL, NULL,
1142 },
1143 .msr = {
1144 .index = MSR_IA32_PERF_CAPABILITIES,
1145 },
1146 },
1147
1148 [FEAT_VMX_PROCBASED_CTLS] = {
1149 .type = MSR_FEATURE_WORD,
1150 .feat_names = {
1151 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1152 NULL, NULL, NULL, "vmx-hlt-exit",
1153 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1154 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1155 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1156 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1157 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1158 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1159 },
1160 .msr = {
1161 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1162 }
1163 },
1164
1165 [FEAT_VMX_SECONDARY_CTLS] = {
1166 .type = MSR_FEATURE_WORD,
1167 .feat_names = {
1168 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1169 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1170 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1171 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1172 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1173 "vmx-xsaves", NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 NULL, NULL, NULL, NULL,
1176 },
1177 .msr = {
1178 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1179 }
1180 },
1181
1182 [FEAT_VMX_PINBASED_CTLS] = {
1183 .type = MSR_FEATURE_WORD,
1184 .feat_names = {
1185 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1186 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1187 NULL, NULL, NULL, NULL,
1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 },
1194 .msr = {
1195 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1196 }
1197 },
1198
1199 [FEAT_VMX_EXIT_CTLS] = {
1200 .type = MSR_FEATURE_WORD,
1201 /*
1202 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1203 * the LM CPUID bit.
1204 */
1205 .feat_names = {
1206 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1207 NULL, NULL, NULL, NULL,
1208 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1209 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1210 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1211 "vmx-exit-save-efer", "vmx-exit-load-efer",
1212 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1213 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1214 NULL, NULL, NULL, NULL,
1215 },
1216 .msr = {
1217 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 }
1219 },
1220
1221 [FEAT_VMX_ENTRY_CTLS] = {
1222 .type = MSR_FEATURE_WORD,
1223 .feat_names = {
1224 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1225 NULL, NULL, NULL, NULL,
1226 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1227 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1228 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1229 NULL, NULL, NULL, NULL,
1230 NULL, NULL, NULL, NULL,
1231 NULL, NULL, NULL, NULL,
1232 },
1233 .msr = {
1234 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1235 }
1236 },
1237
1238 [FEAT_VMX_MISC] = {
1239 .type = MSR_FEATURE_WORD,
1240 .feat_names = {
1241 NULL, NULL, NULL, NULL,
1242 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1243 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1244 NULL, NULL, NULL, NULL,
1245 NULL, NULL, NULL, NULL,
1246 NULL, NULL, NULL, NULL,
1247 NULL, NULL, NULL, NULL,
1248 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1249 },
1250 .msr = {
1251 .index = MSR_IA32_VMX_MISC,
1252 }
1253 },
1254
1255 [FEAT_VMX_EPT_VPID_CAPS] = {
1256 .type = MSR_FEATURE_WORD,
1257 .feat_names = {
1258 "vmx-ept-execonly", NULL, NULL, NULL,
1259 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1260 NULL, NULL, NULL, NULL,
1261 NULL, NULL, NULL, NULL,
1262 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1263 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1264 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1265 NULL, NULL, NULL, NULL,
1266 "vmx-invvpid", NULL, NULL, NULL,
1267 NULL, NULL, NULL, NULL,
1268 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1269 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1270 NULL, NULL, NULL, NULL,
1271 NULL, NULL, NULL, NULL,
1272 NULL, NULL, NULL, NULL,
1273 NULL, NULL, NULL, NULL,
1274 NULL, NULL, NULL, NULL,
1275 },
1276 .msr = {
1277 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1278 }
1279 },
1280
1281 [FEAT_VMX_BASIC] = {
1282 .type = MSR_FEATURE_WORD,
1283 .feat_names = {
1284 [54] = "vmx-ins-outs",
1285 [55] = "vmx-true-ctls",
1286 },
1287 .msr = {
1288 .index = MSR_IA32_VMX_BASIC,
1289 },
1290 /* Just to be safe - we don't support setting the MSEG version field. */
1291 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1292 },
1293
1294 [FEAT_VMX_VMFUNC] = {
1295 .type = MSR_FEATURE_WORD,
1296 .feat_names = {
1297 [0] = "vmx-eptp-switching",
1298 },
1299 .msr = {
1300 .index = MSR_IA32_VMX_VMFUNC,
1301 }
1302 },
1303
1304 };
1305
1306 typedef struct FeatureMask {
1307 FeatureWord index;
1308 uint64_t mask;
1309 } FeatureMask;
1310
1311 typedef struct FeatureDep {
1312 FeatureMask from, to;
1313 } FeatureDep;
1314
1315 static FeatureDep feature_dependencies[] = {
1316 {
1317 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1318 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1319 },
1320 {
1321 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1322 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1323 },
1324 {
1325 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1326 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1327 },
1328 {
1329 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1330 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1331 },
1332 {
1333 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1334 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1335 },
1336 {
1337 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1338 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1339 },
1340 {
1341 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1342 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1343 },
1344 {
1345 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1346 .to = { FEAT_VMX_MISC, ~0ull },
1347 },
1348 {
1349 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1350 .to = { FEAT_VMX_BASIC, ~0ull },
1351 },
1352 {
1353 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1354 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1355 },
1356 {
1357 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1358 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1359 },
1360 {
1361 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1362 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1363 },
1364 {
1365 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1366 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1367 },
1368 {
1369 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1370 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1371 },
1372 {
1373 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1374 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1375 },
1376 {
1377 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1378 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1379 },
1380 {
1381 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1382 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1383 },
1384 {
1385 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1386 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1387 },
1388 {
1389 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1390 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1391 },
1392 {
1393 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1394 .to = { FEAT_VMX_VMFUNC, ~0ull },
1395 },
1396 {
1397 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1398 .to = { FEAT_SVM, ~0ull },
1399 },
1400 };
1401
1402 typedef struct X86RegisterInfo32 {
1403 /* Name of register */
1404 const char *name;
1405 /* QAPI enum value register */
1406 X86CPURegister32 qapi_enum;
1407 } X86RegisterInfo32;
1408
1409 #define REGISTER(reg) \
1410 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1411 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1412 REGISTER(EAX),
1413 REGISTER(ECX),
1414 REGISTER(EDX),
1415 REGISTER(EBX),
1416 REGISTER(ESP),
1417 REGISTER(EBP),
1418 REGISTER(ESI),
1419 REGISTER(EDI),
1420 };
1421 #undef REGISTER
1422
1423 typedef struct ExtSaveArea {
1424 uint32_t feature, bits;
1425 uint32_t offset, size;
1426 } ExtSaveArea;
1427
1428 static const ExtSaveArea x86_ext_save_areas[] = {
1429 [XSTATE_FP_BIT] = {
1430 /* x87 FP state component is always enabled if XSAVE is supported */
1431 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1432 /* x87 state is in the legacy region of the XSAVE area */
1433 .offset = 0,
1434 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1435 },
1436 [XSTATE_SSE_BIT] = {
1437 /* SSE state component is always enabled if XSAVE is supported */
1438 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1439 /* SSE state is in the legacy region of the XSAVE area */
1440 .offset = 0,
1441 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1442 },
1443 [XSTATE_YMM_BIT] =
1444 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1445 .offset = offsetof(X86XSaveArea, avx_state),
1446 .size = sizeof(XSaveAVX) },
1447 [XSTATE_BNDREGS_BIT] =
1448 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1449 .offset = offsetof(X86XSaveArea, bndreg_state),
1450 .size = sizeof(XSaveBNDREG) },
1451 [XSTATE_BNDCSR_BIT] =
1452 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1453 .offset = offsetof(X86XSaveArea, bndcsr_state),
1454 .size = sizeof(XSaveBNDCSR) },
1455 [XSTATE_OPMASK_BIT] =
1456 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1457 .offset = offsetof(X86XSaveArea, opmask_state),
1458 .size = sizeof(XSaveOpmask) },
1459 [XSTATE_ZMM_Hi256_BIT] =
1460 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1461 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1462 .size = sizeof(XSaveZMM_Hi256) },
1463 [XSTATE_Hi16_ZMM_BIT] =
1464 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1465 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1466 .size = sizeof(XSaveHi16_ZMM) },
1467 [XSTATE_PKRU_BIT] =
1468 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1469 .offset = offsetof(X86XSaveArea, pkru_state),
1470 .size = sizeof(XSavePKRU) },
1471 };
1472
1473 static uint32_t xsave_area_size(uint64_t mask)
1474 {
1475 int i;
1476 uint64_t ret = 0;
1477
1478 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1479 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1480 if ((mask >> i) & 1) {
1481 ret = MAX(ret, esa->offset + esa->size);
1482 }
1483 }
1484 return ret;
1485 }
1486
1487 static inline bool accel_uses_host_cpuid(void)
1488 {
1489 return kvm_enabled() || hvf_enabled();
1490 }
1491
1492 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1493 {
1494 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1495 cpu->env.features[FEAT_XSAVE_COMP_LO];
1496 }
1497
1498 const char *get_register_name_32(unsigned int reg)
1499 {
1500 if (reg >= CPU_NB_REGS32) {
1501 return NULL;
1502 }
1503 return x86_reg_info_32[reg].name;
1504 }
1505
1506 /*
1507 * Returns the set of feature flags that are supported and migratable by
1508 * QEMU, for a given FeatureWord.
1509 */
1510 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1511 {
1512 FeatureWordInfo *wi = &feature_word_info[w];
1513 uint64_t r = 0;
1514 int i;
1515
1516 for (i = 0; i < 64; i++) {
1517 uint64_t f = 1ULL << i;
1518
1519 /* If the feature name is known, it is implicitly considered migratable,
1520 * unless it is explicitly set in unmigratable_flags */
1521 if ((wi->migratable_flags & f) ||
1522 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1523 r |= f;
1524 }
1525 }
1526 return r;
1527 }
1528
1529 void host_cpuid(uint32_t function, uint32_t count,
1530 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1531 {
1532 uint32_t vec[4];
1533
1534 #ifdef __x86_64__
1535 asm volatile("cpuid"
1536 : "=a"(vec[0]), "=b"(vec[1]),
1537 "=c"(vec[2]), "=d"(vec[3])
1538 : "0"(function), "c"(count) : "cc");
1539 #elif defined(__i386__)
1540 asm volatile("pusha \n\t"
1541 "cpuid \n\t"
1542 "mov %%eax, 0(%2) \n\t"
1543 "mov %%ebx, 4(%2) \n\t"
1544 "mov %%ecx, 8(%2) \n\t"
1545 "mov %%edx, 12(%2) \n\t"
1546 "popa"
1547 : : "a"(function), "c"(count), "S"(vec)
1548 : "memory", "cc");
1549 #else
1550 abort();
1551 #endif
1552
1553 if (eax)
1554 *eax = vec[0];
1555 if (ebx)
1556 *ebx = vec[1];
1557 if (ecx)
1558 *ecx = vec[2];
1559 if (edx)
1560 *edx = vec[3];
1561 }
1562
1563 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1564 {
1565 uint32_t eax, ebx, ecx, edx;
1566
1567 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1568 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1569
1570 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1571 if (family) {
1572 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1573 }
1574 if (model) {
1575 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1576 }
1577 if (stepping) {
1578 *stepping = eax & 0x0F;
1579 }
1580 }
1581
1582 /* CPU class name definitions: */
1583
1584 /* Return type name for a given CPU model name
1585 * Caller is responsible for freeing the returned string.
1586 */
1587 static char *x86_cpu_type_name(const char *model_name)
1588 {
1589 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1590 }
1591
1592 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1593 {
1594 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1595 return object_class_by_name(typename);
1596 }
1597
1598 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1599 {
1600 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1601 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1602 return g_strndup(class_name,
1603 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1604 }
1605
1606 typedef struct PropValue {
1607 const char *prop, *value;
1608 } PropValue;
1609
1610 typedef struct X86CPUVersionDefinition {
1611 X86CPUVersion version;
1612 const char *alias;
1613 const char *note;
1614 PropValue *props;
1615 } X86CPUVersionDefinition;
1616
1617 /* Base definition for a CPU model */
1618 typedef struct X86CPUDefinition {
1619 const char *name;
1620 uint32_t level;
1621 uint32_t xlevel;
1622 /* vendor is zero-terminated, 12 character ASCII string */
1623 char vendor[CPUID_VENDOR_SZ + 1];
1624 int family;
1625 int model;
1626 int stepping;
1627 FeatureWordArray features;
1628 const char *model_id;
1629 CPUCaches *cache_info;
1630 /*
1631 * Definitions for alternative versions of CPU model.
1632 * List is terminated by item with version == 0.
1633 * If NULL, version 1 will be registered automatically.
1634 */
1635 const X86CPUVersionDefinition *versions;
1636 } X86CPUDefinition;
1637
1638 /* Reference to a specific CPU model version */
1639 struct X86CPUModel {
1640 /* Base CPU definition */
1641 X86CPUDefinition *cpudef;
1642 /* CPU model version */
1643 X86CPUVersion version;
1644 const char *note;
1645 /*
1646 * If true, this is an alias CPU model.
1647 * This matters only for "-cpu help" and query-cpu-definitions
1648 */
1649 bool is_alias;
1650 };
1651
1652 /* Get full model name for CPU version */
1653 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1654 X86CPUVersion version)
1655 {
1656 assert(version > 0);
1657 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1658 }
1659
1660 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1661 {
1662 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1663 static const X86CPUVersionDefinition default_version_list[] = {
1664 { 1 },
1665 { /* end of list */ }
1666 };
1667
1668 return def->versions ?: default_version_list;
1669 }
1670
1671 static CPUCaches epyc_cache_info = {
1672 .l1d_cache = &(CPUCacheInfo) {
1673 .type = DATA_CACHE,
1674 .level = 1,
1675 .size = 32 * KiB,
1676 .line_size = 64,
1677 .associativity = 8,
1678 .partitions = 1,
1679 .sets = 64,
1680 .lines_per_tag = 1,
1681 .self_init = 1,
1682 .no_invd_sharing = true,
1683 },
1684 .l1i_cache = &(CPUCacheInfo) {
1685 .type = INSTRUCTION_CACHE,
1686 .level = 1,
1687 .size = 64 * KiB,
1688 .line_size = 64,
1689 .associativity = 4,
1690 .partitions = 1,
1691 .sets = 256,
1692 .lines_per_tag = 1,
1693 .self_init = 1,
1694 .no_invd_sharing = true,
1695 },
1696 .l2_cache = &(CPUCacheInfo) {
1697 .type = UNIFIED_CACHE,
1698 .level = 2,
1699 .size = 512 * KiB,
1700 .line_size = 64,
1701 .associativity = 8,
1702 .partitions = 1,
1703 .sets = 1024,
1704 .lines_per_tag = 1,
1705 },
1706 .l3_cache = &(CPUCacheInfo) {
1707 .type = UNIFIED_CACHE,
1708 .level = 3,
1709 .size = 8 * MiB,
1710 .line_size = 64,
1711 .associativity = 16,
1712 .partitions = 1,
1713 .sets = 8192,
1714 .lines_per_tag = 1,
1715 .self_init = true,
1716 .inclusive = true,
1717 .complex_indexing = true,
1718 },
1719 };
1720
1721 static CPUCaches epyc_rome_cache_info = {
1722 .l1d_cache = &(CPUCacheInfo) {
1723 .type = DATA_CACHE,
1724 .level = 1,
1725 .size = 32 * KiB,
1726 .line_size = 64,
1727 .associativity = 8,
1728 .partitions = 1,
1729 .sets = 64,
1730 .lines_per_tag = 1,
1731 .self_init = 1,
1732 .no_invd_sharing = true,
1733 },
1734 .l1i_cache = &(CPUCacheInfo) {
1735 .type = INSTRUCTION_CACHE,
1736 .level = 1,
1737 .size = 32 * KiB,
1738 .line_size = 64,
1739 .associativity = 8,
1740 .partitions = 1,
1741 .sets = 64,
1742 .lines_per_tag = 1,
1743 .self_init = 1,
1744 .no_invd_sharing = true,
1745 },
1746 .l2_cache = &(CPUCacheInfo) {
1747 .type = UNIFIED_CACHE,
1748 .level = 2,
1749 .size = 512 * KiB,
1750 .line_size = 64,
1751 .associativity = 8,
1752 .partitions = 1,
1753 .sets = 1024,
1754 .lines_per_tag = 1,
1755 },
1756 .l3_cache = &(CPUCacheInfo) {
1757 .type = UNIFIED_CACHE,
1758 .level = 3,
1759 .size = 16 * MiB,
1760 .line_size = 64,
1761 .associativity = 16,
1762 .partitions = 1,
1763 .sets = 16384,
1764 .lines_per_tag = 1,
1765 .self_init = true,
1766 .inclusive = true,
1767 .complex_indexing = true,
1768 },
1769 };
1770
1771 /* The following VMX features are not supported by KVM and are left out in the
1772 * CPU definitions:
1773 *
1774 * Dual-monitor support (all processors)
1775 * Entry to SMM
1776 * Deactivate dual-monitor treatment
1777 * Number of CR3-target values
1778 * Shutdown activity state
1779 * Wait-for-SIPI activity state
1780 * PAUSE-loop exiting (Westmere and newer)
1781 * EPT-violation #VE (Broadwell and newer)
1782 * Inject event with insn length=0 (Skylake and newer)
1783 * Conceal non-root operation from PT
1784 * Conceal VM exits from PT
1785 * Conceal VM entries from PT
1786 * Enable ENCLS exiting
1787 * Mode-based execute control (XS/XU)
1788 s TSC scaling (Skylake Server and newer)
1789 * GPA translation for PT (IceLake and newer)
1790 * User wait and pause
1791 * ENCLV exiting
1792 * Load IA32_RTIT_CTL
1793 * Clear IA32_RTIT_CTL
1794 * Advanced VM-exit information for EPT violations
1795 * Sub-page write permissions
1796 * PT in VMX operation
1797 */
1798
1799 static X86CPUDefinition builtin_x86_defs[] = {
1800 {
1801 .name = "qemu64",
1802 .level = 0xd,
1803 .vendor = CPUID_VENDOR_AMD,
1804 .family = 6,
1805 .model = 6,
1806 .stepping = 3,
1807 .features[FEAT_1_EDX] =
1808 PPRO_FEATURES |
1809 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1810 CPUID_PSE36,
1811 .features[FEAT_1_ECX] =
1812 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1813 .features[FEAT_8000_0001_EDX] =
1814 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1815 .features[FEAT_8000_0001_ECX] =
1816 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1817 .xlevel = 0x8000000A,
1818 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1819 },
1820 {
1821 .name = "phenom",
1822 .level = 5,
1823 .vendor = CPUID_VENDOR_AMD,
1824 .family = 16,
1825 .model = 2,
1826 .stepping = 3,
1827 /* Missing: CPUID_HT */
1828 .features[FEAT_1_EDX] =
1829 PPRO_FEATURES |
1830 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1831 CPUID_PSE36 | CPUID_VME,
1832 .features[FEAT_1_ECX] =
1833 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1834 CPUID_EXT_POPCNT,
1835 .features[FEAT_8000_0001_EDX] =
1836 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1837 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1838 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1839 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1840 CPUID_EXT3_CR8LEG,
1841 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1842 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1843 .features[FEAT_8000_0001_ECX] =
1844 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1845 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1846 /* Missing: CPUID_SVM_LBRV */
1847 .features[FEAT_SVM] =
1848 CPUID_SVM_NPT,
1849 .xlevel = 0x8000001A,
1850 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1851 },
1852 {
1853 .name = "core2duo",
1854 .level = 10,
1855 .vendor = CPUID_VENDOR_INTEL,
1856 .family = 6,
1857 .model = 15,
1858 .stepping = 11,
1859 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1860 .features[FEAT_1_EDX] =
1861 PPRO_FEATURES |
1862 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1863 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1864 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1865 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1866 .features[FEAT_1_ECX] =
1867 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1868 CPUID_EXT_CX16,
1869 .features[FEAT_8000_0001_EDX] =
1870 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1871 .features[FEAT_8000_0001_ECX] =
1872 CPUID_EXT3_LAHF_LM,
1873 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1874 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1875 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1876 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1877 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1878 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1879 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1880 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1881 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1882 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1883 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1884 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1885 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1886 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1887 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1888 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1889 .features[FEAT_VMX_SECONDARY_CTLS] =
1890 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1891 .xlevel = 0x80000008,
1892 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1893 },
1894 {
1895 .name = "kvm64",
1896 .level = 0xd,
1897 .vendor = CPUID_VENDOR_INTEL,
1898 .family = 15,
1899 .model = 6,
1900 .stepping = 1,
1901 /* Missing: CPUID_HT */
1902 .features[FEAT_1_EDX] =
1903 PPRO_FEATURES | CPUID_VME |
1904 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1905 CPUID_PSE36,
1906 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1907 .features[FEAT_1_ECX] =
1908 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1909 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1910 .features[FEAT_8000_0001_EDX] =
1911 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1912 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1913 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1914 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1915 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1916 .features[FEAT_8000_0001_ECX] =
1917 0,
1918 /* VMX features from Cedar Mill/Prescott */
1919 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1920 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1921 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1922 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1923 VMX_PIN_BASED_NMI_EXITING,
1924 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1925 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1926 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1927 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1928 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1929 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1930 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1931 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1932 .xlevel = 0x80000008,
1933 .model_id = "Common KVM processor"
1934 },
1935 {
1936 .name = "qemu32",
1937 .level = 4,
1938 .vendor = CPUID_VENDOR_INTEL,
1939 .family = 6,
1940 .model = 6,
1941 .stepping = 3,
1942 .features[FEAT_1_EDX] =
1943 PPRO_FEATURES,
1944 .features[FEAT_1_ECX] =
1945 CPUID_EXT_SSE3,
1946 .xlevel = 0x80000004,
1947 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1948 },
1949 {
1950 .name = "kvm32",
1951 .level = 5,
1952 .vendor = CPUID_VENDOR_INTEL,
1953 .family = 15,
1954 .model = 6,
1955 .stepping = 1,
1956 .features[FEAT_1_EDX] =
1957 PPRO_FEATURES | CPUID_VME |
1958 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1959 .features[FEAT_1_ECX] =
1960 CPUID_EXT_SSE3,
1961 .features[FEAT_8000_0001_ECX] =
1962 0,
1963 /* VMX features from Yonah */
1964 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1965 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1966 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1967 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1968 VMX_PIN_BASED_NMI_EXITING,
1969 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1970 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1971 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1972 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1973 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1974 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1975 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
1976 .xlevel = 0x80000008,
1977 .model_id = "Common 32-bit KVM processor"
1978 },
1979 {
1980 .name = "coreduo",
1981 .level = 10,
1982 .vendor = CPUID_VENDOR_INTEL,
1983 .family = 6,
1984 .model = 14,
1985 .stepping = 8,
1986 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1987 .features[FEAT_1_EDX] =
1988 PPRO_FEATURES | CPUID_VME |
1989 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1990 CPUID_SS,
1991 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1992 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1993 .features[FEAT_1_ECX] =
1994 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1995 .features[FEAT_8000_0001_EDX] =
1996 CPUID_EXT2_NX,
1997 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1998 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1999 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2000 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2001 VMX_PIN_BASED_NMI_EXITING,
2002 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2003 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2004 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2005 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2006 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2007 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2008 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2009 .xlevel = 0x80000008,
2010 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2011 },
2012 {
2013 .name = "486",
2014 .level = 1,
2015 .vendor = CPUID_VENDOR_INTEL,
2016 .family = 4,
2017 .model = 8,
2018 .stepping = 0,
2019 .features[FEAT_1_EDX] =
2020 I486_FEATURES,
2021 .xlevel = 0,
2022 .model_id = "",
2023 },
2024 {
2025 .name = "pentium",
2026 .level = 1,
2027 .vendor = CPUID_VENDOR_INTEL,
2028 .family = 5,
2029 .model = 4,
2030 .stepping = 3,
2031 .features[FEAT_1_EDX] =
2032 PENTIUM_FEATURES,
2033 .xlevel = 0,
2034 .model_id = "",
2035 },
2036 {
2037 .name = "pentium2",
2038 .level = 2,
2039 .vendor = CPUID_VENDOR_INTEL,
2040 .family = 6,
2041 .model = 5,
2042 .stepping = 2,
2043 .features[FEAT_1_EDX] =
2044 PENTIUM2_FEATURES,
2045 .xlevel = 0,
2046 .model_id = "",
2047 },
2048 {
2049 .name = "pentium3",
2050 .level = 3,
2051 .vendor = CPUID_VENDOR_INTEL,
2052 .family = 6,
2053 .model = 7,
2054 .stepping = 3,
2055 .features[FEAT_1_EDX] =
2056 PENTIUM3_FEATURES,
2057 .xlevel = 0,
2058 .model_id = "",
2059 },
2060 {
2061 .name = "athlon",
2062 .level = 2,
2063 .vendor = CPUID_VENDOR_AMD,
2064 .family = 6,
2065 .model = 2,
2066 .stepping = 3,
2067 .features[FEAT_1_EDX] =
2068 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2069 CPUID_MCA,
2070 .features[FEAT_8000_0001_EDX] =
2071 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2072 .xlevel = 0x80000008,
2073 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2074 },
2075 {
2076 .name = "n270",
2077 .level = 10,
2078 .vendor = CPUID_VENDOR_INTEL,
2079 .family = 6,
2080 .model = 28,
2081 .stepping = 2,
2082 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2083 .features[FEAT_1_EDX] =
2084 PPRO_FEATURES |
2085 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2086 CPUID_ACPI | CPUID_SS,
2087 /* Some CPUs got no CPUID_SEP */
2088 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2089 * CPUID_EXT_XTPR */
2090 .features[FEAT_1_ECX] =
2091 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2092 CPUID_EXT_MOVBE,
2093 .features[FEAT_8000_0001_EDX] =
2094 CPUID_EXT2_NX,
2095 .features[FEAT_8000_0001_ECX] =
2096 CPUID_EXT3_LAHF_LM,
2097 .xlevel = 0x80000008,
2098 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2099 },
2100 {
2101 .name = "Conroe",
2102 .level = 10,
2103 .vendor = CPUID_VENDOR_INTEL,
2104 .family = 6,
2105 .model = 15,
2106 .stepping = 3,
2107 .features[FEAT_1_EDX] =
2108 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2109 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2110 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2111 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2112 CPUID_DE | CPUID_FP87,
2113 .features[FEAT_1_ECX] =
2114 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2115 .features[FEAT_8000_0001_EDX] =
2116 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2117 .features[FEAT_8000_0001_ECX] =
2118 CPUID_EXT3_LAHF_LM,
2119 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2120 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2121 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2122 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2123 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2124 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2125 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2126 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2127 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2128 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2129 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2130 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2131 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2132 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2133 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2134 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2135 .features[FEAT_VMX_SECONDARY_CTLS] =
2136 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2137 .xlevel = 0x80000008,
2138 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2139 },
2140 {
2141 .name = "Penryn",
2142 .level = 10,
2143 .vendor = CPUID_VENDOR_INTEL,
2144 .family = 6,
2145 .model = 23,
2146 .stepping = 3,
2147 .features[FEAT_1_EDX] =
2148 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2149 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2150 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2151 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2152 CPUID_DE | CPUID_FP87,
2153 .features[FEAT_1_ECX] =
2154 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2155 CPUID_EXT_SSE3,
2156 .features[FEAT_8000_0001_EDX] =
2157 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2158 .features[FEAT_8000_0001_ECX] =
2159 CPUID_EXT3_LAHF_LM,
2160 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2161 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2162 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2163 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2164 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2165 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2166 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2167 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2168 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2169 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2170 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2171 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2172 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2173 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2174 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2175 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2176 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2177 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2178 .features[FEAT_VMX_SECONDARY_CTLS] =
2179 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2180 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2181 .xlevel = 0x80000008,
2182 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2183 },
2184 {
2185 .name = "Nehalem",
2186 .level = 11,
2187 .vendor = CPUID_VENDOR_INTEL,
2188 .family = 6,
2189 .model = 26,
2190 .stepping = 3,
2191 .features[FEAT_1_EDX] =
2192 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2193 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2194 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2195 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2196 CPUID_DE | CPUID_FP87,
2197 .features[FEAT_1_ECX] =
2198 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2199 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2200 .features[FEAT_8000_0001_EDX] =
2201 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2202 .features[FEAT_8000_0001_ECX] =
2203 CPUID_EXT3_LAHF_LM,
2204 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2205 MSR_VMX_BASIC_TRUE_CTLS,
2206 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2207 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2208 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2209 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2210 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2211 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2212 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2213 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2214 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2216 .features[FEAT_VMX_EXIT_CTLS] =
2217 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2218 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2219 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2220 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2221 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2222 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2223 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2224 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2225 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2226 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2227 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2228 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2229 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2230 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2231 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2232 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2233 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2234 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2235 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2236 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2237 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2238 .features[FEAT_VMX_SECONDARY_CTLS] =
2239 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2240 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2241 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2242 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2243 VMX_SECONDARY_EXEC_ENABLE_VPID,
2244 .xlevel = 0x80000008,
2245 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2246 .versions = (X86CPUVersionDefinition[]) {
2247 { .version = 1 },
2248 {
2249 .version = 2,
2250 .alias = "Nehalem-IBRS",
2251 .props = (PropValue[]) {
2252 { "spec-ctrl", "on" },
2253 { "model-id",
2254 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2255 { /* end of list */ }
2256 }
2257 },
2258 { /* end of list */ }
2259 }
2260 },
2261 {
2262 .name = "Westmere",
2263 .level = 11,
2264 .vendor = CPUID_VENDOR_INTEL,
2265 .family = 6,
2266 .model = 44,
2267 .stepping = 1,
2268 .features[FEAT_1_EDX] =
2269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2273 CPUID_DE | CPUID_FP87,
2274 .features[FEAT_1_ECX] =
2275 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2276 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2277 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2278 .features[FEAT_8000_0001_EDX] =
2279 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2280 .features[FEAT_8000_0001_ECX] =
2281 CPUID_EXT3_LAHF_LM,
2282 .features[FEAT_6_EAX] =
2283 CPUID_6_EAX_ARAT,
2284 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2285 MSR_VMX_BASIC_TRUE_CTLS,
2286 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2287 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2288 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2289 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2290 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2291 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2292 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2293 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2294 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2296 .features[FEAT_VMX_EXIT_CTLS] =
2297 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2298 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2299 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2300 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2301 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2302 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2303 MSR_VMX_MISC_STORE_LMA,
2304 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2305 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2306 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2307 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2308 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2309 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2310 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2311 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2312 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2313 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2314 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2315 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2316 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2317 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2318 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2319 .features[FEAT_VMX_SECONDARY_CTLS] =
2320 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2321 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2322 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2323 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2324 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2325 .xlevel = 0x80000008,
2326 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2327 .versions = (X86CPUVersionDefinition[]) {
2328 { .version = 1 },
2329 {
2330 .version = 2,
2331 .alias = "Westmere-IBRS",
2332 .props = (PropValue[]) {
2333 { "spec-ctrl", "on" },
2334 { "model-id",
2335 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2336 { /* end of list */ }
2337 }
2338 },
2339 { /* end of list */ }
2340 }
2341 },
2342 {
2343 .name = "SandyBridge",
2344 .level = 0xd,
2345 .vendor = CPUID_VENDOR_INTEL,
2346 .family = 6,
2347 .model = 42,
2348 .stepping = 1,
2349 .features[FEAT_1_EDX] =
2350 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2351 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2352 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2353 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2354 CPUID_DE | CPUID_FP87,
2355 .features[FEAT_1_ECX] =
2356 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2357 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2358 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2359 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2360 CPUID_EXT_SSE3,
2361 .features[FEAT_8000_0001_EDX] =
2362 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2363 CPUID_EXT2_SYSCALL,
2364 .features[FEAT_8000_0001_ECX] =
2365 CPUID_EXT3_LAHF_LM,
2366 .features[FEAT_XSAVE] =
2367 CPUID_XSAVE_XSAVEOPT,
2368 .features[FEAT_6_EAX] =
2369 CPUID_6_EAX_ARAT,
2370 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2371 MSR_VMX_BASIC_TRUE_CTLS,
2372 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2373 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2374 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2375 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2376 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2377 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2378 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2379 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2380 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2381 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2382 .features[FEAT_VMX_EXIT_CTLS] =
2383 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2384 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2385 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2386 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2387 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2388 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2389 MSR_VMX_MISC_STORE_LMA,
2390 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2391 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2392 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2393 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2394 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2395 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2396 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2397 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2398 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2399 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2400 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2401 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2402 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2403 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2404 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2405 .features[FEAT_VMX_SECONDARY_CTLS] =
2406 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2407 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2408 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2409 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2410 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2411 .xlevel = 0x80000008,
2412 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2413 .versions = (X86CPUVersionDefinition[]) {
2414 { .version = 1 },
2415 {
2416 .version = 2,
2417 .alias = "SandyBridge-IBRS",
2418 .props = (PropValue[]) {
2419 { "spec-ctrl", "on" },
2420 { "model-id",
2421 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2422 { /* end of list */ }
2423 }
2424 },
2425 { /* end of list */ }
2426 }
2427 },
2428 {
2429 .name = "IvyBridge",
2430 .level = 0xd,
2431 .vendor = CPUID_VENDOR_INTEL,
2432 .family = 6,
2433 .model = 58,
2434 .stepping = 9,
2435 .features[FEAT_1_EDX] =
2436 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2437 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2438 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2439 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2440 CPUID_DE | CPUID_FP87,
2441 .features[FEAT_1_ECX] =
2442 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2443 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2444 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2445 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2446 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2447 .features[FEAT_7_0_EBX] =
2448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2449 CPUID_7_0_EBX_ERMS,
2450 .features[FEAT_8000_0001_EDX] =
2451 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2452 CPUID_EXT2_SYSCALL,
2453 .features[FEAT_8000_0001_ECX] =
2454 CPUID_EXT3_LAHF_LM,
2455 .features[FEAT_XSAVE] =
2456 CPUID_XSAVE_XSAVEOPT,
2457 .features[FEAT_6_EAX] =
2458 CPUID_6_EAX_ARAT,
2459 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2460 MSR_VMX_BASIC_TRUE_CTLS,
2461 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2462 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2463 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2464 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2465 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2466 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2467 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2468 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2469 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2470 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2471 .features[FEAT_VMX_EXIT_CTLS] =
2472 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2473 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2474 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2475 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2476 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2477 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2478 MSR_VMX_MISC_STORE_LMA,
2479 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2480 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2481 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2482 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2483 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2484 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2485 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2486 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2487 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2488 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2489 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2490 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2491 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2492 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2493 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2494 .features[FEAT_VMX_SECONDARY_CTLS] =
2495 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2496 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2497 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2498 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2499 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2500 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2501 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2502 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2503 .xlevel = 0x80000008,
2504 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2505 .versions = (X86CPUVersionDefinition[]) {
2506 { .version = 1 },
2507 {
2508 .version = 2,
2509 .alias = "IvyBridge-IBRS",
2510 .props = (PropValue[]) {
2511 { "spec-ctrl", "on" },
2512 { "model-id",
2513 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2514 { /* end of list */ }
2515 }
2516 },
2517 { /* end of list */ }
2518 }
2519 },
2520 {
2521 .name = "Haswell",
2522 .level = 0xd,
2523 .vendor = CPUID_VENDOR_INTEL,
2524 .family = 6,
2525 .model = 60,
2526 .stepping = 4,
2527 .features[FEAT_1_EDX] =
2528 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2529 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2530 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2531 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2532 CPUID_DE | CPUID_FP87,
2533 .features[FEAT_1_ECX] =
2534 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2535 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2536 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2537 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2538 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2539 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2540 .features[FEAT_8000_0001_EDX] =
2541 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2542 CPUID_EXT2_SYSCALL,
2543 .features[FEAT_8000_0001_ECX] =
2544 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2545 .features[FEAT_7_0_EBX] =
2546 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2547 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2548 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2549 CPUID_7_0_EBX_RTM,
2550 .features[FEAT_XSAVE] =
2551 CPUID_XSAVE_XSAVEOPT,
2552 .features[FEAT_6_EAX] =
2553 CPUID_6_EAX_ARAT,
2554 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2555 MSR_VMX_BASIC_TRUE_CTLS,
2556 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2557 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2558 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2559 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2560 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2561 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2562 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2563 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2564 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2565 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2566 .features[FEAT_VMX_EXIT_CTLS] =
2567 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2568 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2569 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2570 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2571 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2572 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2573 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2574 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2575 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2576 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2577 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2578 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2579 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2580 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2581 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2582 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2583 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2584 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2585 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2586 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2587 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2588 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2589 .features[FEAT_VMX_SECONDARY_CTLS] =
2590 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2591 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2592 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2593 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2594 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2595 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2596 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2597 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2598 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2599 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2600 .xlevel = 0x80000008,
2601 .model_id = "Intel Core Processor (Haswell)",
2602 .versions = (X86CPUVersionDefinition[]) {
2603 { .version = 1 },
2604 {
2605 .version = 2,
2606 .alias = "Haswell-noTSX",
2607 .props = (PropValue[]) {
2608 { "hle", "off" },
2609 { "rtm", "off" },
2610 { "stepping", "1" },
2611 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2612 { /* end of list */ }
2613 },
2614 },
2615 {
2616 .version = 3,
2617 .alias = "Haswell-IBRS",
2618 .props = (PropValue[]) {
2619 /* Restore TSX features removed by -v2 above */
2620 { "hle", "on" },
2621 { "rtm", "on" },
2622 /*
2623 * Haswell and Haswell-IBRS had stepping=4 in
2624 * QEMU 4.0 and older
2625 */
2626 { "stepping", "4" },
2627 { "spec-ctrl", "on" },
2628 { "model-id",
2629 "Intel Core Processor (Haswell, IBRS)" },
2630 { /* end of list */ }
2631 }
2632 },
2633 {
2634 .version = 4,
2635 .alias = "Haswell-noTSX-IBRS",
2636 .props = (PropValue[]) {
2637 { "hle", "off" },
2638 { "rtm", "off" },
2639 /* spec-ctrl was already enabled by -v3 above */
2640 { "stepping", "1" },
2641 { "model-id",
2642 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2643 { /* end of list */ }
2644 }
2645 },
2646 { /* end of list */ }
2647 }
2648 },
2649 {
2650 .name = "Broadwell",
2651 .level = 0xd,
2652 .vendor = CPUID_VENDOR_INTEL,
2653 .family = 6,
2654 .model = 61,
2655 .stepping = 2,
2656 .features[FEAT_1_EDX] =
2657 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2658 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2659 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2660 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2661 CPUID_DE | CPUID_FP87,
2662 .features[FEAT_1_ECX] =
2663 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2664 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2665 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2666 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2667 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2668 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2669 .features[FEAT_8000_0001_EDX] =
2670 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2671 CPUID_EXT2_SYSCALL,
2672 .features[FEAT_8000_0001_ECX] =
2673 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2674 .features[FEAT_7_0_EBX] =
2675 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2676 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2677 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2678 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2679 CPUID_7_0_EBX_SMAP,
2680 .features[FEAT_XSAVE] =
2681 CPUID_XSAVE_XSAVEOPT,
2682 .features[FEAT_6_EAX] =
2683 CPUID_6_EAX_ARAT,
2684 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2685 MSR_VMX_BASIC_TRUE_CTLS,
2686 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2687 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2688 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2689 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2690 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2691 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2692 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2693 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2694 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2695 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2696 .features[FEAT_VMX_EXIT_CTLS] =
2697 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2698 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2699 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2700 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2701 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2702 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2703 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2704 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2705 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2706 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2707 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2708 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2709 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2710 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2711 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2712 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2713 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2714 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2715 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2716 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2717 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2718 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2719 .features[FEAT_VMX_SECONDARY_CTLS] =
2720 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2721 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2722 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2723 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2724 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2725 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2726 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2727 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2728 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2729 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2730 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2731 .xlevel = 0x80000008,
2732 .model_id = "Intel Core Processor (Broadwell)",
2733 .versions = (X86CPUVersionDefinition[]) {
2734 { .version = 1 },
2735 {
2736 .version = 2,
2737 .alias = "Broadwell-noTSX",
2738 .props = (PropValue[]) {
2739 { "hle", "off" },
2740 { "rtm", "off" },
2741 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2742 { /* end of list */ }
2743 },
2744 },
2745 {
2746 .version = 3,
2747 .alias = "Broadwell-IBRS",
2748 .props = (PropValue[]) {
2749 /* Restore TSX features removed by -v2 above */
2750 { "hle", "on" },
2751 { "rtm", "on" },
2752 { "spec-ctrl", "on" },
2753 { "model-id",
2754 "Intel Core Processor (Broadwell, IBRS)" },
2755 { /* end of list */ }
2756 }
2757 },
2758 {
2759 .version = 4,
2760 .alias = "Broadwell-noTSX-IBRS",
2761 .props = (PropValue[]) {
2762 { "hle", "off" },
2763 { "rtm", "off" },
2764 /* spec-ctrl was already enabled by -v3 above */
2765 { "model-id",
2766 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2767 { /* end of list */ }
2768 }
2769 },
2770 { /* end of list */ }
2771 }
2772 },
2773 {
2774 .name = "Skylake-Client",
2775 .level = 0xd,
2776 .vendor = CPUID_VENDOR_INTEL,
2777 .family = 6,
2778 .model = 94,
2779 .stepping = 3,
2780 .features[FEAT_1_EDX] =
2781 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2782 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2783 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2784 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2785 CPUID_DE | CPUID_FP87,
2786 .features[FEAT_1_ECX] =
2787 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2788 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2789 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2790 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2791 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2792 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2793 .features[FEAT_8000_0001_EDX] =
2794 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2795 CPUID_EXT2_SYSCALL,
2796 .features[FEAT_8000_0001_ECX] =
2797 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2798 .features[FEAT_7_0_EBX] =
2799 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2800 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2801 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2802 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2803 CPUID_7_0_EBX_SMAP,
2804 /* Missing: XSAVES (not supported by some Linux versions,
2805 * including v4.1 to v4.12).
2806 * KVM doesn't yet expose any XSAVES state save component,
2807 * and the only one defined in Skylake (processor tracing)
2808 * probably will block migration anyway.
2809 */
2810 .features[FEAT_XSAVE] =
2811 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2812 CPUID_XSAVE_XGETBV1,
2813 .features[FEAT_6_EAX] =
2814 CPUID_6_EAX_ARAT,
2815 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2816 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2817 MSR_VMX_BASIC_TRUE_CTLS,
2818 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2819 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2820 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2821 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2822 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2823 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2824 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2825 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2826 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2827 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2828 .features[FEAT_VMX_EXIT_CTLS] =
2829 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2830 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2831 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2832 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2833 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2834 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2835 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2836 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2837 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2838 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2839 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2840 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2841 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2842 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2843 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2844 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2845 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2846 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2847 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2848 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2849 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2850 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2851 .features[FEAT_VMX_SECONDARY_CTLS] =
2852 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2853 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2854 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2855 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2856 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2857 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2858 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2859 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2860 .xlevel = 0x80000008,
2861 .model_id = "Intel Core Processor (Skylake)",
2862 .versions = (X86CPUVersionDefinition[]) {
2863 { .version = 1 },
2864 {
2865 .version = 2,
2866 .alias = "Skylake-Client-IBRS",
2867 .props = (PropValue[]) {
2868 { "spec-ctrl", "on" },
2869 { "model-id",
2870 "Intel Core Processor (Skylake, IBRS)" },
2871 { /* end of list */ }
2872 }
2873 },
2874 {
2875 .version = 3,
2876 .alias = "Skylake-Client-noTSX-IBRS",
2877 .props = (PropValue[]) {
2878 { "hle", "off" },
2879 { "rtm", "off" },
2880 { "model-id",
2881 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2882 { /* end of list */ }
2883 }
2884 },
2885 { /* end of list */ }
2886 }
2887 },
2888 {
2889 .name = "Skylake-Server",
2890 .level = 0xd,
2891 .vendor = CPUID_VENDOR_INTEL,
2892 .family = 6,
2893 .model = 85,
2894 .stepping = 4,
2895 .features[FEAT_1_EDX] =
2896 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2897 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2898 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2899 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2900 CPUID_DE | CPUID_FP87,
2901 .features[FEAT_1_ECX] =
2902 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2903 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2904 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2905 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2906 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2907 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2908 .features[FEAT_8000_0001_EDX] =
2909 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2910 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2911 .features[FEAT_8000_0001_ECX] =
2912 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2913 .features[FEAT_7_0_EBX] =
2914 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2915 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2916 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2917 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2918 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2919 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2920 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2921 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2922 .features[FEAT_7_0_ECX] =
2923 CPUID_7_0_ECX_PKU,
2924 /* Missing: XSAVES (not supported by some Linux versions,
2925 * including v4.1 to v4.12).
2926 * KVM doesn't yet expose any XSAVES state save component,
2927 * and the only one defined in Skylake (processor tracing)
2928 * probably will block migration anyway.
2929 */
2930 .features[FEAT_XSAVE] =
2931 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2932 CPUID_XSAVE_XGETBV1,
2933 .features[FEAT_6_EAX] =
2934 CPUID_6_EAX_ARAT,
2935 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2936 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2937 MSR_VMX_BASIC_TRUE_CTLS,
2938 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2939 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2940 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2941 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2942 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2943 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2944 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2945 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2946 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2947 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2948 .features[FEAT_VMX_EXIT_CTLS] =
2949 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2950 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2951 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2952 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2953 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2954 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2955 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2956 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2957 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2958 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2959 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2960 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2961 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2962 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2963 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2964 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2965 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2966 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2967 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2968 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2969 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2970 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2971 .features[FEAT_VMX_SECONDARY_CTLS] =
2972 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2973 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2974 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2975 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2976 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2977 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2978 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2979 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2980 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2981 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2982 .xlevel = 0x80000008,
2983 .model_id = "Intel Xeon Processor (Skylake)",
2984 .versions = (X86CPUVersionDefinition[]) {
2985 { .version = 1 },
2986 {
2987 .version = 2,
2988 .alias = "Skylake-Server-IBRS",
2989 .props = (PropValue[]) {
2990 /* clflushopt was not added to Skylake-Server-IBRS */
2991 /* TODO: add -v3 including clflushopt */
2992 { "clflushopt", "off" },
2993 { "spec-ctrl", "on" },
2994 { "model-id",
2995 "Intel Xeon Processor (Skylake, IBRS)" },
2996 { /* end of list */ }
2997 }
2998 },
2999 {
3000 .version = 3,
3001 .alias = "Skylake-Server-noTSX-IBRS",
3002 .props = (PropValue[]) {
3003 { "hle", "off" },
3004 { "rtm", "off" },
3005 { "model-id",
3006 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3007 { /* end of list */ }
3008 }
3009 },
3010 {
3011 .version = 4,
3012 .props = (PropValue[]) {
3013 { "vmx-eptp-switching", "on" },
3014 { /* end of list */ }
3015 }
3016 },
3017 { /* end of list */ }
3018 }
3019 },
3020 {
3021 .name = "Cascadelake-Server",
3022 .level = 0xd,
3023 .vendor = CPUID_VENDOR_INTEL,
3024 .family = 6,
3025 .model = 85,
3026 .stepping = 6,
3027 .features[FEAT_1_EDX] =
3028 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3029 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3030 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3031 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3032 CPUID_DE | CPUID_FP87,
3033 .features[FEAT_1_ECX] =
3034 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3035 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3036 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3037 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3038 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3039 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3040 .features[FEAT_8000_0001_EDX] =
3041 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3042 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3043 .features[FEAT_8000_0001_ECX] =
3044 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3045 .features[FEAT_7_0_EBX] =
3046 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3047 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3048 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3049 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3050 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3051 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3052 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3053 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3054 .features[FEAT_7_0_ECX] =
3055 CPUID_7_0_ECX_PKU |
3056 CPUID_7_0_ECX_AVX512VNNI,
3057 .features[FEAT_7_0_EDX] =
3058 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3059 /* Missing: XSAVES (not supported by some Linux versions,
3060 * including v4.1 to v4.12).
3061 * KVM doesn't yet expose any XSAVES state save component,
3062 * and the only one defined in Skylake (processor tracing)
3063 * probably will block migration anyway.
3064 */
3065 .features[FEAT_XSAVE] =
3066 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3067 CPUID_XSAVE_XGETBV1,
3068 .features[FEAT_6_EAX] =
3069 CPUID_6_EAX_ARAT,
3070 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3071 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3072 MSR_VMX_BASIC_TRUE_CTLS,
3073 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3074 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3075 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3076 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3077 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3078 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3079 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3080 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3081 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3082 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3083 .features[FEAT_VMX_EXIT_CTLS] =
3084 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3085 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3086 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3087 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3088 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3089 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3090 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3091 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3092 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3093 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3094 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3095 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3096 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3097 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3098 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3099 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3100 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3101 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3102 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3103 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3104 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3105 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3106 .features[FEAT_VMX_SECONDARY_CTLS] =
3107 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3108 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3109 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3110 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3111 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3112 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3113 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3114 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3115 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3116 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3117 .xlevel = 0x80000008,
3118 .model_id = "Intel Xeon Processor (Cascadelake)",
3119 .versions = (X86CPUVersionDefinition[]) {
3120 { .version = 1 },
3121 { .version = 2,
3122 .note = "ARCH_CAPABILITIES",
3123 .props = (PropValue[]) {
3124 { "arch-capabilities", "on" },
3125 { "rdctl-no", "on" },
3126 { "ibrs-all", "on" },
3127 { "skip-l1dfl-vmentry", "on" },
3128 { "mds-no", "on" },
3129 { /* end of list */ }
3130 },
3131 },
3132 { .version = 3,
3133 .alias = "Cascadelake-Server-noTSX",
3134 .note = "ARCH_CAPABILITIES, no TSX",
3135 .props = (PropValue[]) {
3136 { "hle", "off" },
3137 { "rtm", "off" },
3138 { /* end of list */ }
3139 },
3140 },
3141 { .version = 4,
3142 .note = "ARCH_CAPABILITIES, no TSX",
3143 .props = (PropValue[]) {
3144 { "vmx-eptp-switching", "on" },
3145 { /* end of list */ }
3146 },
3147 },
3148 { /* end of list */ }
3149 }
3150 },
3151 {
3152 .name = "Cooperlake",
3153 .level = 0xd,
3154 .vendor = CPUID_VENDOR_INTEL,
3155 .family = 6,
3156 .model = 85,
3157 .stepping = 10,
3158 .features[FEAT_1_EDX] =
3159 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3160 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3161 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3162 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3163 CPUID_DE | CPUID_FP87,
3164 .features[FEAT_1_ECX] =
3165 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3166 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3167 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3168 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3169 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3170 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3171 .features[FEAT_8000_0001_EDX] =
3172 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3173 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3174 .features[FEAT_8000_0001_ECX] =
3175 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3176 .features[FEAT_7_0_EBX] =
3177 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3178 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3179 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3180 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3181 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3182 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3183 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3184 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3185 .features[FEAT_7_0_ECX] =
3186 CPUID_7_0_ECX_PKU |
3187 CPUID_7_0_ECX_AVX512VNNI,
3188 .features[FEAT_7_0_EDX] =
3189 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3190 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3191 .features[FEAT_ARCH_CAPABILITIES] =
3192 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3193 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3194 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3195 .features[FEAT_7_1_EAX] =
3196 CPUID_7_1_EAX_AVX512_BF16,
3197 /*
3198 * Missing: XSAVES (not supported by some Linux versions,
3199 * including v4.1 to v4.12).
3200 * KVM doesn't yet expose any XSAVES state save component,
3201 * and the only one defined in Skylake (processor tracing)
3202 * probably will block migration anyway.
3203 */
3204 .features[FEAT_XSAVE] =
3205 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3206 CPUID_XSAVE_XGETBV1,
3207 .features[FEAT_6_EAX] =
3208 CPUID_6_EAX_ARAT,
3209 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3210 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3211 MSR_VMX_BASIC_TRUE_CTLS,
3212 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3213 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3214 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3215 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3216 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3217 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3218 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3219 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3220 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3221 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3222 .features[FEAT_VMX_EXIT_CTLS] =
3223 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3224 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3225 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3226 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3227 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3228 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3229 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3230 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3231 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3232 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3233 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3234 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3235 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3236 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3237 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3238 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3239 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3240 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3241 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3242 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3243 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3244 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3245 .features[FEAT_VMX_SECONDARY_CTLS] =
3246 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3247 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3248 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3249 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3250 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3251 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3252 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3253 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3254 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3255 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3256 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3257 .xlevel = 0x80000008,
3258 .model_id = "Intel Xeon Processor (Cooperlake)",
3259 },
3260 {
3261 .name = "Icelake-Client",
3262 .level = 0xd,
3263 .vendor = CPUID_VENDOR_INTEL,
3264 .family = 6,
3265 .model = 126,
3266 .stepping = 0,
3267 .features[FEAT_1_EDX] =
3268 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3269 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3270 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3271 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3272 CPUID_DE | CPUID_FP87,
3273 .features[FEAT_1_ECX] =
3274 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3275 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3276 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3277 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3278 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3279 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3280 .features[FEAT_8000_0001_EDX] =
3281 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3282 CPUID_EXT2_SYSCALL,
3283 .features[FEAT_8000_0001_ECX] =
3284 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3285 .features[FEAT_8000_0008_EBX] =
3286 CPUID_8000_0008_EBX_WBNOINVD,
3287 .features[FEAT_7_0_EBX] =
3288 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3289 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3290 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3291 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3292 CPUID_7_0_EBX_SMAP,
3293 .features[FEAT_7_0_ECX] =
3294 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3295 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3296 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3297 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3298 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3299 .features[FEAT_7_0_EDX] =
3300 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3301 /* Missing: XSAVES (not supported by some Linux versions,
3302 * including v4.1 to v4.12).
3303 * KVM doesn't yet expose any XSAVES state save component,
3304 * and the only one defined in Skylake (processor tracing)
3305 * probably will block migration anyway.
3306 */
3307 .features[FEAT_XSAVE] =
3308 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3309 CPUID_XSAVE_XGETBV1,
3310 .features[FEAT_6_EAX] =
3311 CPUID_6_EAX_ARAT,
3312 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3313 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3314 MSR_VMX_BASIC_TRUE_CTLS,
3315 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3316 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3317 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3318 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3319 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3320 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3321 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3322 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3323 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3324 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3325 .features[FEAT_VMX_EXIT_CTLS] =
3326 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3327 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3328 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3329 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3330 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3331 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3332 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3333 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3334 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3335 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3336 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3337 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3338 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3339 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3340 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3341 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3342 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3343 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3344 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3345 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3346 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3347 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3348 .features[FEAT_VMX_SECONDARY_CTLS] =
3349 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3350 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3351 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3352 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3353 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3354 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3355 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3356 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3357 .xlevel = 0x80000008,
3358 .model_id = "Intel Core Processor (Icelake)",
3359 .versions = (X86CPUVersionDefinition[]) {
3360 { .version = 1 },
3361 {
3362 .version = 2,
3363 .note = "no TSX",
3364 .alias = "Icelake-Client-noTSX",
3365 .props = (PropValue[]) {
3366 { "hle", "off" },
3367 { "rtm", "off" },
3368 { /* end of list */ }
3369 },
3370 },
3371 { /* end of list */ }
3372 }
3373 },
3374 {
3375 .name = "Icelake-Server",
3376 .level = 0xd,
3377 .vendor = CPUID_VENDOR_INTEL,
3378 .family = 6,
3379 .model = 134,
3380 .stepping = 0,
3381 .features[FEAT_1_EDX] =
3382 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3383 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3384 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3385 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3386 CPUID_DE | CPUID_FP87,
3387 .features[FEAT_1_ECX] =
3388 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3389 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3390 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3391 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3392 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3393 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3394 .features[FEAT_8000_0001_EDX] =
3395 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3396 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3397 .features[FEAT_8000_0001_ECX] =
3398 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3399 .features[FEAT_8000_0008_EBX] =
3400 CPUID_8000_0008_EBX_WBNOINVD,
3401 .features[FEAT_7_0_EBX] =
3402 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3403 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3404 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3405 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3406 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3407 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3408 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3409 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3410 .features[FEAT_7_0_ECX] =
3411 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3412 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3413 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3414 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3415 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3416 .features[FEAT_7_0_EDX] =
3417 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3418 /* Missing: XSAVES (not supported by some Linux versions,
3419 * including v4.1 to v4.12).
3420 * KVM doesn't yet expose any XSAVES state save component,
3421 * and the only one defined in Skylake (processor tracing)
3422 * probably will block migration anyway.
3423 */
3424 .features[FEAT_XSAVE] =
3425 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3426 CPUID_XSAVE_XGETBV1,
3427 .features[FEAT_6_EAX] =
3428 CPUID_6_EAX_ARAT,
3429 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3430 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3431 MSR_VMX_BASIC_TRUE_CTLS,
3432 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3433 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3434 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3435 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3436 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3437 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3438 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3439 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3440 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3441 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3442 .features[FEAT_VMX_EXIT_CTLS] =
3443 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3444 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3445 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3446 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3447 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3448 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3449 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3450 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3451 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3452 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3453 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3454 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3455 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3456 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3457 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3458 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3459 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3460 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3461 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3462 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3463 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3464 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3465 .features[FEAT_VMX_SECONDARY_CTLS] =
3466 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3467 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3468 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3469 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3470 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3471 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3472 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3473 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3474 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3475 .xlevel = 0x80000008,
3476 .model_id = "Intel Xeon Processor (Icelake)",
3477 .versions = (X86CPUVersionDefinition[]) {
3478 { .version = 1 },
3479 {
3480 .version = 2,
3481 .note = "no TSX",
3482 .alias = "Icelake-Server-noTSX",
3483 .props = (PropValue[]) {
3484 { "hle", "off" },
3485 { "rtm", "off" },
3486 { /* end of list */ }
3487 },
3488 },
3489 {
3490 .version = 3,
3491 .props = (PropValue[]) {
3492 { "arch-capabilities", "on" },
3493 { "rdctl-no", "on" },
3494 { "ibrs-all", "on" },
3495 { "skip-l1dfl-vmentry", "on" },
3496 { "mds-no", "on" },
3497 { "pschange-mc-no", "on" },
3498 { "taa-no", "on" },
3499 { /* end of list */ }
3500 },
3501 },
3502 {
3503 .version = 4,
3504 .props = (PropValue[]) {
3505 { "sha-ni", "on" },
3506 { "avx512ifma", "on" },
3507 { "rdpid", "on" },
3508 { "fsrm", "on" },
3509 { "vmx-rdseed-exit", "on" },
3510 { "vmx-pml", "on" },
3511 { "vmx-eptp-switching", "on" },
3512 { "model", "106" },
3513 { /* end of list */ }
3514 },
3515 },
3516 { /* end of list */ }
3517 }
3518 },
3519 {
3520 .name = "Denverton",
3521 .level = 21,
3522 .vendor = CPUID_VENDOR_INTEL,
3523 .family = 6,
3524 .model = 95,
3525 .stepping = 1,
3526 .features[FEAT_1_EDX] =
3527 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3528 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3529 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3530 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3531 CPUID_SSE | CPUID_SSE2,
3532 .features[FEAT_1_ECX] =
3533 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3534 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3535 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3536 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3537 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3538 .features[FEAT_8000_0001_EDX] =
3539 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3540 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3541 .features[FEAT_8000_0001_ECX] =
3542 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3543 .features[FEAT_7_0_EBX] =
3544 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3545 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3546 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3547 .features[FEAT_7_0_EDX] =
3548 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3549 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3550 /*
3551 * Missing: XSAVES (not supported by some Linux versions,
3552 * including v4.1 to v4.12).
3553 * KVM doesn't yet expose any XSAVES state save component,
3554 * and the only one defined in Skylake (processor tracing)
3555 * probably will block migration anyway.
3556 */
3557 .features[FEAT_XSAVE] =
3558 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3559 .features[FEAT_6_EAX] =
3560 CPUID_6_EAX_ARAT,
3561 .features[FEAT_ARCH_CAPABILITIES] =
3562 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3563 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3564 MSR_VMX_BASIC_TRUE_CTLS,
3565 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3566 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3567 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3568 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3569 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3570 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3571 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3572 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3573 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3574 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3575 .features[FEAT_VMX_EXIT_CTLS] =
3576 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3577 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3578 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3579 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3580 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3581 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3582 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3583 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3584 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3585 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3586 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3587 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3588 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3589 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3590 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3591 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3592 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3593 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3594 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3595 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3596 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3597 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3598 .features[FEAT_VMX_SECONDARY_CTLS] =
3599 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3600 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3601 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3602 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3603 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3604 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3605 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3606 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3607 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3608 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3609 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3610 .xlevel = 0x80000008,
3611 .model_id = "Intel Atom Processor (Denverton)",
3612 .versions = (X86CPUVersionDefinition[]) {
3613 { .version = 1 },
3614 {
3615 .version = 2,
3616 .note = "no MPX, no MONITOR",
3617 .props = (PropValue[]) {
3618 { "monitor", "off" },
3619 { "mpx", "off" },
3620 { /* end of list */ },
3621 },
3622 },
3623 { /* end of list */ },
3624 },
3625 },
3626 {
3627 .name = "Snowridge",
3628 .level = 27,
3629 .vendor = CPUID_VENDOR_INTEL,
3630 .family = 6,
3631 .model = 134,
3632 .stepping = 1,
3633 .features[FEAT_1_EDX] =
3634 /* missing: CPUID_PN CPUID_IA64 */
3635 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3636 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3637 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3638 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3639 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3640 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3641 CPUID_MMX |
3642 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3643 .features[FEAT_1_ECX] =
3644 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3645 CPUID_EXT_SSSE3 |
3646 CPUID_EXT_CX16 |
3647 CPUID_EXT_SSE41 |
3648 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3649 CPUID_EXT_POPCNT |
3650 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3651 CPUID_EXT_RDRAND,
3652 .features[FEAT_8000_0001_EDX] =
3653 CPUID_EXT2_SYSCALL |
3654 CPUID_EXT2_NX |
3655 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3656 CPUID_EXT2_LM,
3657 .features[FEAT_8000_0001_ECX] =
3658 CPUID_EXT3_LAHF_LM |
3659 CPUID_EXT3_3DNOWPREFETCH,
3660 .features[FEAT_7_0_EBX] =
3661 CPUID_7_0_EBX_FSGSBASE |
3662 CPUID_7_0_EBX_SMEP |
3663 CPUID_7_0_EBX_ERMS |
3664 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3665 CPUID_7_0_EBX_RDSEED |
3666 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3667 CPUID_7_0_EBX_CLWB |
3668 CPUID_7_0_EBX_SHA_NI,
3669 .features[FEAT_7_0_ECX] =
3670 CPUID_7_0_ECX_UMIP |
3671 /* missing bit 5 */
3672 CPUID_7_0_ECX_GFNI |
3673 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3674 CPUID_7_0_ECX_MOVDIR64B,
3675 .features[FEAT_7_0_EDX] =
3676 CPUID_7_0_EDX_SPEC_CTRL |
3677 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3678 CPUID_7_0_EDX_CORE_CAPABILITY,
3679 .features[FEAT_CORE_CAPABILITY] =
3680 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3681 /*
3682 * Missing: XSAVES (not supported by some Linux versions,
3683 * including v4.1 to v4.12).
3684 * KVM doesn't yet expose any XSAVES state save component,
3685 * and the only one defined in Skylake (processor tracing)
3686 * probably will block migration anyway.
3687 */
3688 .features[FEAT_XSAVE] =
3689 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3690 CPUID_XSAVE_XGETBV1,
3691 .features[FEAT_6_EAX] =
3692 CPUID_6_EAX_ARAT,
3693 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3694 MSR_VMX_BASIC_TRUE_CTLS,
3695 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3696 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3697 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3698 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3699 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3700 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3701 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3702 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3703 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3704 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3705 .features[FEAT_VMX_EXIT_CTLS] =
3706 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3707 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3708 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3709 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3710 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3711 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3712 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3713 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3714 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3715 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3716 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3717 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3718 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3719 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3720 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3721 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3722 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3723 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3724 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3725 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3726 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3727 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3728 .features[FEAT_VMX_SECONDARY_CTLS] =
3729 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3730 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3731 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3732 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3733 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3734 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3735 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3736 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3737 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3738 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3739 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3740 .xlevel = 0x80000008,
3741 .model_id = "Intel Atom Processor (SnowRidge)",
3742 .versions = (X86CPUVersionDefinition[]) {
3743 { .version = 1 },
3744 {
3745 .version = 2,
3746 .props = (PropValue[]) {
3747 { "mpx", "off" },
3748 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3749 { /* end of list */ },
3750 },
3751 },
3752 { /* end of list */ },
3753 },
3754 },
3755 {
3756 .name = "KnightsMill",
3757 .level = 0xd,
3758 .vendor = CPUID_VENDOR_INTEL,
3759 .family = 6,
3760 .model = 133,
3761 .stepping = 0,
3762 .features[FEAT_1_EDX] =
3763 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3764 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3765 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3766 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3767 CPUID_PSE | CPUID_DE | CPUID_FP87,
3768 .features[FEAT_1_ECX] =
3769 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3770 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3771 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3772 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3773 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3774 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3775 .features[FEAT_8000_0001_EDX] =
3776 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3777 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3778 .features[FEAT_8000_0001_ECX] =
3779 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3780 .features[FEAT_7_0_EBX] =
3781 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3782 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3783 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3784 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3785 CPUID_7_0_EBX_AVX512ER,
3786 .features[FEAT_7_0_ECX] =
3787 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3788 .features[FEAT_7_0_EDX] =
3789 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3790 .features[FEAT_XSAVE] =
3791 CPUID_XSAVE_XSAVEOPT,
3792 .features[FEAT_6_EAX] =
3793 CPUID_6_EAX_ARAT,
3794 .xlevel = 0x80000008,
3795 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3796 },
3797 {
3798 .name = "Opteron_G1",
3799 .level = 5,
3800 .vendor = CPUID_VENDOR_AMD,
3801 .family = 15,
3802 .model = 6,
3803 .stepping = 1,
3804 .features[FEAT_1_EDX] =
3805 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3809 CPUID_DE | CPUID_FP87,
3810 .features[FEAT_1_ECX] =
3811 CPUID_EXT_SSE3,
3812 .features[FEAT_8000_0001_EDX] =
3813 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3814 .xlevel = 0x80000008,
3815 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3816 },
3817 {
3818 .name = "Opteron_G2",
3819 .level = 5,
3820 .vendor = CPUID_VENDOR_AMD,
3821 .family = 15,
3822 .model = 6,
3823 .stepping = 1,
3824 .features[FEAT_1_EDX] =
3825 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3826 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3827 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3828 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3829 CPUID_DE | CPUID_FP87,
3830 .features[FEAT_1_ECX] =
3831 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
3832 .features[FEAT_8000_0001_EDX] =
3833 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3834 .features[FEAT_8000_0001_ECX] =
3835 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3836 .xlevel = 0x80000008,
3837 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3838 },
3839 {
3840 .name = "Opteron_G3",
3841 .level = 5,
3842 .vendor = CPUID_VENDOR_AMD,
3843 .family = 16,
3844 .model = 2,
3845 .stepping = 3,
3846 .features[FEAT_1_EDX] =
3847 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3848 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3849 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3850 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3851 CPUID_DE | CPUID_FP87,
3852 .features[FEAT_1_ECX] =
3853 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3854 CPUID_EXT_SSE3,
3855 .features[FEAT_8000_0001_EDX] =
3856 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3857 CPUID_EXT2_RDTSCP,
3858 .features[FEAT_8000_0001_ECX] =
3859 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3860 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3861 .xlevel = 0x80000008,
3862 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3863 },
3864 {
3865 .name = "Opteron_G4",
3866 .level = 0xd,
3867 .vendor = CPUID_VENDOR_AMD,
3868 .family = 21,
3869 .model = 1,
3870 .stepping = 2,
3871 .features[FEAT_1_EDX] =
3872 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3873 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3874 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3875 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3876 CPUID_DE | CPUID_FP87,
3877 .features[FEAT_1_ECX] =
3878 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3879 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3880 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3881 CPUID_EXT_SSE3,
3882 .features[FEAT_8000_0001_EDX] =
3883 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3884 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3885 .features[FEAT_8000_0001_ECX] =
3886 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3887 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3888 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3889 CPUID_EXT3_LAHF_LM,
3890 .features[FEAT_SVM] =
3891 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3892 /* no xsaveopt! */
3893 .xlevel = 0x8000001A,
3894 .model_id = "AMD Opteron 62xx class CPU",
3895 },
3896 {
3897 .name = "Opteron_G5",
3898 .level = 0xd,
3899 .vendor = CPUID_VENDOR_AMD,
3900 .family = 21,
3901 .model = 2,
3902 .stepping = 0,
3903 .features[FEAT_1_EDX] =
3904 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3905 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3906 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3907 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3908 CPUID_DE | CPUID_FP87,
3909 .features[FEAT_1_ECX] =
3910 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
3911 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3912 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3913 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3914 .features[FEAT_8000_0001_EDX] =
3915 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3916 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3917 .features[FEAT_8000_0001_ECX] =
3918 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3919 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3920 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3921 CPUID_EXT3_LAHF_LM,
3922 .features[FEAT_SVM] =
3923 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3924 /* no xsaveopt! */
3925 .xlevel = 0x8000001A,
3926 .model_id = "AMD Opteron 63xx class CPU",
3927 },
3928 {
3929 .name = "EPYC",
3930 .level = 0xd,
3931 .vendor = CPUID_VENDOR_AMD,
3932 .family = 23,
3933 .model = 1,
3934 .stepping = 2,
3935 .features[FEAT_1_EDX] =
3936 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3937 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3938 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3939 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3940 CPUID_VME | CPUID_FP87,
3941 .features[FEAT_1_ECX] =
3942 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3943 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3944 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3945 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3946 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3947 .features[FEAT_8000_0001_EDX] =
3948 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3949 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3950 CPUID_EXT2_SYSCALL,
3951 .features[FEAT_8000_0001_ECX] =
3952 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3953 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3954 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3955 CPUID_EXT3_TOPOEXT,
3956 .features[FEAT_7_0_EBX] =
3957 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3958 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3959 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3960 CPUID_7_0_EBX_SHA_NI,
3961 .features[FEAT_XSAVE] =
3962 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3963 CPUID_XSAVE_XGETBV1,
3964 .features[FEAT_6_EAX] =
3965 CPUID_6_EAX_ARAT,
3966 .features[FEAT_SVM] =
3967 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3968 .xlevel = 0x8000001E,
3969 .model_id = "AMD EPYC Processor",
3970 .cache_info = &epyc_cache_info,
3971 .versions = (X86CPUVersionDefinition[]) {
3972 { .version = 1 },
3973 {
3974 .version = 2,
3975 .alias = "EPYC-IBPB",
3976 .props = (PropValue[]) {
3977 { "ibpb", "on" },
3978 { "model-id",
3979 "AMD EPYC Processor (with IBPB)" },
3980 { /* end of list */ }
3981 }
3982 },
3983 {
3984 .version = 3,
3985 .props = (PropValue[]) {
3986 { "ibpb", "on" },
3987 { "perfctr-core", "on" },
3988 { "clzero", "on" },
3989 { "xsaveerptr", "on" },
3990 { "xsaves", "on" },
3991 { "model-id",
3992 "AMD EPYC Processor" },
3993 { /* end of list */ }
3994 }
3995 },
3996 { /* end of list */ }
3997 }
3998 },
3999 {
4000 .name = "Dhyana",
4001 .level = 0xd,
4002 .vendor = CPUID_VENDOR_HYGON,
4003 .family = 24,
4004 .model = 0,
4005 .stepping = 1,
4006 .features[FEAT_1_EDX] =
4007 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4008 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4009 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4010 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4011 CPUID_VME | CPUID_FP87,
4012 .features[FEAT_1_ECX] =
4013 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4014 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4015 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4016 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4017 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4018 .features[FEAT_8000_0001_EDX] =
4019 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4020 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4021 CPUID_EXT2_SYSCALL,
4022 .features[FEAT_8000_0001_ECX] =
4023 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4024 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4025 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4026 CPUID_EXT3_TOPOEXT,
4027 .features[FEAT_8000_0008_EBX] =
4028 CPUID_8000_0008_EBX_IBPB,
4029 .features[FEAT_7_0_EBX] =
4030 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4031 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4032 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
4033 /*
4034 * Missing: XSAVES (not supported by some Linux versions,
4035 * including v4.1 to v4.12).
4036 * KVM doesn't yet expose any XSAVES state save component.
4037 */
4038 .features[FEAT_XSAVE] =
4039 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4040 CPUID_XSAVE_XGETBV1,
4041 .features[FEAT_6_EAX] =
4042 CPUID_6_EAX_ARAT,
4043 .features[FEAT_SVM] =
4044 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4045 .xlevel = 0x8000001E,
4046 .model_id = "Hygon Dhyana Processor",
4047 .cache_info = &epyc_cache_info,
4048 },
4049 {
4050 .name = "EPYC-Rome",
4051 .level = 0xd,
4052 .vendor = CPUID_VENDOR_AMD,
4053 .family = 23,
4054 .model = 49,
4055 .stepping = 0,
4056 .features[FEAT_1_EDX] =
4057 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4058 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4059 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4060 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4061 CPUID_VME | CPUID_FP87,
4062 .features[FEAT_1_ECX] =
4063 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4064 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4065 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4066 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4067 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4068 .features[FEAT_8000_0001_EDX] =
4069 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4070 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4071 CPUID_EXT2_SYSCALL,
4072 .features[FEAT_8000_0001_ECX] =
4073 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4074 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4075 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4076 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4077 .features[FEAT_8000_0008_EBX] =
4078 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4079 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4080 CPUID_8000_0008_EBX_STIBP,
4081 .features[FEAT_7_0_EBX] =
4082 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4083 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4084 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4085 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4086 .features[FEAT_7_0_ECX] =
4087 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4088 .features[FEAT_XSAVE] =
4089 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4090 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4091 .features[FEAT_6_EAX] =
4092 CPUID_6_EAX_ARAT,
4093 .features[FEAT_SVM] =
4094 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4095 .xlevel = 0x8000001E,
4096 .model_id = "AMD EPYC-Rome Processor",
4097 .cache_info = &epyc_rome_cache_info,
4098 },
4099 };
4100
4101 /* KVM-specific features that are automatically added/removed
4102 * from all CPU models when KVM is enabled.
4103 */
4104 static PropValue kvm_default_props[] = {
4105 { "kvmclock", "on" },
4106 { "kvm-nopiodelay", "on" },
4107 { "kvm-asyncpf", "on" },
4108 { "kvm-steal-time", "on" },
4109 { "kvm-pv-eoi", "on" },
4110 { "kvmclock-stable-bit", "on" },
4111 { "x2apic", "on" },
4112 { "acpi", "off" },
4113 { "monitor", "off" },
4114 { "svm", "off" },
4115 { NULL, NULL },
4116 };
4117
4118 /* TCG-specific defaults that override all CPU models when using TCG
4119 */
4120 static PropValue tcg_default_props[] = {
4121 { "vme", "off" },
4122 { NULL, NULL },
4123 };
4124
4125
4126 /*
4127 * We resolve CPU model aliases using -v1 when using "-machine
4128 * none", but this is just for compatibility while libvirt isn't
4129 * adapted to resolve CPU model versions before creating VMs.
4130 * See "Runnability guarantee of CPU models" at * qemu-deprecated.texi.
4131 */
4132 X86CPUVersion default_cpu_version = 1;
4133
4134 void x86_cpu_set_default_version(X86CPUVersion version)
4135 {
4136 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4137 assert(version != CPU_VERSION_AUTO);
4138 default_cpu_version = version;
4139 }
4140
4141 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4142 {
4143 int v = 0;
4144 const X86CPUVersionDefinition *vdef =
4145 x86_cpu_def_get_versions(model->cpudef);
4146 while (vdef->version) {
4147 v = vdef->version;
4148 vdef++;
4149 }
4150 return v;
4151 }
4152
4153 /* Return the actual version being used for a specific CPU model */
4154 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4155 {
4156 X86CPUVersion v = model->version;
4157 if (v == CPU_VERSION_AUTO) {
4158 v = default_cpu_version;
4159 }
4160 if (v == CPU_VERSION_LATEST) {
4161 return x86_cpu_model_last_version(model);
4162 }
4163 return v;
4164 }
4165
4166 void x86_cpu_change_kvm_default(const char *prop, const char *value)
4167 {
4168 PropValue *pv;
4169 for (pv = kvm_default_props; pv->prop; pv++) {
4170 if (!strcmp(pv->prop, prop)) {
4171 pv->value = value;
4172 break;
4173 }
4174 }
4175
4176 /* It is valid to call this function only for properties that
4177 * are already present in the kvm_default_props table.
4178 */
4179 assert(pv->prop);
4180 }
4181
4182 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4183 bool migratable_only);
4184
4185 static bool lmce_supported(void)
4186 {
4187 uint64_t mce_cap = 0;
4188
4189 #ifdef CONFIG_KVM
4190 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
4191 return false;
4192 }
4193 #endif
4194
4195 return !!(mce_cap & MCG_LMCE_P);
4196 }
4197
4198 #define CPUID_MODEL_ID_SZ 48
4199
4200 /**
4201 * cpu_x86_fill_model_id:
4202 * Get CPUID model ID string from host CPU.
4203 *
4204 * @str should have at least CPUID_MODEL_ID_SZ bytes
4205 *
4206 * The function does NOT add a null terminator to the string
4207 * automatically.
4208 */
4209 static int cpu_x86_fill_model_id(char *str)
4210 {
4211 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
4212 int i;
4213
4214 for (i = 0; i < 3; i++) {
4215 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
4216 memcpy(str + i * 16 + 0, &eax, 4);
4217 memcpy(str + i * 16 + 4, &ebx, 4);
4218 memcpy(str + i * 16 + 8, &ecx, 4);
4219 memcpy(str + i * 16 + 12, &edx, 4);
4220 }
4221 return 0;
4222 }
4223
4224 static Property max_x86_cpu_properties[] = {
4225 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
4226 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
4227 DEFINE_PROP_END_OF_LIST()
4228 };
4229
4230 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
4231 {
4232 DeviceClass *dc = DEVICE_CLASS(oc);
4233 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4234
4235 xcc->ordering = 9;
4236
4237 xcc->model_description =
4238 "Enables all features supported by the accelerator in the current host";
4239
4240 device_class_set_props(dc, max_x86_cpu_properties);
4241 }
4242
4243 static void max_x86_cpu_initfn(Object *obj)
4244 {
4245 X86CPU *cpu = X86_CPU(obj);
4246 CPUX86State *env = &cpu->env;
4247 KVMState *s = kvm_state;
4248
4249 /* We can't fill the features array here because we don't know yet if
4250 * "migratable" is true or false.
4251 */
4252 cpu->max_features = true;
4253
4254 if (accel_uses_host_cpuid()) {
4255 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
4256 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
4257 int family, model, stepping;
4258
4259 host_vendor_fms(vendor, &family, &model, &stepping);
4260 cpu_x86_fill_model_id(model_id);
4261
4262 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
4263 object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
4264 object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
4265 object_property_set_int(OBJECT(cpu), "stepping", stepping,
4266 &error_abort);
4267 object_property_set_str(OBJECT(cpu), "model-id", model_id,
4268 &error_abort);
4269
4270 if (kvm_enabled()) {
4271 env->cpuid_min_level =
4272 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
4273 env->cpuid_min_xlevel =
4274 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
4275 env->cpuid_min_xlevel2 =
4276 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
4277 } else {
4278 env->cpuid_min_level =
4279 hvf_get_supported_cpuid(0x0, 0, R_EAX);
4280 env->cpuid_min_xlevel =
4281 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
4282 env->cpuid_min_xlevel2 =
4283 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
4284 }
4285
4286 if (lmce_supported()) {
4287 object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
4288 }
4289 } else {
4290 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4291 &error_abort);
4292 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4293 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4294 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
4295 object_property_set_str(OBJECT(cpu), "model-id",
4296 "QEMU TCG CPU version " QEMU_HW_VERSION,
4297 &error_abort);
4298 }
4299
4300 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
4301 }
4302
4303 static const TypeInfo max_x86_cpu_type_info = {
4304 .name = X86_CPU_TYPE_NAME("max"),
4305 .parent = TYPE_X86_CPU,
4306 .instance_init = max_x86_cpu_initfn,
4307 .class_init = max_x86_cpu_class_init,
4308 };
4309
4310 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4311 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
4312 {
4313 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4314
4315 xcc->host_cpuid_required = true;
4316 xcc->ordering = 8;
4317
4318 #if defined(CONFIG_KVM)
4319 xcc->model_description =
4320 "KVM processor with all supported host features ";
4321 #elif defined(CONFIG_HVF)
4322 xcc->model_description =
4323 "HVF processor with all supported host features ";
4324 #endif
4325 }
4326
4327 static const TypeInfo host_x86_cpu_type_info = {
4328 .name = X86_CPU_TYPE_NAME("host"),
4329 .parent = X86_CPU_TYPE_NAME("max"),
4330 .class_init = host_x86_cpu_class_init,
4331 };
4332
4333 #endif
4334
4335 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4336 {
4337 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4338
4339 switch (f->type) {
4340 case CPUID_FEATURE_WORD:
4341 {
4342 const char *reg = get_register_name_32(f->cpuid.reg);
4343 assert(reg);
4344 return g_strdup_printf("CPUID.%02XH:%s",
4345 f->cpuid.eax, reg);
4346 }
4347 case MSR_FEATURE_WORD:
4348 return g_strdup_printf("MSR(%02XH)",
4349 f->msr.index);
4350 }
4351
4352 return NULL;
4353 }
4354
4355 static bool x86_cpu_have_filtered_features(X86CPU *cpu)
4356 {
4357 FeatureWord w;
4358
4359 for (w = 0; w < FEATURE_WORDS; w++) {
4360 if (cpu->filtered_features[w]) {
4361 return true;
4362 }
4363 }
4364
4365 return false;
4366 }
4367
4368 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
4369 const char *verbose_prefix)
4370 {
4371 CPUX86State *env = &cpu->env;
4372 FeatureWordInfo *f = &feature_word_info[w];
4373 int i;
4374
4375 if (!cpu->force_features) {
4376 env->features[w] &= ~mask;
4377 }
4378 cpu->filtered_features[w] |= mask;
4379
4380 if (!verbose_prefix) {
4381 return;
4382 }
4383
4384 for (i = 0; i < 64; ++i) {
4385 if ((1ULL << i) & mask) {
4386 g_autofree char *feat_word_str = feature_word_description(f, i);
4387 warn_report("%s: %s%s%s [bit %d]",
4388 verbose_prefix,
4389 feat_word_str,
4390 f->feat_names[i] ? "." : "",
4391 f->feat_names[i] ? f->feat_names[i] : "", i);
4392 }
4393 }
4394 }
4395
4396 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4397 const char *name, void *opaque,
4398 Error **errp)
4399 {
4400 X86CPU *cpu = X86_CPU(obj);
4401 CPUX86State *env = &cpu->env;
4402 int64_t value;
4403
4404 value = (env->cpuid_version >> 8) & 0xf;
4405 if (value == 0xf) {
4406 value += (env->cpuid_version >> 20) & 0xff;
4407 }
4408 visit_type_int(v, name, &value, errp);
4409 }
4410
4411 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4412 const char *name, void *opaque,
4413 Error **errp)
4414 {
4415 X86CPU *cpu = X86_CPU(obj);
4416 CPUX86State *env = &cpu->env;
4417 const int64_t min = 0;
4418 const int64_t max = 0xff + 0xf;
4419 int64_t value;
4420
4421 if (!visit_type_int(v, name, &value, errp)) {
4422 return;
4423 }
4424 if (value < min || value > max) {
4425 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4426 name ? name : "null", value, min, max);
4427 return;
4428 }
4429
4430 env->cpuid_version &= ~0xff00f00;
4431 if (value > 0x0f) {
4432 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
4433 } else {
4434 env->cpuid_version |= value << 8;
4435 }
4436 }
4437
4438 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4439 const char *name, void *opaque,
4440 Error **errp)
4441 {
4442 X86CPU *cpu = X86_CPU(obj);
4443 CPUX86State *env = &cpu->env;
4444 int64_t value;
4445
4446 value = (env->cpuid_version >> 4) & 0xf;
4447 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
4448 visit_type_int(v, name, &value, errp);
4449 }
4450
4451 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4452 const char *name, void *opaque,
4453 Error **errp)
4454 {
4455 X86CPU *cpu = X86_CPU(obj);
4456 CPUX86State *env = &cpu->env;
4457 const int64_t min = 0;
4458 const int64_t max = 0xff;
4459 int64_t value;
4460
4461 if (!visit_type_int(v, name, &value, errp)) {
4462 return;
4463 }
4464 if (value < min || value > max) {
4465 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4466 name ? name : "null", value, min, max);
4467 return;
4468 }
4469
4470 env->cpuid_version &= ~0xf00f0;
4471 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
4472 }
4473
4474 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
4475 const char *name, void *opaque,
4476 Error **errp)
4477 {
4478 X86CPU *cpu = X86_CPU(obj);
4479 CPUX86State *env = &cpu->env;
4480 int64_t value;
4481
4482 value = env->cpuid_version & 0xf;
4483 visit_type_int(v, name, &value, errp);
4484 }
4485
4486 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
4487 const char *name, void *opaque,
4488 Error **errp)
4489 {
4490 X86CPU *cpu = X86_CPU(obj);
4491 CPUX86State *env = &cpu->env;
4492 const int64_t min = 0;
4493 const int64_t max = 0xf;
4494 int64_t value;
4495
4496 if (!visit_type_int(v, name, &value, errp)) {
4497 return;
4498 }
4499 if (value < min || value > max) {
4500 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4501 name ? name : "null", value, min, max);
4502 return;
4503 }
4504
4505 env->cpuid_version &= ~0xf;
4506 env->cpuid_version |= value & 0xf;
4507 }
4508
4509 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4510 {
4511 X86CPU *cpu = X86_CPU(obj);
4512 CPUX86State *env = &cpu->env;
4513 char *value;
4514
4515 value = g_malloc(CPUID_VENDOR_SZ + 1);
4516 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4517 env->cpuid_vendor3);
4518 return value;
4519 }
4520
4521 static void x86_cpuid_set_vendor(Object *obj, const char *value,
4522 Error **errp)
4523 {
4524 X86CPU *cpu = X86_CPU(obj);
4525 CPUX86State *env = &cpu->env;
4526 int i;
4527
4528 if (strlen(value) != CPUID_VENDOR_SZ) {
4529 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
4530 return;
4531 }
4532
4533 env->cpuid_vendor1 = 0;
4534 env->cpuid_vendor2 = 0;
4535 env->cpuid_vendor3 = 0;
4536 for (i = 0; i < 4; i++) {
4537 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4538 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4539 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4540 }
4541 }
4542
4543 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4544 {
4545 X86CPU *cpu = X86_CPU(obj);
4546 CPUX86State *env = &cpu->env;
4547 char *value;
4548 int i;
4549
4550 value = g_malloc(48 + 1);
4551 for (i = 0; i < 48; i++) {
4552 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4553 }
4554 value[48] = '\0';
4555 return value;
4556 }
4557
4558 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4559 Error **errp)
4560 {
4561 X86CPU *cpu = X86_CPU(obj);
4562 CPUX86State *env = &cpu->env;
4563 int c, len, i;
4564
4565 if (model_id == NULL) {
4566 model_id = "";
4567 }
4568 len = strlen(model_id);
4569 memset(env->cpuid_model, 0, 48);
4570 for (i = 0; i < 48; i++) {
4571 if (i >= len) {
4572 c = '\0';
4573 } else {
4574 c = (uint8_t)model_id[i];
4575 }
4576 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4577 }
4578 }
4579
4580 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4581 void *opaque, Error **errp)
4582 {
4583 X86CPU *cpu = X86_CPU(obj);
4584 int64_t value;
4585
4586 value = cpu->env.tsc_khz * 1000;
4587 visit_type_int(v, name, &value, errp);
4588 }
4589
4590 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4591 void *opaque, Error **errp)
4592 {
4593 X86CPU *cpu = X86_CPU(obj);
4594 const int64_t min = 0;
4595 const int64_t max = INT64_MAX;
4596 int64_t value;
4597
4598 if (!visit_type_int(v, name, &value, errp)) {
4599 return;
4600 }
4601 if (value < min || value > max) {
4602 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4603 name ? name : "null", value, min, max);
4604 return;
4605 }
4606
4607 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
4608 }
4609
4610 /* Generic getter for "feature-words" and "filtered-features" properties */
4611 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4612 const char *name, void *opaque,
4613 Error **errp)
4614 {
4615 uint64_t *array = (uint64_t *)opaque;
4616 FeatureWord w;
4617 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4618 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4619 X86CPUFeatureWordInfoList *list = NULL;
4620
4621 for (w = 0; w < FEATURE_WORDS; w++) {
4622 FeatureWordInfo *wi = &feature_word_info[w];
4623 /*
4624 * We didn't have MSR features when "feature-words" was
4625 * introduced. Therefore skipped other type entries.
4626 */
4627 if (wi->type != CPUID_FEATURE_WORD) {
4628 continue;
4629 }
4630 X86CPUFeatureWordInfo *qwi = &word_infos[w];
4631 qwi->cpuid_input_eax = wi->cpuid.eax;
4632 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4633 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4634 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
4635 qwi->features = array[w];
4636
4637 /* List will be in reverse order, but order shouldn't matter */
4638 list_entries[w].next = list;
4639 list_entries[w].value = &word_infos[w];
4640 list = &list_entries[w];
4641 }
4642
4643 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
4644 }
4645
4646 /* Convert all '_' in a feature string option name to '-', to make feature
4647 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4648 */
4649 static inline void feat2prop(char *s)
4650 {
4651 while ((s = strchr(s, '_'))) {
4652 *s = '-';
4653 }
4654 }
4655
4656 /* Return the feature property name for a feature flag bit */
4657 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4658 {
4659 const char *name;
4660 /* XSAVE components are automatically enabled by other features,
4661 * so return the original feature name instead
4662 */
4663 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4664 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4665
4666 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4667 x86_ext_save_areas[comp].bits) {
4668 w = x86_ext_save_areas[comp].feature;
4669 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4670 }
4671 }
4672
4673 assert(bitnr < 64);
4674 assert(w < FEATURE_WORDS);
4675 name = feature_word_info[w].feat_names[bitnr];
4676 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4677 return name;
4678 }
4679
4680 /* Compatibily hack to maintain legacy +-feat semantic,
4681 * where +-feat overwrites any feature set by
4682 * feat=on|feat even if the later is parsed after +-feat
4683 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4684 */
4685 static GList *plus_features, *minus_features;
4686
4687 static gint compare_string(gconstpointer a, gconstpointer b)
4688 {
4689 return g_strcmp0(a, b);
4690 }
4691
4692 /* Parse "+feature,-feature,feature=foo" CPU feature string
4693 */
4694 static void x86_cpu_parse_featurestr(const char *typename, char *features,
4695 Error **errp)
4696 {
4697 char *featurestr; /* Single 'key=value" string being parsed */
4698 static bool cpu_globals_initialized;
4699 bool ambiguous = false;
4700
4701 if (cpu_globals_initialized) {
4702 return;
4703 }
4704 cpu_globals_initialized = true;
4705
4706 if (!features) {
4707 return;
4708 }
4709
4710 for (featurestr = strtok(features, ",");
4711 featurestr;
4712 featurestr = strtok(NULL, ",")) {
4713 const char *name;
4714 const char *val = NULL;
4715 char *eq = NULL;
4716 char num[32];
4717 GlobalProperty *prop;
4718
4719 /* Compatibility syntax: */
4720 if (featurestr[0] == '+') {
4721 plus_features = g_list_append(plus_features,
4722 g_strdup(featurestr + 1));
4723 continue;
4724 } else if (featurestr[0] == '-') {
4725 minus_features = g_list_append(minus_features,
4726 g_strdup(featurestr + 1));
4727 continue;
4728 }
4729
4730 eq = strchr(featurestr, '=');
4731 if (eq) {
4732 *eq++ = 0;
4733 val = eq;
4734 } else {
4735 val = "on";
4736 }
4737
4738 feat2prop(featurestr);
4739 name = featurestr;
4740
4741 if (g_list_find_custom(plus_features, name, compare_string)) {
4742 warn_report("Ambiguous CPU model string. "
4743 "Don't mix both \"+%s\" and \"%s=%s\"",
4744 name, name, val);
4745 ambiguous = true;
4746 }
4747 if (g_list_find_custom(minus_features, name, compare_string)) {
4748 warn_report("Ambiguous CPU model string. "
4749 "Don't mix both \"-%s\" and \"%s=%s\"",
4750 name, name, val);
4751 ambiguous = true;
4752 }
4753
4754 /* Special case: */
4755 if (!strcmp(name, "tsc-freq")) {
4756 int ret;
4757 uint64_t tsc_freq;
4758
4759 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
4760 if (ret < 0 || tsc_freq > INT64_MAX) {
4761 error_setg(errp, "bad numerical value %s", val);
4762 return;
4763 }
4764 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4765 val = num;
4766 name = "tsc-frequency";
4767 }
4768
4769 prop = g_new0(typeof(*prop), 1);
4770 prop->driver = typename;
4771 prop->property = g_strdup(name);
4772 prop->value = g_strdup(val);
4773 qdev_prop_register_global(prop);
4774 }
4775
4776 if (ambiguous) {
4777 warn_report("Compatibility of ambiguous CPU model "
4778 "strings won't be kept on future QEMU versions");
4779 }
4780 }
4781
4782 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
4783 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
4784
4785 /* Build a list with the name of all features on a feature word array */
4786 static void x86_cpu_list_feature_names(FeatureWordArray features,
4787 strList **feat_names)
4788 {
4789 FeatureWord w;
4790 strList **next = feat_names;
4791
4792 for (w = 0; w < FEATURE_WORDS; w++) {
4793 uint64_t filtered = features[w];
4794 int i;
4795 for (i = 0; i < 64; i++) {
4796 if (filtered & (1ULL << i)) {
4797 strList *new = g_new0(strList, 1);
4798 new->value = g_strdup(x86_cpu_feature_name(w, i));
4799 *next = new;
4800 next = &new->next;
4801 }
4802 }
4803 }
4804 }
4805
4806 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4807 const char *name, void *opaque,
4808 Error **errp)
4809 {
4810 X86CPU *xc = X86_CPU(obj);
4811 strList *result = NULL;
4812
4813 x86_cpu_list_feature_names(xc->filtered_features, &result);
4814 visit_type_strList(v, "unavailable-features", &result, errp);
4815 }
4816
4817 /* Check for missing features that may prevent the CPU class from
4818 * running using the current machine and accelerator.
4819 */
4820 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4821 strList **missing_feats)
4822 {
4823 X86CPU *xc;
4824 Error *err = NULL;
4825 strList **next = missing_feats;
4826
4827 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
4828 strList *new = g_new0(strList, 1);
4829 new->value = g_strdup("kvm");
4830 *missing_feats = new;
4831 return;
4832 }
4833
4834 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
4835
4836 x86_cpu_expand_features(xc, &err);
4837 if (err) {
4838 /* Errors at x86_cpu_expand_features should never happen,
4839 * but in case it does, just report the model as not
4840 * runnable at all using the "type" property.
4841 */
4842 strList *new = g_new0(strList, 1);
4843 new->value = g_strdup("type");
4844 *next = new;
4845 next = &new->next;
4846 error_free(err);
4847 }
4848
4849 x86_cpu_filter_features(xc, false);
4850
4851 x86_cpu_list_feature_names(xc->filtered_features, next);
4852
4853 object_unref(OBJECT(xc));
4854 }
4855
4856 /* Print all cpuid feature names in featureset
4857 */
4858 static void listflags(GList *features)
4859 {
4860 size_t len = 0;
4861 GList *tmp;
4862
4863 for (tmp = features; tmp; tmp = tmp->next) {
4864 const char *name = tmp->data;
4865 if ((len + strlen(name) + 1) >= 75) {
4866 qemu_printf("\n");
4867 len = 0;
4868 }
4869 qemu_printf("%s%s", len == 0 ? " " : " ", name);
4870 len += strlen(name) + 1;
4871 }
4872 qemu_printf("\n");
4873 }
4874
4875 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
4876 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4877 {
4878 ObjectClass *class_a = (ObjectClass *)a;
4879 ObjectClass *class_b = (ObjectClass *)b;
4880 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4881 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
4882 int ret;
4883
4884 if (cc_a->ordering != cc_b->ordering) {
4885 ret = cc_a->ordering - cc_b->ordering;
4886 } else {
4887 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4888 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
4889 ret = strcmp(name_a, name_b);
4890 }
4891 return ret;
4892 }
4893
4894 static GSList *get_sorted_cpu_model_list(void)
4895 {
4896 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4897 list = g_slist_sort(list, x86_cpu_list_compare);
4898 return list;
4899 }
4900
4901 static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4902 {
4903 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
4904 char *r = object_property_get_str(obj, "model-id", &error_abort);
4905 object_unref(obj);
4906 return r;
4907 }
4908
4909 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4910 {
4911 X86CPUVersion version;
4912
4913 if (!cc->model || !cc->model->is_alias) {
4914 return NULL;
4915 }
4916 version = x86_cpu_model_resolve_version(cc->model);
4917 if (version <= 0) {
4918 return NULL;
4919 }
4920 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4921 }
4922
4923 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4924 {
4925 ObjectClass *oc = data;
4926 X86CPUClass *cc = X86_CPU_CLASS(oc);
4927 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4928 g_autofree char *desc = g_strdup(cc->model_description);
4929 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
4930 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
4931
4932 if (!desc && alias_of) {
4933 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4934 desc = g_strdup("(alias configured by machine type)");
4935 } else {
4936 desc = g_strdup_printf("(alias of %s)", alias_of);
4937 }
4938 }
4939 if (!desc && cc->model && cc->model->note) {
4940 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4941 }
4942 if (!desc) {
4943 desc = g_strdup_printf("%s", model_id);
4944 }
4945
4946 qemu_printf("x86 %-20s %-58s\n", name, desc);
4947 }
4948
4949 /* list available CPU models and flags */
4950 void x86_cpu_list(void)
4951 {
4952 int i, j;
4953 GSList *list;
4954 GList *names = NULL;
4955
4956 qemu_printf("Available CPUs:\n");
4957 list = get_sorted_cpu_model_list();
4958 g_slist_foreach(list, x86_cpu_list_entry, NULL);
4959 g_slist_free(list);
4960
4961 names = NULL;
4962 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4963 FeatureWordInfo *fw = &feature_word_info[i];
4964 for (j = 0; j < 64; j++) {
4965 if (fw->feat_names[j]) {
4966 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4967 }
4968 }
4969 }
4970
4971 names = g_list_sort(names, (GCompareFunc)strcmp);
4972
4973 qemu_printf("\nRecognized CPUID flags:\n");
4974 listflags(names);
4975 qemu_printf("\n");
4976 g_list_free(names);
4977 }
4978
4979 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4980 {
4981 ObjectClass *oc = data;
4982 X86CPUClass *cc = X86_CPU_CLASS(oc);
4983 CpuDefinitionInfoList **cpu_list = user_data;
4984 CpuDefinitionInfoList *entry;
4985 CpuDefinitionInfo *info;
4986
4987 info = g_malloc0(sizeof(*info));
4988 info->name = x86_cpu_class_get_model_name(cc);
4989 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4990 info->has_unavailable_features = true;
4991 info->q_typename = g_strdup(object_class_get_name(oc));
4992 info->migration_safe = cc->migration_safe;
4993 info->has_migration_safe = true;
4994 info->q_static = cc->static_model;
4995 /*
4996 * Old machine types won't report aliases, so that alias translation
4997 * doesn't break compatibility with previous QEMU versions.
4998 */
4999 if (default_cpu_version != CPU_VERSION_LEGACY) {
5000 info->alias_of = x86_cpu_class_get_alias_of(cc);
5001 info->has_alias_of = !!info->alias_of;
5002 }
5003
5004 entry = g_malloc0(sizeof(*entry));
5005 entry->value = info;
5006 entry->next = *cpu_list;
5007 *cpu_list = entry;
5008 }
5009
5010 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
5011 {
5012 CpuDefinitionInfoList *cpu_list = NULL;
5013 GSList *list = get_sorted_cpu_model_list();
5014 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
5015 g_slist_free(list);
5016 return cpu_list;
5017 }
5018
5019 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
5020 bool migratable_only)
5021 {
5022 FeatureWordInfo *wi = &feature_word_info[w];
5023 uint64_t r = 0;
5024
5025 if (kvm_enabled()) {
5026 switch (wi->type) {
5027 case CPUID_FEATURE_WORD:
5028 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
5029 wi->cpuid.ecx,
5030 wi->cpuid.reg);
5031 break;
5032 case MSR_FEATURE_WORD:
5033 r = kvm_arch_get_supported_msr_feature(kvm_state,
5034 wi->msr.index);
5035 break;
5036 }
5037 } else if (hvf_enabled()) {
5038 if (wi->type != CPUID_FEATURE_WORD) {
5039 return 0;
5040 }
5041 r = hvf_get_supported_cpuid(wi->cpuid.eax,
5042 wi->cpuid.ecx,
5043 wi->cpuid.reg);
5044 } else if (tcg_enabled()) {
5045 r = wi->tcg_features;
5046 } else {
5047 return ~0;
5048 }
5049 if (migratable_only) {
5050 r &= x86_cpu_get_migratable_flags(w);
5051 }
5052 return r;
5053 }
5054
5055 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5056 {
5057 PropValue *pv;
5058 for (pv = props; pv->prop; pv++) {
5059 if (!pv->value) {
5060 continue;
5061 }
5062 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5063 &error_abort);
5064 }
5065 }
5066
5067 /* Apply properties for the CPU model version specified in model */
5068 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5069 {
5070 const X86CPUVersionDefinition *vdef;
5071 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5072
5073 if (version == CPU_VERSION_LEGACY) {
5074 return;
5075 }
5076
5077 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5078 PropValue *p;
5079
5080 for (p = vdef->props; p && p->prop; p++) {
5081 object_property_parse(OBJECT(cpu), p->prop, p->value,
5082 &error_abort);
5083 }
5084
5085 if (vdef->version == version) {
5086 break;
5087 }
5088 }
5089
5090 /*
5091 * If we reached the end of the list, version number was invalid
5092 */
5093 assert(vdef->version == version);
5094 }
5095
5096 /* Load data from X86CPUDefinition into a X86CPU object
5097 */
5098 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
5099 {
5100 X86CPUDefinition *def = model->cpudef;
5101 CPUX86State *env = &cpu->env;
5102 const char *vendor;
5103 char host_vendor[CPUID_VENDOR_SZ + 1];
5104 FeatureWord w;
5105
5106 /*NOTE: any property set by this function should be returned by
5107 * x86_cpu_static_props(), so static expansion of
5108 * query-cpu-model-expansion is always complete.
5109 */
5110
5111 /* CPU models only set _minimum_ values for level/xlevel: */
5112 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
5113 &error_abort);
5114 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
5115 &error_abort);
5116
5117 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5118 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5119 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
5120 &error_abort);
5121 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
5122 &error_abort);
5123 for (w = 0; w < FEATURE_WORDS; w++) {
5124 env->features[w] = def->features[w];
5125 }
5126
5127 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5128 cpu->legacy_cache = !def->cache_info;
5129
5130 /* Special cases not set in the X86CPUDefinition structs: */
5131 /* TODO: in-kernel irqchip for hvf */
5132 if (kvm_enabled()) {
5133 if (!kvm_irqchip_in_kernel()) {
5134 x86_cpu_change_kvm_default("x2apic", "off");
5135 }
5136
5137 x86_cpu_apply_props(cpu, kvm_default_props);
5138 } else if (tcg_enabled()) {
5139 x86_cpu_apply_props(cpu, tcg_default_props);
5140 }
5141
5142 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
5143
5144 /* sysenter isn't supported in compatibility mode on AMD,
5145 * syscall isn't supported in compatibility mode on Intel.
5146 * Normally we advertise the actual CPU vendor, but you can
5147 * override this using the 'vendor' property if you want to use
5148 * KVM's sysenter/syscall emulation in compatibility mode and
5149 * when doing cross vendor migration
5150 */
5151 vendor = def->vendor;
5152 if (accel_uses_host_cpuid()) {
5153 uint32_t ebx = 0, ecx = 0, edx = 0;
5154 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
5155 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
5156 vendor = host_vendor;
5157 }
5158
5159 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
5160
5161 x86_cpu_apply_version_props(cpu, model);
5162
5163 /*
5164 * Properties in versioned CPU model are not user specified features.
5165 * We can simply clear env->user_features here since it will be filled later
5166 * in x86_cpu_expand_features() based on plus_features and minus_features.
5167 */
5168 memset(&env->user_features, 0, sizeof(env->user_features));
5169 }
5170
5171 #ifndef CONFIG_USER_ONLY
5172 /* Return a QDict containing keys for all properties that can be included
5173 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
5174 * must be included in the dictionary.
5175 */
5176 static QDict *x86_cpu_static_props(void)
5177 {
5178 FeatureWord w;
5179 int i;
5180 static const char *props[] = {
5181 "min-level",
5182 "min-xlevel",
5183 "family",
5184 "model",
5185 "stepping",
5186 "model-id",
5187 "vendor",
5188 "lmce",
5189 NULL,
5190 };
5191 static QDict *d;
5192
5193 if (d) {
5194 return d;
5195 }
5196
5197 d = qdict_new();
5198 for (i = 0; props[i]; i++) {
5199 qdict_put_null(d, props[i]);
5200 }
5201
5202 for (w = 0; w < FEATURE_WORDS; w++) {
5203 FeatureWordInfo *fi = &feature_word_info[w];
5204 int bit;
5205 for (bit = 0; bit < 64; bit++) {
5206 if (!fi->feat_names[bit]) {
5207 continue;
5208 }
5209 qdict_put_null(d, fi->feat_names[bit]);
5210 }
5211 }
5212
5213 return d;
5214 }
5215
5216 /* Add an entry to @props dict, with the value for property. */
5217 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5218 {
5219 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5220 &error_abort);
5221
5222 qdict_put_obj(props, prop, value);
5223 }
5224
5225 /* Convert CPU model data from X86CPU object to a property dictionary
5226 * that can recreate exactly the same CPU model.
5227 */
5228 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5229 {
5230 QDict *sprops = x86_cpu_static_props();
5231 const QDictEntry *e;
5232
5233 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5234 const char *prop = qdict_entry_key(e);
5235 x86_cpu_expand_prop(cpu, props, prop);
5236 }
5237 }
5238
5239 /* Convert CPU model data from X86CPU object to a property dictionary
5240 * that can recreate exactly the same CPU model, including every
5241 * writeable QOM property.
5242 */
5243 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5244 {
5245 ObjectPropertyIterator iter;
5246 ObjectProperty *prop;
5247
5248 object_property_iter_init(&iter, OBJECT(cpu));
5249 while ((prop = object_property_iter_next(&iter))) {
5250 /* skip read-only or write-only properties */
5251 if (!prop->get || !prop->set) {
5252 continue;
5253 }
5254
5255 /* "hotplugged" is the only property that is configurable
5256 * on the command-line but will be set differently on CPUs
5257 * created using "-cpu ... -smp ..." and by CPUs created
5258 * on the fly by x86_cpu_from_model() for querying. Skip it.
5259 */
5260 if (!strcmp(prop->name, "hotplugged")) {
5261 continue;
5262 }
5263 x86_cpu_expand_prop(cpu, props, prop->name);
5264 }
5265 }
5266
5267 static void object_apply_props(Object *obj, QDict *props, Error **errp)
5268 {
5269 const QDictEntry *prop;
5270
5271 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
5272 if (!object_property_set_qobject(obj, qdict_entry_key(prop),
5273 qdict_entry_value(prop), errp)) {
5274 break;
5275 }
5276 }
5277 }
5278
5279 /* Create X86CPU object according to model+props specification */
5280 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5281 {
5282 X86CPU *xc = NULL;
5283 X86CPUClass *xcc;
5284 Error *err = NULL;
5285
5286 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5287 if (xcc == NULL) {
5288 error_setg(&err, "CPU model '%s' not found", model);
5289 goto out;
5290 }
5291
5292 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5293 if (props) {
5294 object_apply_props(OBJECT(xc), props, &err);
5295 if (err) {
5296 goto out;
5297 }
5298 }
5299
5300 x86_cpu_expand_features(xc, &err);
5301 if (err) {
5302 goto out;
5303 }
5304
5305 out:
5306 if (err) {
5307 error_propagate(errp, err);
5308 object_unref(OBJECT(xc));
5309 xc = NULL;
5310 }
5311 return xc;
5312 }
5313
5314 CpuModelExpansionInfo *
5315 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
5316 CpuModelInfo *model,
5317 Error **errp)
5318 {
5319 X86CPU *xc = NULL;
5320 Error *err = NULL;
5321 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5322 QDict *props = NULL;
5323 const char *base_name;
5324
5325 xc = x86_cpu_from_model(model->name,
5326 model->has_props ?
5327 qobject_to(QDict, model->props) :
5328 NULL, &err);
5329 if (err) {
5330 goto out;
5331 }
5332
5333 props = qdict_new();
5334 ret->model = g_new0(CpuModelInfo, 1);
5335 ret->model->props = QOBJECT(props);
5336 ret->model->has_props = true;
5337
5338 switch (type) {
5339 case CPU_MODEL_EXPANSION_TYPE_STATIC:
5340 /* Static expansion will be based on "base" only */
5341 base_name = "base";
5342 x86_cpu_to_dict(xc, props);
5343 break;
5344 case CPU_MODEL_EXPANSION_TYPE_FULL:
5345 /* As we don't return every single property, full expansion needs
5346 * to keep the original model name+props, and add extra
5347 * properties on top of that.
5348 */
5349 base_name = model->name;
5350 x86_cpu_to_dict_full(xc, props);
5351 break;
5352 default:
5353 error_setg(&err, "Unsupported expansion type");
5354 goto out;
5355 }
5356
5357 x86_cpu_to_dict(xc, props);
5358
5359 ret->model->name = g_strdup(base_name);
5360
5361 out:
5362 object_unref(OBJECT(xc));
5363 if (err) {
5364 error_propagate(errp, err);
5365 qapi_free_CpuModelExpansionInfo(ret);
5366 ret = NULL;
5367 }
5368 return ret;
5369 }
5370 #endif /* !CONFIG_USER_ONLY */
5371
5372 static gchar *x86_gdb_arch_name(CPUState *cs)
5373 {
5374 #ifdef TARGET_X86_64
5375 return g_strdup("i386:x86-64");
5376 #else
5377 return g_strdup("i386");
5378 #endif
5379 }
5380
5381 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5382 {
5383 X86CPUModel *model = data;
5384 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5385
5386 xcc->model = model;
5387 xcc->migration_safe = true;
5388 }
5389
5390 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
5391 {
5392 g_autofree char *typename = x86_cpu_type_name(name);
5393 TypeInfo ti = {
5394 .name = typename,
5395 .parent = TYPE_X86_CPU,
5396 .class_init = x86_cpu_cpudef_class_init,
5397 .class_data = model,
5398 };
5399
5400 type_register(&ti);
5401 }
5402
5403 static void x86_register_cpudef_types(X86CPUDefinition *def)
5404 {
5405 X86CPUModel *m;
5406 const X86CPUVersionDefinition *vdef;
5407
5408 /* AMD aliases are handled at runtime based on CPUID vendor, so
5409 * they shouldn't be set on the CPU model table.
5410 */
5411 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
5412 /* catch mistakes instead of silently truncating model_id when too long */
5413 assert(def->model_id && strlen(def->model_id) <= 48);
5414
5415 /* Unversioned model: */
5416 m = g_new0(X86CPUModel, 1);
5417 m->cpudef = def;
5418 m->version = CPU_VERSION_AUTO;
5419 m->is_alias = true;
5420 x86_register_cpu_model_type(def->name, m);
5421
5422 /* Versioned models: */
5423
5424 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5425 X86CPUModel *m = g_new0(X86CPUModel, 1);
5426 g_autofree char *name =
5427 x86_cpu_versioned_model_name(def, vdef->version);
5428 m->cpudef = def;
5429 m->version = vdef->version;
5430 m->note = vdef->note;
5431 x86_register_cpu_model_type(name, m);
5432
5433 if (vdef->alias) {
5434 X86CPUModel *am = g_new0(X86CPUModel, 1);
5435 am->cpudef = def;
5436 am->version = vdef->version;
5437 am->is_alias = true;
5438 x86_register_cpu_model_type(vdef->alias, am);
5439 }
5440 }
5441
5442 }
5443
5444 #if !defined(CONFIG_USER_ONLY)
5445
5446 void cpu_clear_apic_feature(CPUX86State *env)
5447 {
5448 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
5449 }
5450
5451 #endif /* !CONFIG_USER_ONLY */
5452
5453 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5454 uint32_t *eax, uint32_t *ebx,
5455 uint32_t *ecx, uint32_t *edx)
5456 {
5457 X86CPU *cpu = env_archcpu(env);
5458 CPUState *cs = env_cpu(env);
5459 uint32_t die_offset;
5460 uint32_t limit;
5461 uint32_t signature[3];
5462 X86CPUTopoInfo topo_info;
5463
5464 topo_info.dies_per_pkg = env->nr_dies;
5465 topo_info.cores_per_die = cs->nr_cores;
5466 topo_info.threads_per_core = cs->nr_threads;
5467
5468 /* Calculate & apply limits for different index ranges */
5469 if (index >= 0xC0000000) {
5470 limit = env->cpuid_xlevel2;
5471 } else if (index >= 0x80000000) {
5472 limit = env->cpuid_xlevel;
5473 } else if (index >= 0x40000000) {
5474 limit = 0x40000001;
5475 } else {
5476 limit = env->cpuid_level;
5477 }
5478
5479 if (index > limit) {
5480 /* Intel documentation states that invalid EAX input will
5481 * return the same information as EAX=cpuid_level
5482 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5483 */
5484 index = env->cpuid_level;
5485 }
5486
5487 switch(index) {
5488 case 0:
5489 *eax = env->cpuid_level;
5490 *ebx = env->cpuid_vendor1;
5491 *edx = env->cpuid_vendor2;
5492 *ecx = env->cpuid_vendor3;
5493 break;
5494 case 1:
5495 *eax = env->cpuid_version;
5496 *ebx = (cpu->apic_id << 24) |
5497 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5498 *ecx = env->features[FEAT_1_ECX];
5499 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5500 *ecx |= CPUID_EXT_OSXSAVE;
5501 }
5502 *edx = env->features[FEAT_1_EDX];
5503 if (cs->nr_cores * cs->nr_threads > 1) {
5504 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
5505 *edx |= CPUID_HT;
5506 }
5507 if (!cpu->enable_pmu) {
5508 *ecx &= ~CPUID_EXT_PDCM;
5509 }
5510 break;
5511 case 2:
5512 /* cache info: needed for Pentium Pro compatibility */
5513 if (cpu->cache_info_passthrough) {
5514 host_cpuid(index, 0, eax, ebx, ecx, edx);
5515 break;
5516 }
5517 *eax = 1; /* Number of CPUID[EAX=2] calls required */
5518 *ebx = 0;
5519 if (!cpu->enable_l3_cache) {
5520 *ecx = 0;
5521 } else {
5522 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
5523 }
5524 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5525 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5526 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
5527 break;
5528 case 4:
5529 /* cache info: needed for Core compatibility */
5530 if (cpu->cache_info_passthrough) {
5531 host_cpuid(index, count, eax, ebx, ecx, edx);
5532 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
5533 *eax &= ~0xFC000000;
5534 if ((*eax & 31) && cs->nr_cores > 1) {
5535 *eax |= (cs->nr_cores - 1) << 26;
5536 }
5537 } else {
5538 *eax = 0;
5539 switch (count) {
5540 case 0: /* L1 dcache info */
5541 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5542 1, cs->nr_cores,
5543 eax, ebx, ecx, edx);
5544 break;
5545 case 1: /* L1 icache info */
5546 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5547 1, cs->nr_cores,
5548 eax, ebx, ecx, edx);
5549 break;
5550 case 2: /* L2 cache info */
5551 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5552 cs->nr_threads, cs->nr_cores,
5553 eax, ebx, ecx, edx);
5554 break;
5555 case 3: /* L3 cache info */
5556 die_offset = apicid_die_offset(&topo_info);
5557 if (cpu->enable_l3_cache) {
5558 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
5559 (1 << die_offset), cs->nr_cores,
5560 eax, ebx, ecx, edx);
5561 break;
5562 }
5563 /* fall through */
5564 default: /* end of info */
5565 *eax = *ebx = *ecx = *edx = 0;
5566 break;
5567 }
5568 }
5569 break;
5570 case 5:
5571 /* MONITOR/MWAIT Leaf */
5572 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5573 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5574 *ecx = cpu->mwait.ecx; /* flags */
5575 *edx = cpu->mwait.edx; /* mwait substates */
5576 break;
5577 case 6:
5578 /* Thermal and Power Leaf */
5579 *eax = env->features[FEAT_6_EAX];
5580 *ebx = 0;
5581 *ecx = 0;
5582 *edx = 0;
5583 break;
5584 case 7:
5585 /* Structured Extended Feature Flags Enumeration Leaf */
5586 if (count == 0) {
5587 /* Maximum ECX value for sub-leaves */
5588 *eax = env->cpuid_level_func7;
5589 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
5590 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
5591 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5592 *ecx |= CPUID_7_0_ECX_OSPKE;
5593 }
5594 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
5595 } else if (count == 1) {
5596 *eax = env->features[FEAT_7_1_EAX];
5597 *ebx = 0;
5598 *ecx = 0;
5599 *edx = 0;
5600 } else {
5601 *eax = 0;
5602 *ebx = 0;
5603 *ecx = 0;
5604 *edx = 0;
5605 }
5606 break;
5607 case 9:
5608 /* Direct Cache Access Information Leaf */
5609 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5610 *ebx = 0;
5611 *ecx = 0;
5612 *edx = 0;
5613 break;
5614 case 0xA:
5615 /* Architectural Performance Monitoring Leaf */
5616 if (kvm_enabled() && cpu->enable_pmu) {
5617 KVMState *s = cs->kvm_state;
5618
5619 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5620 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5621 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5622 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
5623 } else if (hvf_enabled() && cpu->enable_pmu) {
5624 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5625 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5626 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5627 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
5628 } else {
5629 *eax = 0;
5630 *ebx = 0;
5631 *ecx = 0;
5632 *edx = 0;
5633 }
5634 break;
5635 case 0xB:
5636 /* Extended Topology Enumeration Leaf */
5637 if (!cpu->enable_cpuid_0xb) {
5638 *eax = *ebx = *ecx = *edx = 0;
5639 break;
5640 }
5641
5642 *ecx = count & 0xff;
5643 *edx = cpu->apic_id;
5644
5645 switch (count) {
5646 case 0:
5647 *eax = apicid_core_offset(&topo_info);
5648 *ebx = cs->nr_threads;
5649 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5650 break;
5651 case 1:
5652 *eax = apicid_pkg_offset(&topo_info);
5653 *ebx = cs->nr_cores * cs->nr_threads;
5654 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5655 break;
5656 default:
5657 *eax = 0;
5658 *ebx = 0;
5659 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5660 }
5661
5662 assert(!(*eax & ~0x1f));
5663 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5664 break;
5665 case 0x1F:
5666 /* V2 Extended Topology Enumeration Leaf */
5667 if (env->nr_dies < 2) {
5668 *eax = *ebx = *ecx = *edx = 0;
5669 break;
5670 }
5671
5672 *ecx = count & 0xff;
5673 *edx = cpu->apic_id;
5674 switch (count) {
5675 case 0:
5676 *eax = apicid_core_offset(&topo_info);
5677 *ebx = cs->nr_threads;
5678 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5679 break;
5680 case 1:
5681 *eax = apicid_die_offset(&topo_info);
5682 *ebx = cs->nr_cores * cs->nr_threads;
5683 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5684 break;
5685 case 2:
5686 *eax = apicid_pkg_offset(&topo_info);
5687 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5688 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5689 break;
5690 default:
5691 *eax = 0;
5692 *ebx = 0;
5693 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5694 }
5695 assert(!(*eax & ~0x1f));
5696 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5697 break;
5698 case 0xD: {
5699 /* Processor Extended State */
5700 *eax = 0;
5701 *ebx = 0;
5702 *ecx = 0;
5703 *edx = 0;
5704 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
5705 break;
5706 }
5707
5708 if (count == 0) {
5709 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5710 *eax = env->features[FEAT_XSAVE_COMP_LO];
5711 *edx = env->features[FEAT_XSAVE_COMP_HI];
5712 /*
5713 * The initial value of xcr0 and ebx == 0, On host without kvm
5714 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5715 * even through guest update xcr0, this will crash some legacy guest
5716 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5717 */
5718 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
5719 } else if (count == 1) {
5720 *eax = env->features[FEAT_XSAVE];
5721 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
5722 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5723 const ExtSaveArea *esa = &x86_ext_save_areas[count];
5724 *eax = esa->size;
5725 *ebx = esa->offset;
5726 }
5727 }
5728 break;
5729 }
5730 case 0x14: {
5731 /* Intel Processor Trace Enumeration */
5732 *eax = 0;
5733 *ebx = 0;
5734 *ecx = 0;
5735 *edx = 0;
5736 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5737 !kvm_enabled()) {
5738 break;
5739 }
5740
5741 if (count == 0) {
5742 *eax = INTEL_PT_MAX_SUBLEAF;
5743 *ebx = INTEL_PT_MINIMAL_EBX;
5744 *ecx = INTEL_PT_MINIMAL_ECX;
5745 } else if (count == 1) {
5746 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5747 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5748 }
5749 break;
5750 }
5751 case 0x40000000:
5752 /*
5753 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5754 * set here, but we restrict to TCG none the less.
5755 */
5756 if (tcg_enabled() && cpu->expose_tcg) {
5757 memcpy(signature, "TCGTCGTCGTCG", 12);
5758 *eax = 0x40000001;
5759 *ebx = signature[0];
5760 *ecx = signature[1];
5761 *edx = signature[2];
5762 } else {
5763 *eax = 0;
5764 *ebx = 0;
5765 *ecx = 0;
5766 *edx = 0;
5767 }
5768 break;
5769 case 0x40000001:
5770 *eax = 0;
5771 *ebx = 0;
5772 *ecx = 0;
5773 *edx = 0;
5774 break;
5775 case 0x80000000:
5776 *eax = env->cpuid_xlevel;
5777 *ebx = env->cpuid_vendor1;
5778 *edx = env->cpuid_vendor2;
5779 *ecx = env->cpuid_vendor3;
5780 break;
5781 case 0x80000001:
5782 *eax = env->cpuid_version;
5783 *ebx = 0;
5784 *ecx = env->features[FEAT_8000_0001_ECX];
5785 *edx = env->features[FEAT_8000_0001_EDX];
5786
5787 /* The Linux kernel checks for the CMPLegacy bit and
5788 * discards multiple thread information if it is set.
5789 * So don't set it here for Intel to make Linux guests happy.
5790 */
5791 if (cs->nr_cores * cs->nr_threads > 1) {
5792 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5793 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5794 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
5795 *ecx |= 1 << 1; /* CmpLegacy bit */
5796 }
5797 }
5798 break;
5799 case 0x80000002:
5800 case 0x80000003:
5801 case 0x80000004:
5802 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5803 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5804 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5805 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5806 break;
5807 case 0x80000005:
5808 /* cache info (L1 cache) */
5809 if (cpu->cache_info_passthrough) {
5810 host_cpuid(index, 0, eax, ebx, ecx, edx);
5811 break;
5812 }
5813 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5814 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
5815 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5816 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
5817 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5818 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
5819 break;
5820 case 0x80000006:
5821 /* cache info (L2 cache) */
5822 if (cpu->cache_info_passthrough) {
5823 host_cpuid(index, 0, eax, ebx, ecx, edx);
5824 break;
5825 }
5826 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5827 (L2_DTLB_2M_ENTRIES << 16) |
5828 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5829 (L2_ITLB_2M_ENTRIES);
5830 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5831 (L2_DTLB_4K_ENTRIES << 16) |
5832 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5833 (L2_ITLB_4K_ENTRIES);
5834 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5835 cpu->enable_l3_cache ?
5836 env->cache_info_amd.l3_cache : NULL,
5837 ecx, edx);
5838 break;
5839 case 0x80000007:
5840 *eax = 0;
5841 *ebx = 0;
5842 *ecx = 0;
5843 *edx = env->features[FEAT_8000_0007_EDX];
5844 break;
5845 case 0x80000008:
5846 /* virtual & phys address size in low 2 bytes. */
5847 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5848 /* 64 bit processor */
5849 *eax = cpu->phys_bits; /* configurable physical bits */
5850 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5851 *eax |= 0x00003900; /* 57 bits virtual */
5852 } else {
5853 *eax |= 0x00003000; /* 48 bits virtual */
5854 }
5855 } else {
5856 *eax = cpu->phys_bits;
5857 }
5858 *ebx = env->features[FEAT_8000_0008_EBX];
5859 if (cs->nr_cores * cs->nr_threads > 1) {
5860 /*
5861 * Bits 15:12 is "The number of bits in the initial
5862 * Core::X86::Apic::ApicId[ApicId] value that indicate
5863 * thread ID within a package".
5864 * Bits 7:0 is "The number of threads in the package is NC+1"
5865 */
5866 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
5867 ((cs->nr_cores * cs->nr_threads) - 1);
5868 } else {
5869 *ecx = 0;
5870 }
5871 *edx = 0;
5872 break;
5873 case 0x8000000A:
5874 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5875 *eax = 0x00000001; /* SVM Revision */
5876 *ebx = 0x00000010; /* nr of ASIDs */
5877 *ecx = 0;
5878 *edx = env->features[FEAT_SVM]; /* optional features */
5879 } else {
5880 *eax = 0;
5881 *ebx = 0;
5882 *ecx = 0;
5883 *edx = 0;
5884 }
5885 break;
5886 case 0x8000001D:
5887 *eax = 0;
5888 if (cpu->cache_info_passthrough) {
5889 host_cpuid(index, count, eax, ebx, ecx, edx);
5890 break;
5891 }
5892 switch (count) {
5893 case 0: /* L1 dcache info */
5894 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5895 &topo_info, eax, ebx, ecx, edx);
5896 break;
5897 case 1: /* L1 icache info */
5898 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5899 &topo_info, eax, ebx, ecx, edx);
5900 break;
5901 case 2: /* L2 cache info */
5902 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5903 &topo_info, eax, ebx, ecx, edx);
5904 break;
5905 case 3: /* L3 cache info */
5906 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5907 &topo_info, eax, ebx, ecx, edx);
5908 break;
5909 default: /* end of info */
5910 *eax = *ebx = *ecx = *edx = 0;
5911 break;
5912 }
5913 break;
5914 case 0x8000001E:
5915 assert(cpu->core_id <= 255);
5916 encode_topo_cpuid8000001e(cpu, &topo_info,
5917 eax, ebx, ecx, edx);
5918 break;
5919 case 0xC0000000:
5920 *eax = env->cpuid_xlevel2;
5921 *ebx = 0;
5922 *ecx = 0;
5923 *edx = 0;
5924 break;
5925 case 0xC0000001:
5926 /* Support for VIA CPU's CPUID instruction */
5927 *eax = env->cpuid_version;
5928 *ebx = 0;
5929 *ecx = 0;
5930 *edx = env->features[FEAT_C000_0001_EDX];
5931 break;
5932 case 0xC0000002:
5933 case 0xC0000003:
5934 case 0xC0000004:
5935 /* Reserved for the future, and now filled with zero */
5936 *eax = 0;
5937 *ebx = 0;
5938 *ecx = 0;
5939 *edx = 0;
5940 break;
5941 case 0x8000001F:
5942 *eax = sev_enabled() ? 0x2 : 0;
5943 *ebx = sev_get_cbit_position();
5944 *ebx |= sev_get_reduced_phys_bits() << 6;
5945 *ecx = 0;
5946 *edx = 0;
5947 break;
5948 default:
5949 /* reserved values: zero */
5950 *eax = 0;
5951 *ebx = 0;
5952 *ecx = 0;
5953 *edx = 0;
5954 break;
5955 }
5956 }
5957
5958 static void x86_cpu_reset(DeviceState *dev)
5959 {
5960 CPUState *s = CPU(dev);
5961 X86CPU *cpu = X86_CPU(s);
5962 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5963 CPUX86State *env = &cpu->env;
5964 target_ulong cr4;
5965 uint64_t xcr0;
5966 int i;
5967
5968 xcc->parent_reset(dev);
5969
5970 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
5971
5972 env->old_exception = -1;
5973
5974 /* init to reset state */
5975
5976 env->hflags2 |= HF2_GIF_MASK;
5977 env->hflags &= ~HF_GUEST_MASK;
5978
5979 cpu_x86_update_cr0(env, 0x60000010);
5980 env->a20_mask = ~0x0;
5981 env->smbase = 0x30000;
5982 env->msr_smi_count = 0;
5983
5984 env->idt.limit = 0xffff;
5985 env->gdt.limit = 0xffff;
5986 env->ldt.limit = 0xffff;
5987 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5988 env->tr.limit = 0xffff;
5989 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5990
5991 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5992 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5993 DESC_R_MASK | DESC_A_MASK);
5994 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5995 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5996 DESC_A_MASK);
5997 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5998 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5999 DESC_A_MASK);
6000 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
6001 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6002 DESC_A_MASK);
6003 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
6004 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6005 DESC_A_MASK);
6006 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
6007 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6008 DESC_A_MASK);
6009
6010 env->eip = 0xfff0;
6011 env->regs[R_EDX] = env->cpuid_version;
6012
6013 env->eflags = 0x2;
6014
6015 /* FPU init */
6016 for (i = 0; i < 8; i++) {
6017 env->fptags[i] = 1;
6018 }
6019 cpu_set_fpuc(env, 0x37f);
6020
6021 env->mxcsr = 0x1f80;
6022 /* All units are in INIT state. */
6023 env->xstate_bv = 0;
6024
6025 env->pat = 0x0007040600070406ULL;
6026 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
6027 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
6028 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
6029 }
6030
6031 memset(env->dr, 0, sizeof(env->dr));
6032 env->dr[6] = DR6_FIXED_1;
6033 env->dr[7] = DR7_FIXED_1;
6034 cpu_breakpoint_remove_all(s, BP_CPU);
6035 cpu_watchpoint_remove_all(s, BP_CPU);
6036
6037 cr4 = 0;
6038 xcr0 = XSTATE_FP_MASK;
6039
6040 #ifdef CONFIG_USER_ONLY
6041 /* Enable all the features for user-mode. */
6042 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
6043 xcr0 |= XSTATE_SSE_MASK;
6044 }
6045 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6046 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6047 if (env->features[esa->feature] & esa->bits) {
6048 xcr0 |= 1ull << i;
6049 }
6050 }
6051
6052 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6053 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6054 }
6055 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6056 cr4 |= CR4_FSGSBASE_MASK;
6057 }
6058 #endif
6059
6060 env->xcr0 = xcr0;
6061 cpu_x86_update_cr4(env, cr4);
6062
6063 /*
6064 * SDM 11.11.5 requires:
6065 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6066 * - IA32_MTRR_PHYSMASKn.V = 0
6067 * All other bits are undefined. For simplification, zero it all.
6068 */
6069 env->mtrr_deftype = 0;
6070 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6071 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6072
6073 env->interrupt_injected = -1;
6074 env->exception_nr = -1;
6075 env->exception_pending = 0;
6076 env->exception_injected = 0;
6077 env->exception_has_payload = false;
6078 env->exception_payload = 0;
6079 env->nmi_injected = false;
6080 #if !defined(CONFIG_USER_ONLY)
6081 /* We hard-wire the BSP to the first CPU. */
6082 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
6083
6084 s->halted = !cpu_is_bsp(cpu);
6085
6086 if (kvm_enabled()) {
6087 kvm_arch_reset_vcpu(cpu);
6088 }
6089 #endif
6090 }
6091
6092 #ifndef CONFIG_USER_ONLY
6093 bool cpu_is_bsp(X86CPU *cpu)
6094 {
6095 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
6096 }
6097
6098 /* TODO: remove me, when reset over QOM tree is implemented */
6099 static void x86_cpu_machine_reset_cb(void *opaque)
6100 {
6101 X86CPU *cpu = opaque;
6102 cpu_reset(CPU(cpu));
6103 }
6104 #endif
6105
6106 static void mce_init(X86CPU *cpu)
6107 {
6108 CPUX86State *cenv = &cpu->env;
6109 unsigned int bank;
6110
6111 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
6112 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
6113 (CPUID_MCE | CPUID_MCA)) {
6114 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6115 (cpu->enable_lmce ? MCG_LMCE_P : 0);
6116 cenv->mcg_ctl = ~(uint64_t)0;
6117 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6118 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6119 }
6120 }
6121 }
6122
6123 #ifndef CONFIG_USER_ONLY
6124 APICCommonClass *apic_get_class(void)
6125 {
6126 const char *apic_type = "apic";
6127
6128 /* TODO: in-kernel irqchip for hvf */
6129 if (kvm_apic_in_kernel()) {
6130 apic_type = "kvm-apic";
6131 } else if (xen_enabled()) {
6132 apic_type = "xen-apic";
6133 }
6134
6135 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6136 }
6137
6138 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6139 {
6140 APICCommonState *apic;
6141 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6142
6143 cpu->apic_state = DEVICE(object_new_with_class(apic_class));
6144
6145 object_property_add_child(OBJECT(cpu), "lapic",
6146 OBJECT(cpu->apic_state));
6147 object_unref(OBJECT(cpu->apic_state));
6148
6149 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
6150 /* TODO: convert to link<> */
6151 apic = APIC_COMMON(cpu->apic_state);
6152 apic->cpu = cpu;
6153 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
6154 }
6155
6156 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6157 {
6158 APICCommonState *apic;
6159 static bool apic_mmio_map_once;
6160
6161 if (cpu->apic_state == NULL) {
6162 return;
6163 }
6164 qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
6165
6166 /* Map APIC MMIO area */
6167 apic = APIC_COMMON(cpu->apic_state);
6168 if (!apic_mmio_map_once) {
6169 memory_region_add_subregion_overlap(get_system_memory(),
6170 apic->apicbase &
6171 MSR_IA32_APICBASE_BASE,
6172 &apic->io_memory,
6173 0x1000);
6174 apic_mmio_map_once = true;
6175 }
6176 }
6177
6178 static void x86_cpu_machine_done(Notifier *n, void *unused)
6179 {
6180 X86CPU *cpu = container_of(n, X86CPU, machine_done);
6181 MemoryRegion *smram =
6182 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
6183
6184 if (smram) {
6185 cpu->smram = g_new(MemoryRegion, 1);
6186 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
6187 smram, 0, 4 * GiB);
6188 memory_region_set_enabled(cpu->smram, true);
6189 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
6190 }
6191 }
6192 #else
6193 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6194 {
6195 }
6196 #endif
6197
6198 /* Note: Only safe for use on x86(-64) hosts */
6199 static uint32_t x86_host_phys_bits(void)
6200 {
6201 uint32_t eax;
6202 uint32_t host_phys_bits;
6203
6204 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
6205 if (eax >= 0x80000008) {
6206 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
6207 /* Note: According to AMD doc 25481 rev 2.34 they have a field
6208 * at 23:16 that can specify a maximum physical address bits for
6209 * the guest that can override this value; but I've not seen
6210 * anything with that set.
6211 */
6212 host_phys_bits = eax & 0xff;
6213 } else {
6214 /* It's an odd 64 bit machine that doesn't have the leaf for
6215 * physical address bits; fall back to 36 that's most older
6216 * Intel.
6217 */
6218 host_phys_bits = 36;
6219 }
6220
6221 return host_phys_bits;
6222 }
6223
6224 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6225 {
6226 if (*min < value) {
6227 *min = value;
6228 }
6229 }
6230
6231 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6232 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6233 {
6234 CPUX86State *env = &cpu->env;
6235 FeatureWordInfo *fi = &feature_word_info[w];
6236 uint32_t eax = fi->cpuid.eax;
6237 uint32_t region = eax & 0xF0000000;
6238
6239 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
6240 if (!env->features[w]) {
6241 return;
6242 }
6243
6244 switch (region) {
6245 case 0x00000000:
6246 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6247 break;
6248 case 0x80000000:
6249 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6250 break;
6251 case 0xC0000000:
6252 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6253 break;
6254 }
6255
6256 if (eax == 7) {
6257 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6258 fi->cpuid.ecx);
6259 }
6260 }
6261
6262 /* Calculate XSAVE components based on the configured CPU feature flags */
6263 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6264 {
6265 CPUX86State *env = &cpu->env;
6266 int i;
6267 uint64_t mask;
6268
6269 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6270 return;
6271 }
6272
6273 mask = 0;
6274 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6275 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6276 if (env->features[esa->feature] & esa->bits) {
6277 mask |= (1ULL << i);
6278 }
6279 }
6280
6281 env->features[FEAT_XSAVE_COMP_LO] = mask;
6282 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
6283 }
6284
6285 /***** Steps involved on loading and filtering CPUID data
6286 *
6287 * When initializing and realizing a CPU object, the steps
6288 * involved in setting up CPUID data are:
6289 *
6290 * 1) Loading CPU model definition (X86CPUDefinition). This is
6291 * implemented by x86_cpu_load_model() and should be completely
6292 * transparent, as it is done automatically by instance_init.
6293 * No code should need to look at X86CPUDefinition structs
6294 * outside instance_init.
6295 *
6296 * 2) CPU expansion. This is done by realize before CPUID
6297 * filtering, and will make sure host/accelerator data is
6298 * loaded for CPU models that depend on host capabilities
6299 * (e.g. "host"). Done by x86_cpu_expand_features().
6300 *
6301 * 3) CPUID filtering. This initializes extra data related to
6302 * CPUID, and checks if the host supports all capabilities
6303 * required by the CPU. Runnability of a CPU model is
6304 * determined at this step. Done by x86_cpu_filter_features().
6305 *
6306 * Some operations don't require all steps to be performed.
6307 * More precisely:
6308 *
6309 * - CPU instance creation (instance_init) will run only CPU
6310 * model loading. CPU expansion can't run at instance_init-time
6311 * because host/accelerator data may be not available yet.
6312 * - CPU realization will perform both CPU model expansion and CPUID
6313 * filtering, and return an error in case one of them fails.
6314 * - query-cpu-definitions needs to run all 3 steps. It needs
6315 * to run CPUID filtering, as the 'unavailable-features'
6316 * field is set based on the filtering results.
6317 * - The query-cpu-model-expansion QMP command only needs to run
6318 * CPU model loading and CPU expansion. It should not filter
6319 * any CPUID data based on host capabilities.
6320 */
6321
6322 /* Expand CPU configuration data, based on configured features
6323 * and host/accelerator capabilities when appropriate.
6324 */
6325 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
6326 {
6327 CPUX86State *env = &cpu->env;
6328 FeatureWord w;
6329 int i;
6330 GList *l;
6331
6332 for (l = plus_features; l; l = l->next) {
6333 const char *prop = l->data;
6334 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6335 return;
6336 }
6337 }
6338
6339 for (l = minus_features; l; l = l->next) {
6340 const char *prop = l->data;
6341 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6342 return;
6343 }
6344 }
6345
6346 /*TODO: Now cpu->max_features doesn't overwrite features
6347 * set using QOM properties, and we can convert
6348 * plus_features & minus_features to global properties
6349 * inside x86_cpu_parse_featurestr() too.
6350 */
6351 if (cpu->max_features) {
6352 for (w = 0; w < FEATURE_WORDS; w++) {
6353 /* Override only features that weren't set explicitly
6354 * by the user.
6355 */
6356 env->features[w] |=
6357 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
6358 ~env->user_features[w] &
6359 ~feature_word_info[w].no_autoenable_flags;
6360 }
6361 }
6362
6363 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6364 FeatureDep *d = &feature_dependencies[i];
6365 if (!(env->features[d->from.index] & d->from.mask)) {
6366 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
6367
6368 /* Not an error unless the dependent feature was added explicitly. */
6369 mark_unavailable_features(cpu, d->to.index,
6370 unavailable_features & env->user_features[d->to.index],
6371 "This feature depends on other features that were not requested");
6372
6373 env->features[d->to.index] &= ~unavailable_features;
6374 }
6375 }
6376
6377 if (!kvm_enabled() || !cpu->expose_kvm) {
6378 env->features[FEAT_KVM] = 0;
6379 }
6380
6381 x86_cpu_enable_xsave_components(cpu);
6382
6383 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6384 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6385 if (cpu->full_cpuid_auto_level) {
6386 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6387 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6388 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6389 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
6390 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
6391 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6392 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6393 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
6394 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
6395 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6396 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6397 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
6398
6399 /* Intel Processor Trace requires CPUID[0x14] */
6400 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6401 if (cpu->intel_pt_auto_level) {
6402 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6403 } else if (cpu->env.cpuid_min_level < 0x14) {
6404 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6405 CPUID_7_0_EBX_INTEL_PT,
6406 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,min-level=0x14\"");
6407 }
6408 }
6409
6410 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6411 if (env->nr_dies > 1) {
6412 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6413 }
6414
6415 /* SVM requires CPUID[0x8000000A] */
6416 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6417 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6418 }
6419
6420 /* SEV requires CPUID[0x8000001F] */
6421 if (sev_enabled()) {
6422 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6423 }
6424 }
6425
6426 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6427 if (env->cpuid_level_func7 == UINT32_MAX) {
6428 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6429 }
6430 if (env->cpuid_level == UINT32_MAX) {
6431 env->cpuid_level = env->cpuid_min_level;
6432 }
6433 if (env->cpuid_xlevel == UINT32_MAX) {
6434 env->cpuid_xlevel = env->cpuid_min_xlevel;
6435 }
6436 if (env->cpuid_xlevel2 == UINT32_MAX) {
6437 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
6438 }
6439 }
6440
6441 /*
6442 * Finishes initialization of CPUID data, filters CPU feature
6443 * words based on host availability of each feature.
6444 *
6445 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6446 */
6447 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
6448 {
6449 CPUX86State *env = &cpu->env;
6450 FeatureWord w;
6451 const char *prefix = NULL;
6452
6453 if (verbose) {
6454 prefix = accel_uses_host_cpuid()
6455 ? "host doesn't support requested feature"
6456 : "TCG doesn't support requested feature";
6457 }
6458
6459 for (w = 0; w < FEATURE_WORDS; w++) {
6460 uint64_t host_feat =
6461 x86_cpu_get_supported_feature_word(w, false);
6462 uint64_t requested_features = env->features[w];
6463 uint64_t unavailable_features = requested_features & ~host_feat;
6464 mark_unavailable_features(cpu, w, unavailable_features, prefix);
6465 }
6466
6467 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6468 kvm_enabled()) {
6469 KVMState *s = CPU(cpu)->kvm_state;
6470 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6471 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6472 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6473 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6474 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6475
6476 if (!eax_0 ||
6477 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6478 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6479 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6480 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6481 INTEL_PT_ADDR_RANGES_NUM) ||
6482 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
6483 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6484 (ecx_0 & INTEL_PT_IP_LIP)) {
6485 /*
6486 * Processor Trace capabilities aren't configurable, so if the
6487 * host can't emulate the capabilities we report on
6488 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6489 */
6490 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
6491 }
6492 }
6493 }
6494
6495 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6496 {
6497 CPUState *cs = CPU(dev);
6498 X86CPU *cpu = X86_CPU(dev);
6499 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6500 CPUX86State *env = &cpu->env;
6501 Error *local_err = NULL;
6502 static bool ht_warned;
6503
6504 if (xcc->host_cpuid_required) {
6505 if (!accel_uses_host_cpuid()) {
6506 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6507 error_setg(&local_err, "CPU model '%s' requires KVM", name);
6508 goto out;
6509 }
6510 }
6511
6512 if (cpu->max_features && accel_uses_host_cpuid()) {
6513 if (enable_cpu_pm) {
6514 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
6515 &cpu->mwait.ecx, &cpu->mwait.edx);
6516 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
6517 if (kvm_enabled() && kvm_has_waitpkg()) {
6518 env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
6519 }
6520 }
6521 if (kvm_enabled() && cpu->ucode_rev == 0) {
6522 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
6523 MSR_IA32_UCODE_REV);
6524 }
6525 }
6526
6527 if (cpu->ucode_rev == 0) {
6528 /* The default is the same as KVM's. */
6529 if (IS_AMD_CPU(env)) {
6530 cpu->ucode_rev = 0x01000065;
6531 } else {
6532 cpu->ucode_rev = 0x100000000ULL;
6533 }
6534 }
6535
6536 /* mwait extended info: needed for Core compatibility */
6537 /* We always wake on interrupt even if host does not have the capability */
6538 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6539
6540 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6541 error_setg(errp, "apic-id property was not initialized properly");
6542 return;
6543 }
6544
6545 x86_cpu_expand_features(cpu, &local_err);
6546 if (local_err) {
6547 goto out;
6548 }
6549
6550 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6551
6552 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6553 error_setg(&local_err,
6554 accel_uses_host_cpuid() ?
6555 "Host doesn't support requested features" :
6556 "TCG doesn't support requested features");
6557 goto out;
6558 }
6559
6560 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6561 * CPUID[1].EDX.
6562 */
6563 if (IS_AMD_CPU(env)) {
6564 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6565 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
6566 & CPUID_EXT2_AMD_ALIASES);
6567 }
6568
6569 /* For 64bit systems think about the number of physical bits to present.
6570 * ideally this should be the same as the host; anything other than matching
6571 * the host can cause incorrect guest behaviour.
6572 * QEMU used to pick the magic value of 40 bits that corresponds to
6573 * consumer AMD devices but nothing else.
6574 */
6575 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6576 if (accel_uses_host_cpuid()) {
6577 uint32_t host_phys_bits = x86_host_phys_bits();
6578 static bool warned;
6579
6580 /* Print a warning if the user set it to a value that's not the
6581 * host value.
6582 */
6583 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
6584 !warned) {
6585 warn_report("Host physical bits (%u)"
6586 " does not match phys-bits property (%u)",
6587 host_phys_bits, cpu->phys_bits);
6588 warned = true;
6589 }
6590
6591 if (cpu->host_phys_bits) {
6592 /* The user asked for us to use the host physical bits */
6593 cpu->phys_bits = host_phys_bits;
6594 if (cpu->host_phys_bits_limit &&
6595 cpu->phys_bits > cpu->host_phys_bits_limit) {
6596 cpu->phys_bits = cpu->host_phys_bits_limit;
6597 }
6598 }
6599
6600 if (cpu->phys_bits &&
6601 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6602 cpu->phys_bits < 32)) {
6603 error_setg(errp, "phys-bits should be between 32 and %u "
6604 " (but is %u)",
6605 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6606 return;
6607 }
6608 } else {
6609 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
6610 error_setg(errp, "TCG only supports phys-bits=%u",
6611 TCG_PHYS_ADDR_BITS);
6612 return;
6613 }
6614 }
6615 /* 0 means it was not explicitly set by the user (or by machine
6616 * compat_props or by the host code above). In this case, the default
6617 * is the value used by TCG (40).
6618 */
6619 if (cpu->phys_bits == 0) {
6620 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6621 }
6622 } else {
6623 /* For 32 bit systems don't use the user set value, but keep
6624 * phys_bits consistent with what we tell the guest.
6625 */
6626 if (cpu->phys_bits != 0) {
6627 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6628 return;
6629 }
6630
6631 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6632 cpu->phys_bits = 36;
6633 } else {
6634 cpu->phys_bits = 32;
6635 }
6636 }
6637
6638 /* Cache information initialization */
6639 if (!cpu->legacy_cache) {
6640 if (!xcc->model || !xcc->model->cpudef->cache_info) {
6641 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6642 error_setg(errp,
6643 "CPU model '%s' doesn't support legacy-cache=off", name);
6644 return;
6645 }
6646 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
6647 *xcc->model->cpudef->cache_info;
6648 } else {
6649 /* Build legacy cache information */
6650 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6651 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6652 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6653 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6654
6655 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6656 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6657 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6658 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6659
6660 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6661 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6662 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6663 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6664 }
6665
6666
6667 cpu_exec_realizefn(cs, &local_err);
6668 if (local_err != NULL) {
6669 error_propagate(errp, local_err);
6670 return;
6671 }
6672
6673 #ifndef CONFIG_USER_ONLY
6674 MachineState *ms = MACHINE(qdev_get_machine());
6675 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
6676
6677 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
6678 x86_cpu_apic_create(cpu, &local_err);
6679 if (local_err != NULL) {
6680 goto out;
6681 }
6682 }
6683 #endif
6684
6685 mce_init(cpu);
6686
6687 #ifndef CONFIG_USER_ONLY
6688 if (tcg_enabled()) {
6689 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
6690 cpu->cpu_as_root = g_new(MemoryRegion, 1);
6691
6692 /* Outer container... */
6693 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
6694 memory_region_set_enabled(cpu->cpu_as_root, true);
6695
6696 /* ... with two regions inside: normal system memory with low
6697 * priority, and...
6698 */
6699 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
6700 get_system_memory(), 0, ~0ull);
6701 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
6702 memory_region_set_enabled(cpu->cpu_as_mem, true);
6703
6704 cs->num_ases = 2;
6705 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
6706 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
6707
6708 /* ... SMRAM with higher priority, linked from /machine/smram. */
6709 cpu->machine_done.notify = x86_cpu_machine_done;
6710 qemu_add_machine_init_done_notifier(&cpu->machine_done);
6711 }
6712 #endif
6713
6714 qemu_init_vcpu(cs);
6715
6716 /*
6717 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6718 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6719 * based on inputs (sockets,cores,threads), it is still better to give
6720 * users a warning.
6721 *
6722 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6723 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6724 */
6725 if (IS_AMD_CPU(env) &&
6726 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6727 cs->nr_threads > 1 && !ht_warned) {
6728 warn_report("This family of AMD CPU doesn't support "
6729 "hyperthreading(%d)",
6730 cs->nr_threads);
6731 error_printf("Please configure -smp options properly"
6732 " or try enabling topoext feature.\n");
6733 ht_warned = true;
6734 }
6735
6736 x86_cpu_apic_realize(cpu, &local_err);
6737 if (local_err != NULL) {
6738 goto out;
6739 }
6740 cpu_reset(cs);
6741
6742 xcc->parent_realize(dev, &local_err);
6743
6744 out:
6745 if (local_err != NULL) {
6746 error_propagate(errp, local_err);
6747 return;
6748 }
6749 }
6750
6751 static void x86_cpu_unrealizefn(DeviceState *dev)
6752 {
6753 X86CPU *cpu = X86_CPU(dev);
6754 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6755
6756 #ifndef CONFIG_USER_ONLY
6757 cpu_remove_sync(CPU(dev));
6758 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6759 #endif
6760
6761 if (cpu->apic_state) {
6762 object_unparent(OBJECT(cpu->apic_state));
6763 cpu->apic_state = NULL;
6764 }
6765
6766 xcc->parent_unrealize(dev);
6767 }
6768
6769 typedef struct BitProperty {
6770 FeatureWord w;
6771 uint64_t mask;
6772 } BitProperty;
6773
6774 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6775 void *opaque, Error **errp)
6776 {
6777 X86CPU *cpu = X86_CPU(obj);
6778 BitProperty *fp = opaque;
6779 uint64_t f = cpu->env.features[fp->w];
6780 bool value = (f & fp->mask) == fp->mask;
6781 visit_type_bool(v, name, &value, errp);
6782 }
6783
6784 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6785 void *opaque, Error **errp)
6786 {
6787 DeviceState *dev = DEVICE(obj);
6788 X86CPU *cpu = X86_CPU(obj);
6789 BitProperty *fp = opaque;
6790 bool value;
6791
6792 if (dev->realized) {
6793 qdev_prop_set_after_realize(dev, name, errp);
6794 return;
6795 }
6796
6797 if (!visit_type_bool(v, name, &value, errp)) {
6798 return;
6799 }
6800
6801 if (value) {
6802 cpu->env.features[fp->w] |= fp->mask;
6803 } else {
6804 cpu->env.features[fp->w] &= ~fp->mask;
6805 }
6806 cpu->env.user_features[fp->w] |= fp->mask;
6807 }
6808
6809 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
6810 void *opaque)
6811 {
6812 BitProperty *prop = opaque;
6813 g_free(prop);
6814 }
6815
6816 /* Register a boolean property to get/set a single bit in a uint32_t field.
6817 *
6818 * The same property name can be registered multiple times to make it affect
6819 * multiple bits in the same FeatureWord. In that case, the getter will return
6820 * true only if all bits are set.
6821 */
6822 static void x86_cpu_register_bit_prop(X86CPU *cpu,
6823 const char *prop_name,
6824 FeatureWord w,
6825 int bitnr)
6826 {
6827 BitProperty *fp;
6828 ObjectProperty *op;
6829 uint64_t mask = (1ULL << bitnr);
6830
6831 op = object_property_find(OBJECT(cpu), prop_name);
6832 if (op) {
6833 fp = op->opaque;
6834 assert(fp->w == w);
6835 fp->mask |= mask;
6836 } else {
6837 fp = g_new0(BitProperty, 1);
6838 fp->w = w;
6839 fp->mask = mask;
6840 object_property_add(OBJECT(cpu), prop_name, "bool",
6841 x86_cpu_get_bit_prop,
6842 x86_cpu_set_bit_prop,
6843 x86_cpu_release_bit_prop, fp);
6844 }
6845 }
6846
6847 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
6848 FeatureWord w,
6849 int bitnr)
6850 {
6851 FeatureWordInfo *fi = &feature_word_info[w];
6852 const char *name = fi->feat_names[bitnr];
6853
6854 if (!name) {
6855 return;
6856 }
6857
6858 /* Property names should use "-" instead of "_".
6859 * Old names containing underscores are registered as aliases
6860 * using object_property_add_alias()
6861 */
6862 assert(!strchr(name, '_'));
6863 /* aliases don't use "|" delimiters anymore, they are registered
6864 * manually using object_property_add_alias() */
6865 assert(!strchr(name, '|'));
6866 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
6867 }
6868
6869 #if !defined(CONFIG_USER_ONLY)
6870 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6871 {
6872 X86CPU *cpu = X86_CPU(cs);
6873 CPUX86State *env = &cpu->env;
6874 GuestPanicInformation *panic_info = NULL;
6875
6876 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
6877 panic_info = g_malloc0(sizeof(GuestPanicInformation));
6878
6879 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
6880
6881 assert(HV_CRASH_PARAMS >= 5);
6882 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6883 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6884 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6885 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6886 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
6887 }
6888
6889 return panic_info;
6890 }
6891 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6892 const char *name, void *opaque,
6893 Error **errp)
6894 {
6895 CPUState *cs = CPU(obj);
6896 GuestPanicInformation *panic_info;
6897
6898 if (!cs->crash_occurred) {
6899 error_setg(errp, "No crash occured");
6900 return;
6901 }
6902
6903 panic_info = x86_cpu_get_crash_info(cs);
6904 if (panic_info == NULL) {
6905 error_setg(errp, "No crash information");
6906 return;
6907 }
6908
6909 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6910 errp);
6911 qapi_free_GuestPanicInformation(panic_info);
6912 }
6913 #endif /* !CONFIG_USER_ONLY */
6914
6915 static void x86_cpu_initfn(Object *obj)
6916 {
6917 X86CPU *cpu = X86_CPU(obj);
6918 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
6919 CPUX86State *env = &cpu->env;
6920 FeatureWord w;
6921
6922 env->nr_dies = 1;
6923 cpu_set_cpustate_pointers(cpu);
6924
6925 object_property_add(obj, "family", "int",
6926 x86_cpuid_version_get_family,
6927 x86_cpuid_version_set_family, NULL, NULL);
6928 object_property_add(obj, "model", "int",
6929 x86_cpuid_version_get_model,
6930 x86_cpuid_version_set_model, NULL, NULL);
6931 object_property_add(obj, "stepping", "int",
6932 x86_cpuid_version_get_stepping,
6933 x86_cpuid_version_set_stepping, NULL, NULL);
6934 object_property_add_str(obj, "vendor",
6935 x86_cpuid_get_vendor,
6936 x86_cpuid_set_vendor);
6937 object_property_add_str(obj, "model-id",
6938 x86_cpuid_get_model_id,
6939 x86_cpuid_set_model_id);
6940 object_property_add(obj, "tsc-frequency", "int",
6941 x86_cpuid_get_tsc_freq,
6942 x86_cpuid_set_tsc_freq, NULL, NULL);
6943 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6944 x86_cpu_get_feature_words,
6945 NULL, NULL, (void *)env->features);
6946 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6947 x86_cpu_get_feature_words,
6948 NULL, NULL, (void *)cpu->filtered_features);
6949 /*
6950 * The "unavailable-features" property has the same semantics as
6951 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6952 * QMP command: they list the features that would have prevented the
6953 * CPU from running if the "enforce" flag was set.
6954 */
6955 object_property_add(obj, "unavailable-features", "strList",
6956 x86_cpu_get_unavailable_features,
6957 NULL, NULL, NULL);
6958
6959 #if !defined(CONFIG_USER_ONLY)
6960 object_property_add(obj, "crash-information", "GuestPanicInformation",
6961 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
6962 #endif
6963
6964 for (w = 0; w < FEATURE_WORDS; w++) {
6965 int bitnr;
6966
6967 for (bitnr = 0; bitnr < 64; bitnr++) {
6968 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
6969 }
6970 }
6971
6972 object_property_add_alias(obj, "sse3", obj, "pni");
6973 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6974 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6975 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6976 object_property_add_alias(obj, "xd", obj, "nx");
6977 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6978 object_property_add_alias(obj, "i64", obj, "lm");
6979
6980 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6981 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6982 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6983 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6984 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6985 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6986 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6987 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6988 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6989 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6990 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
6991 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6992 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6993 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6994 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6995 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6996 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6997 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6998 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6999 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
7000 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
7001 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
7002
7003 if (xcc->model) {
7004 x86_cpu_load_model(cpu, xcc->model);
7005 }
7006 }
7007
7008 static int64_t x86_cpu_get_arch_id(CPUState *cs)
7009 {
7010 X86CPU *cpu = X86_CPU(cs);
7011
7012 return cpu->apic_id;
7013 }
7014
7015 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
7016 {
7017 X86CPU *cpu = X86_CPU(cs);
7018
7019 return cpu->env.cr[0] & CR0_PG_MASK;
7020 }
7021
7022 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
7023 {
7024 X86CPU *cpu = X86_CPU(cs);
7025
7026 cpu->env.eip = value;
7027 }
7028
7029 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
7030 {
7031 X86CPU *cpu = X86_CPU(cs);
7032
7033 cpu->env.eip = tb->pc - tb->cs_base;
7034 }
7035
7036 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
7037 {
7038 X86CPU *cpu = X86_CPU(cs);
7039 CPUX86State *env = &cpu->env;
7040
7041 #if !defined(CONFIG_USER_ONLY)
7042 if (interrupt_request & CPU_INTERRUPT_POLL) {
7043 return CPU_INTERRUPT_POLL;
7044 }
7045 #endif
7046 if (interrupt_request & CPU_INTERRUPT_SIPI) {
7047 return CPU_INTERRUPT_SIPI;
7048 }
7049
7050 if (env->hflags2 & HF2_GIF_MASK) {
7051 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
7052 !(env->hflags & HF_SMM_MASK)) {
7053 return CPU_INTERRUPT_SMI;
7054 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
7055 !(env->hflags2 & HF2_NMI_MASK)) {
7056 return CPU_INTERRUPT_NMI;
7057 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7058 return CPU_INTERRUPT_MCE;
7059 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7060 (((env->hflags2 & HF2_VINTR_MASK) &&
7061 (env->hflags2 & HF2_HIF_MASK)) ||
7062 (!(env->hflags2 & HF2_VINTR_MASK) &&
7063 (env->eflags & IF_MASK &&
7064 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7065 return CPU_INTERRUPT_HARD;
7066 #if !defined(CONFIG_USER_ONLY)
7067 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
7068 (env->eflags & IF_MASK) &&
7069 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
7070 return CPU_INTERRUPT_VIRQ;
7071 #endif
7072 }
7073 }
7074
7075 return 0;
7076 }
7077
7078 static bool x86_cpu_has_work(CPUState *cs)
7079 {
7080 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
7081 }
7082
7083 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7084 {
7085 X86CPU *cpu = X86_CPU(cs);
7086 CPUX86State *env = &cpu->env;
7087
7088 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7089 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7090 : bfd_mach_i386_i8086);
7091 info->print_insn = print_insn_i386;
7092
7093 info->cap_arch = CS_ARCH_X86;
7094 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7095 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7096 : CS_MODE_16);
7097 info->cap_insn_unit = 1;
7098 info->cap_insn_split = 8;
7099 }
7100
7101 void x86_update_hflags(CPUX86State *env)
7102 {
7103 uint32_t hflags;
7104 #define HFLAG_COPY_MASK \
7105 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7106 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7107 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7108 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7109
7110 hflags = env->hflags & HFLAG_COPY_MASK;
7111 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7112 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7113 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7114 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7115 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7116
7117 if (env->cr[4] & CR4_OSFXSR_MASK) {
7118 hflags |= HF_OSFXSR_MASK;
7119 }
7120
7121 if (env->efer & MSR_EFER_LMA) {
7122 hflags |= HF_LMA_MASK;
7123 }
7124
7125 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7126 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7127 } else {
7128 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7129 (DESC_B_SHIFT - HF_CS32_SHIFT);
7130 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7131 (DESC_B_SHIFT - HF_SS32_SHIFT);
7132 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7133 !(hflags & HF_CS32_MASK)) {
7134 hflags |= HF_ADDSEG_MASK;
7135 } else {
7136 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7137 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7138 }
7139 }
7140 env->hflags = hflags;
7141 }
7142
7143 static Property x86_cpu_properties[] = {
7144 #ifdef CONFIG_USER_ONLY
7145 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7146 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
7147 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7148 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
7149 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
7150 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
7151 #else
7152 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
7153 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7154 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
7155 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
7156 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
7157 #endif
7158 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
7159 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
7160
7161 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7162 HYPERV_SPINLOCK_NEVER_NOTIFY),
7163 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7164 HYPERV_FEAT_RELAXED, 0),
7165 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7166 HYPERV_FEAT_VAPIC, 0),
7167 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7168 HYPERV_FEAT_TIME, 0),
7169 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7170 HYPERV_FEAT_CRASH, 0),
7171 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7172 HYPERV_FEAT_RESET, 0),
7173 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7174 HYPERV_FEAT_VPINDEX, 0),
7175 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7176 HYPERV_FEAT_RUNTIME, 0),
7177 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7178 HYPERV_FEAT_SYNIC, 0),
7179 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7180 HYPERV_FEAT_STIMER, 0),
7181 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7182 HYPERV_FEAT_FREQUENCIES, 0),
7183 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7184 HYPERV_FEAT_REENLIGHTENMENT, 0),
7185 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7186 HYPERV_FEAT_TLBFLUSH, 0),
7187 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7188 HYPERV_FEAT_EVMCS, 0),
7189 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7190 HYPERV_FEAT_IPI, 0),
7191 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7192 HYPERV_FEAT_STIMER_DIRECT, 0),
7193 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7194 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
7195 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
7196
7197 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
7198 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
7199 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
7200 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
7201 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
7202 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
7203 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
7204 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
7205 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7206 UINT32_MAX),
7207 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7208 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7209 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7210 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7211 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7212 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
7213 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
7214 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
7215 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
7216 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
7217 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
7218 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
7219 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7220 false),
7221 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
7222 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
7223 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7224 true),
7225 /*
7226 * lecacy_cache defaults to true unless the CPU model provides its
7227 * own cache information (see x86_cpu_load_def()).
7228 */
7229 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
7230
7231 /*
7232 * From "Requirements for Implementing the Microsoft
7233 * Hypervisor Interface":
7234 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7235 *
7236 * "Starting with Windows Server 2012 and Windows 8, if
7237 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7238 * the hypervisor imposes no specific limit to the number of VPs.
7239 * In this case, Windows Server 2012 guest VMs may use more than
7240 * 64 VPs, up to the maximum supported number of processors applicable
7241 * to the specific Windows version being used."
7242 */
7243 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
7244 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7245 false),
7246 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7247 true),
7248 DEFINE_PROP_END_OF_LIST()
7249 };
7250
7251 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7252 {
7253 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7254 CPUClass *cc = CPU_CLASS(oc);
7255 DeviceClass *dc = DEVICE_CLASS(oc);
7256
7257 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7258 &xcc->parent_realize);
7259 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7260 &xcc->parent_unrealize);
7261 device_class_set_props(dc, x86_cpu_properties);
7262
7263 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
7264 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
7265
7266 cc->class_by_name = x86_cpu_class_by_name;
7267 cc->parse_features = x86_cpu_parse_featurestr;
7268 cc->has_work = x86_cpu_has_work;
7269 #ifdef CONFIG_TCG
7270 cc->do_interrupt = x86_cpu_do_interrupt;
7271 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
7272 #endif
7273 cc->dump_state = x86_cpu_dump_state;
7274 cc->set_pc = x86_cpu_set_pc;
7275 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
7276 cc->gdb_read_register = x86_cpu_gdb_read_register;
7277 cc->gdb_write_register = x86_cpu_gdb_write_register;
7278 cc->get_arch_id = x86_cpu_get_arch_id;
7279 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7280 #ifndef CONFIG_USER_ONLY
7281 cc->asidx_from_attrs = x86_asidx_from_attrs;
7282 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
7283 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
7284 cc->get_crash_info = x86_cpu_get_crash_info;
7285 cc->write_elf64_note = x86_cpu_write_elf64_note;
7286 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7287 cc->write_elf32_note = x86_cpu_write_elf32_note;
7288 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
7289 cc->vmsd = &vmstate_x86_cpu;
7290 #endif
7291 cc->gdb_arch_name = x86_gdb_arch_name;
7292 #ifdef TARGET_X86_64
7293 cc->gdb_core_xml_file = "i386-64bit.xml";
7294 cc->gdb_num_core_regs = 66;
7295 #else
7296 cc->gdb_core_xml_file = "i386-32bit.xml";
7297 cc->gdb_num_core_regs = 50;
7298 #endif
7299 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
7300 cc->debug_excp_handler = breakpoint_handler;
7301 #endif
7302 cc->cpu_exec_enter = x86_cpu_exec_enter;
7303 cc->cpu_exec_exit = x86_cpu_exec_exit;
7304 #ifdef CONFIG_TCG
7305 cc->tcg_initialize = tcg_x86_init;
7306 cc->tlb_fill = x86_cpu_tlb_fill;
7307 #endif
7308 cc->disas_set_info = x86_disas_set_info;
7309
7310 dc->user_creatable = true;
7311 }
7312
7313 static const TypeInfo x86_cpu_type_info = {
7314 .name = TYPE_X86_CPU,
7315 .parent = TYPE_CPU,
7316 .instance_size = sizeof(X86CPU),
7317 .instance_init = x86_cpu_initfn,
7318 .abstract = true,
7319 .class_size = sizeof(X86CPUClass),
7320 .class_init = x86_cpu_common_class_init,
7321 };
7322
7323
7324 /* "base" CPU model, used by query-cpu-model-expansion */
7325 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7326 {
7327 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7328
7329 xcc->static_model = true;
7330 xcc->migration_safe = true;
7331 xcc->model_description = "base CPU model type with no features enabled";
7332 xcc->ordering = 8;
7333 }
7334
7335 static const TypeInfo x86_base_cpu_type_info = {
7336 .name = X86_CPU_TYPE_NAME("base"),
7337 .parent = TYPE_X86_CPU,
7338 .class_init = x86_cpu_base_class_init,
7339 };
7340
7341 static void x86_cpu_register_types(void)
7342 {
7343 int i;
7344
7345 type_register_static(&x86_cpu_type_info);
7346 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
7347 x86_register_cpudef_types(&builtin_x86_defs[i]);
7348 }
7349 type_register_static(&max_x86_cpu_type_info);
7350 type_register_static(&x86_base_cpu_type_info);
7351 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
7352 type_register_static(&host_x86_cpu_type_info);
7353 #endif
7354 }
7355
7356 type_init(x86_cpu_register_types)
AR7 emulation for QEMU