4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "target/arm/idau.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
26 #include "internals.h"
27 #include "qemu-common.h"
28 #include "exec/exec-all.h"
29 #include "hw/qdev-properties.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/loader.h"
33 #include "hw/arm/arm.h"
34 #include "sysemu/sysemu.h"
35 #include "sysemu/hw_accel.h"
37 #include "disas/capstone.h"
38 #include "fpu/softfloat.h"
40 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
42 ARMCPU
*cpu
= ARM_CPU(cs
);
44 cpu
->env
.regs
[15] = value
;
47 static bool arm_cpu_has_work(CPUState
*cs
)
49 ARMCPU
*cpu
= ARM_CPU(cs
);
51 return (cpu
->power_state
!= PSCI_OFF
)
52 && cs
->interrupt_request
&
53 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
54 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
55 | CPU_INTERRUPT_EXITTB
);
58 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
61 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
64 entry
->opaque
= opaque
;
66 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
69 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
72 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
75 entry
->opaque
= opaque
;
77 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
80 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
82 /* Reset a single ARMCPRegInfo register */
83 ARMCPRegInfo
*ri
= value
;
86 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
91 ri
->resetfn(&cpu
->env
, ri
);
95 /* A zero offset is never possible as it would be regs[0]
96 * so we use it to indicate that reset is being handled elsewhere.
97 * This is basically only used for fields in non-core coprocessors
98 * (like the pxa2xx ones).
100 if (!ri
->fieldoffset
) {
104 if (cpreg_field_is_64bit(ri
)) {
105 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
107 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
111 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
113 /* Purely an assertion check: we've already done reset once,
114 * so now check that running the reset for the cpreg doesn't
115 * change its value. This traps bugs where two different cpregs
116 * both try to reset the same state field but to different values.
118 ARMCPRegInfo
*ri
= value
;
119 ARMCPU
*cpu
= opaque
;
120 uint64_t oldvalue
, newvalue
;
122 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
126 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
127 cp_reg_reset(key
, value
, opaque
);
128 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
129 assert(oldvalue
== newvalue
);
132 /* CPUClass::reset() */
133 static void arm_cpu_reset(CPUState
*s
)
135 ARMCPU
*cpu
= ARM_CPU(s
);
136 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
137 CPUARMState
*env
= &cpu
->env
;
139 acc
->parent_reset(s
);
141 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
143 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
144 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
146 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
147 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
148 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
149 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
151 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
152 s
->halted
= cpu
->start_powered_off
;
154 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
155 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
158 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
159 /* 64 bit CPUs always start in 64 bit mode */
161 #if defined(CONFIG_USER_ONLY)
162 env
->pstate
= PSTATE_MODE_EL0t
;
163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
164 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
165 /* Enable all PAC instructions */
166 env
->cp15
.hcr_el2
|= HCR_API
;
167 env
->cp15
.scr_el3
|= SCR_API
;
168 /* and to the FP/Neon instructions */
169 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
170 /* and to the SVE instructions */
171 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
172 env
->cp15
.cptr_el
[3] |= CPTR_EZ
;
173 /* with maximum vector length */
174 env
->vfp
.zcr_el
[1] = cpu
->sve_max_vq
- 1;
175 env
->vfp
.zcr_el
[2] = env
->vfp
.zcr_el
[1];
176 env
->vfp
.zcr_el
[3] = env
->vfp
.zcr_el
[1];
178 /* Reset into the highest available EL */
179 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
180 env
->pstate
= PSTATE_MODE_EL3h
;
181 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
182 env
->pstate
= PSTATE_MODE_EL2h
;
184 env
->pstate
= PSTATE_MODE_EL1h
;
186 env
->pc
= cpu
->rvbar
;
189 #if defined(CONFIG_USER_ONLY)
190 /* Userspace expects access to cp10 and cp11 for FP/Neon */
191 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
195 #if defined(CONFIG_USER_ONLY)
196 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
197 /* For user mode we must enable access to coprocessors */
198 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
199 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
200 env
->cp15
.c15_cpar
= 3;
201 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
202 env
->cp15
.c15_cpar
= 1;
207 * If the highest available EL is EL2, AArch32 will start in Hyp
208 * mode; otherwise it starts in SVC. Note that if we start in
209 * AArch64 then these values in the uncached_cpsr will be ignored.
211 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
212 !arm_feature(env
, ARM_FEATURE_EL3
)) {
213 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
215 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
217 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
219 if (arm_feature(env
, ARM_FEATURE_M
)) {
220 uint32_t initial_msp
; /* Loaded from 0x0 */
221 uint32_t initial_pc
; /* Loaded from 0x4 */
225 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
226 env
->v7m
.secure
= true;
228 /* This bit resets to 0 if security is supported, but 1 if
229 * it is not. The bit is not present in v7M, but we set it
230 * here so we can avoid having to make checks on it conditional
231 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
233 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
236 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
237 * that it resets to 1, so QEMU always does that rather than making
238 * it dependent on CPU model. In v8M it is RES1.
240 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
241 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
242 if (arm_feature(env
, ARM_FEATURE_V8
)) {
243 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
244 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
245 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
247 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
248 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
249 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
252 /* Unlike A/R profile, M profile defines the reset LR value */
253 env
->regs
[14] = 0xffffffff;
255 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
257 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
258 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
259 rom
= rom_ptr(vecbase
, 8);
261 /* Address zero is covered by ROM which hasn't yet been
262 * copied into physical memory.
264 initial_msp
= ldl_p(rom
);
265 initial_pc
= ldl_p(rom
+ 4);
267 /* Address zero not covered by a ROM blob, or the ROM blob
268 * is in non-modifiable memory and this is a second reset after
269 * it got copied into memory. In the latter case, rom_ptr
270 * will return a NULL pointer and we should use ldl_phys instead.
272 initial_msp
= ldl_phys(s
->as
, vecbase
);
273 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
276 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
277 env
->regs
[15] = initial_pc
& ~1;
278 env
->thumb
= initial_pc
& 1;
281 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
282 * executing as AArch32 then check if highvecs are enabled and
283 * adjust the PC accordingly.
285 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
286 env
->regs
[15] = 0xFFFF0000;
289 /* M profile requires that reset clears the exclusive monitor;
290 * A profile does not, but clearing it makes more sense than having it
291 * set with an exclusive access on address zero.
293 arm_clear_exclusive(env
);
295 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
298 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
299 if (cpu
->pmsav7_dregion
> 0) {
300 if (arm_feature(env
, ARM_FEATURE_V8
)) {
301 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
302 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
303 * cpu
->pmsav7_dregion
);
304 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
305 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
306 * cpu
->pmsav7_dregion
);
307 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
308 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
309 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
310 * cpu
->pmsav7_dregion
);
311 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
312 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
313 * cpu
->pmsav7_dregion
);
315 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
316 memset(env
->pmsav7
.drbar
, 0,
317 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
318 memset(env
->pmsav7
.drsr
, 0,
319 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
320 memset(env
->pmsav7
.dracr
, 0,
321 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
324 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
325 env
->pmsav7
.rnr
[M_REG_S
] = 0;
326 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
327 env
->pmsav8
.mair0
[M_REG_S
] = 0;
328 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
329 env
->pmsav8
.mair1
[M_REG_S
] = 0;
332 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
333 if (cpu
->sau_sregion
> 0) {
334 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
335 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
338 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
339 * the Cortex-M33 does.
344 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
345 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
346 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
347 set_float_detect_tininess(float_tininess_before_rounding
,
348 &env
->vfp
.fp_status
);
349 set_float_detect_tininess(float_tininess_before_rounding
,
350 &env
->vfp
.standard_fp_status
);
351 set_float_detect_tininess(float_tininess_before_rounding
,
352 &env
->vfp
.fp_status_f16
);
353 #ifndef CONFIG_USER_ONLY
355 kvm_arm_reset_vcpu(cpu
);
359 hw_breakpoint_update_all(cpu
);
360 hw_watchpoint_update_all(cpu
);
363 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
365 CPUClass
*cc
= CPU_GET_CLASS(cs
);
366 CPUARMState
*env
= cs
->env_ptr
;
367 uint32_t cur_el
= arm_current_el(env
);
368 bool secure
= arm_is_secure(env
);
373 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
375 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
376 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
377 cs
->exception_index
= excp_idx
;
378 env
->exception
.target_el
= target_el
;
379 cc
->do_interrupt(cs
);
383 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
385 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
386 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
387 cs
->exception_index
= excp_idx
;
388 env
->exception
.target_el
= target_el
;
389 cc
->do_interrupt(cs
);
393 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
394 excp_idx
= EXCP_VIRQ
;
396 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
397 cs
->exception_index
= excp_idx
;
398 env
->exception
.target_el
= target_el
;
399 cc
->do_interrupt(cs
);
403 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
404 excp_idx
= EXCP_VFIQ
;
406 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
407 cs
->exception_index
= excp_idx
;
408 env
->exception
.target_el
= target_el
;
409 cc
->do_interrupt(cs
);
417 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
418 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
420 CPUClass
*cc
= CPU_GET_CLASS(cs
);
421 ARMCPU
*cpu
= ARM_CPU(cs
);
422 CPUARMState
*env
= &cpu
->env
;
425 /* ARMv7-M interrupt masking works differently than -A or -R.
426 * There is no FIQ/IRQ distinction. Instead of I and F bits
427 * masking FIQ and IRQ interrupts, an exception is taken only
428 * if it is higher priority than the current execution priority
429 * (which depends on state like BASEPRI, FAULTMASK and the
430 * currently active exception).
432 if (interrupt_request
& CPU_INTERRUPT_HARD
433 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
434 cs
->exception_index
= EXCP_IRQ
;
435 cc
->do_interrupt(cs
);
442 void arm_cpu_update_virq(ARMCPU
*cpu
)
445 * Update the interrupt level for VIRQ, which is the logical OR of
446 * the HCR_EL2.VI bit and the input line level from the GIC.
448 CPUARMState
*env
= &cpu
->env
;
449 CPUState
*cs
= CPU(cpu
);
451 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
452 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
454 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
456 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
458 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
463 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
466 * Update the interrupt level for VFIQ, which is the logical OR of
467 * the HCR_EL2.VF bit and the input line level from the GIC.
469 CPUARMState
*env
= &cpu
->env
;
470 CPUState
*cs
= CPU(cpu
);
472 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
473 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
475 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
477 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
479 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
484 #ifndef CONFIG_USER_ONLY
485 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
487 ARMCPU
*cpu
= opaque
;
488 CPUARMState
*env
= &cpu
->env
;
489 CPUState
*cs
= CPU(cpu
);
490 static const int mask
[] = {
491 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
492 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
493 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
494 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
498 env
->irq_line_state
|= mask
[irq
];
500 env
->irq_line_state
&= ~mask
[irq
];
505 assert(arm_feature(env
, ARM_FEATURE_EL2
));
506 arm_cpu_update_virq(cpu
);
509 assert(arm_feature(env
, ARM_FEATURE_EL2
));
510 arm_cpu_update_vfiq(cpu
);
515 cpu_interrupt(cs
, mask
[irq
]);
517 cpu_reset_interrupt(cs
, mask
[irq
]);
521 g_assert_not_reached();
525 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
528 ARMCPU
*cpu
= opaque
;
529 CPUARMState
*env
= &cpu
->env
;
530 CPUState
*cs
= CPU(cpu
);
531 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
532 uint32_t linestate_bit
;
536 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
537 linestate_bit
= CPU_INTERRUPT_HARD
;
540 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
541 linestate_bit
= CPU_INTERRUPT_FIQ
;
544 g_assert_not_reached();
548 env
->irq_line_state
|= linestate_bit
;
550 env
->irq_line_state
&= ~linestate_bit
;
553 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
554 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
558 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
560 ARMCPU
*cpu
= ARM_CPU(cs
);
561 CPUARMState
*env
= &cpu
->env
;
563 cpu_synchronize_state(cs
);
564 return arm_cpu_data_is_big_endian(env
);
569 static inline void set_feature(CPUARMState
*env
, int feature
)
571 env
->features
|= 1ULL << feature
;
574 static inline void unset_feature(CPUARMState
*env
, int feature
)
576 env
->features
&= ~(1ULL << feature
);
580 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
582 return print_insn_arm(pc
| 1, info
);
585 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
587 ARMCPU
*ac
= ARM_CPU(cpu
);
588 CPUARMState
*env
= &ac
->env
;
592 /* We might not be compiled with the A64 disassembler
593 * because it needs a C++ compiler. Leave print_insn
594 * unset in this case to use the caller default behaviour.
596 #if defined(CONFIG_ARM_A64_DIS)
597 info
->print_insn
= print_insn_arm_a64
;
599 info
->cap_arch
= CS_ARCH_ARM64
;
600 info
->cap_insn_unit
= 4;
601 info
->cap_insn_split
= 4;
605 info
->print_insn
= print_insn_thumb1
;
606 info
->cap_insn_unit
= 2;
607 info
->cap_insn_split
= 4;
608 cap_mode
= CS_MODE_THUMB
;
610 info
->print_insn
= print_insn_arm
;
611 info
->cap_insn_unit
= 4;
612 info
->cap_insn_split
= 4;
613 cap_mode
= CS_MODE_ARM
;
615 if (arm_feature(env
, ARM_FEATURE_V8
)) {
616 cap_mode
|= CS_MODE_V8
;
618 if (arm_feature(env
, ARM_FEATURE_M
)) {
619 cap_mode
|= CS_MODE_MCLASS
;
621 info
->cap_arch
= CS_ARCH_ARM
;
622 info
->cap_mode
= cap_mode
;
625 sctlr_b
= arm_sctlr_b(env
);
626 if (bswap_code(sctlr_b
)) {
627 #ifdef TARGET_WORDS_BIGENDIAN
628 info
->endian
= BFD_ENDIAN_LITTLE
;
630 info
->endian
= BFD_ENDIAN_BIG
;
633 info
->flags
&= ~INSN_ARM_BE32
;
634 #ifndef CONFIG_USER_ONLY
636 info
->flags
|= INSN_ARM_BE32
;
641 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
643 uint32_t Aff1
= idx
/ clustersz
;
644 uint32_t Aff0
= idx
% clustersz
;
645 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
648 static void cpreg_hashtable_data_destroy(gpointer data
)
651 * Destroy function for cpu->cp_regs hashtable data entries.
652 * We must free the name string because it was g_strdup()ed in
653 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
654 * from r->name because we know we definitely allocated it.
656 ARMCPRegInfo
*r
= data
;
658 g_free((void *)r
->name
);
662 static void arm_cpu_initfn(Object
*obj
)
664 CPUState
*cs
= CPU(obj
);
665 ARMCPU
*cpu
= ARM_CPU(obj
);
667 cs
->env_ptr
= &cpu
->env
;
668 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
669 g_free
, cpreg_hashtable_data_destroy
);
671 QLIST_INIT(&cpu
->pre_el_change_hooks
);
672 QLIST_INIT(&cpu
->el_change_hooks
);
674 #ifndef CONFIG_USER_ONLY
675 /* Our inbound IRQ and FIQ lines */
677 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
678 * the same interface as non-KVM CPUs.
680 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
682 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
685 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
686 ARRAY_SIZE(cpu
->gt_timer_outputs
));
688 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
689 "gicv3-maintenance-interrupt", 1);
690 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
694 /* DTB consumers generally don't in fact care what the 'compatible'
695 * string is, so always provide some string and trust that a hypothetical
696 * picky DTB consumer will also provide a helpful error message.
698 cpu
->dtb_compatible
= "qemu,unknown";
699 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
700 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
703 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
707 static Property arm_cpu_reset_cbar_property
=
708 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
710 static Property arm_cpu_reset_hivecs_property
=
711 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
713 static Property arm_cpu_rvbar_property
=
714 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
716 static Property arm_cpu_has_el2_property
=
717 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
719 static Property arm_cpu_has_el3_property
=
720 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
722 static Property arm_cpu_cfgend_property
=
723 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
725 /* use property name "pmu" to match other archs and virt tools */
726 static Property arm_cpu_has_pmu_property
=
727 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
729 static Property arm_cpu_has_mpu_property
=
730 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
732 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
733 * because the CPU initfn will have already set cpu->pmsav7_dregion to
734 * the right value for that particular CPU type, and we don't want
735 * to override that with an incorrect constant value.
737 static Property arm_cpu_pmsav7_dregion_property
=
738 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
740 qdev_prop_uint32
, uint32_t);
742 /* M profile: initial value of the Secure VTOR */
743 static Property arm_cpu_initsvtor_property
=
744 DEFINE_PROP_UINT32("init-svtor", ARMCPU
, init_svtor
, 0);
746 void arm_cpu_post_init(Object
*obj
)
748 ARMCPU
*cpu
= ARM_CPU(obj
);
750 /* M profile implies PMSA. We have to do this here rather than
751 * in realize with the other feature-implication checks because
752 * we look at the PMSA bit to see if we should add some properties.
754 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
755 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
758 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
759 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
760 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
764 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
765 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
769 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
770 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
774 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
775 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
776 * prevent "has_el3" from existing on CPUs which cannot support EL3.
778 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
781 #ifndef CONFIG_USER_ONLY
782 object_property_add_link(obj
, "secure-memory",
784 (Object
**)&cpu
->secure_memory
,
785 qdev_prop_allow_set_link_before_realize
,
786 OBJ_PROP_LINK_STRONG
,
791 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
792 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
796 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
797 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
801 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
802 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
804 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
805 qdev_property_add_static(DEVICE(obj
),
806 &arm_cpu_pmsav7_dregion_property
,
811 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
812 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
813 qdev_prop_allow_set_link_before_realize
,
814 OBJ_PROP_LINK_STRONG
,
816 qdev_property_add_static(DEVICE(obj
), &arm_cpu_initsvtor_property
,
820 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
824 static void arm_cpu_finalizefn(Object
*obj
)
826 ARMCPU
*cpu
= ARM_CPU(obj
);
827 ARMELChangeHook
*hook
, *next
;
829 g_hash_table_destroy(cpu
->cp_regs
);
831 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
832 QLIST_REMOVE(hook
, node
);
835 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
836 QLIST_REMOVE(hook
, node
);
841 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
843 CPUState
*cs
= CPU(dev
);
844 ARMCPU
*cpu
= ARM_CPU(dev
);
845 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
846 CPUARMState
*env
= &cpu
->env
;
848 Error
*local_err
= NULL
;
849 bool no_aa32
= false;
851 /* If we needed to query the host kernel for the CPU features
852 * then it's possible that might have failed in the initfn, but
853 * this is the first point where we can report it.
855 if (cpu
->host_cpu_probe_failed
) {
856 if (!kvm_enabled()) {
857 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
859 error_setg(errp
, "Failed to retrieve host CPU features");
864 #ifndef CONFIG_USER_ONLY
865 /* The NVIC and M-profile CPU are two halves of a single piece of
866 * hardware; trying to use one without the other is a command line
867 * error and will result in segfaults if not caught here.
869 if (arm_feature(env
, ARM_FEATURE_M
)) {
871 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
876 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
881 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
882 arm_gt_ptimer_cb
, cpu
);
883 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
884 arm_gt_vtimer_cb
, cpu
);
885 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
886 arm_gt_htimer_cb
, cpu
);
887 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
888 arm_gt_stimer_cb
, cpu
);
891 cpu_exec_realizefn(cs
, &local_err
);
892 if (local_err
!= NULL
) {
893 error_propagate(errp
, local_err
);
897 /* Some features automatically imply others: */
898 if (arm_feature(env
, ARM_FEATURE_V8
)) {
899 if (arm_feature(env
, ARM_FEATURE_M
)) {
900 set_feature(env
, ARM_FEATURE_V7
);
902 set_feature(env
, ARM_FEATURE_V7VE
);
907 * There exist AArch64 cpus without AArch32 support. When KVM
908 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
909 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
911 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
912 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
915 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
916 /* v7 Virtualization Extensions. In real hardware this implies
917 * EL2 and also the presence of the Security Extensions.
918 * For QEMU, for backwards-compatibility we implement some
919 * CPUs or CPU configs which have no actual EL2 or EL3 but do
920 * include the various other features that V7VE implies.
921 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
922 * Security Extensions is ARM_FEATURE_EL3.
924 assert(no_aa32
|| cpu_isar_feature(arm_div
, cpu
));
925 set_feature(env
, ARM_FEATURE_LPAE
);
926 set_feature(env
, ARM_FEATURE_V7
);
928 if (arm_feature(env
, ARM_FEATURE_V7
)) {
929 set_feature(env
, ARM_FEATURE_VAPA
);
930 set_feature(env
, ARM_FEATURE_THUMB2
);
931 set_feature(env
, ARM_FEATURE_MPIDR
);
932 if (!arm_feature(env
, ARM_FEATURE_M
)) {
933 set_feature(env
, ARM_FEATURE_V6K
);
935 set_feature(env
, ARM_FEATURE_V6
);
938 /* Always define VBAR for V7 CPUs even if it doesn't exist in
939 * non-EL3 configs. This is needed by some legacy boards.
941 set_feature(env
, ARM_FEATURE_VBAR
);
943 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
944 set_feature(env
, ARM_FEATURE_V6
);
945 set_feature(env
, ARM_FEATURE_MVFR
);
947 if (arm_feature(env
, ARM_FEATURE_V6
)) {
948 set_feature(env
, ARM_FEATURE_V5
);
949 if (!arm_feature(env
, ARM_FEATURE_M
)) {
950 assert(no_aa32
|| cpu_isar_feature(jazelle
, cpu
));
951 set_feature(env
, ARM_FEATURE_AUXCR
);
954 if (arm_feature(env
, ARM_FEATURE_V5
)) {
955 set_feature(env
, ARM_FEATURE_V4T
);
957 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
958 set_feature(env
, ARM_FEATURE_VFP3
);
959 set_feature(env
, ARM_FEATURE_VFP_FP16
);
961 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
962 set_feature(env
, ARM_FEATURE_VFP
);
964 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
965 set_feature(env
, ARM_FEATURE_V7MP
);
966 set_feature(env
, ARM_FEATURE_PXN
);
968 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
969 set_feature(env
, ARM_FEATURE_CBAR
);
971 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
972 !arm_feature(env
, ARM_FEATURE_M
)) {
973 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
976 if (arm_feature(env
, ARM_FEATURE_V7
) &&
977 !arm_feature(env
, ARM_FEATURE_M
) &&
978 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
979 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
984 /* For CPUs which might have tiny 1K pages, or which have an
985 * MPU and might have small region sizes, stick with 1K pages.
989 if (!set_preferred_target_page_bits(pagebits
)) {
990 /* This can only ever happen for hotplugging a CPU, or if
991 * the board code incorrectly creates a CPU which it has
992 * promised via minimum_page_size that it will not.
994 error_setg(errp
, "This CPU requires a smaller page size than the "
999 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1000 * We don't support setting cluster ID ([16..23]) (known as Aff2
1001 * in later ARM ARM versions), or any of the higher affinity level fields,
1002 * so these bits always RAZ.
1004 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1005 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1006 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1009 if (cpu
->reset_hivecs
) {
1010 cpu
->reset_sctlr
|= (1 << 13);
1014 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1015 cpu
->reset_sctlr
|= SCTLR_EE
;
1017 cpu
->reset_sctlr
|= SCTLR_B
;
1021 if (!cpu
->has_el3
) {
1022 /* If the has_el3 CPU property is disabled then we need to disable the
1025 unset_feature(env
, ARM_FEATURE_EL3
);
1027 /* Disable the security extension feature bits in the processor feature
1028 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1030 cpu
->id_pfr1
&= ~0xf0;
1031 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1034 if (!cpu
->has_el2
) {
1035 unset_feature(env
, ARM_FEATURE_EL2
);
1038 if (!cpu
->has_pmu
) {
1039 unset_feature(env
, ARM_FEATURE_PMU
);
1041 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1044 if (!kvm_enabled()) {
1045 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1046 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1049 cpu
->id_aa64dfr0
&= ~0xf00;
1054 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1055 /* Disable the hypervisor feature bits in the processor feature
1056 * registers if we don't have EL2. These are id_pfr1[15:12] and
1057 * id_aa64pfr0_el1[11:8].
1059 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1060 cpu
->id_pfr1
&= ~0xf000;
1063 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1064 * to false or by setting pmsav7-dregion to 0.
1066 if (!cpu
->has_mpu
) {
1067 cpu
->pmsav7_dregion
= 0;
1069 if (cpu
->pmsav7_dregion
== 0) {
1070 cpu
->has_mpu
= false;
1073 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1074 arm_feature(env
, ARM_FEATURE_V7
)) {
1075 uint32_t nr
= cpu
->pmsav7_dregion
;
1078 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1083 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1085 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1086 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1087 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1088 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1089 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1092 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1093 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1094 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1099 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1100 uint32_t nr
= cpu
->sau_sregion
;
1103 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1108 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1109 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1113 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1114 set_feature(env
, ARM_FEATURE_VBAR
);
1117 register_cp_regs_for_features(cpu
);
1118 arm_cpu_register_gdb_regs_for_features(cpu
);
1120 init_cpreg_list(cpu
);
1122 #ifndef CONFIG_USER_ONLY
1123 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1126 if (!cpu
->secure_memory
) {
1127 cpu
->secure_memory
= cs
->memory
;
1129 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1130 cpu
->secure_memory
);
1134 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1136 /* No core_count specified, default to smp_cpus. */
1137 if (cpu
->core_count
== -1) {
1138 cpu
->core_count
= smp_cpus
;
1145 acc
->parent_realize(dev
, errp
);
1148 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1153 const char *cpunamestr
;
1155 cpuname
= g_strsplit(cpu_model
, ",", 1);
1156 cpunamestr
= cpuname
[0];
1157 #ifdef CONFIG_USER_ONLY
1158 /* For backwards compatibility usermode emulation allows "-cpu any",
1159 * which has the same semantics as "-cpu max".
1161 if (!strcmp(cpunamestr
, "any")) {
1165 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1166 oc
= object_class_by_name(typename
);
1167 g_strfreev(cpuname
);
1169 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1170 object_class_is_abstract(oc
)) {
1176 /* CPU models. These are not needed for the AArch64 linux-user build. */
1177 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1179 static void arm926_initfn(Object
*obj
)
1181 ARMCPU
*cpu
= ARM_CPU(obj
);
1183 cpu
->dtb_compatible
= "arm,arm926";
1184 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1185 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1186 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1187 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1188 cpu
->midr
= 0x41069265;
1189 cpu
->reset_fpsid
= 0x41011090;
1190 cpu
->ctr
= 0x1dd20d2;
1191 cpu
->reset_sctlr
= 0x00090078;
1194 * ARMv5 does not have the ID_ISAR registers, but we can still
1195 * set the field to indicate Jazelle support within QEMU.
1197 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1200 static void arm946_initfn(Object
*obj
)
1202 ARMCPU
*cpu
= ARM_CPU(obj
);
1204 cpu
->dtb_compatible
= "arm,arm946";
1205 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1206 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1207 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1208 cpu
->midr
= 0x41059461;
1209 cpu
->ctr
= 0x0f004006;
1210 cpu
->reset_sctlr
= 0x00000078;
1213 static void arm1026_initfn(Object
*obj
)
1215 ARMCPU
*cpu
= ARM_CPU(obj
);
1217 cpu
->dtb_compatible
= "arm,arm1026";
1218 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1219 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1220 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1221 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1222 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1223 cpu
->midr
= 0x4106a262;
1224 cpu
->reset_fpsid
= 0x410110a0;
1225 cpu
->ctr
= 0x1dd20d2;
1226 cpu
->reset_sctlr
= 0x00090078;
1227 cpu
->reset_auxcr
= 1;
1230 * ARMv5 does not have the ID_ISAR registers, but we can still
1231 * set the field to indicate Jazelle support within QEMU.
1233 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1236 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1237 ARMCPRegInfo ifar
= {
1238 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1240 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1243 define_one_arm_cp_reg(cpu
, &ifar
);
1247 static void arm1136_r2_initfn(Object
*obj
)
1249 ARMCPU
*cpu
= ARM_CPU(obj
);
1250 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1251 * older core than plain "arm1136". In particular this does not
1252 * have the v6K features.
1253 * These ID register values are correct for 1136 but may be wrong
1254 * for 1136_r2 (in particular r0p2 does not actually implement most
1255 * of the ID registers).
1258 cpu
->dtb_compatible
= "arm,arm1136";
1259 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1260 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1261 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1262 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1263 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1264 cpu
->midr
= 0x4107b362;
1265 cpu
->reset_fpsid
= 0x410120b4;
1266 cpu
->isar
.mvfr0
= 0x11111111;
1267 cpu
->isar
.mvfr1
= 0x00000000;
1268 cpu
->ctr
= 0x1dd20d2;
1269 cpu
->reset_sctlr
= 0x00050078;
1270 cpu
->id_pfr0
= 0x111;
1274 cpu
->id_mmfr0
= 0x01130003;
1275 cpu
->id_mmfr1
= 0x10030302;
1276 cpu
->id_mmfr2
= 0x01222110;
1277 cpu
->isar
.id_isar0
= 0x00140011;
1278 cpu
->isar
.id_isar1
= 0x12002111;
1279 cpu
->isar
.id_isar2
= 0x11231111;
1280 cpu
->isar
.id_isar3
= 0x01102131;
1281 cpu
->isar
.id_isar4
= 0x141;
1282 cpu
->reset_auxcr
= 7;
1285 static void arm1136_initfn(Object
*obj
)
1287 ARMCPU
*cpu
= ARM_CPU(obj
);
1289 cpu
->dtb_compatible
= "arm,arm1136";
1290 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1291 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1292 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1293 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1294 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1295 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1296 cpu
->midr
= 0x4117b363;
1297 cpu
->reset_fpsid
= 0x410120b4;
1298 cpu
->isar
.mvfr0
= 0x11111111;
1299 cpu
->isar
.mvfr1
= 0x00000000;
1300 cpu
->ctr
= 0x1dd20d2;
1301 cpu
->reset_sctlr
= 0x00050078;
1302 cpu
->id_pfr0
= 0x111;
1306 cpu
->id_mmfr0
= 0x01130003;
1307 cpu
->id_mmfr1
= 0x10030302;
1308 cpu
->id_mmfr2
= 0x01222110;
1309 cpu
->isar
.id_isar0
= 0x00140011;
1310 cpu
->isar
.id_isar1
= 0x12002111;
1311 cpu
->isar
.id_isar2
= 0x11231111;
1312 cpu
->isar
.id_isar3
= 0x01102131;
1313 cpu
->isar
.id_isar4
= 0x141;
1314 cpu
->reset_auxcr
= 7;
1317 static void arm1176_initfn(Object
*obj
)
1319 ARMCPU
*cpu
= ARM_CPU(obj
);
1321 cpu
->dtb_compatible
= "arm,arm1176";
1322 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1323 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1324 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1325 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1326 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1327 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1328 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1329 cpu
->midr
= 0x410fb767;
1330 cpu
->reset_fpsid
= 0x410120b5;
1331 cpu
->isar
.mvfr0
= 0x11111111;
1332 cpu
->isar
.mvfr1
= 0x00000000;
1333 cpu
->ctr
= 0x1dd20d2;
1334 cpu
->reset_sctlr
= 0x00050078;
1335 cpu
->id_pfr0
= 0x111;
1336 cpu
->id_pfr1
= 0x11;
1337 cpu
->id_dfr0
= 0x33;
1339 cpu
->id_mmfr0
= 0x01130003;
1340 cpu
->id_mmfr1
= 0x10030302;
1341 cpu
->id_mmfr2
= 0x01222100;
1342 cpu
->isar
.id_isar0
= 0x0140011;
1343 cpu
->isar
.id_isar1
= 0x12002111;
1344 cpu
->isar
.id_isar2
= 0x11231121;
1345 cpu
->isar
.id_isar3
= 0x01102131;
1346 cpu
->isar
.id_isar4
= 0x01141;
1347 cpu
->reset_auxcr
= 7;
1350 static void arm11mpcore_initfn(Object
*obj
)
1352 ARMCPU
*cpu
= ARM_CPU(obj
);
1354 cpu
->dtb_compatible
= "arm,arm11mpcore";
1355 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1356 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1357 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1358 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1359 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1360 cpu
->midr
= 0x410fb022;
1361 cpu
->reset_fpsid
= 0x410120b4;
1362 cpu
->isar
.mvfr0
= 0x11111111;
1363 cpu
->isar
.mvfr1
= 0x00000000;
1364 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1365 cpu
->id_pfr0
= 0x111;
1369 cpu
->id_mmfr0
= 0x01100103;
1370 cpu
->id_mmfr1
= 0x10020302;
1371 cpu
->id_mmfr2
= 0x01222000;
1372 cpu
->isar
.id_isar0
= 0x00100011;
1373 cpu
->isar
.id_isar1
= 0x12002111;
1374 cpu
->isar
.id_isar2
= 0x11221011;
1375 cpu
->isar
.id_isar3
= 0x01102131;
1376 cpu
->isar
.id_isar4
= 0x141;
1377 cpu
->reset_auxcr
= 1;
1380 static void cortex_m0_initfn(Object
*obj
)
1382 ARMCPU
*cpu
= ARM_CPU(obj
);
1383 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1384 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1386 cpu
->midr
= 0x410cc200;
1389 static void cortex_m3_initfn(Object
*obj
)
1391 ARMCPU
*cpu
= ARM_CPU(obj
);
1392 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1393 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1394 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1395 cpu
->midr
= 0x410fc231;
1396 cpu
->pmsav7_dregion
= 8;
1397 cpu
->id_pfr0
= 0x00000030;
1398 cpu
->id_pfr1
= 0x00000200;
1399 cpu
->id_dfr0
= 0x00100000;
1400 cpu
->id_afr0
= 0x00000000;
1401 cpu
->id_mmfr0
= 0x00000030;
1402 cpu
->id_mmfr1
= 0x00000000;
1403 cpu
->id_mmfr2
= 0x00000000;
1404 cpu
->id_mmfr3
= 0x00000000;
1405 cpu
->isar
.id_isar0
= 0x01141110;
1406 cpu
->isar
.id_isar1
= 0x02111000;
1407 cpu
->isar
.id_isar2
= 0x21112231;
1408 cpu
->isar
.id_isar3
= 0x01111110;
1409 cpu
->isar
.id_isar4
= 0x01310102;
1410 cpu
->isar
.id_isar5
= 0x00000000;
1411 cpu
->isar
.id_isar6
= 0x00000000;
1414 static void cortex_m4_initfn(Object
*obj
)
1416 ARMCPU
*cpu
= ARM_CPU(obj
);
1418 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1419 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1420 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1421 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1422 cpu
->midr
= 0x410fc240; /* r0p0 */
1423 cpu
->pmsav7_dregion
= 8;
1424 cpu
->id_pfr0
= 0x00000030;
1425 cpu
->id_pfr1
= 0x00000200;
1426 cpu
->id_dfr0
= 0x00100000;
1427 cpu
->id_afr0
= 0x00000000;
1428 cpu
->id_mmfr0
= 0x00000030;
1429 cpu
->id_mmfr1
= 0x00000000;
1430 cpu
->id_mmfr2
= 0x00000000;
1431 cpu
->id_mmfr3
= 0x00000000;
1432 cpu
->isar
.id_isar0
= 0x01141110;
1433 cpu
->isar
.id_isar1
= 0x02111000;
1434 cpu
->isar
.id_isar2
= 0x21112231;
1435 cpu
->isar
.id_isar3
= 0x01111110;
1436 cpu
->isar
.id_isar4
= 0x01310102;
1437 cpu
->isar
.id_isar5
= 0x00000000;
1438 cpu
->isar
.id_isar6
= 0x00000000;
1441 static void cortex_m33_initfn(Object
*obj
)
1443 ARMCPU
*cpu
= ARM_CPU(obj
);
1445 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1446 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1447 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1448 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
1449 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1450 cpu
->midr
= 0x410fd213; /* r0p3 */
1451 cpu
->pmsav7_dregion
= 16;
1452 cpu
->sau_sregion
= 8;
1453 cpu
->id_pfr0
= 0x00000030;
1454 cpu
->id_pfr1
= 0x00000210;
1455 cpu
->id_dfr0
= 0x00200000;
1456 cpu
->id_afr0
= 0x00000000;
1457 cpu
->id_mmfr0
= 0x00101F40;
1458 cpu
->id_mmfr1
= 0x00000000;
1459 cpu
->id_mmfr2
= 0x01000000;
1460 cpu
->id_mmfr3
= 0x00000000;
1461 cpu
->isar
.id_isar0
= 0x01101110;
1462 cpu
->isar
.id_isar1
= 0x02212000;
1463 cpu
->isar
.id_isar2
= 0x20232232;
1464 cpu
->isar
.id_isar3
= 0x01111131;
1465 cpu
->isar
.id_isar4
= 0x01310132;
1466 cpu
->isar
.id_isar5
= 0x00000000;
1467 cpu
->isar
.id_isar6
= 0x00000000;
1468 cpu
->clidr
= 0x00000000;
1469 cpu
->ctr
= 0x8000c000;
1472 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1474 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1475 CPUClass
*cc
= CPU_CLASS(oc
);
1478 #ifndef CONFIG_USER_ONLY
1479 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1482 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1485 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1486 /* Dummy the TCM region regs for the moment */
1487 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1488 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1489 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1490 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1491 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1492 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1496 static void cortex_r5_initfn(Object
*obj
)
1498 ARMCPU
*cpu
= ARM_CPU(obj
);
1500 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1501 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1502 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1503 cpu
->midr
= 0x411fc153; /* r1p3 */
1504 cpu
->id_pfr0
= 0x0131;
1505 cpu
->id_pfr1
= 0x001;
1506 cpu
->id_dfr0
= 0x010400;
1508 cpu
->id_mmfr0
= 0x0210030;
1509 cpu
->id_mmfr1
= 0x00000000;
1510 cpu
->id_mmfr2
= 0x01200000;
1511 cpu
->id_mmfr3
= 0x0211;
1512 cpu
->isar
.id_isar0
= 0x02101111;
1513 cpu
->isar
.id_isar1
= 0x13112111;
1514 cpu
->isar
.id_isar2
= 0x21232141;
1515 cpu
->isar
.id_isar3
= 0x01112131;
1516 cpu
->isar
.id_isar4
= 0x0010142;
1517 cpu
->isar
.id_isar5
= 0x0;
1518 cpu
->isar
.id_isar6
= 0x0;
1519 cpu
->mp_is_up
= true;
1520 cpu
->pmsav7_dregion
= 16;
1521 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1524 static void cortex_r5f_initfn(Object
*obj
)
1526 ARMCPU
*cpu
= ARM_CPU(obj
);
1528 cortex_r5_initfn(obj
);
1529 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1532 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1533 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1534 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1535 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1536 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1540 static void cortex_a8_initfn(Object
*obj
)
1542 ARMCPU
*cpu
= ARM_CPU(obj
);
1544 cpu
->dtb_compatible
= "arm,cortex-a8";
1545 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1546 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1547 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1548 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1549 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1550 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1551 cpu
->midr
= 0x410fc080;
1552 cpu
->reset_fpsid
= 0x410330c0;
1553 cpu
->isar
.mvfr0
= 0x11110222;
1554 cpu
->isar
.mvfr1
= 0x00011111;
1555 cpu
->ctr
= 0x82048004;
1556 cpu
->reset_sctlr
= 0x00c50078;
1557 cpu
->id_pfr0
= 0x1031;
1558 cpu
->id_pfr1
= 0x11;
1559 cpu
->id_dfr0
= 0x400;
1561 cpu
->id_mmfr0
= 0x31100003;
1562 cpu
->id_mmfr1
= 0x20000000;
1563 cpu
->id_mmfr2
= 0x01202000;
1564 cpu
->id_mmfr3
= 0x11;
1565 cpu
->isar
.id_isar0
= 0x00101111;
1566 cpu
->isar
.id_isar1
= 0x12112111;
1567 cpu
->isar
.id_isar2
= 0x21232031;
1568 cpu
->isar
.id_isar3
= 0x11112131;
1569 cpu
->isar
.id_isar4
= 0x00111142;
1570 cpu
->dbgdidr
= 0x15141000;
1571 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1572 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1573 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1574 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1575 cpu
->reset_auxcr
= 2;
1576 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1579 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1580 /* power_control should be set to maximum latency. Again,
1581 * default to 0 and set by private hook
1583 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1584 .access
= PL1_RW
, .resetvalue
= 0,
1585 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1586 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1587 .access
= PL1_RW
, .resetvalue
= 0,
1588 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1589 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1590 .access
= PL1_RW
, .resetvalue
= 0,
1591 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1592 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1593 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1594 /* TLB lockdown control */
1595 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1596 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1597 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1598 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1599 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1600 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1601 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1602 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1603 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1604 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1608 static void cortex_a9_initfn(Object
*obj
)
1610 ARMCPU
*cpu
= ARM_CPU(obj
);
1612 cpu
->dtb_compatible
= "arm,cortex-a9";
1613 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1614 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1615 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1616 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1617 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1618 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1619 /* Note that A9 supports the MP extensions even for
1620 * A9UP and single-core A9MP (which are both different
1621 * and valid configurations; we don't model A9UP).
1623 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1624 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1625 cpu
->midr
= 0x410fc090;
1626 cpu
->reset_fpsid
= 0x41033090;
1627 cpu
->isar
.mvfr0
= 0x11110222;
1628 cpu
->isar
.mvfr1
= 0x01111111;
1629 cpu
->ctr
= 0x80038003;
1630 cpu
->reset_sctlr
= 0x00c50078;
1631 cpu
->id_pfr0
= 0x1031;
1632 cpu
->id_pfr1
= 0x11;
1633 cpu
->id_dfr0
= 0x000;
1635 cpu
->id_mmfr0
= 0x00100103;
1636 cpu
->id_mmfr1
= 0x20000000;
1637 cpu
->id_mmfr2
= 0x01230000;
1638 cpu
->id_mmfr3
= 0x00002111;
1639 cpu
->isar
.id_isar0
= 0x00101111;
1640 cpu
->isar
.id_isar1
= 0x13112111;
1641 cpu
->isar
.id_isar2
= 0x21232041;
1642 cpu
->isar
.id_isar3
= 0x11112131;
1643 cpu
->isar
.id_isar4
= 0x00111142;
1644 cpu
->dbgdidr
= 0x35141000;
1645 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1646 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1647 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1648 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1651 #ifndef CONFIG_USER_ONLY
1652 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1654 /* Linux wants the number of processors from here.
1655 * Might as well set the interrupt-controller bit too.
1657 return ((smp_cpus
- 1) << 24) | (1 << 23);
1661 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1662 #ifndef CONFIG_USER_ONLY
1663 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1664 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1665 .writefn
= arm_cp_write_ignore
, },
1667 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1668 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1672 static void cortex_a7_initfn(Object
*obj
)
1674 ARMCPU
*cpu
= ARM_CPU(obj
);
1676 cpu
->dtb_compatible
= "arm,cortex-a7";
1677 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
1678 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1679 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1680 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1681 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1682 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1683 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1684 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
1685 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1686 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1687 cpu
->midr
= 0x410fc075;
1688 cpu
->reset_fpsid
= 0x41023075;
1689 cpu
->isar
.mvfr0
= 0x10110222;
1690 cpu
->isar
.mvfr1
= 0x11111111;
1691 cpu
->ctr
= 0x84448003;
1692 cpu
->reset_sctlr
= 0x00c50078;
1693 cpu
->id_pfr0
= 0x00001131;
1694 cpu
->id_pfr1
= 0x00011011;
1695 cpu
->id_dfr0
= 0x02010555;
1696 cpu
->id_afr0
= 0x00000000;
1697 cpu
->id_mmfr0
= 0x10101105;
1698 cpu
->id_mmfr1
= 0x40000000;
1699 cpu
->id_mmfr2
= 0x01240000;
1700 cpu
->id_mmfr3
= 0x02102211;
1701 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
1702 * table 4-41 gives 0x02101110, which includes the arm div insns.
1704 cpu
->isar
.id_isar0
= 0x02101110;
1705 cpu
->isar
.id_isar1
= 0x13112111;
1706 cpu
->isar
.id_isar2
= 0x21232041;
1707 cpu
->isar
.id_isar3
= 0x11112131;
1708 cpu
->isar
.id_isar4
= 0x10011142;
1709 cpu
->dbgdidr
= 0x3515f005;
1710 cpu
->clidr
= 0x0a200023;
1711 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1712 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1713 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1714 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1717 static void cortex_a15_initfn(Object
*obj
)
1719 ARMCPU
*cpu
= ARM_CPU(obj
);
1721 cpu
->dtb_compatible
= "arm,cortex-a15";
1722 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
1723 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1724 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1725 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1726 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1727 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1728 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1729 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
1730 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1731 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1732 cpu
->midr
= 0x412fc0f1;
1733 cpu
->reset_fpsid
= 0x410430f0;
1734 cpu
->isar
.mvfr0
= 0x10110222;
1735 cpu
->isar
.mvfr1
= 0x11111111;
1736 cpu
->ctr
= 0x8444c004;
1737 cpu
->reset_sctlr
= 0x00c50078;
1738 cpu
->id_pfr0
= 0x00001131;
1739 cpu
->id_pfr1
= 0x00011011;
1740 cpu
->id_dfr0
= 0x02010555;
1741 cpu
->id_afr0
= 0x00000000;
1742 cpu
->id_mmfr0
= 0x10201105;
1743 cpu
->id_mmfr1
= 0x20000000;
1744 cpu
->id_mmfr2
= 0x01240000;
1745 cpu
->id_mmfr3
= 0x02102211;
1746 cpu
->isar
.id_isar0
= 0x02101110;
1747 cpu
->isar
.id_isar1
= 0x13112111;
1748 cpu
->isar
.id_isar2
= 0x21232041;
1749 cpu
->isar
.id_isar3
= 0x11112131;
1750 cpu
->isar
.id_isar4
= 0x10011142;
1751 cpu
->dbgdidr
= 0x3515f021;
1752 cpu
->clidr
= 0x0a200023;
1753 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1754 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1755 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1756 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1759 static void ti925t_initfn(Object
*obj
)
1761 ARMCPU
*cpu
= ARM_CPU(obj
);
1762 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1763 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1764 cpu
->midr
= ARM_CPUID_TI925T
;
1765 cpu
->ctr
= 0x5109149;
1766 cpu
->reset_sctlr
= 0x00000070;
1769 static void sa1100_initfn(Object
*obj
)
1771 ARMCPU
*cpu
= ARM_CPU(obj
);
1773 cpu
->dtb_compatible
= "intel,sa1100";
1774 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1775 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1776 cpu
->midr
= 0x4401A11B;
1777 cpu
->reset_sctlr
= 0x00000070;
1780 static void sa1110_initfn(Object
*obj
)
1782 ARMCPU
*cpu
= ARM_CPU(obj
);
1783 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1784 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1785 cpu
->midr
= 0x6901B119;
1786 cpu
->reset_sctlr
= 0x00000070;
1789 static void pxa250_initfn(Object
*obj
)
1791 ARMCPU
*cpu
= ARM_CPU(obj
);
1793 cpu
->dtb_compatible
= "marvell,xscale";
1794 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1795 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1796 cpu
->midr
= 0x69052100;
1797 cpu
->ctr
= 0xd172172;
1798 cpu
->reset_sctlr
= 0x00000078;
1801 static void pxa255_initfn(Object
*obj
)
1803 ARMCPU
*cpu
= ARM_CPU(obj
);
1805 cpu
->dtb_compatible
= "marvell,xscale";
1806 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1807 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1808 cpu
->midr
= 0x69052d00;
1809 cpu
->ctr
= 0xd172172;
1810 cpu
->reset_sctlr
= 0x00000078;
1813 static void pxa260_initfn(Object
*obj
)
1815 ARMCPU
*cpu
= ARM_CPU(obj
);
1817 cpu
->dtb_compatible
= "marvell,xscale";
1818 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1819 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1820 cpu
->midr
= 0x69052903;
1821 cpu
->ctr
= 0xd172172;
1822 cpu
->reset_sctlr
= 0x00000078;
1825 static void pxa261_initfn(Object
*obj
)
1827 ARMCPU
*cpu
= ARM_CPU(obj
);
1829 cpu
->dtb_compatible
= "marvell,xscale";
1830 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1831 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1832 cpu
->midr
= 0x69052d05;
1833 cpu
->ctr
= 0xd172172;
1834 cpu
->reset_sctlr
= 0x00000078;
1837 static void pxa262_initfn(Object
*obj
)
1839 ARMCPU
*cpu
= ARM_CPU(obj
);
1841 cpu
->dtb_compatible
= "marvell,xscale";
1842 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1843 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1844 cpu
->midr
= 0x69052d06;
1845 cpu
->ctr
= 0xd172172;
1846 cpu
->reset_sctlr
= 0x00000078;
1849 static void pxa270a0_initfn(Object
*obj
)
1851 ARMCPU
*cpu
= ARM_CPU(obj
);
1853 cpu
->dtb_compatible
= "marvell,xscale";
1854 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1855 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1856 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1857 cpu
->midr
= 0x69054110;
1858 cpu
->ctr
= 0xd172172;
1859 cpu
->reset_sctlr
= 0x00000078;
1862 static void pxa270a1_initfn(Object
*obj
)
1864 ARMCPU
*cpu
= ARM_CPU(obj
);
1866 cpu
->dtb_compatible
= "marvell,xscale";
1867 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1868 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1869 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1870 cpu
->midr
= 0x69054111;
1871 cpu
->ctr
= 0xd172172;
1872 cpu
->reset_sctlr
= 0x00000078;
1875 static void pxa270b0_initfn(Object
*obj
)
1877 ARMCPU
*cpu
= ARM_CPU(obj
);
1879 cpu
->dtb_compatible
= "marvell,xscale";
1880 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1881 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1882 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1883 cpu
->midr
= 0x69054112;
1884 cpu
->ctr
= 0xd172172;
1885 cpu
->reset_sctlr
= 0x00000078;
1888 static void pxa270b1_initfn(Object
*obj
)
1890 ARMCPU
*cpu
= ARM_CPU(obj
);
1892 cpu
->dtb_compatible
= "marvell,xscale";
1893 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1894 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1895 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1896 cpu
->midr
= 0x69054113;
1897 cpu
->ctr
= 0xd172172;
1898 cpu
->reset_sctlr
= 0x00000078;
1901 static void pxa270c0_initfn(Object
*obj
)
1903 ARMCPU
*cpu
= ARM_CPU(obj
);
1905 cpu
->dtb_compatible
= "marvell,xscale";
1906 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1907 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1908 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1909 cpu
->midr
= 0x69054114;
1910 cpu
->ctr
= 0xd172172;
1911 cpu
->reset_sctlr
= 0x00000078;
1914 static void pxa270c5_initfn(Object
*obj
)
1916 ARMCPU
*cpu
= ARM_CPU(obj
);
1918 cpu
->dtb_compatible
= "marvell,xscale";
1919 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1920 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1921 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1922 cpu
->midr
= 0x69054117;
1923 cpu
->ctr
= 0xd172172;
1924 cpu
->reset_sctlr
= 0x00000078;
1927 #ifndef TARGET_AARCH64
1928 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
1929 * otherwise, a CPU with as many features enabled as our emulation supports.
1930 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1931 * this only needs to handle 32 bits.
1933 static void arm_max_initfn(Object
*obj
)
1935 ARMCPU
*cpu
= ARM_CPU(obj
);
1937 if (kvm_enabled()) {
1938 kvm_arm_set_cpu_features_from_host(cpu
);
1940 cortex_a15_initfn(obj
);
1941 #ifdef CONFIG_USER_ONLY
1942 /* We don't set these in system emulation mode for the moment,
1943 * since we don't correctly set (all of) the ID registers to
1946 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1950 t
= cpu
->isar
.id_isar5
;
1951 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
1952 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
1953 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
1954 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
1955 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
1956 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
1957 cpu
->isar
.id_isar5
= t
;
1959 t
= cpu
->isar
.id_isar6
;
1960 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
1961 cpu
->isar
.id_isar6
= t
;
1964 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
1972 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1976 void (*initfn
)(Object
*obj
);
1977 void (*class_init
)(ObjectClass
*oc
, void *data
);
1980 static const ARMCPUInfo arm_cpus
[] = {
1981 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1982 { .name
= "arm926", .initfn
= arm926_initfn
},
1983 { .name
= "arm946", .initfn
= arm946_initfn
},
1984 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1985 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1986 * older core than plain "arm1136". In particular this does not
1987 * have the v6K features.
1989 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1990 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1991 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1992 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1993 { .name
= "cortex-m0", .initfn
= cortex_m0_initfn
,
1994 .class_init
= arm_v7m_class_init
},
1995 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1996 .class_init
= arm_v7m_class_init
},
1997 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1998 .class_init
= arm_v7m_class_init
},
1999 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
2000 .class_init
= arm_v7m_class_init
},
2001 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
2002 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
2003 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2004 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2005 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2006 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2007 { .name
= "ti925t", .initfn
= ti925t_initfn
},
2008 { .name
= "sa1100", .initfn
= sa1100_initfn
},
2009 { .name
= "sa1110", .initfn
= sa1110_initfn
},
2010 { .name
= "pxa250", .initfn
= pxa250_initfn
},
2011 { .name
= "pxa255", .initfn
= pxa255_initfn
},
2012 { .name
= "pxa260", .initfn
= pxa260_initfn
},
2013 { .name
= "pxa261", .initfn
= pxa261_initfn
},
2014 { .name
= "pxa262", .initfn
= pxa262_initfn
},
2015 /* "pxa270" is an alias for "pxa270-a0" */
2016 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
2017 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
2018 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
2019 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
2020 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
2021 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
2022 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
2023 #ifndef TARGET_AARCH64
2024 { .name
= "max", .initfn
= arm_max_initfn
},
2026 #ifdef CONFIG_USER_ONLY
2027 { .name
= "any", .initfn
= arm_max_initfn
},
2033 static Property arm_cpu_properties
[] = {
2034 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
2035 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2036 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
2037 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2038 mp_affinity
, ARM64_AFFINITY_INVALID
),
2039 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2040 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2041 DEFINE_PROP_END_OF_LIST()
2044 #ifdef CONFIG_USER_ONLY
2045 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int size
,
2046 int rw
, int mmu_idx
)
2048 ARMCPU
*cpu
= ARM_CPU(cs
);
2049 CPUARMState
*env
= &cpu
->env
;
2051 env
->exception
.vaddress
= address
;
2053 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
2055 cs
->exception_index
= EXCP_DATA_ABORT
;
2061 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2063 ARMCPU
*cpu
= ARM_CPU(cs
);
2064 CPUARMState
*env
= &cpu
->env
;
2066 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2067 return g_strdup("iwmmxt");
2069 return g_strdup("arm");
2072 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2074 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2075 CPUClass
*cc
= CPU_CLASS(acc
);
2076 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2078 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2079 &acc
->parent_realize
);
2080 dc
->props
= arm_cpu_properties
;
2082 acc
->parent_reset
= cc
->reset
;
2083 cc
->reset
= arm_cpu_reset
;
2085 cc
->class_by_name
= arm_cpu_class_by_name
;
2086 cc
->has_work
= arm_cpu_has_work
;
2087 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2088 cc
->dump_state
= arm_cpu_dump_state
;
2089 cc
->set_pc
= arm_cpu_set_pc
;
2090 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2091 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2092 #ifdef CONFIG_USER_ONLY
2093 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
2095 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2096 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2097 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2098 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2099 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2100 cc
->vmsd
= &vmstate_arm_cpu
;
2101 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2102 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2103 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2105 cc
->gdb_num_core_regs
= 26;
2106 cc
->gdb_core_xml_file
= "arm-core.xml";
2107 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2108 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2109 cc
->gdb_stop_before_watchpoint
= true;
2110 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2111 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2112 #if !defined(CONFIG_USER_ONLY)
2113 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2116 cc
->disas_set_info
= arm_disas_set_info
;
2118 cc
->tcg_initialize
= arm_translate_init
;
2123 static void arm_host_initfn(Object
*obj
)
2125 ARMCPU
*cpu
= ARM_CPU(obj
);
2127 kvm_arm_set_cpu_features_from_host(cpu
);
2128 arm_cpu_post_init(obj
);
2131 static const TypeInfo host_arm_cpu_type_info
= {
2132 .name
= TYPE_ARM_HOST_CPU
,
2133 #ifdef TARGET_AARCH64
2134 .parent
= TYPE_AARCH64_CPU
,
2136 .parent
= TYPE_ARM_CPU
,
2138 .instance_init
= arm_host_initfn
,
2143 static void arm_cpu_instance_init(Object
*obj
)
2145 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2147 acc
->info
->initfn(obj
);
2148 arm_cpu_post_init(obj
);
2151 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2153 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2158 static void cpu_register(const ARMCPUInfo
*info
)
2160 TypeInfo type_info
= {
2161 .parent
= TYPE_ARM_CPU
,
2162 .instance_size
= sizeof(ARMCPU
),
2163 .instance_init
= arm_cpu_instance_init
,
2164 .class_size
= sizeof(ARMCPUClass
),
2165 .class_init
= info
->class_init
?: cpu_register_class_init
,
2166 .class_data
= (void *)info
,
2169 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2170 type_register(&type_info
);
2171 g_free((void *)type_info
.name
);
2174 static const TypeInfo arm_cpu_type_info
= {
2175 .name
= TYPE_ARM_CPU
,
2177 .instance_size
= sizeof(ARMCPU
),
2178 .instance_init
= arm_cpu_initfn
,
2179 .instance_finalize
= arm_cpu_finalizefn
,
2181 .class_size
= sizeof(ARMCPUClass
),
2182 .class_init
= arm_cpu_class_init
,
2185 static const TypeInfo idau_interface_type_info
= {
2186 .name
= TYPE_IDAU_INTERFACE
,
2187 .parent
= TYPE_INTERFACE
,
2188 .class_size
= sizeof(IDAUInterfaceClass
),
2191 static void arm_cpu_register_types(void)
2193 const ARMCPUInfo
*info
= arm_cpus
;
2195 type_register_static(&arm_cpu_type_info
);
2196 type_register_static(&idau_interface_type_info
);
2198 while (info
->name
) {
2204 type_register_static(&host_arm_cpu_type_info
);
2208 type_init(arm_cpu_register_types
)