disas/mips.c

   1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003
   4    Free Software Foundation, Inc.
   5    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "disas/bfd.h"
  23
  24 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
  25    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
  26    Free Software Foundation, Inc.
  27    Contributed by Ralph Campbell and OSF
  28    Commented and modified by Ian Lance Taylor, Cygnus Support
  29
  30 This file is part of GDB, GAS, and the GNU binutils.
  31
  32 GDB, GAS, and the GNU binutils are free software; you can redistribute
  33 them and/or modify them under the terms of the GNU General Public
  34 License as published by the Free Software Foundation; either version
  35 1, or (at your option) any later version.
  36
  37 GDB, GAS, and the GNU binutils are distributed in the hope that they
  38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  40 the GNU General Public License for more details.
  41
  42 You should have received a copy of the GNU General Public License
  43 along with this file; see the file COPYING.  If not,
  44 see <http://www.gnu.org/licenses/>.  */
  45
  46 /* These are bit masks and shift counts to use to access the various
  47    fields of an instruction.  To retrieve the X field of an
  48    instruction, use the expression
  49         (i >> OP_SH_X) & OP_MASK_X
  50    To set the same field (to j), use
  51         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  52
  53    Make sure you use fields that are appropriate for the instruction,
  54    of course.
  55
  56    The 'i' format uses OP, RS, RT and IMMEDIATE.
  57
  58    The 'j' format uses OP and TARGET.
  59
  60    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  61
  62    The 'b' format uses OP, RS, RT and DELTA.
  63
  64    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  65
  66    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  67
  68    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  69    breakpoint instruction are not defined; Kane says the breakpoint
  70    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  71    only use ten bits).  An optional two-operand form of break/sdbbp
  72    allows the lower ten bits to be set too, and MIPS32 and later
  73    architectures allow 20 bits to be set with a signal operand
  74    (using CODE20).
  75
  76    The syscall instruction uses CODE20.
  77
  78    The general coprocessor instructions use COPZ.  */
  79
  80 #define OP_MASK_OP              0x3f
  81 #define OP_SH_OP                26
  82 #define OP_MASK_RS              0x1f
  83 #define OP_SH_RS                21
  84 #define OP_MASK_FR              0x1f
  85 #define OP_SH_FR                21
  86 #define OP_MASK_FMT             0x1f
  87 #define OP_SH_FMT               21
  88 #define OP_MASK_BCC             0x7
  89 #define OP_SH_BCC               18
  90 #define OP_MASK_CODE            0x3ff
  91 #define OP_SH_CODE              16
  92 #define OP_MASK_CODE2           0x3ff
  93 #define OP_SH_CODE2             6
  94 #define OP_MASK_RT              0x1f
  95 #define OP_SH_RT                16
  96 #define OP_MASK_FT              0x1f
  97 #define OP_SH_FT                16
  98 #define OP_MASK_CACHE           0x1f
  99 #define OP_SH_CACHE             16
 100 #define OP_MASK_RD              0x1f
 101 #define OP_SH_RD                11
 102 #define OP_MASK_FS              0x1f
 103 #define OP_SH_FS                11
 104 #define OP_MASK_PREFX           0x1f
 105 #define OP_SH_PREFX             11
 106 #define OP_MASK_CCC             0x7
 107 #define OP_SH_CCC               8
 108 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
 109 #define OP_SH_CODE20            6
 110 #define OP_MASK_SHAMT           0x1f
 111 #define OP_SH_SHAMT             6
 112 #define OP_MASK_FD              0x1f
 113 #define OP_SH_FD                6
 114 #define OP_MASK_TARGET          0x3ffffff
 115 #define OP_SH_TARGET            0
 116 #define OP_MASK_COPZ            0x1ffffff
 117 #define OP_SH_COPZ              0
 118 #define OP_MASK_IMMEDIATE       0xffff
 119 #define OP_SH_IMMEDIATE         0
 120 #define OP_MASK_DELTA           0xffff
 121 #define OP_SH_DELTA             0
 122 #define OP_MASK_DELTA_R6        0x1ff
 123 #define OP_SH_DELTA_R6          7
 124 #define OP_MASK_FUNCT           0x3f
 125 #define OP_SH_FUNCT             0
 126 #define OP_MASK_SPEC            0x3f
 127 #define OP_SH_SPEC              0
 128 #define OP_SH_LOCC              8       /* FP condition code.  */
 129 #define OP_SH_HICC              18      /* FP condition code.  */
 130 #define OP_MASK_CC              0x7
 131 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 132 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 133 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 134 #define OP_MASK_COP1SPEC        0xf
 135 #define OP_MASK_COP1SCLR        0x4
 136 #define OP_MASK_COP1CMP         0x3
 137 #define OP_SH_COP1CMP           4
 138 #define OP_SH_FORMAT            21      /* FP short format field.  */
 139 #define OP_MASK_FORMAT          0x7
 140 #define OP_SH_TRUE              16
 141 #define OP_MASK_TRUE            0x1
 142 #define OP_SH_GE                17
 143 #define OP_MASK_GE              0x01
 144 #define OP_SH_UNSIGNED          16
 145 #define OP_MASK_UNSIGNED        0x1
 146 #define OP_SH_HINT              16
 147 #define OP_MASK_HINT            0x1f
 148 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 149 #define OP_MASK_MMI             0x3f
 150 #define OP_SH_MMISUB            6
 151 #define OP_MASK_MMISUB          0x1f
 152 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 153 #define OP_SH_PERFREG           1
 154 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 155 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 156 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 157 #define OP_MASK_CODE19          0x7ffff
 158 #define OP_SH_ALN               21
 159 #define OP_MASK_ALN             0x7
 160 #define OP_SH_VSEL              21
 161 #define OP_MASK_VSEL            0x1f
 162 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 163                                            but 0x8-0xf don't select bytes.  */
 164 #define OP_SH_VECBYTE           22
 165 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 166 #define OP_SH_VECALIGN          21
 167 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 168 #define OP_SH_INSMSB            11
 169 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 170 #define OP_SH_EXTMSBD           11
 171
 172 #define OP_OP_COP0              0x10
 173 #define OP_OP_COP1              0x11
 174 #define OP_OP_COP2              0x12
 175 #define OP_OP_COP3              0x13
 176 #define OP_OP_LWC1              0x31
 177 #define OP_OP_LWC2              0x32
 178 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 179 #define OP_OP_LDC1              0x35
 180 #define OP_OP_LDC2              0x36
 181 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 182 #define OP_OP_SWC1              0x39
 183 #define OP_OP_SWC2              0x3a
 184 #define OP_OP_SWC3              0x3b
 185 #define OP_OP_SDC1              0x3d
 186 #define OP_OP_SDC2              0x3e
 187 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 188
 189 /* MIPS DSP ASE */
 190 #define OP_SH_DSPACC            11
 191 #define OP_MASK_DSPACC          0x3
 192 #define OP_SH_DSPACC_S          21
 193 #define OP_MASK_DSPACC_S        0x3
 194 #define OP_SH_DSPSFT            20
 195 #define OP_MASK_DSPSFT          0x3f
 196 #define OP_SH_DSPSFT_7          19
 197 #define OP_MASK_DSPSFT_7        0x7f
 198 #define OP_SH_SA3               21
 199 #define OP_MASK_SA3             0x7
 200 #define OP_SH_SA4               21
 201 #define OP_MASK_SA4             0xf
 202 #define OP_SH_IMM8              16
 203 #define OP_MASK_IMM8            0xff
 204 #define OP_SH_IMM10             16
 205 #define OP_MASK_IMM10           0x3ff
 206 #define OP_SH_WRDSP             11
 207 #define OP_MASK_WRDSP           0x3f
 208 #define OP_SH_RDDSP             16
 209 #define OP_MASK_RDDSP           0x3f
 210 #define OP_SH_BP                11
 211 #define OP_MASK_BP              0x3
 212
 213 /* MIPS MT ASE */
 214 #define OP_SH_MT_U              5
 215 #define OP_MASK_MT_U            0x1
 216 #define OP_SH_MT_H              4
 217 #define OP_MASK_MT_H            0x1
 218 #define OP_SH_MTACC_T           18
 219 #define OP_MASK_MTACC_T         0x3
 220 #define OP_SH_MTACC_D           13
 221 #define OP_MASK_MTACC_D         0x3
 222
 223 #define OP_OP_COP0              0x10
 224 #define OP_OP_COP1              0x11
 225 #define OP_OP_COP2              0x12
 226 #define OP_OP_COP3              0x13
 227 #define OP_OP_LWC1              0x31
 228 #define OP_OP_LWC2              0x32
 229 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 230 #define OP_OP_LDC1              0x35
 231 #define OP_OP_LDC2              0x36
 232 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 233 #define OP_OP_SWC1              0x39
 234 #define OP_OP_SWC2              0x3a
 235 #define OP_OP_SWC3              0x3b
 236 #define OP_OP_SDC1              0x3d
 237 #define OP_OP_SDC2              0x3e
 238 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 239
 240 /* Values in the 'VSEL' field.  */
 241 #define MDMX_FMTSEL_IMM_QH      0x1d
 242 #define MDMX_FMTSEL_IMM_OB      0x1e
 243 #define MDMX_FMTSEL_VEC_QH      0x15
 244 #define MDMX_FMTSEL_VEC_OB      0x16
 245
 246 /* UDI */
 247 #define OP_SH_UDI1              6
 248 #define OP_MASK_UDI1            0x1f
 249 #define OP_SH_UDI2              6
 250 #define OP_MASK_UDI2            0x3ff
 251 #define OP_SH_UDI3              6
 252 #define OP_MASK_UDI3            0x7fff
 253 #define OP_SH_UDI4              6
 254 #define OP_MASK_UDI4            0xfffff
 255 /* This structure holds information for a particular instruction.  */
 256
 257 struct mips_opcode
 258 {
 259   /* The name of the instruction.  */
 260   const char *name;
 261   /* A string describing the arguments for this instruction.  */
 262   const char *args;
 263   /* The basic opcode for the instruction.  When assembling, this
 264      opcode is modified by the arguments to produce the actual opcode
 265      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 266   unsigned long match;
 267   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 268      relevant portions of the opcode when disassembling.  If the
 269      actual opcode anded with the match field equals the opcode field,
 270      then we have found the correct instruction.  If pinfo is
 271      INSN_MACRO, then this field is the macro identifier.  */
 272   unsigned long mask;
 273   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 274      of bits describing the instruction, notably any relevant hazard
 275      information.  */
 276   unsigned long pinfo;
 277   /* A collection of additional bits describing the instruction. */
 278   unsigned long pinfo2;
 279   /* A collection of bits describing the instruction sets of which this
 280      instruction or macro is a member. */
 281   unsigned long membership;
 282 };
 283
 284 /* These are the characters which may appear in the args field of an
 285    instruction.  They appear in the order in which the fields appear
 286    when the instruction is used.  Commas and parentheses in the args
 287    string are ignored when assembling, and written into the output
 288    when disassembling.
 289
 290    Each of these characters corresponds to a mask field defined above.
 291
 292    "<" 5 bit shift amount (OP_*_SHAMT)
 293    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 294    "a" 26 bit target address (OP_*_TARGET)
 295    "b" 5 bit base register (OP_*_RS)
 296    "c" 10 bit breakpoint code (OP_*_CODE)
 297    "d" 5 bit destination register specifier (OP_*_RD)
 298    "h" 5 bit prefx hint (OP_*_PREFX)
 299    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 300    "j" 16 bit signed immediate (OP_*_DELTA)
 301    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 302        Also used for immediate operands in vr5400 vector insns.
 303    "o" 16 bit signed offset (OP_*_DELTA)
 304    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 305    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 306    "r" 5 bit same register used as both source and target (OP_*_RS)
 307    "s" 5 bit source register specifier (OP_*_RS)
 308    "t" 5 bit target register (OP_*_RT)
 309    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 310    "v" 5 bit same register used as both source and destination (OP_*_RS)
 311    "w" 5 bit same register used as both target and destination (OP_*_RT)
 312    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 313        (used by clo and clz)
 314    "C" 25 bit coprocessor function code (OP_*_COPZ)
 315    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 316    "J" 19 bit wait function code (OP_*_CODE19)
 317    "x" accept and ignore register name
 318    "z" must be zero register
 319    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 320    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 321         LSB (OP_*_SHAMT).
 322         Enforces: 0 <= pos < 32.
 323    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 324         Requires that "+A" or "+E" occur first to set position.
 325         Enforces: 0 < (pos+size) <= 32.
 326    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 327         Requires that "+A" or "+E" occur first to set position.
 328         Enforces: 0 < (pos+size) <= 32.
 329         (Also used by "dext" w/ different limits, but limits for
 330         that are checked by the M_DEXT macro.)
 331    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 332         Enforces: 32 <= pos < 64.
 333    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 334         Requires that "+A" or "+E" occur first to set position.
 335         Enforces: 32 < (pos+size) <= 64.
 336    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 337         Requires that "+A" or "+E" occur first to set position.
 338         Enforces: 32 < (pos+size) <= 64.
 339    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 340         Requires that "+A" or "+E" occur first to set position.
 341         Enforces: 32 < (pos+size) <= 64.
 342
 343    Floating point instructions:
 344    "D" 5 bit destination register (OP_*_FD)
 345    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 346    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 347    "S" 5 bit fs source 1 register (OP_*_FS)
 348    "T" 5 bit ft source 2 register (OP_*_FT)
 349    "R" 5 bit fr source 3 register (OP_*_FR)
 350    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 351    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 352
 353    Coprocessor instructions:
 354    "E" 5 bit target register (OP_*_RT)
 355    "G" 5 bit destination register (OP_*_RD)
 356    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 357    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 358    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 359    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 360    see also "k" above
 361    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 362         for pretty-printing in disassembly only.
 363
 364    Macro instructions:
 365    "A" General 32 bit expression
 366    "I" 32 bit immediate (value placed in imm_expr).
 367    "+I" 32 bit immediate (value placed in imm2_expr).
 368    "F" 64 bit floating point constant in .rdata
 369    "L" 64 bit floating point constant in .lit8
 370    "f" 32 bit floating point constant
 371    "l" 32 bit floating point constant in .lit4
 372
 373    MDMX instruction operands (note that while these use the FP register
 374    fields, they accept both $fN and $vN names for the registers):
 375    "O"  MDMX alignment offset (OP_*_ALN)
 376    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 377    "X"  MDMX destination register (OP_*_FD)
 378    "Y"  MDMX source register (OP_*_FS)
 379    "Z"  MDMX source register (OP_*_FT)
 380
 381    DSP ASE usage:
 382    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 383    "3" 3 bit unsigned immediate (OP_*_SA3)
 384    "4" 4 bit unsigned immediate (OP_*_SA4)
 385    "5" 8 bit unsigned immediate (OP_*_IMM8)
 386    "6" 5 bit unsigned immediate (OP_*_RS)
 387    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 388    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 389    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 390    "0" 6 bit signed immediate (OP_*_DSPSFT)
 391    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 392    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 393    "@" 10 bit signed immediate (OP_*_IMM10)
 394
 395    MT ASE usage:
 396    "!" 1 bit usermode flag (OP_*_MT_U)
 397    "$" 1 bit load high flag (OP_*_MT_H)
 398    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 399    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 400    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 401    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 402    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 403
 404    UDI immediates:
 405    "+1" UDI immediate bits 6-10
 406    "+2" UDI immediate bits 6-15
 407    "+3" UDI immediate bits 6-20
 408    "+4" UDI immediate bits 6-25
 409
 410    Other:
 411    "()" parens surrounding optional value
 412    ","  separates operands
 413    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 414    "+"  Start of extension sequence.
 415
 416    Characters used so far, for quick reference when adding more:
 417    "234567890"
 418    "%[]<>(),+:'@!$*&"
 419    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 420    "abcdefghijklopqrstuvwxz"
 421
 422    Extension character sequences used so far ("+" followed by the
 423    following), for quick reference when adding more:
 424    "1234"
 425    "ABCDEFGHIT"
 426    "t"
 427 */
 428
 429 /* These are the bits which may be set in the pinfo field of an
 430    instructions, if it is not equal to INSN_MACRO.  */
 431
 432 /* Modifies the general purpose register in OP_*_RD.  */
 433 #define INSN_WRITE_GPR_D            0x00000001
 434 /* Modifies the general purpose register in OP_*_RT.  */
 435 #define INSN_WRITE_GPR_T            0x00000002
 436 /* Modifies general purpose register 31.  */
 437 #define INSN_WRITE_GPR_31           0x00000004
 438 /* Modifies the floating point register in OP_*_FD.  */
 439 #define INSN_WRITE_FPR_D            0x00000008
 440 /* Modifies the floating point register in OP_*_FS.  */
 441 #define INSN_WRITE_FPR_S            0x00000010
 442 /* Modifies the floating point register in OP_*_FT.  */
 443 #define INSN_WRITE_FPR_T            0x00000020
 444 /* Reads the general purpose register in OP_*_RS.  */
 445 #define INSN_READ_GPR_S             0x00000040
 446 /* Reads the general purpose register in OP_*_RT.  */
 447 #define INSN_READ_GPR_T             0x00000080
 448 /* Reads the floating point register in OP_*_FS.  */
 449 #define INSN_READ_FPR_S             0x00000100
 450 /* Reads the floating point register in OP_*_FT.  */
 451 #define INSN_READ_FPR_T             0x00000200
 452 /* Reads the floating point register in OP_*_FR.  */
 453 #define INSN_READ_FPR_R             0x00000400
 454 /* Modifies coprocessor condition code.  */
 455 #define INSN_WRITE_COND_CODE        0x00000800
 456 /* Reads coprocessor condition code.  */
 457 #define INSN_READ_COND_CODE         0x00001000
 458 /* TLB operation.  */
 459 #define INSN_TLB                    0x00002000
 460 /* Reads coprocessor register other than floating point register.  */
 461 #define INSN_COP                    0x00004000
 462 /* Instruction loads value from memory, requiring delay.  */
 463 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 464 /* Instruction loads value from coprocessor, requiring delay.  */
 465 #define INSN_LOAD_COPROC_DELAY      0x00010000
 466 /* Instruction has unconditional branch delay slot.  */
 467 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 468 /* Instruction has conditional branch delay slot.  */
 469 #define INSN_COND_BRANCH_DELAY      0x00040000
 470 /* Conditional branch likely: if branch not taken, insn nullified.  */
 471 #define INSN_COND_BRANCH_LIKELY     0x00080000
 472 /* Moves to coprocessor register, requiring delay.  */
 473 #define INSN_COPROC_MOVE_DELAY      0x00100000
 474 /* Loads coprocessor register from memory, requiring delay.  */
 475 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 476 /* Reads the HI register.  */
 477 #define INSN_READ_HI                0x00400000
 478 /* Reads the LO register.  */
 479 #define INSN_READ_LO                0x00800000
 480 /* Modifies the HI register.  */
 481 #define INSN_WRITE_HI               0x01000000
 482 /* Modifies the LO register.  */
 483 #define INSN_WRITE_LO               0x02000000
 484 /* Takes a trap (easier to keep out of delay slot).  */
 485 #define INSN_TRAP                   0x04000000
 486 /* Instruction stores value into memory.  */
 487 #define INSN_STORE_MEMORY           0x08000000
 488 /* Instruction uses single precision floating point.  */
 489 #define FP_S                        0x10000000
 490 /* Instruction uses double precision floating point.  */
 491 #define FP_D                        0x20000000
 492 /* Instruction is part of the tx39's integer multiply family.    */
 493 #define INSN_MULT                   0x40000000
 494 /* Instruction synchronize shared memory.  */
 495 #define INSN_SYNC                   0x80000000
 496
 497 /* These are the bits which may be set in the pinfo2 field of an
 498    instruction. */
 499
 500 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 501 #define INSN2_ALIAS                 0x00000001
 502 /* Instruction reads MDMX accumulator. */
 503 #define INSN2_READ_MDMX_ACC         0x00000002
 504 /* Instruction writes MDMX accumulator. */
 505 #define INSN2_WRITE_MDMX_ACC        0x00000004
 506
 507 /* Instruction is actually a macro.  It should be ignored by the
 508    disassembler, and requires special treatment by the assembler.  */
 509 #define INSN_MACRO                  0xffffffff
 510
 511 /* Masks used to mark instructions to indicate which MIPS ISA level
 512    they were introduced in.  ISAs, as defined below, are logical
 513    ORs of these bits, indicating that they support the instructions
 514    defined at the given level.  */
 515
 516 #define INSN_ISA_MASK             0x00000fff
 517 #define INSN_ISA1                 0x00000001
 518 #define INSN_ISA2                 0x00000002
 519 #define INSN_ISA3                 0x00000004
 520 #define INSN_ISA4                 0x00000008
 521 #define INSN_ISA5                 0x00000010
 522 #define INSN_ISA32                0x00000020
 523 #define INSN_ISA64                0x00000040
 524 #define INSN_ISA32R2              0x00000080
 525 #define INSN_ISA64R2              0x00000100
 526 #define INSN_ISA32R6              0x00000200
 527 #define INSN_ISA64R6              0x00000400
 528
 529 /* Masks used for MIPS-defined ASEs.  */
 530 #define INSN_ASE_MASK             0x0000f000
 531
 532 /* DSP ASE */
 533 #define INSN_DSP                  0x00001000
 534 #define INSN_DSP64                0x00002000
 535 /* MIPS 16 ASE */
 536 #define INSN_MIPS16               0x00004000
 537 /* MIPS-3D ASE */
 538 #define INSN_MIPS3D               0x00008000
 539
 540 /* Chip specific instructions.  These are bitmasks.  */
 541
 542 /* MIPS R4650 instruction.  */
 543 #define INSN_4650                 0x00010000
 544 /* LSI R4010 instruction.  */
 545 #define INSN_4010                 0x00020000
 546 /* NEC VR4100 instruction.  */
 547 #define INSN_4100                 0x00040000
 548 /* Toshiba R3900 instruction.  */
 549 #define INSN_3900                 0x00080000
 550 /* MIPS R10000 instruction.  */
 551 #define INSN_10000                0x00100000
 552 /* Broadcom SB-1 instruction.  */
 553 #define INSN_SB1                  0x00200000
 554 /* NEC VR4111/VR4181 instruction.  */
 555 #define INSN_4111                 0x00400000
 556 /* NEC VR4120 instruction.  */
 557 #define INSN_4120                 0x00800000
 558 /* NEC VR5400 instruction.  */
 559 #define INSN_5400                 0x01000000
 560 /* NEC VR5500 instruction.  */
 561 #define INSN_5500                 0x02000000
 562
 563 /* MDMX ASE */
 564 #define INSN_MDMX                 0x04000000
 565 /* MT ASE */
 566 #define INSN_MT                   0x08000000
 567 /* SmartMIPS ASE  */
 568 #define INSN_SMARTMIPS            0x10000000
 569 /* DSP R2 ASE  */
 570 #define INSN_DSPR2                0x20000000
 571
 572 /* ST Microelectronics Loongson 2E.  */
 573 #define INSN_LOONGSON_2E          0x40000000
 574 /* ST Microelectronics Loongson 2F.  */
 575 #define INSN_LOONGSON_2F          0x80000000
 576
 577 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 578
 579 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 580 #define       ISA_MIPS1       (INSN_ISA1)
 581 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 582 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 583 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 584 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 585
 586 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 587 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 588
 589 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 590 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
 591
 592 #define       ISA_MIPS32R6    (ISA_MIPS32R2 | INSN_ISA32R6)
 593 #define       ISA_MIPS64R6    (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
 594
 595 /* CPU defines, use instead of hardcoding processor number. Keep this
 596    in sync with bfd/archures.c in order for machine selection to work.  */
 597 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 598 #define CPU_R3000       3000
 599 #define CPU_R3900       3900
 600 #define CPU_R4000       4000
 601 #define CPU_R4010       4010
 602 #define CPU_VR4100      4100
 603 #define CPU_R4111       4111
 604 #define CPU_VR4120      4120
 605 #define CPU_R4300       4300
 606 #define CPU_R4400       4400
 607 #define CPU_R4600       4600
 608 #define CPU_R4650       4650
 609 #define CPU_R5000       5000
 610 #define CPU_VR5400      5400
 611 #define CPU_VR5500      5500
 612 #define CPU_R6000       6000
 613 #define CPU_RM7000      7000
 614 #define CPU_R8000       8000
 615 #define CPU_R10000      10000
 616 #define CPU_R12000      12000
 617 #define CPU_MIPS16      16
 618 #define CPU_MIPS32      32
 619 #define CPU_MIPS32R2    33
 620 #define CPU_MIPS5       5
 621 #define CPU_MIPS64      64
 622 #define CPU_MIPS64R2    65
 623 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 624
 625 /* Test for membership in an ISA including chip specific ISAs.  INSN
 626    is pointer to an element of the opcode table; ISA is the specified
 627    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 628    test, or zero if no CPU specific ISA test is desired.  */
 629
 630 #if 0
 631 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 632     (((insn)->membership & isa) != 0                                    \
 633      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 634      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)    \
 635      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)    \
 636      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 637      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 638      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 639      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 640          && ((insn)->membership & INSN_10000) != 0)                     \
 641      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 642      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 643      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 644      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 645      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 646      || 0)      /* Please keep this term for easier source merging.  */
 647 #else
 648 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
 649     (1 != 0)
 650 #endif
 651
 652 /* This is a list of macro expanded instructions.
 653
 654    _I appended means immediate
 655    _A appended means address
 656    _AB appended means address with base register
 657    _D appended means 64 bit floating point constant
 658    _S appended means 32 bit floating point constant.  */
 659
 660 enum
 661 {
 662   M_ABS,
 663   M_ADD_I,
 664   M_ADDU_I,
 665   M_AND_I,
 666   M_BALIGN,
 667   M_BEQ,
 668   M_BEQ_I,
 669   M_BEQL_I,
 670   M_BGE,
 671   M_BGEL,
 672   M_BGE_I,
 673   M_BGEL_I,
 674   M_BGEU,
 675   M_BGEUL,
 676   M_BGEU_I,
 677   M_BGEUL_I,
 678   M_BGT,
 679   M_BGTL,
 680   M_BGT_I,
 681   M_BGTL_I,
 682   M_BGTU,
 683   M_BGTUL,
 684   M_BGTU_I,
 685   M_BGTUL_I,
 686   M_BLE,
 687   M_BLEL,
 688   M_BLE_I,
 689   M_BLEL_I,
 690   M_BLEU,
 691   M_BLEUL,
 692   M_BLEU_I,
 693   M_BLEUL_I,
 694   M_BLT,
 695   M_BLTL,
 696   M_BLT_I,
 697   M_BLTL_I,
 698   M_BLTU,
 699   M_BLTUL,
 700   M_BLTU_I,
 701   M_BLTUL_I,
 702   M_BNE,
 703   M_BNE_I,
 704   M_BNEL_I,
 705   M_CACHE_AB,
 706   M_DABS,
 707   M_DADD_I,
 708   M_DADDU_I,
 709   M_DDIV_3,
 710   M_DDIV_3I,
 711   M_DDIVU_3,
 712   M_DDIVU_3I,
 713   M_DEXT,
 714   M_DINS,
 715   M_DIV_3,
 716   M_DIV_3I,
 717   M_DIVU_3,
 718   M_DIVU_3I,
 719   M_DLA_AB,
 720   M_DLCA_AB,
 721   M_DLI,
 722   M_DMUL,
 723   M_DMUL_I,
 724   M_DMULO,
 725   M_DMULO_I,
 726   M_DMULOU,
 727   M_DMULOU_I,
 728   M_DREM_3,
 729   M_DREM_3I,
 730   M_DREMU_3,
 731   M_DREMU_3I,
 732   M_DSUB_I,
 733   M_DSUBU_I,
 734   M_DSUBU_I_2,
 735   M_J_A,
 736   M_JAL_1,
 737   M_JAL_2,
 738   M_JAL_A,
 739   M_L_DOB,
 740   M_L_DAB,
 741   M_LA_AB,
 742   M_LB_A,
 743   M_LB_AB,
 744   M_LBU_A,
 745   M_LBU_AB,
 746   M_LCA_AB,
 747   M_LD_A,
 748   M_LD_OB,
 749   M_LD_AB,
 750   M_LDC1_AB,
 751   M_LDC2_AB,
 752   M_LDC3_AB,
 753   M_LDL_AB,
 754   M_LDR_AB,
 755   M_LH_A,
 756   M_LH_AB,
 757   M_LHU_A,
 758   M_LHU_AB,
 759   M_LI,
 760   M_LI_D,
 761   M_LI_DD,
 762   M_LI_S,
 763   M_LI_SS,
 764   M_LL_AB,
 765   M_LLD_AB,
 766   M_LS_A,
 767   M_LW_A,
 768   M_LW_AB,
 769   M_LWC0_A,
 770   M_LWC0_AB,
 771   M_LWC1_A,
 772   M_LWC1_AB,
 773   M_LWC2_A,
 774   M_LWC2_AB,
 775   M_LWC3_A,
 776   M_LWC3_AB,
 777   M_LWL_A,
 778   M_LWL_AB,
 779   M_LWR_A,
 780   M_LWR_AB,
 781   M_LWU_AB,
 782   M_MOVE,
 783   M_MUL,
 784   M_MUL_I,
 785   M_MULO,
 786   M_MULO_I,
 787   M_MULOU,
 788   M_MULOU_I,
 789   M_NOR_I,
 790   M_OR_I,
 791   M_REM_3,
 792   M_REM_3I,
 793   M_REMU_3,
 794   M_REMU_3I,
 795   M_DROL,
 796   M_ROL,
 797   M_DROL_I,
 798   M_ROL_I,
 799   M_DROR,
 800   M_ROR,
 801   M_DROR_I,
 802   M_ROR_I,
 803   M_S_DA,
 804   M_S_DOB,
 805   M_S_DAB,
 806   M_S_S,
 807   M_SC_AB,
 808   M_SCD_AB,
 809   M_SD_A,
 810   M_SD_OB,
 811   M_SD_AB,
 812   M_SDC1_AB,
 813   M_SDC2_AB,
 814   M_SDC3_AB,
 815   M_SDL_AB,
 816   M_SDR_AB,
 817   M_SEQ,
 818   M_SEQ_I,
 819   M_SGE,
 820   M_SGE_I,
 821   M_SGEU,
 822   M_SGEU_I,
 823   M_SGT,
 824   M_SGT_I,
 825   M_SGTU,
 826   M_SGTU_I,
 827   M_SLE,
 828   M_SLE_I,
 829   M_SLEU,
 830   M_SLEU_I,
 831   M_SLT_I,
 832   M_SLTU_I,
 833   M_SNE,
 834   M_SNE_I,
 835   M_SB_A,
 836   M_SB_AB,
 837   M_SH_A,
 838   M_SH_AB,
 839   M_SW_A,
 840   M_SW_AB,
 841   M_SWC0_A,
 842   M_SWC0_AB,
 843   M_SWC1_A,
 844   M_SWC1_AB,
 845   M_SWC2_A,
 846   M_SWC2_AB,
 847   M_SWC3_A,
 848   M_SWC3_AB,
 849   M_SWL_A,
 850   M_SWL_AB,
 851   M_SWR_A,
 852   M_SWR_AB,
 853   M_SUB_I,
 854   M_SUBU_I,
 855   M_SUBU_I_2,
 856   M_TEQ_I,
 857   M_TGE_I,
 858   M_TGEU_I,
 859   M_TLT_I,
 860   M_TLTU_I,
 861   M_TNE_I,
 862   M_TRUNCWD,
 863   M_TRUNCWS,
 864   M_ULD,
 865   M_ULD_A,
 866   M_ULH,
 867   M_ULH_A,
 868   M_ULHU,
 869   M_ULHU_A,
 870   M_ULW,
 871   M_ULW_A,
 872   M_USH,
 873   M_USH_A,
 874   M_USW,
 875   M_USW_A,
 876   M_USD,
 877   M_USD_A,
 878   M_XOR_I,
 879   M_COP0,
 880   M_COP1,
 881   M_COP2,
 882   M_COP3,
 883   M_NUM_MACROS
 884 };
 885
 886
 887 /* The order of overloaded instructions matters.  Label arguments and
 888    register arguments look the same. Instructions that can have either
 889    for arguments must apear in the correct order in this table for the
 890    assembler to pick the right one. In other words, entries with
 891    immediate operands must apear after the same instruction with
 892    registers.
 893
 894    Many instructions are short hand for other instructions (i.e., The
 895    jal <register> instruction is short for jalr <register>).  */
 896
 897 extern const struct mips_opcode mips_builtin_opcodes[];
 898 extern const int bfd_mips_num_builtin_opcodes;
 899 extern struct mips_opcode *mips_opcodes;
 900 extern int bfd_mips_num_opcodes;
 901 #define NUMOPCODES bfd_mips_num_opcodes
 902
 903 \f
 904 /* The rest of this file adds definitions for the mips16 TinyRISC
 905    processor.  */
 906
 907 /* These are the bitmasks and shift counts used for the different
 908    fields in the instruction formats.  Other than OP, no masks are
 909    provided for the fixed portions of an instruction, since they are
 910    not needed.
 911
 912    The I format uses IMM11.
 913
 914    The RI format uses RX and IMM8.
 915
 916    The RR format uses RX, and RY.
 917
 918    The RRI format uses RX, RY, and IMM5.
 919
 920    The RRR format uses RX, RY, and RZ.
 921
 922    The RRI_A format uses RX, RY, and IMM4.
 923
 924    The SHIFT format uses RX, RY, and SHAMT.
 925
 926    The I8 format uses IMM8.
 927
 928    The I8_MOVR32 format uses RY and REGR32.
 929
 930    The IR_MOV32R format uses REG32R and MOV32Z.
 931
 932    The I64 format uses IMM8.
 933
 934    The RI64 format uses RY and IMM5.
 935    */
 936
 937 #define MIPS16OP_MASK_OP        0x1f
 938 #define MIPS16OP_SH_OP          11
 939 #define MIPS16OP_MASK_IMM11     0x7ff
 940 #define MIPS16OP_SH_IMM11       0
 941 #define MIPS16OP_MASK_RX        0x7
 942 #define MIPS16OP_SH_RX          8
 943 #define MIPS16OP_MASK_IMM8      0xff
 944 #define MIPS16OP_SH_IMM8        0
 945 #define MIPS16OP_MASK_RY        0x7
 946 #define MIPS16OP_SH_RY          5
 947 #define MIPS16OP_MASK_IMM5      0x1f
 948 #define MIPS16OP_SH_IMM5        0
 949 #define MIPS16OP_MASK_RZ        0x7
 950 #define MIPS16OP_SH_RZ          2
 951 #define MIPS16OP_MASK_IMM4      0xf
 952 #define MIPS16OP_SH_IMM4        0
 953 #define MIPS16OP_MASK_REGR32    0x1f
 954 #define MIPS16OP_SH_REGR32      0
 955 #define MIPS16OP_MASK_REG32R    0x1f
 956 #define MIPS16OP_SH_REG32R      3
 957 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 958 #define MIPS16OP_MASK_MOVE32Z   0x7
 959 #define MIPS16OP_SH_MOVE32Z     0
 960 #define MIPS16OP_MASK_IMM6      0x3f
 961 #define MIPS16OP_SH_IMM6        5
 962
 963 /* These are the characters which may appears in the args field of an
 964    instruction.  They appear in the order in which the fields appear
 965    when the instruction is used.  Commas and parentheses in the args
 966    string are ignored when assembling, and written into the output
 967    when disassembling.
 968
 969    "y" 3 bit register (MIPS16OP_*_RY)
 970    "x" 3 bit register (MIPS16OP_*_RX)
 971    "z" 3 bit register (MIPS16OP_*_RZ)
 972    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 973    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 974    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 975    "0" zero register ($0)
 976    "S" stack pointer ($sp or $29)
 977    "P" program counter
 978    "R" return address register ($ra or $31)
 979    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 980    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 981    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 982    "a" 26 bit jump address
 983    "e" 11 bit extension value
 984    "l" register list for entry instruction
 985    "L" register list for exit instruction
 986
 987    The remaining codes may be extended.  Except as otherwise noted,
 988    the full extended operand is a 16 bit signed value.
 989    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 990    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 991    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 992    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 993    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 994    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 995    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 996    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 997    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 998    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 999    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1000    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1001    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1002    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1003    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1004    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1005    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1006    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1007    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1008    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1009    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1010    */
1011
1012 /* Save/restore encoding for the args field when all 4 registers are
1013    either saved as arguments or saved/restored as statics.  */
1014 #define MIPS16_ALL_ARGS    0xe
1015 #define MIPS16_ALL_STATICS 0xb
1016
1017 /* For the mips16, we use the same opcode table format and a few of
1018    the same flags.  However, most of the flags are different.  */
1019
1020 /* Modifies the register in MIPS16OP_*_RX.  */
1021 #define MIPS16_INSN_WRITE_X                 0x00000001
1022 /* Modifies the register in MIPS16OP_*_RY.  */
1023 #define MIPS16_INSN_WRITE_Y                 0x00000002
1024 /* Modifies the register in MIPS16OP_*_RZ.  */
1025 #define MIPS16_INSN_WRITE_Z                 0x00000004
1026 /* Modifies the T ($24) register.  */
1027 #define MIPS16_INSN_WRITE_T                 0x00000008
1028 /* Modifies the SP ($29) register.  */
1029 #define MIPS16_INSN_WRITE_SP                0x00000010
1030 /* Modifies the RA ($31) register.  */
1031 #define MIPS16_INSN_WRITE_31                0x00000020
1032 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1033 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1034 /* Reads the register in MIPS16OP_*_RX.  */
1035 #define MIPS16_INSN_READ_X                  0x00000080
1036 /* Reads the register in MIPS16OP_*_RY.  */
1037 #define MIPS16_INSN_READ_Y                  0x00000100
1038 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1039 #define MIPS16_INSN_READ_Z                  0x00000200
1040 /* Reads the T ($24) register.  */
1041 #define MIPS16_INSN_READ_T                  0x00000400
1042 /* Reads the SP ($29) register.  */
1043 #define MIPS16_INSN_READ_SP                 0x00000800
1044 /* Reads the RA ($31) register.  */
1045 #define MIPS16_INSN_READ_31                 0x00001000
1046 /* Reads the program counter.  */
1047 #define MIPS16_INSN_READ_PC                 0x00002000
1048 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1049 #define MIPS16_INSN_READ_GPR_X              0x00004000
1050 /* Is a branch insn. */
1051 #define MIPS16_INSN_BRANCH                  0x00010000
1052
1053 /* The following flags have the same value for the mips16 opcode
1054    table:
1055    INSN_UNCOND_BRANCH_DELAY
1056    INSN_COND_BRANCH_DELAY
1057    INSN_COND_BRANCH_LIKELY (never used)
1058    INSN_READ_HI
1059    INSN_READ_LO
1060    INSN_WRITE_HI
1061    INSN_WRITE_LO
1062    INSN_TRAP
1063    INSN_ISA3
1064    */
1065
1066 extern const struct mips_opcode mips16_opcodes[];
1067 extern const int bfd_mips16_num_opcodes;
1068
1069 /* Short hand so the lines aren't too long.  */
1070
1071 #define LDD     INSN_LOAD_MEMORY_DELAY
1072 #define LCD     INSN_LOAD_COPROC_DELAY
1073 #define UBD     INSN_UNCOND_BRANCH_DELAY
1074 #define CBD     INSN_COND_BRANCH_DELAY
1075 #define COD     INSN_COPROC_MOVE_DELAY
1076 #define CLD     INSN_COPROC_MEMORY_DELAY
1077 #define CBL     INSN_COND_BRANCH_LIKELY
1078 #define TRAP    INSN_TRAP
1079 #define SM      INSN_STORE_MEMORY
1080
1081 #define WR_d    INSN_WRITE_GPR_D
1082 #define WR_t    INSN_WRITE_GPR_T
1083 #define WR_31   INSN_WRITE_GPR_31
1084 #define WR_D    INSN_WRITE_FPR_D
1085 #define WR_T    INSN_WRITE_FPR_T
1086 #define WR_S    INSN_WRITE_FPR_S
1087 #define RD_s    INSN_READ_GPR_S
1088 #define RD_b    INSN_READ_GPR_S
1089 #define RD_t    INSN_READ_GPR_T
1090 #define RD_S    INSN_READ_FPR_S
1091 #define RD_T    INSN_READ_FPR_T
1092 #define RD_R    INSN_READ_FPR_R
1093 #define WR_CC   INSN_WRITE_COND_CODE
1094 #define RD_CC   INSN_READ_COND_CODE
1095 #define RD_C0   INSN_COP
1096 #define RD_C1   INSN_COP
1097 #define RD_C2   INSN_COP
1098 #define RD_C3   INSN_COP
1099 #define WR_C0   INSN_COP
1100 #define WR_C1   INSN_COP
1101 #define WR_C2   INSN_COP
1102 #define WR_C3   INSN_COP
1103
1104 #define WR_HI   INSN_WRITE_HI
1105 #define RD_HI   INSN_READ_HI
1106 #define MOD_HI  WR_HI|RD_HI
1107
1108 #define WR_LO   INSN_WRITE_LO
1109 #define RD_LO   INSN_READ_LO
1110 #define MOD_LO  WR_LO|RD_LO
1111
1112 #define WR_HILO WR_HI|WR_LO
1113 #define RD_HILO RD_HI|RD_LO
1114 #define MOD_HILO WR_HILO|RD_HILO
1115
1116 #define IS_M    INSN_MULT
1117
1118 #define WR_MACC INSN2_WRITE_MDMX_ACC
1119 #define RD_MACC INSN2_READ_MDMX_ACC
1120
1121 #define I1      INSN_ISA1
1122 #define I2      INSN_ISA2
1123 #define I3      INSN_ISA3
1124 #define I4      INSN_ISA4
1125 #define I5      INSN_ISA5
1126 #define I32     INSN_ISA32
1127 #define I64     INSN_ISA64
1128 #define I33     INSN_ISA32R2
1129 #define I65     INSN_ISA64R2
1130 #define I32R6   INSN_ISA32R6
1131 #define I64R6   INSN_ISA64R6
1132
1133 /* MIPS64 MIPS-3D ASE support.  */
1134 #define I16     INSN_MIPS16
1135
1136 /* MIPS32 SmartMIPS ASE support.  */
1137 #define SMT     INSN_SMARTMIPS
1138
1139 /* MIPS64 MIPS-3D ASE support.  */
1140 #define M3D     INSN_MIPS3D
1141
1142 /* MIPS64 MDMX ASE support.  */
1143 #define MX      INSN_MDMX
1144
1145 #define IL2E    (INSN_LOONGSON_2E)
1146 #define IL2F    (INSN_LOONGSON_2F)
1147
1148 #define P3      INSN_4650
1149 #define L1      INSN_4010
1150 #define V1      (INSN_4100 | INSN_4111 | INSN_4120)
1151 #define T3      INSN_3900
1152 #define M1      INSN_10000
1153 #define SB1     INSN_SB1
1154 #define N411    INSN_4111
1155 #define N412    INSN_4120
1156 #define N5      (INSN_5400 | INSN_5500)
1157 #define N54     INSN_5400
1158 #define N55     INSN_5500
1159
1160 #define G1      (T3             \
1161                  )
1162
1163 #define G2      (T3             \
1164                  )
1165
1166 #define G3      (I4             \
1167                  )
1168
1169 /* MIPS DSP ASE support.
1170    NOTE:
1171    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
1172    of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
1173    the same structure as $ac0 (HI + LO).  For DSP instructions that write or
1174    read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1175    (RD_HILO) attributes, such that HILO dependencies are maintained
1176    conservatively.
1177
1178    2. For some mul. instructions that use integer registers as destinations
1179    but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1180
1181    3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1182    (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
1183    certain fields of the DSP control register.  For simplicity, we decide not
1184    to track dependencies of these fields.
1185    However, "bposge32" is a branch instruction that depends on the "pos"
1186    field.  In order to make sure that GAS does not reorder DSP instructions
1187    that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1188    attribute to those instructions that write the "pos" field.  */
1189
1190 #define WR_a    WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */
1191 #define RD_a    RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */
1192 #define MOD_a   WR_a|RD_a
1193 #define DSP_VOLA        INSN_TRAP
1194 #define D32     INSN_DSP
1195 #define D33     INSN_DSPR2
1196 #define D64     INSN_DSP64
1197
1198 /* MIPS MT ASE support.  */
1199 #define MT32    INSN_MT
1200
1201 /* The order of overloaded instructions matters.  Label arguments and
1202    register arguments look the same. Instructions that can have either
1203    for arguments must apear in the correct order in this table for the
1204    assembler to pick the right one. In other words, entries with
1205    immediate operands must apear after the same instruction with
1206    registers.
1207
1208    Because of the lookup algorithm used, entries with the same opcode
1209    name must be contiguous.
1210
1211    Many instructions are short hand for other instructions (i.e., The
1212    jal <register> instruction is short for jalr <register>).  */
1213
1214 const struct mips_opcode mips_builtin_opcodes[] =
1215 {
1216 /* These instructions appear first so that the disassembler will find
1217    them first.  The assemblers uses a hash table based on the
1218    instruction name anyhow.  */
1219 /* name,    args,       match,      mask,       pinfo,                  membership */
1220 {"ll",      "t,o(b)",   0x7c000036, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},
1221 {"sc",      "t,o(b)",   0x7c000026, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},
1222 {"lld",     "t,o(b)",   0x7c000037, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},
1223 {"scd",     "t,o(b)",   0x7c000027, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},
1224 {"pref",    "h,o(b)",   0x7c000035, 0xfc00007f, RD_b,                 0, I32R6},
1225 {"cache",   "k,o(b)",   0x7c000025, 0xfc00007f, RD_b,                 0, I32R6},
1226 {"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1227 {"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1228 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,              I4|I32|G3       },
1229 {"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4|I33  },
1230 {"nop",     "",         0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,    I1      }, /* sll */
1231 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,    I32|N55 }, /* sll */
1232 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,    I33     }, /* sll */
1233 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* addiu */
1234 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */
1235 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO,             0,              I1      },
1236 {"move",    "d,s",      0,    (int) M_MOVE,     INSN_MACRO,             0,              I1      },
1237 {"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I3      },/* daddu */
1238 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* addu */
1239 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* or */
1240 {"b",       "p",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* beq 0,0 */
1241 {"b",       "p",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* bgez 0 */
1242 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS,    I1      },/* bgezal 0*/
1243
1244 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
1245 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1246 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1247 {"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1248 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1249 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
1250 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1251 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1252 {"add.ob",  "X,Y,Q",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1253 {"add.ob",  "D,S,T",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1254 {"add.ob",  "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1255 {"add.ob",  "D,S,k",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1256 {"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1257 {"add.qh",  "X,Y,Q",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1258 {"adda.ob", "Y,Q",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1259 {"adda.qh", "Y,Q",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1260 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1261 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1262 {"addl.ob", "Y,Q",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1263 {"addl.qh", "Y,Q",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1264 {"addr.ps", "D,S,T",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1265 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1266 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
1267 {"alni.ob", "X,Y,Z,O",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1268 {"alni.ob", "D,S,T,%",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
1269 {"alni.qh", "X,Y,Z,O",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1270 {"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1271 {"alnv.ob", "X,Y,Z,s",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX|SB1  },
1272 {"alnv.qh", "X,Y,Z,s",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
1273 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1274 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
1275 {"and.ob",  "X,Y,Q",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1276 {"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1277 {"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1278 {"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1279 {"and.qh",  "X,Y,Q",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1280 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1281 /* b is at the top of the table.  */
1282 /* bal is at the top of the table.  */
1283 /* bc0[tf]l? are at the bottom of the table.  */
1284 {"bc1any2f", "N,p",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1285 {"bc1any2t", "N,p",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1286 {"bc1any4f", "N,p",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1287 {"bc1any4t", "N,p",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1288 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
1289 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
1290 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
1291 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
1292 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
1293 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
1294 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
1295 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
1296 /* bc2* are at the bottom of the table.  */
1297 /* bc3* are at the bottom of the table.  */
1298 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1299 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1300 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
1301 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO,             0,              I1      },
1302 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
1303 {"beql",    "s,I,p",    0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I2|T3   },
1304 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO,             0,              I1      },
1305 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO,             0,              I1      },
1306 {"bgel",    "s,t,p",    0,    (int) M_BGEL,     INSN_MACRO,             0,              I2|T3   },
1307 {"bgel",    "s,I,p",    0,    (int) M_BGEL_I,   INSN_MACRO,             0,              I2|T3   },
1308 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO,             0,              I1      },
1309 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO,             0,              I1      },
1310 {"bgeul",   "s,t,p",    0,    (int) M_BGEUL,    INSN_MACRO,             0,              I2|T3   },
1311 {"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,  INSN_MACRO,             0,              I2|T3   },
1312 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1313 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1314 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
1315 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
1316 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO,             0,              I1      },
1317 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO,             0,              I1      },
1318 {"bgtl",    "s,t,p",    0,    (int) M_BGTL,     INSN_MACRO,             0,              I2|T3   },
1319 {"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,   INSN_MACRO,             0,              I2|T3   },
1320 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO,             0,              I1      },
1321 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO,             0,              I1      },
1322 {"bgtul",   "s,t,p",    0,    (int) M_BGTUL,    INSN_MACRO,             0,              I2|T3   },
1323 {"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,  INSN_MACRO,             0,              I2|T3   },
1324 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1325 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1326 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO,             0,              I1      },
1327 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO,             0,              I1      },
1328 {"blel",    "s,t,p",    0,    (int) M_BLEL,     INSN_MACRO,             0,              I2|T3   },
1329 {"blel",    "s,I,p",    0,    (int) M_BLEL_I,   INSN_MACRO,             0,              I2|T3   },
1330 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO,             0,              I1      },
1331 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO,             0,              I1      },
1332 {"bleul",   "s,t,p",    0,    (int) M_BLEUL,    INSN_MACRO,             0,              I2|T3   },
1333 {"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,  INSN_MACRO,             0,              I2|T3   },
1334 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1335 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1336 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO,             0,              I1      },
1337 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO,             0,              I1      },
1338 {"bltl",    "s,t,p",    0,    (int) M_BLTL,     INSN_MACRO,             0,              I2|T3   },
1339 {"bltl",    "s,I,p",    0,    (int) M_BLTL_I,   INSN_MACRO,             0,              I2|T3   },
1340 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO,             0,              I1      },
1341 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO,             0,              I1      },
1342 {"bltul",   "s,t,p",    0,    (int) M_BLTUL,    INSN_MACRO,             0,              I2|T3   },
1343 {"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,  INSN_MACRO,             0,              I2|T3   },
1344 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1345 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1346 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
1347 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
1348 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1349 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1350 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
1351 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO,             0,              I1      },
1352 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
1353 {"bnel",    "s,I,p",    0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I2|T3   },
1354 {"break",   "",         0x0000000d, 0xffffffff, TRAP,                   0,              I1      },
1355 {"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   0,              I1      },
1356 {"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   0,              I1      },
1357 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1358 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1359 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1360 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1361 {"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1362 {"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1363 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1364 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1365 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1366 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1367 {"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1368 {"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1369 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1370 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1371 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1372 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1373 {"c.eq.ob", "Y,Q",      0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1374 {"c.eq.ob", "S,T",      0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1375 {"c.eq.ob", "S,T[e]",   0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1376 {"c.eq.ob", "S,k",      0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1377 {"c.eq.ps", "S,T",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1378 {"c.eq.ps", "M,S,T",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1379 {"c.eq.qh", "Y,Q",      0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1380 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1381 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1382 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1383 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1384 {"c.ueq.ps","S,T",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1385 {"c.ueq.ps","M,S,T",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1386 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1387 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1388 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1389 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1390 {"c.olt.ps","S,T",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1391 {"c.olt.ps","M,S,T",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1392 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1393 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1394 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1395 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1396 {"c.ult.ps","S,T",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1397 {"c.ult.ps","M,S,T",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1398 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1399 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1400 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1401 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1402 {"c.ole.ps","S,T",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1403 {"c.ole.ps","M,S,T",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1404 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1405 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1406 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1407 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1408 {"c.ule.ps","S,T",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1409 {"c.ule.ps","M,S,T",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1410 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1411 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1412 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1413 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1414 {"c.sf.ps", "S,T",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1415 {"c.sf.ps", "M,S,T",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1416 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1417 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1418 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1419 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1420 {"c.ngle.ps","S,T",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1421 {"c.ngle.ps","M,S,T",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1422 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1423 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1424 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1425 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1426 {"c.seq.ps","S,T",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1427 {"c.seq.ps","M,S,T",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1428 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1429 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1430 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1431 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1432 {"c.ngl.ps","S,T",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1433 {"c.ngl.ps","M,S,T",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1434 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1435 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1436 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1437 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1438 {"c.lt.ob", "Y,Q",      0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1439 {"c.lt.ob", "S,T",      0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1440 {"c.lt.ob", "S,T[e]",   0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1441 {"c.lt.ob", "S,k",      0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1442 {"c.lt.ps", "S,T",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1443 {"c.lt.ps", "M,S,T",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1444 {"c.lt.qh", "Y,Q",      0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1445 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1446 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1447 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1448 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1449 {"c.nge.ps","S,T",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1450 {"c.nge.ps","M,S,T",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1451 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1452 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1453 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1454 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1455 {"c.le.ob", "Y,Q",      0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1456 {"c.le.ob", "S,T",      0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1457 {"c.le.ob", "S,T[e]",   0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1458 {"c.le.ob", "S,k",      0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1459 {"c.le.ps", "S,T",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1460 {"c.le.ps", "M,S,T",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1461 {"c.le.qh", "Y,Q",      0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1462 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1463 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1464 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1465 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1466 {"c.ngt.ps","S,T",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1467 {"c.ngt.ps","M,S,T",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1468 {"cabs.eq.d",  "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1469 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1470 {"cabs.eq.s",  "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1471 {"cabs.f.d",   "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1472 {"cabs.f.ps",  "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1473 {"cabs.f.s",   "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1474 {"cabs.le.d",  "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1475 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1476 {"cabs.le.s",  "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1477 {"cabs.lt.d",  "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1478 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1479 {"cabs.lt.s",  "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1480 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1481 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1482 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1483 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1484 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1485 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1486 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1487 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1488 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1489 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1490 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1491 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1492 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1493 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1494 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1495 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1496 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1497 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1498 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1499 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1500 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1501 {"cabs.sf.d",  "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1502 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1503 {"cabs.sf.s",  "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1504 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1505 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1506 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1507 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1508 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1509 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1510 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1511 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1512 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1513 {"cabs.un.d",  "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1514 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1515 {"cabs.un.s",  "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1516 /* CW4010 instructions which are aliases for the cache instruction.  */
1517 {"flushi",  "",         0xbc010000, 0xffffffff, 0,                      0,              L1      },
1518 {"flushd",  "",         0xbc020000, 0xffffffff, 0,                      0,              L1      },
1519 {"flushid", "",         0xbc030000, 0xffffffff, 0,                      0,              L1      },
1520 {"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                0,              L1      },
1521 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   0,              I3|I32|T3},
1522 {"cache",   "k,A(b)",   0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3|I32|T3},
1523 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1524 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1525 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
1526 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
1527 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
1528 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
1529 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
1530 /* cfc2 is at the bottom of the table.  */
1531 /* cfc3 is at the bottom of the table.  */
1532 {"cftc1",   "d,E",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
1533 {"cftc1",   "d,T",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
1534 {"cftc2",   "d,E",      0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1535 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
1536 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
1537 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
1538 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
1539 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
1540 /* ctc2 is at the bottom of the table.  */
1541 /* ctc3 is at the bottom of the table.  */
1542 {"cttc1",   "t,g",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
1543 {"cttc1",   "t,S",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
1544 {"cttc2",   "t,g",      0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
1545 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1546 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1547 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1548 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1549 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1550 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1551 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1552 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1553 {"cvt.s.pl","D,S",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
1554 {"cvt.s.pu","D,S",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
1555 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1556 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1557 {"cvt.ps.pw", "D,S",    0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
1558 {"cvt.ps.s","D,V,T",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5|I33  },
1559 {"cvt.pw.ps", "D,S",    0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
1560 {"dabs",    "d,v",      0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
1561 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1562 {"dadd",    "t,r,I",    0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
1563 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
1564 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
1565 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1566 {"daddu",   "t,r,I",    0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3      },
1567 {"dbreak",  "",         0x7000003f, 0xffffffff, 0,                      0,              N5      },
1568 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
1569 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
1570 /* dctr and dctw are used on the r5000.  */
1571 {"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,                   0,              I3      },
1572 {"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,                   0,              I3      },
1573 {"deret",   "",         0x4200001f, 0xffffffff, 0,                      0,              I32|G2  },
1574 {"dext",    "t,r,I,+I", 0,    (int) M_DEXT,     INSN_MACRO,             0,              I65     },
1575 {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1576 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1577 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1578 /* For ddiv, see the comments about div.  */
1579 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1580 {"ddiv",    "d,v,t",    0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3      },
1581 {"ddiv",    "d,v,I",    0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3      },
1582 /* For ddivu, see the comments about div.  */
1583 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1584 {"ddivu",   "d,v,t",    0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
1585 {"ddivu",   "d,v,I",    0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
1586 {"di",      "",         0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
1587 {"di",      "t",        0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
1588 {"dins",    "t,r,I,+I", 0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
1589 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1590 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1591 {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1592 /* The MIPS assembler treats the div opcode with two operands as
1593    though the first operand appeared twice (the first operand is both
1594    a source and a destination).  To get the div machine instruction,
1595    you must use an explicit destination of $0.  */
1596 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1597 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1598 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO,             0,              I1      },
1599 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1      },
1600 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1601 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1602 {"div.ps",  "D,V,T",    0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
1603 /* For divu, see the comments about div.  */
1604 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1605 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1606 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO,             0,              I1      },
1607 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO,             0,              I1      },
1608 {"dla",     "t,A(b)",   0,    (int) M_DLA_AB,   INSN_MACRO,             0,              I3      },
1609 {"dlca",    "t,A(b)",   0,    (int) M_DLCA_AB,  INSN_MACRO,             0,              I3      },
1610 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                   0,              I3      }, /* addiu */
1611 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,                   0,              I3      }, /* ori */
1612 {"dli",     "t,I",      0,    (int) M_DLI,      INSN_MACRO,             0,              I3      },
1613 {"dmacc",   "d,s,t",    0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1614 {"dmacchi", "d,s,t",    0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1615 {"dmacchis", "d,s,t",   0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1616 {"dmacchiu", "d,s,t",   0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1617 {"dmacchius", "d,s,t",  0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1618 {"dmaccs",  "d,s,t",    0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1619 {"dmaccu",  "d,s,t",    0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1620 {"dmaccus", "d,s,t",    0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1621 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,              N411    },
1622 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
1623 {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
1624 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
1625 {"dmt",     "",         0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
1626 {"dmt",     "t",        0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1627 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
1628 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
1629 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
1630 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
1631 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
1632 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
1633 {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
1634 /* dmfc2 is at the bottom of the table.  */
1635 /* dmtc2 is at the bottom of the table.  */
1636 /* dmfc3 is at the bottom of the table.  */
1637 /* dmtc3 is at the bottom of the table.  */
1638 {"dmul",    "d,v,t",    0,    (int) M_DMUL,     INSN_MACRO,             0,              I3      },
1639 {"dmul",    "d,v,I",    0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3      },
1640 {"dmulo",   "d,v,t",    0,    (int) M_DMULO,    INSN_MACRO,             0,              I3      },
1641 {"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3      },
1642 {"dmulou",  "d,v,t",    0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3      },
1643 {"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3      },
1644 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1645 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1646 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
1647 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
1648 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1649 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
1650 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
1651 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1652 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
1653 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
1654 {"dret",    "",         0x7000003e, 0xffffffff, 0,                      0,              N5      },
1655 {"drol",    "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
1656 {"drol",    "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },
1657 {"dror",    "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I3      },
1658 {"dror",    "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I3      },
1659 {"dror",    "d,w,<",    0x0020003a, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
1660 {"drorv",   "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I65  },
1661 {"dror32",  "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
1662 {"drotl",   "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I65     },
1663 {"drotl",   "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I65     },
1664 {"drotr",   "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I65     },
1665 {"drotr",   "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I65     },
1666 {"drotrv",  "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I65     },
1667 {"drotr32", "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              I65     },
1668 {"dsbh",    "d,w",      0x7c0000a4, 0xffe007ff, WR_d|RD_t,              0,              I65     },
1669 {"dshd",    "d,w",      0x7c000164, 0xffe007ff, WR_d|RD_t,              0,              I65     },
1670 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1671 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1672 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsllv */
1673 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsll32 */
1674 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1675 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1676 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1677 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrav */
1678 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsra32 */
1679 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1680 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1681 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1682 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrlv */
1683 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsrl32 */
1684 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1685 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1686 {"dsub",    "d,v,I",    0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3      },
1687 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1688 {"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
1689 {"dvpe",    "",         0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
1690 {"dvpe",    "t",        0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1691 {"ei",      "",         0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
1692 {"ei",      "t",        0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
1693 {"emt",     "",         0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
1694 {"emt",     "t",        0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1695 {"eret",    "",         0x42000018, 0xffffffff, 0,                      0,              I3|I32  },
1696 {"evpe",    "",         0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
1697 {"evpe",    "t",        0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1698 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,             0,              I33     },
1699 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1700 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1701 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
1702 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
1703 {"hibernate","",        0x42000023, 0xffffffff, 0,                      0,              V1      },
1704 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,             0,              I33     },
1705 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      },
1706 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1707    the same hazard barrier effect.  */
1708 {"jr.hb",   "s",        0x00000408, 0xfc1fffff, UBD|RD_s,               0,              I32     },
1709 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      }, /* jr */
1710 /* SVR4 PIC code requires special handling for j, so it must be a
1711    macro.  */
1712 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO,             0,              I1      },
1713 /* This form of j is used by the disassembler and internally by the
1714    assembler, but will never match user input (because the line above
1715    will match first).  */
1716 {"j",       "a",        0x08000000, 0xfc000000, UBD,                    0,              I1      },
1717 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I1      },
1718 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I1      },
1719 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1720    with the same hazard barrier effect.  */
1721 {"jalr.hb", "s",        0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I32     },
1722 {"jalr.hb", "d,s",      0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I32     },
1723 /* SVR4 PIC code requires special handling for jal, so it must be a
1724    macro.  */
1725 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO,             0,              I1      },
1726 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO,             0,              I1      },
1727 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO,             0,              I1      },
1728 /* This form of jal is used by the disassembler and internally by the
1729    assembler, but will never match user input (because the line above
1730    will match first).  */
1731 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31,              0,              I1      },
1732 {"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,              0,              I16     },
1733 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1      },
1734 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1735 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO,             0,              I1      },
1736 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1737 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO,             0,              I1      },
1738 {"lca",     "t,A(b)",   0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1      },
1739 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              0,              I3      },
1740 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO,             0,              I1      },
1741 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1      },
1742 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
1743 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
1744 {"ldc1",    "T,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
1745 {"ldc1",    "E,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
1746 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      }, /* ldc1 */
1747 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO,             0,              I1      },
1748 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO,             0,              I1      },
1749 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
1750 {"ldc2",    "E,A(b)",   0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2      },
1751 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
1752 {"ldc3",    "E,A(b)",   0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2      },
1753 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
1754 {"ldl",     "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
1755 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
1756 {"ldr",     "t,A(b)",   0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3      },
1757 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
1758 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1759 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1      },
1760 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1761 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1      },
1762 /* li is at the start of the table.  */
1763 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO,             0,              I1      },
1764 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO,             0,              I1      },
1765 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO,             0,              I1      },
1766 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO,             0,              I1      },
1767 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      },
1768 {"ll",      "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2      },
1769 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
1770 {"lld",     "t,A(b)",   0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3      },
1771 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t,                   0,              I1      },
1772 {"luxc1",   "D,t(b)",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5|I33|N55},
1773 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1774 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
1775 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1776 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1      },
1777 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
1778 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
1779 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1780 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1781 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
1782 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1783 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1784 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1      },
1785 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1786 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1      },
1787 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1788 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1      },
1789 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
1790 {"lcache",  "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2      }, /* as lwl */
1791 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1792 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1      },
1793 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
1794 {"flush",   "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2      }, /* as lwr */
1795 {"fork",    "d,s,t",    0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
1796 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
1797 {"lwu",     "t,A(b)",   0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
1798 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
1799 {"lwxs",    "d,t(b)",   0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              SMT     },
1800 {"macc",    "d,s,t",    0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1801 {"macc",    "d,s,t",    0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1802 {"maccs",   "d,s,t",    0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1803 {"macchi",  "d,s,t",    0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1804 {"macchi",  "d,s,t",    0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1805 {"macchis", "d,s,t",    0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1806 {"macchiu", "d,s,t",    0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1807 {"macchiu", "d,s,t",    0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1808 {"macchius","d,s,t",    0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1809 {"maccu",   "d,s,t",    0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1810 {"maccu",   "d,s,t",    0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1811 {"maccus",  "d,s,t",    0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1812 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
1813 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
1814 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4|I33  },
1815 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4|I33  },
1816 {"madd.ps", "D,R,S,T",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5|I33  },
1817 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
1818 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
1819 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
1820 {"madd",    "7,s,t",    0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
1821 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1822 {"maddp",   "s,t",      0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         SMT     },
1823 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
1824 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
1825 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
1826 {"maddu",   "7,s,t",    0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
1827 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1828 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              N411    },
1829 {"max.ob",  "X,Y,Q",    0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1830 {"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1831 {"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1832 {"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1833 {"max.qh",  "X,Y,Q",    0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1834 {"mfpc",    "t,P",      0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
1835 {"mfps",    "t,P",      0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
1836 {"mftacx",  "d",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1837 {"mftacx",  "d,*",      0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1838 {"mftc0",   "d,+t",     0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1839 {"mftc0",   "d,+T",     0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1840 {"mftc0",   "d,E,H",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1841 {"mftc1",   "d,T",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
1842 {"mftc1",   "d,E",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
1843 {"mftc2",   "d,E",      0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1844 {"mftdsp",  "d",        0x41100021, 0xffff07ff, TRAP|WR_d,              0,              MT32    },
1845 {"mftgpr",  "d,t",      0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
1846 {"mfthc1",  "d,T",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
1847 {"mfthc1",  "d,E",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
1848 {"mfthc2",  "d,E",      0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1849 {"mfthi",   "d",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1850 {"mfthi",   "d,*",      0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1851 {"mftlo",   "d",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1852 {"mftlo",   "d,*",      0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1853 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,             0,              MT32    },
1854 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
1855 {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
1856 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
1857 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
1858 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
1859 {"mfhc1",   "t,S",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
1860 {"mfhc1",   "t,G",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
1861 /* mfc2 is at the bottom of the table.  */
1862 /* mfhc2 is at the bottom of the table.  */
1863 /* mfc3 is at the bottom of the table.  */
1864 {"mfdr",    "t,G",      0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         0,              N5      },
1865 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI,             0,              I1      },
1866 {"mfhi",    "d,9",      0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,              D32     },
1867 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO,             0,              I1      },
1868 {"mflo",    "d,9",      0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              D32     },
1869 {"mflhxu",  "d",        0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              SMT     },
1870 {"min.ob",  "X,Y,Q",    0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1871 {"min.ob",  "D,S,T",    0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1872 {"min.ob",  "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1873 {"min.ob",  "D,S,k",    0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1874 {"min.qh",  "X,Y,Q",    0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1875 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1876 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1877 {"mov.ps",  "D,S",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1878 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
1879 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
1880 {"movf.l",  "D,S,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1881 {"movf.l",  "X,Y,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1882 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
1883 {"movf.ps", "D,S,N",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
1884 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
1885 {"ffc",     "d,v",      0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
1886 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
1887 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1888 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1889 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
1890 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
1891 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
1892 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
1893 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1894 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1895 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
1896 {"movt.ps", "D,S,N",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
1897 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
1898 {"ffs",     "d,v",      0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
1899 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
1900 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1901 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1902 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
1903 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
1904 {"msac",    "d,s,t",    0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1905 {"msacu",   "d,s,t",    0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1906 {"msachi",  "d,s,t",    0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1907 {"msachiu", "d,s,t",    0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1908 /* move is at the top of the table.  */
1909 {"msgn.qh", "X,Y,Q",    0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1910 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
1911 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
1912 {"msub.ps", "D,R,S,T",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
1913 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
1914 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
1915 {"msub",    "7,s,t",    0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
1916 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
1917 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
1918 {"msubu",   "7,s,t",    0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
1919 {"mtpc",    "t,P",      0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
1920 {"mtps",    "t,P",      0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
1921 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
1922 {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
1923 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
1924 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
1925 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
1926 {"mthc1",   "t,S",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
1927 {"mthc1",   "t,G",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
1928 /* mtc2 is at the bottom of the table.  */
1929 /* mthc2 is at the bottom of the table.  */
1930 /* mtc3 is at the bottom of the table.  */
1931 {"mtdr",    "t,G",      0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         0,              N5      },
1932 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,              I1      },
1933 {"mthi",    "s,7",      0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,              D32     },
1934 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,              I1      },
1935 {"mtlo",    "s,7",      0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              D32     },
1936 {"mtlhx",   "s",        0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              SMT     },
1937 {"mttc0",   "t,G",      0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1938 {"mttc0",   "t,+D",     0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1939 {"mttc0",   "t,G,H",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1940 {"mttc1",   "t,S",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
1941 {"mttc1",   "t,G",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
1942 {"mttc2",   "t,g",      0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
1943 {"mttacx",  "t",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1944 {"mttacx",  "t,&",      0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1945 {"mttdsp",  "t",        0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              MT32    },
1946 {"mttgpr",  "t,d",      0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
1947 {"mtthc1",  "t,S",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
1948 {"mtthc1",  "t,G",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
1949 {"mtthc2",  "t,g",      0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
1950 {"mtthi",   "t",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1951 {"mtthi",   "t,&",      0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1952 {"mttlo",   "t",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1953 {"mttlo",   "t,&",      0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1954 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,             0,              MT32    },
1955 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1956 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1957 {"mul.ob",  "X,Y,Q",    0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1958 {"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1959 {"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1960 {"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1961 {"mul.ps",  "D,V,T",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1962 {"mul.qh",  "X,Y,Q",    0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1963 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              I32|P3|N55},
1964 {"mul",     "d,s,t",    0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
1965 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO,             0,              I1      },
1966 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1      },
1967 {"mula.ob", "Y,Q",      0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1968 {"mula.ob", "S,T",      0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1969 {"mula.ob", "S,T[e]",   0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1970 {"mula.ob", "S,k",      0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1971 {"mula.qh", "Y,Q",      0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1972 {"mulhi",   "d,s,t",    0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1973 {"mulhiu",  "d,s,t",    0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1974 {"mull.ob", "Y,Q",      0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1975 {"mull.ob", "S,T",      0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1976 {"mull.ob", "S,T[e]",   0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1977 {"mull.ob", "S,k",      0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1978 {"mull.qh", "Y,Q",      0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1979 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO,             0,              I1      },
1980 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1      },
1981 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO,             0,              I1      },
1982 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1      },
1983 {"mulr.ps", "D,S,T",    0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1984 {"muls",    "d,s,t",    0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1985 {"mulsu",   "d,s,t",    0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1986 {"mulshi",  "d,s,t",    0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1987 {"mulshiu", "d,s,t",    0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1988 {"muls.ob", "Y,Q",      0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1989 {"muls.ob", "S,T",      0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1990 {"muls.ob", "S,T[e]",   0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1991 {"muls.ob", "S,k",      0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1992 {"muls.qh", "Y,Q",      0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1993 {"mulsl.ob", "Y,Q",     0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1994 {"mulsl.ob", "S,T",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1995 {"mulsl.ob", "S,T[e]",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1996 {"mulsl.ob", "S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1997 {"mulsl.qh", "Y,Q",     0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1998 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
1999 {"mult",    "7,s,t",    0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
2000 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2001 {"multp",   "s,t",      0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              SMT     },
2002 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
2003 {"multu",   "7,s,t",    0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
2004 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2005 {"mulu",    "d,s,t",    0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2006 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */
2007 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
2008 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
2009 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2010 {"neg.ps",  "D,V",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
2011 {"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2012 {"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2013 {"nmadd.ps","D,R,S,T",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2014 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2015 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2016 {"nmsub.ps","D,R,S,T",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2017 /* nop is at the start of the table.  */
2018 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2019 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
2020 {"nor.ob",  "X,Y,Q",    0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2021 {"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2022 {"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2023 {"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2024 {"nor.qh",  "X,Y,Q",    0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2025 {"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
2026 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2027 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
2028 {"or.ob",   "X,Y,Q",    0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2029 {"or.ob",   "D,S,T",    0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2030 {"or.ob",   "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2031 {"or.ob",   "D,S,k",    0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2032 {"or.qh",   "X,Y,Q",    0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2033 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2034 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2035 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1     },
2036 {"pavg.ob", "X,Y,Q",    0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2037 {"pickf.ob", "X,Y,Q",   0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2038 {"pickf.ob", "D,S,T",   0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2039 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2040 {"pickf.ob", "D,S,k",   0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2041 {"pickf.qh", "X,Y,Q",   0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2042 {"pickt.ob", "X,Y,Q",   0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2043 {"pickt.ob", "D,S,T",   0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2044 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2045 {"pickt.ob", "D,S,k",   0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2046 {"pickt.qh", "X,Y,Q",   0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2047 {"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2048 {"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2049   /* pref and prefx are at the start of the table.  */
2050 {"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2051 {"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2052 {"pperm",   "s,t",      0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              SMT     },
2053 {"rach.ob", "X",        0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2054 {"rach.ob", "D",        0x4a00003f, 0xfffff83f, WR_D,                   0,              N54     },
2055 {"rach.qh", "X",        0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2056 {"racl.ob", "X",        0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2057 {"racl.ob", "D",        0x4800003f, 0xfffff83f, WR_D,                   0,              N54     },
2058 {"racl.qh", "X",        0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2059 {"racm.ob", "X",        0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2060 {"racm.ob", "D",        0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
2061 {"racm.qh", "X",        0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2062 {"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2063 {"recip.ps","D,S",      0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2064 {"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2065 {"recip1.d",  "D,S",    0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2066 {"recip1.ps", "D,S",    0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2067 {"recip1.s",  "D,S",    0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2068 {"recip2.d",  "D,S,T",  0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2069 {"recip2.ps", "D,S,T",  0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2070 {"recip2.s",  "D,S,T",  0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2071 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2072 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO,             0,              I1      },
2073 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1      },
2074 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2075 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1      },
2076 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1      },
2077 {"rdhwr",   "t,K",      0x7c00003b, 0xffe007ff, WR_t,                   0,              I33     },
2078 {"rdpgpr",  "d,w",      0x41400000, 0xffe007ff, WR_d,                   0,              I33     },
2079 {"rfe",     "",         0x42000010, 0xffffffff, 0,                      0,              I1|T3   },
2080 {"rnas.qh", "X,Q",      0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2081 {"rnau.ob", "X,Q",      0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2082 {"rnau.qh", "X,Q",      0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2083 {"rnes.qh", "X,Q",      0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2084 {"rneu.ob", "X,Q",      0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2085 {"rneu.qh", "X,Q",      0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2086 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I1      },
2087 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I1      },
2088 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I1      },
2089 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I1      },
2090 {"ror",     "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,              N5|I33|SMT },
2091 {"rorv",    "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I33|SMT },
2092 {"rotl",    "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I33|SMT },
2093 {"rotl",    "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|SMT },
2094 {"rotr",    "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I33|SMT },
2095 {"rotr",    "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|SMT },
2096 {"rotrv",   "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33|SMT },
2097 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2098 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2099 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2100 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2101 {"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2102 {"rsqrt.ps","D,S",      0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2103 {"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2104 {"rsqrt1.d",  "D,S",    0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2105 {"rsqrt1.ps", "D,S",    0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2106 {"rsqrt1.s",  "D,S",    0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2107 {"rsqrt2.d",  "D,S,T",  0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2108 {"rsqrt2.ps", "D,S,T",  0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2109 {"rsqrt2.s",  "D,S,T",  0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2110 {"rzs.qh",  "X,Q",      0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2111 {"rzu.ob",  "X,Q",      0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2112 {"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         0,              N54     },
2113 {"rzu.qh",  "X,Q",      0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2114 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2115 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO,             0,              I1      },
2116 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I2      },
2117 {"sc",      "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2      },
2118 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I3      },
2119 {"scd",     "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3      },
2120 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2121 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO,             0,              I1      },
2122 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1      },
2123 {"sdbbp",   "",         0x0000000e, 0xffffffff, TRAP,                   0,              G2      },
2124 {"sdbbp",   "c",        0x0000000e, 0xfc00ffff, TRAP,                   0,              G2      },
2125 {"sdbbp",   "c,q",      0x0000000e, 0xfc00003f, TRAP,                   0,              G2      },
2126 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   0,              I32     },
2127 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   0,              I32     },
2128 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2129 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2130 {"sdc1",    "T,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2131 {"sdc1",    "E,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2132 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2      },
2133 {"sdc2",    "E,A(b)",   0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2      },
2134 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2      },
2135 {"sdc3",    "E,A(b)",   0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2      },
2136 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2137 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO,             0,              I1      },
2138 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO,             0,              I1      },
2139 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2140 {"sdl",     "t,A(b)",   0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3      },
2141 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2142 {"sdr",     "t,A(b)",   0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3      },
2143 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0,              I4|I33  },
2144 {"seb",     "d,w",      0x7c000420, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2145 {"seh",     "d,w",      0x7c000620, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2146 {"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2147 {"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2148 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO,             0,              I1      },
2149 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1      },
2150 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO,             0,              I1      },
2151 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1      },
2152 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO,             0,              I1      },
2153 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO,             0,              I1      },
2154 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO,             0,              I1      },
2155 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO,             0,              I1      },
2156 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO,             0,              I1      },
2157 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO,             0,              I1      },
2158 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2159 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO,             0,              I1      },
2160 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2161 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2162 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2163 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2164 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2165 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2166 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2167 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2168 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2169 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2170 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2171 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2172 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2173 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2174 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
2175 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
2176 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO,             0,              I1      },
2177 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1      },
2178 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2179 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* sllv */
2180 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2181 {"sll.ob",  "X,Y,Q",    0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2182 {"sll.ob",  "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2183 {"sll.ob",  "D,S,k",    0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2184 {"sll.qh",  "X,Y,Q",    0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2185 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2186 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
2187 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2188 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2189 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2190 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1      },
2191 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO,             0,              I1      },
2192 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1      },
2193 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
2194 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2195 {"sqrt.ps", "D,S",      0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2196 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2197 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srav */
2198 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2199 {"sra.qh",  "X,Y,Q",    0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2200 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2201 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
2202 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2203 {"srl.ob",  "X,Y,Q",    0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2204 {"srl.ob",  "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2205 {"srl.ob",  "D,S,k",    0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2206 {"srl.qh",  "X,Y,Q",    0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2207 /* ssnop is at the start of the table.  */
2208 {"standby", "",         0x42000021, 0xffffffff, 0,                      0,              V1      },
2209 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2210 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
2211 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2212 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2213 {"sub.ob",  "X,Y,Q",    0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2214 {"sub.ob",  "D,S,T",    0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2215 {"sub.ob",  "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2216 {"sub.ob",  "D,S,k",    0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2217 {"sub.ps",  "D,V,T",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2218 {"sub.qh",  "X,Y,Q",    0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2219 {"suba.ob", "Y,Q",      0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2220 {"suba.qh", "Y,Q",      0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2221 {"subl.ob", "Y,Q",      0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2222 {"subl.qh", "Y,Q",      0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2223 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2224 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
2225 {"suspend", "",         0x42000022, 0xffffffff, 0,                      0,              V1      },
2226 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      0,              I5|I33|N55},
2227 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2228 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1      },
2229 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1      },
2230 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1      },
2231 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2232 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2233 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2234 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2235 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
2236 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2237 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1      },
2238 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1      },
2239 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1      },
2240 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1      },
2241 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2242 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1      },
2243 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2244 {"scache",  "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I2      }, /* as swl */
2245 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2246 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1      },
2247 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2248 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2      }, /* as swr */
2249 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0,              I4|I33  },
2250 {"sync",    "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
2251 {"sync.p",  "",         0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
2252 {"sync.l",  "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2      },
2253 {"synci",   "o(b)",     0x041f0000, 0xfc1f0000, SM|RD_b,                0,              I33     },
2254 {"syscall", "",         0x0000000c, 0xffffffff, TRAP,                   0,              I1      },
2255 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,                   0,              I1      },
2256 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2257 {"teq",     "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2258 {"teq",     "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2259 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* teqi */
2260 {"teq",     "s,I",      0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2      },
2261 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2262 {"tge",     "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2263 {"tge",     "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2264 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgei */
2265 {"tge",     "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2      },
2266 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2267 {"tgeu",    "s,t",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2268 {"tgeu",    "s,t,q",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2269 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgeiu */
2270 {"tgeu",    "s,I",      0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2      },
2271 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               0,              I1      },
2272 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               0,              I1      },
2273 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               0,              I1      },
2274 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               0,              I1      },
2275 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2276 {"tlt",     "s,t",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2277 {"tlt",     "s,t,q",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2278 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tlti */
2279 {"tlt",     "s,I",      0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2      },
2280 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2281 {"tltu",    "s,t",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2282 {"tltu",    "s,t,q",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2283 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tltiu */
2284 {"tltu",    "s,I",      0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2      },
2285 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2286 {"tne",     "s,t",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2287 {"tne",     "s,t,q",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2288 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tnei */
2289 {"tne",     "s,I",      0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
2290 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2291 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2292 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2293 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2294 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO,             0,              I1      },
2295 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2296 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2297 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO,             0,              I1      },
2298 {"uld",     "t,o(b)",   0,    (int) M_ULD,      INSN_MACRO,             0,              I3      },
2299 {"uld",     "t,A(b)",   0,    (int) M_ULD_A,    INSN_MACRO,             0,              I3      },
2300 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO,             0,              I1      },
2301 {"ulh",     "t,A(b)",   0,    (int) M_ULH_A,    INSN_MACRO,             0,              I1      },
2302 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO,             0,              I1      },
2303 {"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,   INSN_MACRO,             0,              I1      },
2304 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO,             0,              I1      },
2305 {"ulw",     "t,A(b)",   0,    (int) M_ULW_A,    INSN_MACRO,             0,              I1      },
2306 {"usd",     "t,o(b)",   0,    (int) M_USD,      INSN_MACRO,             0,              I3      },
2307 {"usd",     "t,A(b)",   0,    (int) M_USD_A,    INSN_MACRO,             0,              I3      },
2308 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO,             0,              I1      },
2309 {"ush",     "t,A(b)",   0,    (int) M_USH_A,    INSN_MACRO,             0,              I1      },
2310 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO,             0,              I1      },
2311 {"usw",     "t,A(b)",   0,    (int) M_USW_A,    INSN_MACRO,             0,              I1      },
2312 {"wach.ob", "Y",        0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
2313 {"wach.ob", "S",        0x4a00003e, 0xffff07ff, RD_S,                   0,              N54     },
2314 {"wach.qh", "Y",        0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
2315 {"wacl.ob", "Y,Z",      0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2316 {"wacl.ob", "S,T",      0x4800003e, 0xffe007ff, RD_S|RD_T,              0,              N54     },
2317 {"wacl.qh", "Y,Z",      0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2318 {"wait",    "",         0x42000020, 0xffffffff, TRAP,                   0,              I3|I32  },
2319 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                   0,              I32|N55 },
2320 {"waiti",   "",         0x42000020, 0xffffffff, TRAP,                   0,              L1      },
2321 {"wrpgpr",  "d,w",      0x41c00000, 0xffe007ff, RD_t,                   0,              I33     },
2322 {"wsbh",    "d,w",      0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2323 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2324 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
2325 {"xor.ob",  "X,Y,Q",    0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2326 {"xor.ob",  "D,S,T",    0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2327 {"xor.ob",  "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2328 {"xor.ob",  "D,S,k",    0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2329 {"xor.qh",  "X,Y,Q",    0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2330 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2331 {"yield",   "s",        0x7c000009, 0xfc1fffff, TRAP|RD_s,              0,              MT32    },
2332 {"yield",   "d,s",      0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,         0,              MT32    },
2333
2334 /* User Defined Instruction.  */
2335 {"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2336 {"udi0",     "s,t,+2",  0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2337 {"udi0",     "s,+3",    0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2338 {"udi0",     "+4",      0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2339 {"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2340 {"udi1",     "s,t,+2",  0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2341 {"udi1",     "s,+3",    0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2342 {"udi1",     "+4",      0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2343 {"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2344 {"udi2",     "s,t,+2",  0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2345 {"udi2",     "s,+3",    0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2346 {"udi2",     "+4",      0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2347 {"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2348 {"udi3",     "s,t,+2",  0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2349 {"udi3",     "s,+3",    0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2350 {"udi3",     "+4",      0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2351 {"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2352 {"udi4",     "s,t,+2",  0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2353 {"udi4",     "s,+3",    0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2354 {"udi4",     "+4",      0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2355 {"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2356 {"udi5",     "s,t,+2",  0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2357 {"udi5",     "s,+3",    0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2358 {"udi5",     "+4",      0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2359 {"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2360 {"udi6",     "s,t,+2",  0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2361 {"udi6",     "s,+3",    0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2362 {"udi6",     "+4",      0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2363 {"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2364 {"udi7",     "s,t,+2",  0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2365 {"udi7",     "s,+3",    0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2366 {"udi7",     "+4",      0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2367 {"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2368 {"udi8",     "s,t,+2",  0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2369 {"udi8",     "s,+3",    0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2370 {"udi8",     "+4",      0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2371 {"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2372 {"udi9",      "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2373 {"udi9",     "s,+3",    0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2374 {"udi9",     "+4",      0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2375 {"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2376 {"udi10",    "s,t,+2",  0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2377 {"udi10",    "s,+3",    0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2378 {"udi10",    "+4",      0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2379 {"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2380 {"udi11",    "s,t,+2",  0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2381 {"udi11",    "s,+3",    0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2382 {"udi11",    "+4",      0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2383 {"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2384 {"udi12",    "s,t,+2",  0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2385 {"udi12",    "s,+3",    0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2386 {"udi12",    "+4",      0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2387 {"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2388 {"udi13",    "s,t,+2",  0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2389 {"udi13",    "s,+3",    0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2390 {"udi13",    "+4",      0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2391 {"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2392 {"udi14",    "s,t,+2",  0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2393 {"udi14",    "s,+3",    0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2394 {"udi14",    "+4",      0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2395 {"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2396 {"udi15",    "s,t,+2",  0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2397 {"udi15",    "s,+3",    0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2398 {"udi15",    "+4",      0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2399
2400 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2401    instructions so they are here for the latters to take precedence.  */
2402 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2403 {"bc2f",    "N,p",      0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32     },
2404 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2405 {"bc2fl",   "N,p",      0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32     },
2406 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2407 {"bc2t",    "N,p",      0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32     },
2408 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2409 {"bc2tl",   "N,p",      0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
2410 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
2411 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2412 {"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
2413 {"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
2414 {"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
2415 {"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
2416 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
2417 {"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
2418 {"mfhc2",   "t,G",      0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },
2419 {"mfhc2",   "t,G,H",    0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33     },
2420 {"mfhc2",   "t,i",      0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33     },
2421 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1      },
2422 {"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32     },
2423 {"mthc2",   "t,G",      0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2424 {"mthc2",   "t,G,H",    0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2425 {"mthc2",   "t,i",      0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2426
2427 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
2428    instructions, so they are here for the latters to take precedence.  */
2429 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2430 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2431 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2432 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2433 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
2434 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2435 {"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3      },
2436 {"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3      },
2437 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
2438 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32     },
2439 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
2440 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32     },
2441
2442 /* No hazard protection on coprocessor instructions--they shouldn't
2443    change the state of the processor and if they do it's up to the
2444    user to put in nops as necessary.  These are at the end so that the
2445    disassembler recognizes more specific versions first.  */
2446 {"c0",      "C",        0x42000000, 0xfe000000, 0,                      0,              I1      },
2447 {"c1",      "C",        0x46000000, 0xfe000000, 0,                      0,              I1      },
2448 {"c2",      "C",        0x4a000000, 0xfe000000, 0,                      0,              I1      },
2449 {"c3",      "C",        0x4e000000, 0xfe000000, 0,                      0,              I1      },
2450 {"cop0",     "C",       0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
2451 {"cop1",     "C",       0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
2452 {"cop2",     "C",       0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
2453 {"cop3",     "C",       0,    (int) M_COP3,     INSN_MACRO,             0,              I1      },
2454   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
2455      4010 any more, so move this insn out of the way.  If the object
2456      format gave us more info, we could do this right.  */
2457 {"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,              0,              L1      },
2458 /* MIPS DSP ASE */
2459 {"absq_s.ph", "d,t",    0x7c000252, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2460 {"absq_s.pw", "d,t",    0x7c000456, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2461 {"absq_s.qh", "d,t",    0x7c000256, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2462 {"absq_s.w", "d,t",     0x7c000452, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2463 {"addq.ph", "d,s,t",    0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2464 {"addq.pw", "d,s,t",    0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2465 {"addq.qh", "d,s,t",    0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2466 {"addq_s.ph", "d,s,t",  0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2467 {"addq_s.pw", "d,s,t",  0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2468 {"addq_s.qh", "d,s,t",  0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2469 {"addq_s.w", "d,s,t",   0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2470 {"addsc",   "d,s,t",    0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2471 {"addu.ob", "d,s,t",    0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2472 {"addu.qb", "d,s,t",    0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2473 {"addu_s.ob", "d,s,t",  0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2474 {"addu_s.qb", "d,s,t",  0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2475 {"addwc",   "d,s,t",    0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2476 {"bitrev",  "d,t",      0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2477 {"bposge32", "p",       0x041c0000, 0xffff0000, CBD,                    0,              D32     },
2478 {"bposge64", "p",       0x041d0000, 0xffff0000, CBD,                    0,              D64     },
2479 {"cmp.eq.ph", "s,t",    0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2480 {"cmp.eq.pw", "s,t",    0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2481 {"cmp.eq.qh", "s,t",    0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2482 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2483 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2484 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2485 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2486 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2487 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2488 {"cmp.le.ph", "s,t",    0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2489 {"cmp.le.pw", "s,t",    0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2490 {"cmp.le.qh", "s,t",    0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2491 {"cmp.lt.ph", "s,t",    0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2492 {"cmp.lt.pw", "s,t",    0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2493 {"cmp.lt.qh", "s,t",    0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2494 {"cmpu.eq.ob", "s,t",   0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2495 {"cmpu.eq.qb", "s,t",   0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2496 {"cmpu.le.ob", "s,t",   0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2497 {"cmpu.le.qb", "s,t",   0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2498 {"cmpu.lt.ob", "s,t",   0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2499 {"cmpu.lt.qb", "s,t",   0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2500 {"dextpdp", "t,7,6",    0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D64     },
2501 {"dextpdpv", "t,7,s",   0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D64     },
2502 {"dextp",   "t,7,6",    0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2503 {"dextpv",  "t,7,s",    0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2504 {"dextr.l", "t,7,6",    0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2505 {"dextr_r.l", "t,7,6",  0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2506 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2507 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2508 {"dextr_r.w", "t,7,6",  0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2509 {"dextr_s.h", "t,7,6",  0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2510 {"dextrv.l", "t,7,s",   0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2511 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2512 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
2513 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
2514 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2515 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2516 {"dextrv.w", "t,7,s",   0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2517 {"dextr.w", "t,7,6",    0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2518 {"dinsv",   "t,s",      0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,              D64     },
2519 {"dmadd",   "7,s,t",    0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2520 {"dmaddu",  "7,s,t",    0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2521 {"dmsub",   "7,s,t",    0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2522 {"dmsubu",  "7,s,t",    0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2523 {"dmthlip", "s,7",      0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D64     },
2524 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2525 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2526 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2527 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2528 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2529 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2530 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2531 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2532 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2533 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2534 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2535 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2536 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2537 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2538 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2539 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2540 {"dshilo",  "7,:",      0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,              D64     },
2541 {"dshilov", "7,s",      0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,              D64     },
2542 {"extpdp",  "t,7,6",    0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D32     },
2543 {"extpdpv", "t,7,s",    0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D32     },
2544 {"extp",    "t,7,6",    0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2545 {"extpv",   "t,7,s",    0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2546 {"extr_rs.w", "t,7,6",  0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2547 {"extr_r.w", "t,7,6",   0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2548 {"extr_s.h", "t,7,6",   0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2549 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2550 {"extrv_r.w", "t,7,s",  0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2551 {"extrv_s.h", "t,7,s",  0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2552 {"extrv.w", "t,7,s",    0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2553 {"extr.w",  "t,7,6",    0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2554 {"insv",    "t,s",      0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
2555 {"lbux",    "d,t(b)",   0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2556 {"ldx",     "d,t(b)",   0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D64     },
2557 {"lhx",     "d,t(b)",   0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2558 {"lwx",     "d,t(b)",   0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2559 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
2560 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
2561 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2562 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2563 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2564 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2565 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2566 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2567 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2568 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2569 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2570 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2571 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2572 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2573 {"modsub",  "d,s,t",    0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2574 {"mthlip",  "s,7",      0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D32     },
2575 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2576 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2577 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
2578 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
2579 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
2580 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
2581 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2582 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2583 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32     },
2584 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D64     },
2585 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2586 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D32     },
2587 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2588 {"packrl.ph", "d,s,t",  0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2589 {"packrl.pw", "d,s,t",  0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2590 {"pick.ob", "d,s,t",    0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2591 {"pick.ph", "d,s,t",    0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2592 {"pick.pw", "d,s,t",    0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2593 {"pick.qb", "d,s,t",    0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2594 {"pick.qh", "d,s,t",    0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2595 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2596 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2597 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2598 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2599 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2600 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2601 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,           0,              D32     },
2602 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2603 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,           0,              D32     },
2604 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2605 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,           0,              D64     },
2606 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2607 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,           0,              D64     },
2608 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2609 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2610 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2611 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2612 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,             0,              D32     },
2613 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2614 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,             0,              D32     },
2615 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2616 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2617 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2618 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2619 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
2620 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2621 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2622 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
2623 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
2624 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,     0,              D32     },
2625 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
2626 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
2627 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D32     },
2628 {"raddu.l.ob", "d,s",   0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,              D64     },
2629 {"raddu.w.qb", "d,s",   0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,              D32     },
2630 {"rddsp",   "d",        0x7fff04b8, 0xffff07ff, WR_d,                   0,              D32     },
2631 {"rddsp",   "d,'",      0x7c0004b8, 0xffc007ff, WR_d,                   0,              D32     },
2632 {"repl.ob", "d,5",      0x7c000096, 0xff0007ff, WR_d,                   0,              D64     },
2633 {"repl.ph", "d,@",      0x7c000292, 0xfc0007ff, WR_d,                   0,              D32     },
2634 {"repl.pw", "d,@",      0x7c000496, 0xfc0007ff, WR_d,                   0,              D64     },
2635 {"repl.qb", "d,5",      0x7c000092, 0xff0007ff, WR_d,                   0,              D32     },
2636 {"repl.qh", "d,@",      0x7c000296, 0xfc0007ff, WR_d,                   0,              D64     },
2637 {"replv.ob", "d,t",     0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2638 {"replv.ph", "d,t",     0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2639 {"replv.pw", "d,t",     0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2640 {"replv.qb", "d,t",     0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2641 {"replv.qh", "d,t",     0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2642 {"shilo",   "7,0",      0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,              D32     },
2643 {"shilov",  "7,s",      0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,              D32     },
2644 {"shll.ob", "d,t,3",    0x7c000017, 0xff0007ff, WR_d|RD_t,              0,              D64     },
2645 {"shll.ph", "d,t,4",    0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2646 {"shll.pw", "d,t,6",    0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2647 {"shll.qb", "d,t,3",    0x7c000013, 0xff0007ff, WR_d|RD_t,              0,              D32     },
2648 {"shll.qh", "d,t,4",    0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2649 {"shll_s.ph", "d,t,4",  0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2650 {"shll_s.pw", "d,t,6",  0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2651 {"shll_s.qh", "d,t,4",  0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2652 {"shll_s.w", "d,t,6",   0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
2653 {"shllv.ob", "d,t,s",   0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2654 {"shllv.ph", "d,t,s",   0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2655 {"shllv.pw", "d,t,s",   0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2656 {"shllv.qb", "d,t,s",   0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2657 {"shllv.qh", "d,t,s",   0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2658 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2659 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2660 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2661 {"shllv_s.w", "d,t,s",  0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2662 {"shra.ph", "d,t,4",    0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2663 {"shra.pw", "d,t,6",    0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2664 {"shra.qh", "d,t,4",    0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2665 {"shra_r.ph", "d,t,4",  0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2666 {"shra_r.pw", "d,t,6",  0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2667 {"shra_r.qh", "d,t,4",  0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2668 {"shra_r.w", "d,t,6",   0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
2669 {"shrav.ph", "d,t,s",   0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2670 {"shrav.pw", "d,t,s",   0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2671 {"shrav.qh", "d,t,s",   0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2672 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2673 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2674 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2675 {"shrav_r.w", "d,t,s",  0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2676 {"shrl.ob", "d,t,3",    0x7c000057, 0xff0007ff, WR_d|RD_t,              0,              D64     },
2677 {"shrl.qb", "d,t,3",    0x7c000053, 0xff0007ff, WR_d|RD_t,              0,              D32     },
2678 {"shrlv.ob", "d,t,s",   0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2679 {"shrlv.qb", "d,t,s",   0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2680 {"subq.ph", "d,s,t",    0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2681 {"subq.pw", "d,s,t",    0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2682 {"subq.qh", "d,s,t",    0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2683 {"subq_s.ph", "d,s,t",  0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2684 {"subq_s.pw", "d,s,t",  0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2685 {"subq_s.qh", "d,s,t",  0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2686 {"subq_s.w", "d,s,t",   0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2687 {"subu.ob", "d,s,t",    0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2688 {"subu.qb", "d,s,t",    0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2689 {"subu_s.ob", "d,s,t",  0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2690 {"subu_s.qb", "d,s,t",  0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2691 {"wrdsp",   "s",        0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,              D32     },
2692 {"wrdsp",   "s,8",      0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,              D32     },
2693 /* MIPS DSP ASE Rev2 */
2694 {"absq_s.qb", "d,t",    0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33     },
2695 {"addu.ph", "d,s,t",    0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2696 {"addu_s.ph", "d,s,t",  0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2697 {"adduh.qb", "d,s,t",   0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2698 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2699 {"append",  "t,s,h",    0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
2700 {"balign",  "t,s,I",    0,    (int) M_BALIGN,   INSN_MACRO,             0,              D33     },
2701 {"balign",  "t,s,2",    0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33     },
2702 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2703 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2704 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2705 {"dpa.w.ph", "7,s,t",   0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2706 {"dps.w.ph", "7,s,t",   0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2707 {"mul.ph",  "d,s,t",    0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2708 {"mul_s.ph", "d,s,t",   0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2709 {"mulq_rs.w", "d,s,t",  0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2710 {"mulq_s.ph", "d,s,t",  0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2711 {"mulq_s.w", "d,s,t",   0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2712 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2713 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33     },
2714 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33     },
2715 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33     },
2716 {"prepend", "t,s,h",    0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
2717 {"shra.qb", "d,t,3",    0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33     },
2718 {"shra_r.qb", "d,t,3",  0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33     },
2719 {"shrav.qb", "d,t,s",   0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2720 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2721 {"shrl.ph", "d,t,4",    0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33     },
2722 {"shrlv.ph", "d,t,s",   0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2723 {"subu.ph", "d,s,t",    0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2724 {"subu_s.ph", "d,s,t",  0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2725 {"subuh.qb", "d,s,t",   0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2726 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2727 {"addqh.ph", "d,s,t",   0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2728 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2729 {"addqh.w", "d,s,t",    0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2730 {"addqh_r.w", "d,s,t",  0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2731 {"subqh.ph", "d,s,t",   0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2732 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2733 {"subqh.w", "d,s,t",    0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2734 {"subqh_r.w", "d,s,t",  0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2735 {"dpax.w.ph", "7,s,t",  0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2736 {"dpsx.w.ph", "7,s,t",  0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2737 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
2738 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
2739 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
2740 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
2741 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
2742 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2743 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2744 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2745 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2746 /* ST Microelectronics Loongson-2E and -2F.  */
2747 {"mult.g",      "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2748 {"mult.g",      "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2749 {"multu.g",     "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2750 {"multu.g",     "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2751 {"dmult.g",     "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2752 {"dmult.g",     "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2753 {"dmultu.g",    "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2754 {"dmultu.g",    "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2755 {"div.g",       "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2756 {"div.g",       "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2757 {"divu.g",      "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2758 {"divu.g",      "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2759 {"ddiv.g",      "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2760 {"ddiv.g",      "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2761 {"ddivu.g",     "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2762 {"ddivu.g",     "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2763 {"mod.g",       "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2764 {"mod.g",       "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2765 {"modu.g",      "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2766 {"modu.g",      "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2767 {"dmod.g",      "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2768 {"dmod.g",      "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2769 {"dmodu.g",     "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
2770 {"dmodu.g",     "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
2771 };
2772
2773 #define MIPS_NUM_OPCODES \
2774         ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
2775 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
2776
2777 /* const removed from the following to allow for dynamic extensions to the
2778  * built-in instruction set. */
2779 struct mips_opcode *mips_opcodes =
2780   (struct mips_opcode *) mips_builtin_opcodes;
2781 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
2782 #undef MIPS_NUM_OPCODES
2783
2784 /* Mips instructions are at maximum this many bytes long.  */
2785 #define INSNLEN 4
2786
2787 \f
2788 /* FIXME: These should be shared with gdb somehow.  */
2789
2790 struct mips_cp0sel_name
2791 {
2792   unsigned int cp0reg;
2793   unsigned int sel;
2794   const char * const name;
2795 };
2796
2797 /* The mips16 registers.  */
2798 static const unsigned int mips16_to_32_reg_map[] =
2799 {
2800   16, 17, 2, 3, 4, 5, 6, 7
2801 };
2802
2803 #define mips16_reg_names(rn)    mips_gpr_names[mips16_to_32_reg_map[rn]]
2804
2805
2806 static const char * const mips_gpr_names_numeric[32] =
2807 {
2808   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
2809   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
2810   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
2811   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
2812 };
2813
2814 static const char * const mips_gpr_names_oldabi[32] =
2815 {
2816   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
2817   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
2818   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
2819   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
2820 };
2821
2822 static const char * const mips_gpr_names_newabi[32] =
2823 {
2824   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
2825   "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
2826   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
2827   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
2828 };
2829
2830 static const char * const mips_fpr_names_numeric[32] =
2831 {
2832   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
2833   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
2834   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
2835   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
2836 };
2837
2838 static const char * const mips_fpr_names_32[32] =
2839 {
2840   "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
2841   "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
2842   "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
2843   "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
2844 };
2845
2846 static const char * const mips_fpr_names_n32[32] =
2847 {
2848   "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
2849   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
2850   "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
2851   "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
2852 };
2853
2854 static const char * const mips_fpr_names_64[32] =
2855 {
2856   "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
2857   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
2858   "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
2859   "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
2860 };
2861
2862 static const char * const mips_cp0_names_numeric[32] =
2863 {
2864   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
2865   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
2866   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
2867   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
2868 };
2869
2870 static const char * const mips_cp0_names_mips3264[32] =
2871 {
2872   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
2873   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
2874   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
2875   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
2876   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
2877   "c0_xcontext",  "$21",          "$22",          "c0_debug",
2878   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
2879   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
2880 };
2881
2882 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
2883 {
2884   {  4, 1, "c0_contextconfig"   },
2885   {  0, 1, "c0_mvpcontrol"      },
2886   {  0, 2, "c0_mvpconf0"        },
2887   {  0, 3, "c0_mvpconf1"        },
2888   {  1, 1, "c0_vpecontrol"      },
2889   {  1, 2, "c0_vpeconf0"        },
2890   {  1, 3, "c0_vpeconf1"        },
2891   {  1, 4, "c0_yqmask"          },
2892   {  1, 5, "c0_vpeschedule"     },
2893   {  1, 6, "c0_vpeschefback"    },
2894   {  2, 1, "c0_tcstatus"        },
2895   {  2, 2, "c0_tcbind"          },
2896   {  2, 3, "c0_tcrestart"       },
2897   {  2, 4, "c0_tchalt"          },
2898   {  2, 5, "c0_tccontext"       },
2899   {  2, 6, "c0_tcschedule"      },
2900   {  2, 7, "c0_tcschefback"     },
2901   {  5, 1, "c0_pagegrain"       },
2902   {  6, 1, "c0_srsconf0"        },
2903   {  6, 2, "c0_srsconf1"        },
2904   {  6, 3, "c0_srsconf2"        },
2905   {  6, 4, "c0_srsconf3"        },
2906   {  6, 5, "c0_srsconf4"        },
2907   { 12, 1, "c0_intctl"          },
2908   { 12, 2, "c0_srsctl"          },
2909   { 12, 3, "c0_srsmap"          },
2910   { 15, 1, "c0_ebase"           },
2911   { 16, 1, "c0_config1"         },
2912   { 16, 2, "c0_config2"         },
2913   { 16, 3, "c0_config3"         },
2914   { 18, 1, "c0_watchlo,1"       },
2915   { 18, 2, "c0_watchlo,2"       },
2916   { 18, 3, "c0_watchlo,3"       },
2917   { 18, 4, "c0_watchlo,4"       },
2918   { 18, 5, "c0_watchlo,5"       },
2919   { 18, 6, "c0_watchlo,6"       },
2920   { 18, 7, "c0_watchlo,7"       },
2921   { 19, 1, "c0_watchhi,1"       },
2922   { 19, 2, "c0_watchhi,2"       },
2923   { 19, 3, "c0_watchhi,3"       },
2924   { 19, 4, "c0_watchhi,4"       },
2925   { 19, 5, "c0_watchhi,5"       },
2926   { 19, 6, "c0_watchhi,6"       },
2927   { 19, 7, "c0_watchhi,7"       },
2928   { 23, 1, "c0_tracecontrol"    },
2929   { 23, 2, "c0_tracecontrol2"   },
2930   { 23, 3, "c0_usertracedata"   },
2931   { 23, 4, "c0_tracebpc"        },
2932   { 25, 1, "c0_perfcnt,1"       },
2933   { 25, 2, "c0_perfcnt,2"       },
2934   { 25, 3, "c0_perfcnt,3"       },
2935   { 25, 4, "c0_perfcnt,4"       },
2936   { 25, 5, "c0_perfcnt,5"       },
2937   { 25, 6, "c0_perfcnt,6"       },
2938   { 25, 7, "c0_perfcnt,7"       },
2939   { 27, 1, "c0_cacheerr,1"      },
2940   { 27, 2, "c0_cacheerr,2"      },
2941   { 27, 3, "c0_cacheerr,3"      },
2942   { 28, 1, "c0_datalo"          },
2943   { 28, 2, "c0_taglo1"          },
2944   { 28, 3, "c0_datalo1"         },
2945   { 28, 4, "c0_taglo2"          },
2946   { 28, 5, "c0_datalo2"         },
2947   { 28, 6, "c0_taglo3"          },
2948   { 28, 7, "c0_datalo3"         },
2949   { 29, 1, "c0_datahi"          },
2950   { 29, 2, "c0_taghi1"          },
2951   { 29, 3, "c0_datahi1"         },
2952   { 29, 4, "c0_taghi2"          },
2953   { 29, 5, "c0_datahi2"         },
2954   { 29, 6, "c0_taghi3"          },
2955   { 29, 7, "c0_datahi3"         },
2956 };
2957
2958 static const char * const mips_cp0_names_mips3264r2[32] =
2959 {
2960   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
2961   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
2962   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
2963   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
2964   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
2965   "c0_xcontext",  "$21",          "$22",          "c0_debug",
2966   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
2967   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
2968 };
2969
2970 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
2971 {
2972   {  4, 1, "c0_contextconfig"   },
2973   {  5, 1, "c0_pagegrain"       },
2974   { 12, 1, "c0_intctl"          },
2975   { 12, 2, "c0_srsctl"          },
2976   { 12, 3, "c0_srsmap"          },
2977   { 15, 1, "c0_ebase"           },
2978   { 16, 1, "c0_config1"         },
2979   { 16, 2, "c0_config2"         },
2980   { 16, 3, "c0_config3"         },
2981   { 18, 1, "c0_watchlo,1"       },
2982   { 18, 2, "c0_watchlo,2"       },
2983   { 18, 3, "c0_watchlo,3"       },
2984   { 18, 4, "c0_watchlo,4"       },
2985   { 18, 5, "c0_watchlo,5"       },
2986   { 18, 6, "c0_watchlo,6"       },
2987   { 18, 7, "c0_watchlo,7"       },
2988   { 19, 1, "c0_watchhi,1"       },
2989   { 19, 2, "c0_watchhi,2"       },
2990   { 19, 3, "c0_watchhi,3"       },
2991   { 19, 4, "c0_watchhi,4"       },
2992   { 19, 5, "c0_watchhi,5"       },
2993   { 19, 6, "c0_watchhi,6"       },
2994   { 19, 7, "c0_watchhi,7"       },
2995   { 23, 1, "c0_tracecontrol"    },
2996   { 23, 2, "c0_tracecontrol2"   },
2997   { 23, 3, "c0_usertracedata"   },
2998   { 23, 4, "c0_tracebpc"        },
2999   { 25, 1, "c0_perfcnt,1"       },
3000   { 25, 2, "c0_perfcnt,2"       },
3001   { 25, 3, "c0_perfcnt,3"       },
3002   { 25, 4, "c0_perfcnt,4"       },
3003   { 25, 5, "c0_perfcnt,5"       },
3004   { 25, 6, "c0_perfcnt,6"       },
3005   { 25, 7, "c0_perfcnt,7"       },
3006   { 27, 1, "c0_cacheerr,1"      },
3007   { 27, 2, "c0_cacheerr,2"      },
3008   { 27, 3, "c0_cacheerr,3"      },
3009   { 28, 1, "c0_datalo"          },
3010   { 28, 2, "c0_taglo1"          },
3011   { 28, 3, "c0_datalo1"         },
3012   { 28, 4, "c0_taglo2"          },
3013   { 28, 5, "c0_datalo2"         },
3014   { 28, 6, "c0_taglo3"          },
3015   { 28, 7, "c0_datalo3"         },
3016   { 29, 1, "c0_datahi"          },
3017   { 29, 2, "c0_taghi1"          },
3018   { 29, 3, "c0_datahi1"         },
3019   { 29, 4, "c0_taghi2"          },
3020   { 29, 5, "c0_datahi2"         },
3021   { 29, 6, "c0_taghi3"          },
3022   { 29, 7, "c0_datahi3"         },
3023 };
3024
3025 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
3026 static const char * const mips_cp0_names_sb1[32] =
3027 {
3028   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3029   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
3030   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3031   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3032   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3033   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3034   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
3035   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
3036 };
3037
3038 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3039 {
3040   { 16, 1, "c0_config1"         },
3041   { 18, 1, "c0_watchlo,1"       },
3042   { 19, 1, "c0_watchhi,1"       },
3043   { 22, 0, "c0_perftrace"       },
3044   { 23, 3, "c0_edebug"          },
3045   { 25, 1, "c0_perfcnt,1"       },
3046   { 25, 2, "c0_perfcnt,2"       },
3047   { 25, 3, "c0_perfcnt,3"       },
3048   { 25, 4, "c0_perfcnt,4"       },
3049   { 25, 5, "c0_perfcnt,5"       },
3050   { 25, 6, "c0_perfcnt,6"       },
3051   { 25, 7, "c0_perfcnt,7"       },
3052   { 26, 1, "c0_buserr_pa"       },
3053   { 27, 1, "c0_cacheerr_d"      },
3054   { 27, 3, "c0_cacheerr_d_pa"   },
3055   { 28, 1, "c0_datalo_i"        },
3056   { 28, 2, "c0_taglo_d"         },
3057   { 28, 3, "c0_datalo_d"        },
3058   { 29, 1, "c0_datahi_i"        },
3059   { 29, 2, "c0_taghi_d"         },
3060   { 29, 3, "c0_datahi_d"        },
3061 };
3062
3063 static const char * const mips_hwr_names_numeric[32] =
3064 {
3065   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3066   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3067   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3068   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3069 };
3070
3071 static const char * const mips_hwr_names_mips3264r2[32] =
3072 {
3073   "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
3074   "$4",          "$5",            "$6",           "$7",
3075   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3076   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3077   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3078 };
3079
3080 struct mips_abi_choice
3081 {
3082   const char *name;
3083   const char * const *gpr_names;
3084   const char * const *fpr_names;
3085 };
3086
3087 static struct mips_abi_choice mips_abi_choices[] =
3088 {
3089   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3090   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3091   { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3092   { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3093 };
3094
3095 struct mips_arch_choice
3096 {
3097   const char *name;
3098   int bfd_mach_valid;
3099   unsigned long bfd_mach;
3100   int processor;
3101   int isa;
3102   const char * const *cp0_names;
3103   const struct mips_cp0sel_name *cp0sel_names;
3104   unsigned int cp0sel_names_len;
3105   const char * const *hwr_names;
3106 };
3107
3108 #define bfd_mach_mips3000              3000
3109 #define bfd_mach_mips3900              3900
3110 #define bfd_mach_mips4000              4000
3111 #define bfd_mach_mips4010              4010
3112 #define bfd_mach_mips4100              4100
3113 #define bfd_mach_mips4111              4111
3114 #define bfd_mach_mips4120              4120
3115 #define bfd_mach_mips4300              4300
3116 #define bfd_mach_mips4400              4400
3117 #define bfd_mach_mips4600              4600
3118 #define bfd_mach_mips4650              4650
3119 #define bfd_mach_mips5000              5000
3120 #define bfd_mach_mips5400              5400
3121 #define bfd_mach_mips5500              5500
3122 #define bfd_mach_mips6000              6000
3123 #define bfd_mach_mips7000              7000
3124 #define bfd_mach_mips8000              8000
3125 #define bfd_mach_mips9000              9000
3126 #define bfd_mach_mips10000             10000
3127 #define bfd_mach_mips12000             12000
3128 #define bfd_mach_mips16                16
3129 #define bfd_mach_mips5                 5
3130 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
3131 #define bfd_mach_mipsisa32             32
3132 #define bfd_mach_mipsisa32r2           33
3133 #define bfd_mach_mipsisa64             64
3134 #define bfd_mach_mipsisa64r2           65
3135
3136 static const struct mips_arch_choice mips_arch_choices[] =
3137 {
3138   { "numeric",  0, 0, 0, 0,
3139     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3140
3141   { "r3000",    1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3142     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3143   { "r3900",    1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3144     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3145   { "r4000",    1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3146     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3147   { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3148     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3149   { "vr4100",   1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3150     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3151   { "vr4111",   1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3152     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3153   { "vr4120",   1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3154     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3155   { "r4300",    1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3156     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3157   { "r4400",    1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3158     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3159   { "r4600",    1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3160     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3161   { "r4650",    1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3162     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3163   { "r5000",    1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3164     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3165   { "vr5400",   1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3166     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3167   { "vr5500",   1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3168     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3169   { "r6000",    1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3170     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3171   { "rm7000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3172     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3173   { "rm9000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3174     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3175   { "r8000",    1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3176     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3177   { "r10000",   1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3178     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3179   { "r12000",   1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3180     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3181   { "mips5",    1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3182     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3183
3184   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3185      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
3186      _MIPS32 Architecture For Programmers Volume I: Introduction to the
3187      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3188      page 1.  */
3189   { "mips32",   1, bfd_mach_mipsisa32, CPU_MIPS32,
3190     ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3191     mips_cp0_names_mips3264,
3192     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3193     mips_hwr_names_numeric },
3194
3195   { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3196     (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3197      | INSN_MIPS3D | INSN_MT),
3198     mips_cp0_names_mips3264r2,
3199     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3200     mips_hwr_names_mips3264r2 },
3201
3202   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
3203   { "mips64",   1, bfd_mach_mipsisa64, CPU_MIPS64,
3204     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3205     mips_cp0_names_mips3264,
3206     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3207     mips_hwr_names_numeric },
3208
3209   { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3210     (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3211      | INSN_DSP64 | INSN_MT | INSN_MDMX),
3212     mips_cp0_names_mips3264r2,
3213     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3214     mips_hwr_names_mips3264r2 },
3215
3216   { "sb1",      1, bfd_mach_mips_sb1, CPU_SB1,
3217     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3218     mips_cp0_names_sb1,
3219     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3220     mips_hwr_names_numeric },
3221
3222   /* This entry, mips16, is here only for ISA/processor selection; do
3223      not print its name.  */
3224   { "",         1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3225     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3226 };
3227
3228 /* ISA and processor type to disassemble for, and register names to use.
3229    set_default_mips_dis_options and parse_mips_dis_options fill in these
3230    values.  */
3231 static int mips_processor;
3232 static int mips_isa;
3233 static const char * const *mips_gpr_names;
3234 static const char * const *mips_fpr_names;
3235 static const char * const *mips_cp0_names;
3236 static const struct mips_cp0sel_name *mips_cp0sel_names;
3237 static int mips_cp0sel_names_len;
3238 static const char * const *mips_hwr_names;
3239
3240 /* Other options */
3241 static int no_aliases;  /* If set disassemble as most general inst.  */
3242 \f
3243 static const struct mips_abi_choice *
3244 choose_abi_by_name (const char *name, unsigned int namelen)
3245 {
3246   const struct mips_abi_choice *c;
3247   unsigned int i;
3248
3249   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3250     if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3251         && strlen (mips_abi_choices[i].name) == namelen)
3252       c = &mips_abi_choices[i];
3253
3254   return c;
3255 }
3256
3257 static const struct mips_arch_choice *
3258 choose_arch_by_name (const char *name, unsigned int namelen)
3259 {
3260   const struct mips_arch_choice *c = NULL;
3261   unsigned int i;
3262
3263   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3264     if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
3265         && strlen (mips_arch_choices[i].name) == namelen)
3266       c = &mips_arch_choices[i];
3267
3268   return c;
3269 }
3270
3271 static const struct mips_arch_choice *
3272 choose_arch_by_number (unsigned long mach)
3273 {
3274   static unsigned long hint_bfd_mach;
3275   static const struct mips_arch_choice *hint_arch_choice;
3276   const struct mips_arch_choice *c;
3277   unsigned int i;
3278
3279   /* We optimize this because even if the user specifies no
3280      flags, this will be done for every instruction!  */
3281   if (hint_bfd_mach == mach
3282       && hint_arch_choice != NULL
3283       && hint_arch_choice->bfd_mach == hint_bfd_mach)
3284     return hint_arch_choice;
3285
3286   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3287     {
3288       if (mips_arch_choices[i].bfd_mach_valid
3289           && mips_arch_choices[i].bfd_mach == mach)
3290         {
3291           c = &mips_arch_choices[i];
3292           hint_bfd_mach = mach;
3293           hint_arch_choice = c;
3294         }
3295     }
3296   return c;
3297 }
3298
3299 static void
3300 set_default_mips_dis_options (struct disassemble_info *info)
3301 {
3302   const struct mips_arch_choice *chosen_arch;
3303
3304   /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
3305      and numeric FPR, CP0 register, and HWR names.  */
3306   mips_isa = ISA_MIPS3;
3307   mips_processor =  CPU_R3000;
3308   mips_gpr_names = mips_gpr_names_oldabi;
3309   mips_fpr_names = mips_fpr_names_numeric;
3310   mips_cp0_names = mips_cp0_names_numeric;
3311   mips_cp0sel_names = NULL;
3312   mips_cp0sel_names_len = 0;
3313   mips_hwr_names = mips_hwr_names_numeric;
3314   no_aliases = 0;
3315
3316   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
3317 #if 0
3318   if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
3319     {
3320       Elf_Internal_Ehdr *header;
3321
3322       header = elf_elfheader (info->section->owner);
3323       if (is_newabi (header))
3324         mips_gpr_names = mips_gpr_names_newabi;
3325     }
3326 #endif
3327
3328   /* Set ISA, architecture, and cp0 register names as best we can.  */
3329 #if !defined(SYMTAB_AVAILABLE) && 0
3330   /* This is running out on a target machine, not in a host tool.
3331      FIXME: Where does mips_target_info come from?  */
3332   target_processor = mips_target_info.processor;
3333   mips_isa = mips_target_info.isa;
3334 #else
3335   chosen_arch = choose_arch_by_number (info->mach);
3336   if (chosen_arch != NULL)
3337     {
3338       mips_processor = chosen_arch->processor;
3339       mips_isa = chosen_arch->isa;
3340       mips_cp0_names = chosen_arch->cp0_names;
3341       mips_cp0sel_names = chosen_arch->cp0sel_names;
3342       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3343       mips_hwr_names = chosen_arch->hwr_names;
3344     }
3345 #endif
3346 }
3347
3348 static void
3349 parse_mips_dis_option (const char *option, unsigned int len)
3350 {
3351   unsigned int i, optionlen, vallen;
3352   const char *val;
3353   const struct mips_abi_choice *chosen_abi;
3354   const struct mips_arch_choice *chosen_arch;
3355
3356   /* Look for the = that delimits the end of the option name.  */
3357   for (i = 0; i < len; i++)
3358     {
3359       if (option[i] == '=')
3360         break;
3361     }
3362   if (i == 0)           /* Invalid option: no name before '='.  */
3363     return;
3364   if (i == len)         /* Invalid option: no '='.  */
3365     return;
3366   if (i == (len - 1))   /* Invalid option: no value after '='.  */
3367     return;
3368
3369   optionlen = i;
3370   val = option + (optionlen + 1);
3371   vallen = len - (optionlen + 1);
3372
3373   if (strncmp("gpr-names", option, optionlen) == 0
3374       && strlen("gpr-names") == optionlen)
3375     {
3376       chosen_abi = choose_abi_by_name (val, vallen);
3377       if (chosen_abi != NULL)
3378         mips_gpr_names = chosen_abi->gpr_names;
3379       return;
3380     }
3381
3382   if (strncmp("fpr-names", option, optionlen) == 0
3383       && strlen("fpr-names") == optionlen)
3384     {
3385       chosen_abi = choose_abi_by_name (val, vallen);
3386       if (chosen_abi != NULL)
3387         mips_fpr_names = chosen_abi->fpr_names;
3388       return;
3389     }
3390
3391   if (strncmp("cp0-names", option, optionlen) == 0
3392       && strlen("cp0-names") == optionlen)
3393     {
3394       chosen_arch = choose_arch_by_name (val, vallen);
3395       if (chosen_arch != NULL)
3396         {
3397           mips_cp0_names = chosen_arch->cp0_names;
3398           mips_cp0sel_names = chosen_arch->cp0sel_names;
3399           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3400         }
3401       return;
3402     }
3403
3404   if (strncmp("hwr-names", option, optionlen) == 0
3405       && strlen("hwr-names") == optionlen)
3406     {
3407       chosen_arch = choose_arch_by_name (val, vallen);
3408       if (chosen_arch != NULL)
3409         mips_hwr_names = chosen_arch->hwr_names;
3410       return;
3411     }
3412
3413   if (strncmp("reg-names", option, optionlen) == 0
3414       && strlen("reg-names") == optionlen)
3415     {
3416       /* We check both ABI and ARCH here unconditionally, so
3417          that "numeric" will do the desirable thing: select
3418          numeric register names for all registers.  Other than
3419          that, a given name probably won't match both.  */
3420       chosen_abi = choose_abi_by_name (val, vallen);
3421       if (chosen_abi != NULL)
3422         {
3423           mips_gpr_names = chosen_abi->gpr_names;
3424           mips_fpr_names = chosen_abi->fpr_names;
3425         }
3426       chosen_arch = choose_arch_by_name (val, vallen);
3427       if (chosen_arch != NULL)
3428         {
3429           mips_cp0_names = chosen_arch->cp0_names;
3430           mips_cp0sel_names = chosen_arch->cp0sel_names;
3431           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3432           mips_hwr_names = chosen_arch->hwr_names;
3433         }
3434       return;
3435     }
3436
3437   /* Invalid option.  */
3438 }
3439
3440 static void
3441 parse_mips_dis_options (const char *options)
3442 {
3443   const char *option_end;
3444
3445   if (options == NULL)
3446     return;
3447
3448   while (*options != '\0')
3449     {
3450       /* Skip empty options.  */
3451       if (*options == ',')
3452         {
3453           options++;
3454           continue;
3455         }
3456
3457       /* We know that *options is neither NUL or a comma.  */
3458       option_end = options + 1;
3459       while (*option_end != ',' && *option_end != '\0')
3460         option_end++;
3461
3462       parse_mips_dis_option (options, option_end - options);
3463
3464       /* Go on to the next one.  If option_end points to a comma, it
3465          will be skipped above.  */
3466       options = option_end;
3467     }
3468 }
3469
3470 static const struct mips_cp0sel_name *
3471 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
3472                          unsigned int len,
3473                          unsigned int cp0reg,
3474                          unsigned int sel)
3475 {
3476   unsigned int i;
3477
3478   for (i = 0; i < len; i++)
3479     if (names[i].cp0reg == cp0reg && names[i].sel == sel)
3480       return &names[i];
3481   return NULL;
3482 }
3483 \f
3484 /* Print insn arguments for 32/64-bit code.  */
3485
3486 static void
3487 print_insn_args (const char *d,
3488                  register unsigned long int l,
3489                  bfd_vma pc,
3490                  struct disassemble_info *info,
3491                  const struct mips_opcode *opp)
3492 {
3493   int op, delta;
3494   unsigned int lsb, msb, msbd;
3495
3496   lsb = 0;
3497
3498   for (; *d != '\0'; d++)
3499     {
3500       switch (*d)
3501         {
3502         case ',':
3503         case '(':
3504         case ')':
3505         case '[':
3506         case ']':
3507           (*info->fprintf_func) (info->stream, "%c", *d);
3508           break;
3509
3510         case '+':
3511           /* Extension character; switch for second char.  */
3512           d++;
3513           switch (*d)
3514             {
3515             case '\0':
3516               /* xgettext:c-format */
3517               (*info->fprintf_func) (info->stream,
3518                                      _("# internal error, incomplete extension sequence (+)"));
3519               return;
3520
3521             case 'A':
3522               lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
3523               (*info->fprintf_func) (info->stream, "0x%x", lsb);
3524               break;
3525
3526             case 'B':
3527               msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
3528               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3529               break;
3530
3531             case '1':
3532               (*info->fprintf_func) (info->stream, "0x%lx",
3533                                      (l >> OP_SH_UDI1) & OP_MASK_UDI1);
3534               break;
3535
3536             case '2':
3537               (*info->fprintf_func) (info->stream, "0x%lx",
3538                                      (l >> OP_SH_UDI2) & OP_MASK_UDI2);
3539               break;
3540
3541             case '3':
3542               (*info->fprintf_func) (info->stream, "0x%lx",
3543                                      (l >> OP_SH_UDI3) & OP_MASK_UDI3);
3544               break;
3545
3546             case '4':
3547               (*info->fprintf_func) (info->stream, "0x%lx",
3548                                      (l >> OP_SH_UDI4) & OP_MASK_UDI4);
3549               break;
3550
3551             case 'C':
3552             case 'H':
3553               msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
3554               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3555               break;
3556
3557             case 'D':
3558               {
3559                 const struct mips_cp0sel_name *n;
3560                 unsigned int cp0reg, sel;
3561
3562                 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
3563                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3564
3565                 /* CP0 register including 'sel' code for mtcN (et al.), to be
3566                    printed textually if known.  If not known, print both
3567                    CP0 register name and sel numerically since CP0 register
3568                    with sel 0 may have a name unrelated to register being
3569                    printed.  */
3570                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3571                                             mips_cp0sel_names_len, cp0reg, sel);
3572                 if (n != NULL)
3573                   (*info->fprintf_func) (info->stream, "%s", n->name);
3574                 else
3575                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3576                 break;
3577               }
3578
3579             case 'E':
3580               lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
3581               (*info->fprintf_func) (info->stream, "0x%x", lsb);
3582               break;
3583
3584             case 'F':
3585               msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
3586               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3587               break;
3588
3589             case 'G':
3590               msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
3591               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3592               break;
3593
3594             case 't': /* Coprocessor 0 reg name */
3595               (*info->fprintf_func) (info->stream, "%s",
3596                                      mips_cp0_names[(l >> OP_SH_RT) &
3597                                                      OP_MASK_RT]);
3598               break;
3599
3600             case 'T': /* Coprocessor 0 reg name */
3601               {
3602                 const struct mips_cp0sel_name *n;
3603                 unsigned int cp0reg, sel;
3604
3605                 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
3606                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3607
3608                 /* CP0 register including 'sel' code for mftc0, to be
3609                    printed textually if known.  If not known, print both
3610                    CP0 register name and sel numerically since CP0 register
3611                    with sel 0 may have a name unrelated to register being
3612                    printed.  */
3613                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3614                                             mips_cp0sel_names_len, cp0reg, sel);
3615                 if (n != NULL)
3616                   (*info->fprintf_func) (info->stream, "%s", n->name);
3617                 else
3618                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3619                 break;
3620               }
3621
3622             default:
3623               /* xgettext:c-format */
3624               (*info->fprintf_func) (info->stream,
3625                                      _("# internal error, undefined extension sequence (+%c)"),
3626                                      *d);
3627               return;
3628             }
3629           break;
3630
3631         case '2':
3632           (*info->fprintf_func) (info->stream, "0x%lx",
3633                                  (l >> OP_SH_BP) & OP_MASK_BP);
3634           break;
3635
3636         case '3':
3637           (*info->fprintf_func) (info->stream, "0x%lx",
3638                                  (l >> OP_SH_SA3) & OP_MASK_SA3);
3639           break;
3640
3641         case '4':
3642           (*info->fprintf_func) (info->stream, "0x%lx",
3643                                  (l >> OP_SH_SA4) & OP_MASK_SA4);
3644           break;
3645
3646         case '5':
3647           (*info->fprintf_func) (info->stream, "0x%lx",
3648                                  (l >> OP_SH_IMM8) & OP_MASK_IMM8);
3649           break;
3650
3651         case '6':
3652           (*info->fprintf_func) (info->stream, "0x%lx",
3653                                  (l >> OP_SH_RS) & OP_MASK_RS);
3654           break;
3655
3656         case '7':
3657           (*info->fprintf_func) (info->stream, "$ac%ld",
3658                                  (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
3659           break;
3660
3661         case '8':
3662           (*info->fprintf_func) (info->stream, "0x%lx",
3663                                  (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
3664           break;
3665
3666         case '9':
3667           (*info->fprintf_func) (info->stream, "$ac%ld",
3668                                  (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
3669           break;
3670
3671         case '0': /* dsp 6-bit signed immediate in bit 20 */
3672           delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
3673           if (delta & 0x20) /* test sign bit */
3674             delta |= ~OP_MASK_DSPSFT;
3675           (*info->fprintf_func) (info->stream, "%d", delta);
3676           break;
3677
3678         case ':': /* dsp 7-bit signed immediate in bit 19 */
3679           delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
3680           if (delta & 0x40) /* test sign bit */
3681             delta |= ~OP_MASK_DSPSFT_7;
3682           (*info->fprintf_func) (info->stream, "%d", delta);
3683           break;
3684
3685         case '\'':
3686           (*info->fprintf_func) (info->stream, "0x%lx",
3687                                  (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
3688           break;
3689
3690         case '@': /* dsp 10-bit signed immediate in bit 16 */
3691           delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
3692           if (delta & 0x200) /* test sign bit */
3693             delta |= ~OP_MASK_IMM10;
3694           (*info->fprintf_func) (info->stream, "%d", delta);
3695           break;
3696
3697         case '!':
3698           (*info->fprintf_func) (info->stream, "%ld",
3699                                  (l >> OP_SH_MT_U) & OP_MASK_MT_U);
3700           break;
3701
3702         case '$':
3703           (*info->fprintf_func) (info->stream, "%ld",
3704                                  (l >> OP_SH_MT_H) & OP_MASK_MT_H);
3705           break;
3706
3707         case '*':
3708           (*info->fprintf_func) (info->stream, "$ac%ld",
3709                                  (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
3710           break;
3711
3712         case '&':
3713           (*info->fprintf_func) (info->stream, "$ac%ld",
3714                                  (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
3715           break;
3716
3717         case 'g':
3718           /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */
3719           (*info->fprintf_func) (info->stream, "$%ld",
3720                                  (l >> OP_SH_RD) & OP_MASK_RD);
3721           break;
3722
3723         case 's':
3724         case 'b':
3725         case 'r':
3726         case 'v':
3727           (*info->fprintf_func) (info->stream, "%s",
3728                                  mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
3729           break;
3730
3731         case 't':
3732         case 'w':
3733           (*info->fprintf_func) (info->stream, "%s",
3734                                  mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3735           break;
3736
3737         case 'i':
3738         case 'u':
3739           (*info->fprintf_func) (info->stream, "0x%lx",
3740                                  (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
3741           break;
3742
3743         case 'j': /* Same as i, but sign-extended.  */
3744         case 'o':
3745             delta = (opp->membership == I32R6) ?
3746                 (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6 :
3747                 (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3748
3749           if (delta & 0x8000)
3750             delta |= ~0xffff;
3751           (*info->fprintf_func) (info->stream, "%d",
3752                                  delta);
3753           break;
3754
3755         case 'h':
3756           (*info->fprintf_func) (info->stream, "0x%x",
3757                                  (unsigned int) ((l >> OP_SH_PREFX)
3758                                                  & OP_MASK_PREFX));
3759           break;
3760
3761         case 'k':
3762           (*info->fprintf_func) (info->stream, "0x%x",
3763                                  (unsigned int) ((l >> OP_SH_CACHE)
3764                                                  & OP_MASK_CACHE));
3765           break;
3766
3767         case 'a':
3768           info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
3769                           | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
3770           /* For gdb disassembler, force odd address on jalx.  */
3771           if (info->flavour == bfd_target_unknown_flavour
3772               && strcmp (opp->name, "jalx") == 0)
3773             info->target |= 1;
3774           (*info->print_address_func) (info->target, info);
3775           break;
3776
3777         case 'p':
3778           /* Sign extend the displacement.  */
3779           delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3780           if (delta & 0x8000)
3781             delta |= ~0xffff;
3782           info->target = (delta << 2) + pc + INSNLEN;
3783           (*info->print_address_func) (info->target, info);
3784           break;
3785
3786         case 'd':
3787           (*info->fprintf_func) (info->stream, "%s",
3788                                  mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3789           break;
3790
3791         case 'U':
3792           {
3793             /* First check for both rd and rt being equal.  */
3794             unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
3795             if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
3796               (*info->fprintf_func) (info->stream, "%s",
3797                                      mips_gpr_names[reg]);
3798             else
3799               {
3800                 /* If one is zero use the other.  */
3801                 if (reg == 0)
3802                   (*info->fprintf_func) (info->stream, "%s",
3803                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3804                 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
3805                   (*info->fprintf_func) (info->stream, "%s",
3806                                          mips_gpr_names[reg]);
3807                 else /* Bogus, result depends on processor.  */
3808                   (*info->fprintf_func) (info->stream, "%s or %s",
3809                                          mips_gpr_names[reg],
3810                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3811               }
3812           }
3813           break;
3814
3815         case 'z':
3816           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
3817           break;
3818
3819         case '<':
3820           (*info->fprintf_func) (info->stream, "0x%lx",
3821                                  (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
3822           break;
3823
3824         case 'c':
3825           (*info->fprintf_func) (info->stream, "0x%lx",
3826                                  (l >> OP_SH_CODE) & OP_MASK_CODE);
3827           break;
3828
3829         case 'q':
3830           (*info->fprintf_func) (info->stream, "0x%lx",
3831                                  (l >> OP_SH_CODE2) & OP_MASK_CODE2);
3832           break;
3833
3834         case 'C':
3835           (*info->fprintf_func) (info->stream, "0x%lx",
3836                                  (l >> OP_SH_COPZ) & OP_MASK_COPZ);
3837           break;
3838
3839         case 'B':
3840           (*info->fprintf_func) (info->stream, "0x%lx",
3841
3842                                  (l >> OP_SH_CODE20) & OP_MASK_CODE20);
3843           break;
3844
3845         case 'J':
3846           (*info->fprintf_func) (info->stream, "0x%lx",
3847                                  (l >> OP_SH_CODE19) & OP_MASK_CODE19);
3848           break;
3849
3850         case 'S':
3851         case 'V':
3852           (*info->fprintf_func) (info->stream, "%s",
3853                                  mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
3854           break;
3855
3856         case 'T':
3857         case 'W':
3858           (*info->fprintf_func) (info->stream, "%s",
3859                                  mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
3860           break;
3861
3862         case 'D':
3863           (*info->fprintf_func) (info->stream, "%s",
3864                                  mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
3865           break;
3866
3867         case 'R':
3868           (*info->fprintf_func) (info->stream, "%s",
3869                                  mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
3870           break;
3871
3872         case 'E':
3873           /* Coprocessor register for lwcN instructions, et al.
3874
3875              Note that there is no load/store cp0 instructions, and
3876              that FPU (cp1) instructions disassemble this field using
3877              'T' format.  Therefore, until we gain understanding of
3878              cp2 register names, we can simply print the register
3879              numbers.  */
3880           (*info->fprintf_func) (info->stream, "$%ld",
3881                                  (l >> OP_SH_RT) & OP_MASK_RT);
3882           break;
3883
3884         case 'G':
3885           /* Coprocessor register for mtcN instructions, et al.  Note
3886              that FPU (cp1) instructions disassemble this field using
3887              'S' format.  Therefore, we only need to worry about cp0,
3888              cp2, and cp3.  */
3889           op = (l >> OP_SH_OP) & OP_MASK_OP;
3890           if (op == OP_OP_COP0)
3891             (*info->fprintf_func) (info->stream, "%s",
3892                                    mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3893           else
3894             (*info->fprintf_func) (info->stream, "$%ld",
3895                                    (l >> OP_SH_RD) & OP_MASK_RD);
3896           break;
3897
3898         case 'K':
3899           (*info->fprintf_func) (info->stream, "%s",
3900                                  mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3901           break;
3902
3903         case 'N':
3904           (*info->fprintf_func) (info->stream,
3905                                  ((opp->pinfo & (FP_D | FP_S)) != 0
3906                                   ? "$fcc%ld" : "$cc%ld"),
3907                                  (l >> OP_SH_BCC) & OP_MASK_BCC);
3908           break;
3909
3910         case 'M':
3911           (*info->fprintf_func) (info->stream, "$fcc%ld",
3912                                  (l >> OP_SH_CCC) & OP_MASK_CCC);
3913           break;
3914
3915         case 'P':
3916           (*info->fprintf_func) (info->stream, "%ld",
3917                                  (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
3918           break;
3919
3920         case 'e':
3921           (*info->fprintf_func) (info->stream, "%ld",
3922                                  (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
3923           break;
3924
3925         case '%':
3926           (*info->fprintf_func) (info->stream, "%ld",
3927                                  (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
3928           break;
3929
3930         case 'H':
3931           (*info->fprintf_func) (info->stream, "%ld",
3932                                  (l >> OP_SH_SEL) & OP_MASK_SEL);
3933           break;
3934
3935         case 'O':
3936           (*info->fprintf_func) (info->stream, "%ld",
3937                                  (l >> OP_SH_ALN) & OP_MASK_ALN);
3938           break;
3939
3940         case 'Q':
3941           {
3942             unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
3943
3944             if ((vsel & 0x10) == 0)
3945               {
3946                 int fmt;
3947
3948                 vsel &= 0x0f;
3949                 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
3950                   if ((vsel & 1) == 0)
3951                     break;
3952                 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
3953                                        (l >> OP_SH_FT) & OP_MASK_FT,
3954                                        vsel >> 1);
3955               }
3956             else if ((vsel & 0x08) == 0)
3957               {
3958                 (*info->fprintf_func) (info->stream, "$v%ld",
3959                                        (l >> OP_SH_FT) & OP_MASK_FT);
3960               }
3961             else
3962               {
3963                 (*info->fprintf_func) (info->stream, "0x%lx",
3964                                        (l >> OP_SH_FT) & OP_MASK_FT);
3965               }
3966           }
3967           break;
3968
3969         case 'X':
3970           (*info->fprintf_func) (info->stream, "$v%ld",
3971                                  (l >> OP_SH_FD) & OP_MASK_FD);
3972           break;
3973
3974         case 'Y':
3975           (*info->fprintf_func) (info->stream, "$v%ld",
3976                                  (l >> OP_SH_FS) & OP_MASK_FS);
3977           break;
3978
3979         case 'Z':
3980           (*info->fprintf_func) (info->stream, "$v%ld",
3981                                  (l >> OP_SH_FT) & OP_MASK_FT);
3982           break;
3983
3984         default:
3985           /* xgettext:c-format */
3986           (*info->fprintf_func) (info->stream,
3987                                  _("# internal error, undefined modifier(%c)"),
3988                                  *d);
3989           return;
3990         }
3991     }
3992 }
3993 \f
3994 /* Check if the object uses NewABI conventions.  */
3995 #if 0
3996 static int
3997 is_newabi (header)
3998      Elf_Internal_Ehdr *header;
3999 {
4000   /* There are no old-style ABIs which use 64-bit ELF.  */
4001   if (header->e_ident[EI_CLASS] == ELFCLASS64)
4002     return 1;
4003
4004   /* If a 32-bit ELF file, n32 is a new-style ABI.  */
4005   if ((header->e_flags & EF_MIPS_ABI2) != 0)
4006     return 1;
4007
4008   return 0;
4009 }
4010 #endif
4011 \f
4012 /* Print the mips instruction at address MEMADDR in debugged memory,
4013    on using INFO.  Returns length of the instruction, in bytes, which is
4014    always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
4015    this is little-endian code.  */
4016
4017 static int
4018 print_insn_mips (bfd_vma memaddr,
4019                  unsigned long int word,
4020                  struct disassemble_info *info)
4021 {
4022   const struct mips_opcode *op;
4023   static bfd_boolean init = 0;
4024   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
4025
4026   /* Build a hash table to shorten the search time.  */
4027   if (! init)
4028     {
4029       unsigned int i;
4030
4031       for (i = 0; i <= OP_MASK_OP; i++)
4032         {
4033           for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
4034             {
4035               if (op->pinfo == INSN_MACRO
4036                   || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
4037                 continue;
4038               if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
4039                 {
4040                   mips_hash[i] = op;
4041                   break;
4042                 }
4043             }
4044         }
4045
4046       init = 1;
4047     }
4048
4049   info->bytes_per_chunk = INSNLEN;
4050   info->display_endian = info->endian;
4051   info->insn_info_valid = 1;
4052   info->branch_delay_insns = 0;
4053   info->data_size = 0;
4054   info->insn_type = dis_nonbranch;
4055   info->target = 0;
4056   info->target2 = 0;
4057
4058   op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4059   if (op != NULL)
4060     {
4061       for (; op < &mips_opcodes[NUMOPCODES]; op++)
4062         {
4063           if (op->pinfo != INSN_MACRO
4064               && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4065               && (word & op->mask) == op->match)
4066             {
4067               const char *d;
4068
4069               /* We always allow to disassemble the jalx instruction.  */
4070               if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4071                   && strcmp (op->name, "jalx"))
4072                 continue;
4073
4074               /* Figure out instruction type and branch delay information.  */
4075               if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4076                 {
4077                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4078                     info->insn_type = dis_jsr;
4079                   else
4080                     info->insn_type = dis_branch;
4081                   info->branch_delay_insns = 1;
4082                 }
4083               else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4084                                      | INSN_COND_BRANCH_LIKELY)) != 0)
4085                 {
4086                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4087                     info->insn_type = dis_condjsr;
4088                   else
4089                     info->insn_type = dis_condbranch;
4090                   info->branch_delay_insns = 1;
4091                 }
4092               else if ((op->pinfo & (INSN_STORE_MEMORY
4093                                      | INSN_LOAD_MEMORY_DELAY)) != 0)
4094                 info->insn_type = dis_dref;
4095
4096               (*info->fprintf_func) (info->stream, "%s", op->name);
4097
4098               d = op->args;
4099               if (d != NULL && *d != '\0')
4100                 {
4101                   (*info->fprintf_func) (info->stream, "\t");
4102                   print_insn_args (d, word, memaddr, info, op);
4103                 }
4104
4105               return INSNLEN;
4106             }
4107         }
4108     }
4109
4110   /* Handle undefined instructions.  */
4111   info->insn_type = dis_noninsn;
4112   (*info->fprintf_func) (info->stream, "0x%lx", word);
4113   return INSNLEN;
4114 }
4115 \f
4116 /* In an environment where we do not know the symbol type of the
4117    instruction we are forced to assume that the low order bit of the
4118    instructions' address may mark it as a mips16 instruction.  If we
4119    are single stepping, or the pc is within the disassembled function,
4120    this works.  Otherwise, we need a clue.  Sometimes.  */
4121
4122 static int
4123 _print_insn_mips (bfd_vma memaddr,
4124                   struct disassemble_info *info,
4125                   enum bfd_endian endianness)
4126 {
4127   bfd_byte buffer[INSNLEN];
4128   int status;
4129
4130   set_default_mips_dis_options (info);
4131   parse_mips_dis_options (info->disassembler_options);
4132
4133 #if 0
4134 #if 1
4135   /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
4136   /* Only a few tools will work this way.  */
4137   if (memaddr & 0x01)
4138     return print_insn_mips16 (memaddr, info);
4139 #endif
4140
4141 #if SYMTAB_AVAILABLE
4142   if (info->mach == bfd_mach_mips16
4143       || (info->flavour == bfd_target_elf_flavour
4144           && info->symbols != NULL
4145           && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
4146               == STO_MIPS16)))
4147     return print_insn_mips16 (memaddr, info);
4148 #endif
4149 #endif
4150
4151   status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
4152   if (status == 0)
4153     {
4154       unsigned long insn;
4155
4156       if (endianness == BFD_ENDIAN_BIG)
4157         insn = (unsigned long) bfd_getb32 (buffer);
4158       else
4159         insn = (unsigned long) bfd_getl32 (buffer);
4160
4161       return print_insn_mips (memaddr, insn, info);
4162     }
4163   else
4164     {
4165       (*info->memory_error_func) (status, memaddr, info);
4166       return -1;
4167     }
4168 }
4169
4170 int
4171 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
4172 {
4173   return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
4174 }
4175
4176 int
4177 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
4178 {
4179   return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
4180 }
4181 \f
4182 /* Disassemble mips16 instructions.  */
4183 #if 0
4184 static int
4185 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
4186 {
4187   int status;
4188   bfd_byte buffer[2];
4189   int length;
4190   int insn;
4191   bfd_boolean use_extend;
4192   int extend = 0;
4193   const struct mips_opcode *op, *opend;
4194
4195   info->bytes_per_chunk = 2;
4196   info->display_endian = info->endian;
4197   info->insn_info_valid = 1;
4198   info->branch_delay_insns = 0;
4199   info->data_size = 0;
4200   info->insn_type = dis_nonbranch;
4201   info->target = 0;
4202   info->target2 = 0;
4203
4204   status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4205   if (status != 0)
4206     {
4207       (*info->memory_error_func) (status, memaddr, info);
4208       return -1;
4209     }
4210
4211   length = 2;
4212
4213   if (info->endian == BFD_ENDIAN_BIG)
4214     insn = bfd_getb16 (buffer);
4215   else
4216     insn = bfd_getl16 (buffer);
4217
4218   /* Handle the extend opcode specially.  */
4219   use_extend = FALSE;
4220   if ((insn & 0xf800) == 0xf000)
4221     {
4222       use_extend = TRUE;
4223       extend = insn & 0x7ff;
4224
4225       memaddr += 2;
4226
4227       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4228       if (status != 0)
4229         {
4230           (*info->fprintf_func) (info->stream, "extend 0x%x",
4231                                  (unsigned int) extend);
4232           (*info->memory_error_func) (status, memaddr, info);
4233           return -1;
4234         }
4235
4236       if (info->endian == BFD_ENDIAN_BIG)
4237         insn = bfd_getb16 (buffer);
4238       else
4239         insn = bfd_getl16 (buffer);
4240
4241       /* Check for an extend opcode followed by an extend opcode.  */
4242       if ((insn & 0xf800) == 0xf000)
4243         {
4244           (*info->fprintf_func) (info->stream, "extend 0x%x",
4245                                  (unsigned int) extend);
4246           info->insn_type = dis_noninsn;
4247           return length;
4248         }
4249
4250       length += 2;
4251     }
4252
4253   /* FIXME: Should probably use a hash table on the major opcode here.  */
4254
4255   opend = mips16_opcodes + bfd_mips16_num_opcodes;
4256   for (op = mips16_opcodes; op < opend; op++)
4257     {
4258       if (op->pinfo != INSN_MACRO
4259           && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4260           && (insn & op->mask) == op->match)
4261         {
4262           const char *s;
4263
4264           if (strchr (op->args, 'a') != NULL)
4265             {
4266               if (use_extend)
4267                 {
4268                   (*info->fprintf_func) (info->stream, "extend 0x%x",
4269                                          (unsigned int) extend);
4270                   info->insn_type = dis_noninsn;
4271                   return length - 2;
4272                 }
4273
4274               use_extend = FALSE;
4275
4276               memaddr += 2;
4277
4278               status = (*info->read_memory_func) (memaddr, buffer, 2,
4279                                                   info);
4280               if (status == 0)
4281                 {
4282                   use_extend = TRUE;
4283                   if (info->endian == BFD_ENDIAN_BIG)
4284                     extend = bfd_getb16 (buffer);
4285                   else
4286                     extend = bfd_getl16 (buffer);
4287                   length += 2;
4288                 }
4289             }
4290
4291           (*info->fprintf_func) (info->stream, "%s", op->name);
4292           if (op->args[0] != '\0')
4293             (*info->fprintf_func) (info->stream, "\t");
4294
4295           for (s = op->args; *s != '\0'; s++)
4296             {
4297               if (*s == ','
4298                   && s[1] == 'w'
4299                   && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
4300                       == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
4301                 {
4302                   /* Skip the register and the comma.  */
4303                   ++s;
4304                   continue;
4305                 }
4306               if (*s == ','
4307                   && s[1] == 'v'
4308                   && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
4309                       == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
4310                 {
4311                   /* Skip the register and the comma.  */
4312                   ++s;
4313                   continue;
4314                 }
4315               print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
4316                                      info);
4317             }
4318
4319           if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4320             {
4321               info->branch_delay_insns = 1;
4322               if (info->insn_type != dis_jsr)
4323                 info->insn_type = dis_branch;
4324             }
4325
4326           return length;
4327         }
4328     }
4329
4330   if (use_extend)
4331     (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
4332   (*info->fprintf_func) (info->stream, "0x%x", insn);
4333   info->insn_type = dis_noninsn;
4334
4335   return length;
4336 }
4337
4338 /* Disassemble an operand for a mips16 instruction.  */
4339
4340 static void
4341 print_mips16_insn_arg (char type,
4342                        const struct mips_opcode *op,
4343                        int l,
4344                        bfd_boolean use_extend,
4345                        int extend,
4346                        bfd_vma memaddr,
4347                        struct disassemble_info *info)
4348 {
4349   switch (type)
4350     {
4351     case ',':
4352     case '(':
4353     case ')':
4354       (*info->fprintf_func) (info->stream, "%c", type);
4355       break;
4356
4357     case 'y':
4358     case 'w':
4359       (*info->fprintf_func) (info->stream, "%s",
4360                              mips16_reg_names(((l >> MIPS16OP_SH_RY)
4361                                                & MIPS16OP_MASK_RY)));
4362       break;
4363
4364     case 'x':
4365     case 'v':
4366       (*info->fprintf_func) (info->stream, "%s",
4367                              mips16_reg_names(((l >> MIPS16OP_SH_RX)
4368                                                & MIPS16OP_MASK_RX)));
4369       break;
4370
4371     case 'z':
4372       (*info->fprintf_func) (info->stream, "%s",
4373                              mips16_reg_names(((l >> MIPS16OP_SH_RZ)
4374                                                & MIPS16OP_MASK_RZ)));
4375       break;
4376
4377     case 'Z':
4378       (*info->fprintf_func) (info->stream, "%s",
4379                              mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
4380                                                & MIPS16OP_MASK_MOVE32Z)));
4381       break;
4382
4383     case '0':
4384       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4385       break;
4386
4387     case 'S':
4388       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
4389       break;
4390
4391     case 'P':
4392       (*info->fprintf_func) (info->stream, "$pc");
4393       break;
4394
4395     case 'R':
4396       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
4397       break;
4398
4399     case 'X':
4400       (*info->fprintf_func) (info->stream, "%s",
4401                              mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
4402                                             & MIPS16OP_MASK_REGR32)]);
4403       break;
4404
4405     case 'Y':
4406       (*info->fprintf_func) (info->stream, "%s",
4407                              mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
4408       break;
4409
4410     case '<':
4411     case '>':
4412     case '[':
4413     case ']':
4414     case '4':
4415     case '5':
4416     case 'H':
4417     case 'W':
4418     case 'D':
4419     case 'j':
4420     case '6':
4421     case '8':
4422     case 'V':
4423     case 'C':
4424     case 'U':
4425     case 'k':
4426     case 'K':
4427     case 'p':
4428     case 'q':
4429     case 'A':
4430     case 'B':
4431     case 'E':
4432       {
4433         int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
4434
4435         shift = 0;
4436         signedp = 0;
4437         extbits = 16;
4438         pcrel = 0;
4439         extu = 0;
4440         branch = 0;
4441         switch (type)
4442           {
4443           case '<':
4444             nbits = 3;
4445             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4446             extbits = 5;
4447             extu = 1;
4448             break;
4449           case '>':
4450             nbits = 3;
4451             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4452             extbits = 5;
4453             extu = 1;
4454             break;
4455           case '[':
4456             nbits = 3;
4457             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4458             extbits = 6;
4459             extu = 1;
4460             break;
4461           case ']':
4462             nbits = 3;
4463             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4464             extbits = 6;
4465             extu = 1;
4466             break;
4467           case '4':
4468             nbits = 4;
4469             immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
4470             signedp = 1;
4471             extbits = 15;
4472             break;
4473           case '5':
4474             nbits = 5;
4475             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4476             info->insn_type = dis_dref;
4477             info->data_size = 1;
4478             break;
4479           case 'H':
4480             nbits = 5;
4481             shift = 1;
4482             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4483             info->insn_type = dis_dref;
4484             info->data_size = 2;
4485             break;
4486           case 'W':
4487             nbits = 5;
4488             shift = 2;
4489             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4490             if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
4491                 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
4492               {
4493                 info->insn_type = dis_dref;
4494                 info->data_size = 4;
4495               }
4496             break;
4497           case 'D':
4498             nbits = 5;
4499             shift = 3;
4500             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4501             info->insn_type = dis_dref;
4502             info->data_size = 8;
4503             break;
4504           case 'j':
4505             nbits = 5;
4506             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4507             signedp = 1;
4508             break;
4509           case '6':
4510             nbits = 6;
4511             immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4512             break;
4513           case '8':
4514             nbits = 8;
4515             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4516             break;
4517           case 'V':
4518             nbits = 8;
4519             shift = 2;
4520             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4521             /* FIXME: This might be lw, or it might be addiu to $sp or
4522                $pc.  We assume it's load.  */
4523             info->insn_type = dis_dref;
4524             info->data_size = 4;
4525             break;
4526           case 'C':
4527             nbits = 8;
4528             shift = 3;
4529             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4530             info->insn_type = dis_dref;
4531             info->data_size = 8;
4532             break;
4533           case 'U':
4534             nbits = 8;
4535             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4536             extu = 1;
4537             break;
4538           case 'k':
4539             nbits = 8;
4540             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4541             signedp = 1;
4542             break;
4543           case 'K':
4544             nbits = 8;
4545             shift = 3;
4546             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4547             signedp = 1;
4548             break;
4549           case 'p':
4550             nbits = 8;
4551             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4552             signedp = 1;
4553             pcrel = 1;
4554             branch = 1;
4555             info->insn_type = dis_condbranch;
4556             break;
4557           case 'q':
4558             nbits = 11;
4559             immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
4560             signedp = 1;
4561             pcrel = 1;
4562             branch = 1;
4563             info->insn_type = dis_branch;
4564             break;
4565           case 'A':
4566             nbits = 8;
4567             shift = 2;
4568             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4569             pcrel = 1;
4570             /* FIXME: This can be lw or la.  We assume it is lw.  */
4571             info->insn_type = dis_dref;
4572             info->data_size = 4;
4573             break;
4574           case 'B':
4575             nbits = 5;
4576             shift = 3;
4577             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4578             pcrel = 1;
4579             info->insn_type = dis_dref;
4580             info->data_size = 8;
4581             break;
4582           case 'E':
4583             nbits = 5;
4584             shift = 2;
4585             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4586             pcrel = 1;
4587             break;
4588           default:
4589             abort ();
4590           }
4591
4592         if (! use_extend)
4593           {
4594             if (signedp && immed >= (1 << (nbits - 1)))
4595               immed -= 1 << nbits;
4596             immed <<= shift;
4597             if ((type == '<' || type == '>' || type == '[' || type == ']')
4598                 && immed == 0)
4599               immed = 8;
4600           }
4601         else
4602           {
4603             if (extbits == 16)
4604               immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
4605             else if (extbits == 15)
4606               immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
4607             else
4608               immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
4609             immed &= (1 << extbits) - 1;
4610             if (! extu && immed >= (1 << (extbits - 1)))
4611               immed -= 1 << extbits;
4612           }
4613
4614         if (! pcrel)
4615           (*info->fprintf_func) (info->stream, "%d", immed);
4616         else
4617           {
4618             bfd_vma baseaddr;
4619
4620             if (branch)
4621               {
4622                 immed *= 2;
4623                 baseaddr = memaddr + 2;
4624               }
4625             else if (use_extend)
4626               baseaddr = memaddr - 2;
4627             else
4628               {
4629                 int status;
4630                 bfd_byte buffer[2];
4631
4632                 baseaddr = memaddr;
4633
4634                 /* If this instruction is in the delay slot of a jr
4635                    instruction, the base address is the address of the
4636                    jr instruction.  If it is in the delay slot of jalr
4637                    instruction, the base address is the address of the
4638                    jalr instruction.  This test is unreliable: we have
4639                    no way of knowing whether the previous word is
4640                    instruction or data.  */
4641                 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
4642                                                     info);
4643                 if (status == 0
4644                     && (((info->endian == BFD_ENDIAN_BIG
4645                           ? bfd_getb16 (buffer)
4646                           : bfd_getl16 (buffer))
4647                          & 0xf800) == 0x1800))
4648                   baseaddr = memaddr - 4;
4649                 else
4650                   {
4651                     status = (*info->read_memory_func) (memaddr - 2, buffer,
4652                                                         2, info);
4653                     if (status == 0
4654                         && (((info->endian == BFD_ENDIAN_BIG
4655                               ? bfd_getb16 (buffer)
4656                               : bfd_getl16 (buffer))
4657                              & 0xf81f) == 0xe800))
4658                       baseaddr = memaddr - 2;
4659                   }
4660               }
4661             info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
4662             if (pcrel && branch
4663                 && info->flavour == bfd_target_unknown_flavour)
4664               /* For gdb disassembler, maintain odd address.  */
4665               info->target |= 1;
4666             (*info->print_address_func) (info->target, info);
4667           }
4668       }
4669       break;
4670
4671     case 'a':
4672       {
4673         int jalx = l & 0x400;
4674
4675         if (! use_extend)
4676           extend = 0;
4677         l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
4678         if (!jalx && info->flavour == bfd_target_unknown_flavour)
4679           /* For gdb disassembler, maintain odd address.  */
4680           l |= 1;
4681       }
4682       info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
4683       (*info->print_address_func) (info->target, info);
4684       info->insn_type = dis_jsr;
4685       info->branch_delay_insns = 1;
4686       break;
4687
4688     case 'l':
4689     case 'L':
4690       {
4691         int need_comma, amask, smask;
4692
4693         need_comma = 0;
4694
4695         l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4696
4697         amask = (l >> 3) & 7;
4698
4699         if (amask > 0 && amask < 5)
4700           {
4701             (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4702             if (amask > 1)
4703               (*info->fprintf_func) (info->stream, "-%s",
4704                                      mips_gpr_names[amask + 3]);
4705             need_comma = 1;
4706           }
4707
4708         smask = (l >> 1) & 3;
4709         if (smask == 3)
4710           {
4711             (*info->fprintf_func) (info->stream, "%s??",
4712                                    need_comma ? "," : "");
4713             need_comma = 1;
4714           }
4715         else if (smask > 0)
4716           {
4717             (*info->fprintf_func) (info->stream, "%s%s",
4718                                    need_comma ? "," : "",
4719                                    mips_gpr_names[16]);
4720             if (smask > 1)
4721               (*info->fprintf_func) (info->stream, "-%s",
4722                                      mips_gpr_names[smask + 15]);
4723             need_comma = 1;
4724           }
4725
4726         if (l & 1)
4727           {
4728             (*info->fprintf_func) (info->stream, "%s%s",
4729                                    need_comma ? "," : "",
4730                                    mips_gpr_names[31]);
4731             need_comma = 1;
4732           }
4733
4734         if (amask == 5 || amask == 6)
4735           {
4736             (*info->fprintf_func) (info->stream, "%s$f0",
4737                                    need_comma ? "," : "");
4738             if (amask == 6)
4739               (*info->fprintf_func) (info->stream, "-$f1");
4740           }
4741       }
4742       break;
4743
4744     case 'm':
4745     case 'M':
4746       /* MIPS16e save/restore.  */
4747       {
4748       int need_comma = 0;
4749       int amask, args, statics;
4750       int nsreg, smask;
4751       int framesz;
4752       int i, j;
4753
4754       l = l & 0x7f;
4755       if (use_extend)
4756         l |= extend << 16;
4757
4758       amask = (l >> 16) & 0xf;
4759       if (amask == MIPS16_ALL_ARGS)
4760         {
4761           args = 4;
4762           statics = 0;
4763         }
4764       else if (amask == MIPS16_ALL_STATICS)
4765         {
4766           args = 0;
4767           statics = 4;
4768         }
4769       else
4770         {
4771           args = amask >> 2;
4772           statics = amask & 3;
4773         }
4774
4775       if (args > 0) {
4776           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4777           if (args > 1)
4778             (*info->fprintf_func) (info->stream, "-%s",
4779                                    mips_gpr_names[4 + args - 1]);
4780           need_comma = 1;
4781       }
4782
4783       framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
4784       if (framesz == 0 && !use_extend)
4785         framesz = 128;
4786
4787       (*info->fprintf_func) (info->stream, "%s%d",
4788                              need_comma ? "," : "",
4789                              framesz);
4790
4791       if (l & 0x40)                   /* $ra */
4792         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
4793
4794       nsreg = (l >> 24) & 0x7;
4795       smask = 0;
4796       if (l & 0x20)                   /* $s0 */
4797         smask |= 1 << 0;
4798       if (l & 0x10)                   /* $s1 */
4799         smask |= 1 << 1;
4800       if (nsreg > 0)                  /* $s2-$s8 */
4801         smask |= ((1 << nsreg) - 1) << 2;
4802
4803       /* Find first set static reg bit.  */
4804       for (i = 0; i < 9; i++)
4805         {
4806           if (smask & (1 << i))
4807             {
4808               (*info->fprintf_func) (info->stream, ",%s",
4809                                      mips_gpr_names[i == 8 ? 30 : (16 + i)]);
4810               /* Skip over string of set bits.  */
4811               for (j = i; smask & (2 << j); j++)
4812                 continue;
4813               if (j > i)
4814                 (*info->fprintf_func) (info->stream, "-%s",
4815                                        mips_gpr_names[j == 8 ? 30 : (16 + j)]);
4816               i = j + 1;
4817             }
4818         }
4819
4820       /* Statics $ax - $a3.  */
4821       if (statics == 1)
4822         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
4823       else if (statics > 0)
4824         (*info->fprintf_func) (info->stream, ",%s-%s",
4825                                mips_gpr_names[7 - statics + 1],
4826                                mips_gpr_names[7]);
4827       }
4828       break;
4829
4830     default:
4831       /* xgettext:c-format */
4832       (*info->fprintf_func)
4833         (info->stream,
4834          _("# internal disassembler error, unrecognised modifier (%c)"),
4835          type);
4836       abort ();
4837     }
4838 }
4839
4840 void
4841 print_mips_disassembler_options (FILE *stream)
4842 {
4843   unsigned int i;
4844
4845   fprintf (stream, _("\n\
4846 The following MIPS specific disassembler options are supported for use\n\
4847 with the -M switch (multiple options should be separated by commas):\n"));
4848
4849   fprintf (stream, _("\n\
4850   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
4851                            Default: based on binary being disassembled.\n"));
4852
4853   fprintf (stream, _("\n\
4854   fpr-names=ABI            Print FPR names according to specified ABI.\n\
4855                            Default: numeric.\n"));
4856
4857   fprintf (stream, _("\n\
4858   cp0-names=ARCH           Print CP0 register names according to\n\
4859                            specified architecture.\n\
4860                            Default: based on binary being disassembled.\n"));
4861
4862   fprintf (stream, _("\n\
4863   hwr-names=ARCH           Print HWR names according to specified\n\
4864                            architecture.\n\
4865                            Default: based on binary being disassembled.\n"));
4866
4867   fprintf (stream, _("\n\
4868   reg-names=ABI            Print GPR and FPR names according to\n\
4869                            specified ABI.\n"));
4870
4871   fprintf (stream, _("\n\
4872   reg-names=ARCH           Print CP0 register and HWR names according to\n\
4873                            specified architecture.\n"));
4874
4875   fprintf (stream, _("\n\
4876   For the options above, the following values are supported for \"ABI\":\n\
4877    "));
4878   for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
4879     fprintf (stream, " %s", mips_abi_choices[i].name);
4880   fprintf (stream, _("\n"));
4881
4882   fprintf (stream, _("\n\
4883   For the options above, The following values are supported for \"ARCH\":\n\
4884    "));
4885   for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
4886     if (*mips_arch_choices[i].name != '\0')
4887       fprintf (stream, " %s", mips_arch_choices[i].name);
4888   fprintf (stream, _("\n"));
4889
4890   fprintf (stream, _("\n"));
4891 }
4892 #endif