tcg/mips/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
   5  * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
   6  * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #ifndef TCG_TARGET_MIPS
  27 #define TCG_TARGET_MIPS 1
  28
  29 #define TCG_TARGET_INSN_UNIT_SIZE 4
  30 #define TCG_TARGET_NB_REGS 32
  31
  32 typedef enum {
  33     TCG_REG_ZERO = 0,
  34     TCG_REG_AT,
  35     TCG_REG_V0,
  36     TCG_REG_V1,
  37     TCG_REG_A0,
  38     TCG_REG_A1,
  39     TCG_REG_A2,
  40     TCG_REG_A3,
  41     TCG_REG_T0,
  42     TCG_REG_T1,
  43     TCG_REG_T2,
  44     TCG_REG_T3,
  45     TCG_REG_T4,
  46     TCG_REG_T5,
  47     TCG_REG_T6,
  48     TCG_REG_T7,
  49     TCG_REG_S0,
  50     TCG_REG_S1,
  51     TCG_REG_S2,
  52     TCG_REG_S3,
  53     TCG_REG_S4,
  54     TCG_REG_S5,
  55     TCG_REG_S6,
  56     TCG_REG_S7,
  57     TCG_REG_T8,
  58     TCG_REG_T9,
  59     TCG_REG_K0,
  60     TCG_REG_K1,
  61     TCG_REG_GP,
  62     TCG_REG_SP,
  63     TCG_REG_S8,
  64     TCG_REG_RA,
  65
  66     TCG_REG_CALL_STACK = TCG_REG_SP,
  67     TCG_AREG0 = TCG_REG_S0,
  68 } TCGReg;
  69
  70 /* used for function call generation */
  71 #define TCG_TARGET_STACK_ALIGN 8
  72 #define TCG_TARGET_CALL_STACK_OFFSET 16
  73 #define TCG_TARGET_CALL_ALIGN_ARGS 1
  74
  75 /* MOVN/MOVZ instructions detection */
  76 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
  77     defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
  78     defined(_MIPS_ARCH_MIPS4)
  79 #define use_movnz_instructions  1
  80 #else
  81 extern bool use_movnz_instructions;
  82 #endif
  83
  84 /* MIPS32 instruction set detection */
  85 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
  86 #define use_mips32_instructions  1
  87 #else
  88 extern bool use_mips32_instructions;
  89 #endif
  90
  91 /* MIPS32R2 instruction set detection */
  92 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
  93 #define use_mips32r2_instructions  1
  94 #else
  95 extern bool use_mips32r2_instructions;
  96 #endif
  97
  98 /* optional instructions */
  99 #define TCG_TARGET_HAS_div_i32          1
 100 #define TCG_TARGET_HAS_rem_i32          1
 101 #define TCG_TARGET_HAS_not_i32          1
 102 #define TCG_TARGET_HAS_nor_i32          1
 103 #define TCG_TARGET_HAS_andc_i32         0
 104 #define TCG_TARGET_HAS_orc_i32          0
 105 #define TCG_TARGET_HAS_eqv_i32          0
 106 #define TCG_TARGET_HAS_nand_i32         0
 107 #define TCG_TARGET_HAS_mulu2_i32        1
 108 #define TCG_TARGET_HAS_muls2_i32        1
 109 #define TCG_TARGET_HAS_muluh_i32        1
 110 #define TCG_TARGET_HAS_mulsh_i32        1
 111
 112 /* optional instructions detected at runtime */
 113 #define TCG_TARGET_HAS_movcond_i32      use_movnz_instructions
 114 #define TCG_TARGET_HAS_bswap16_i32      use_mips32r2_instructions
 115 #define TCG_TARGET_HAS_bswap32_i32      use_mips32r2_instructions
 116 #define TCG_TARGET_HAS_deposit_i32      use_mips32r2_instructions
 117 #define TCG_TARGET_HAS_ext8s_i32        use_mips32r2_instructions
 118 #define TCG_TARGET_HAS_ext16s_i32       use_mips32r2_instructions
 119 #define TCG_TARGET_HAS_rot_i32          use_mips32r2_instructions
 120
 121 /* optional instructions automatically implemented */
 122 #define TCG_TARGET_HAS_neg_i32          0 /* sub  rd, zero, rt   */
 123 #define TCG_TARGET_HAS_ext8u_i32        0 /* andi rt, rs, 0xff   */
 124 #define TCG_TARGET_HAS_ext16u_i32       0 /* andi rt, rs, 0xffff */
 125
 126 #ifdef __OpenBSD__
 127 #include <machine/sysarch.h>
 128 #else
 129 #include <sys/cachectl.h>
 130 #endif
 131
 132 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 133 {
 134     cacheflush ((void *)start, stop-start, ICACHE);
 135 }
 136
 137 #endif