2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "qemu/error-report.h"
15 #include "target/ppc/cpu.h"
16 #include "sysemu/cpus.h"
17 #include "monitor/monitor.h"
18 #include "hw/ppc/fdt.h"
19 #include "hw/ppc/spapr.h"
20 #include "hw/ppc/spapr_cpu_core.h"
21 #include "hw/ppc/spapr_xive.h"
22 #include "hw/ppc/xive.h"
23 #include "hw/ppc/xive_regs.h"
26 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
27 * use for the ESB pages and the TIMA pages
29 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
30 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
33 * The allocation of VP blocks is a complex operation in OPAL and the
34 * VP identifiers have a relation with the number of HW chips, the
35 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
36 * controller model does not have the same constraints and can use a
37 * simple mapping scheme of the CPU vcpu_id
39 * These identifiers are never returned to the OS.
42 #define SPAPR_XIVE_NVT_BASE 0x400
45 * sPAPR NVT and END indexing helpers
47 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
49 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
52 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
53 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
58 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
62 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
66 static int spapr_xive_target_to_nvt(uint32_t target
,
67 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
69 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
75 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
80 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
83 int spapr_xive_end_to_target(uint8_t end_blk
, uint32_t end_idx
,
84 uint32_t *out_server
, uint8_t *out_prio
)
87 assert(end_blk
== SPAPR_XIVE_BLOCK_ID
);
90 *out_server
= end_idx
>> 3;
94 *out_prio
= end_idx
& 0x7;
99 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
100 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
105 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
109 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
113 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
114 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
116 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
122 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
127 * On sPAPR machines, use a simplified output for the XIVE END
128 * structure dumping only the information related to the OS EQ.
130 static void spapr_xive_end_pic_print_info(SpaprXive
*xive
, XiveEND
*end
,
133 uint64_t qaddr_base
= xive_end_qaddr(end
);
134 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
135 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
136 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
137 uint32_t qentries
= 1 << (qsize
+ 10);
138 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
139 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
141 monitor_printf(mon
, "%3d/%d % 6d/%5d @%"PRIx64
" ^%d",
142 spapr_xive_nvt_to_target(0, nvt
),
143 priority
, qindex
, qentries
, qaddr_base
, qgen
);
145 xive_end_queue_pic_print_info(end
, 6, mon
);
146 monitor_printf(mon
, "]");
149 void spapr_xive_pic_print_info(SpaprXive
*xive
, Monitor
*mon
)
151 XiveSource
*xsrc
= &xive
->source
;
154 if (kvm_irqchip_in_kernel()) {
155 Error
*local_err
= NULL
;
157 kvmppc_xive_synchronize_state(xive
, &local_err
);
159 error_report_err(local_err
);
164 monitor_printf(mon
, " LISN PQ EISN CPU/PRIO EQ\n");
166 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
167 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
168 XiveEAS
*eas
= &xive
->eat
[i
];
170 if (!xive_eas_is_valid(eas
)) {
174 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
175 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
176 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
177 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
178 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
179 xive_eas_is_masked(eas
) ? "M" : " ",
180 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
182 if (!xive_eas_is_masked(eas
)) {
183 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
186 assert(end_idx
< xive
->nr_ends
);
187 end
= &xive
->endt
[end_idx
];
189 if (xive_end_is_valid(end
)) {
190 spapr_xive_end_pic_print_info(xive
, end
, mon
);
193 monitor_printf(mon
, "\n");
197 void spapr_xive_mmio_set_enabled(SpaprXive
*xive
, bool enable
)
199 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
200 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
202 /* Disable the END ESBs until a guest OS makes use of them */
203 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
207 * When a Virtual Processor is scheduled to run on a HW thread, the
208 * hypervisor pushes its identifier in the OS CAM line. Emulate the
209 * same behavior under QEMU.
211 void spapr_xive_set_tctx_os_cam(XiveTCTX
*tctx
)
217 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx
->cs
), &nvt_blk
, &nvt_idx
);
219 nvt_cam
= cpu_to_be32(TM_QW1W2_VO
| xive_nvt_cam_line(nvt_blk
, nvt_idx
));
220 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &nvt_cam
, 4);
223 static void spapr_xive_end_reset(XiveEND
*end
)
225 memset(end
, 0, sizeof(*end
));
227 /* switch off the escalation and notification ESBs */
228 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
231 static void spapr_xive_reset(void *dev
)
233 SpaprXive
*xive
= SPAPR_XIVE(dev
);
237 * The XiveSource has its own reset handler, which mask off all
241 /* Mask all valid EASs in the IRQ number space. */
242 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
243 XiveEAS
*eas
= &xive
->eat
[i
];
244 if (xive_eas_is_valid(eas
)) {
245 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
252 for (i
= 0; i
< xive
->nr_ends
; i
++) {
253 spapr_xive_end_reset(&xive
->endt
[i
]);
257 static void spapr_xive_instance_init(Object
*obj
)
259 SpaprXive
*xive
= SPAPR_XIVE(obj
);
261 object_initialize_child(obj
, "source", &xive
->source
, sizeof(xive
->source
),
262 TYPE_XIVE_SOURCE
, &error_abort
, NULL
);
264 object_initialize_child(obj
, "end_source", &xive
->end_source
,
265 sizeof(xive
->end_source
), TYPE_XIVE_END_SOURCE
,
268 /* Not connected to the KVM XIVE device */
272 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
274 SpaprXive
*xive
= SPAPR_XIVE(dev
);
275 XiveSource
*xsrc
= &xive
->source
;
276 XiveENDSource
*end_xsrc
= &xive
->end_source
;
277 Error
*local_err
= NULL
;
279 if (!xive
->nr_irqs
) {
280 error_setg(errp
, "Number of interrupt needs to be greater 0");
284 if (!xive
->nr_ends
) {
285 error_setg(errp
, "Number of interrupt needs to be greater 0");
290 * Initialize the internal sources, for IPIs and virtual devices.
292 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
294 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
296 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
298 error_propagate(errp
, local_err
);
301 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
304 * Initialize the END ESB source
306 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
308 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
310 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
312 error_propagate(errp
, local_err
);
315 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
317 /* Set the mapping address of the END ESB pages after the source ESBs */
318 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
321 * Allocate the routing tables
323 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
324 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
326 xive
->nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
327 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
329 qemu_register_reset(spapr_xive_reset
, dev
);
331 /* TIMA initialization */
332 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
333 "xive.tima", 4ull << TM_SHIFT
);
334 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
337 * Map all regions. These will be enabled or disabled at reset and
338 * can also be overridden by KVM memory regions if active
340 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
341 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
342 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
345 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
346 uint32_t eas_idx
, XiveEAS
*eas
)
348 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
350 if (eas_idx
>= xive
->nr_irqs
) {
354 *eas
= xive
->eat
[eas_idx
];
358 static int spapr_xive_get_end(XiveRouter
*xrtr
,
359 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
361 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
363 if (end_idx
>= xive
->nr_ends
) {
367 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
371 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
372 uint32_t end_idx
, XiveEND
*end
,
375 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
377 if (end_idx
>= xive
->nr_ends
) {
381 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
385 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
386 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
388 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
389 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
392 /* TODO: should we assert() if we can find a NVT ? */
397 * sPAPR does not maintain a NVT table. Return that the NVT is
398 * valid if we have found a matching CPU
400 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
404 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
405 uint32_t nvt_idx
, XiveNVT
*nvt
,
409 * We don't need to write back to the NVTs because the sPAPR
410 * machine should never hit a non-scheduled NVT. It should never
413 g_assert_not_reached();
416 static XiveTCTX
*spapr_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
418 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
420 return spapr_cpu_state(cpu
)->tctx
;
423 static const VMStateDescription vmstate_spapr_xive_end
= {
424 .name
= TYPE_SPAPR_XIVE
"/end",
426 .minimum_version_id
= 1,
427 .fields
= (VMStateField
[]) {
428 VMSTATE_UINT32(w0
, XiveEND
),
429 VMSTATE_UINT32(w1
, XiveEND
),
430 VMSTATE_UINT32(w2
, XiveEND
),
431 VMSTATE_UINT32(w3
, XiveEND
),
432 VMSTATE_UINT32(w4
, XiveEND
),
433 VMSTATE_UINT32(w5
, XiveEND
),
434 VMSTATE_UINT32(w6
, XiveEND
),
435 VMSTATE_UINT32(w7
, XiveEND
),
436 VMSTATE_END_OF_LIST()
440 static const VMStateDescription vmstate_spapr_xive_eas
= {
441 .name
= TYPE_SPAPR_XIVE
"/eas",
443 .minimum_version_id
= 1,
444 .fields
= (VMStateField
[]) {
445 VMSTATE_UINT64(w
, XiveEAS
),
446 VMSTATE_END_OF_LIST()
450 static int vmstate_spapr_xive_pre_save(void *opaque
)
452 if (kvm_irqchip_in_kernel()) {
453 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque
));
460 * Called by the sPAPR IRQ backend 'post_load' method at the machine
463 int spapr_xive_post_load(SpaprXive
*xive
, int version_id
)
465 if (kvm_irqchip_in_kernel()) {
466 return kvmppc_xive_post_load(xive
, version_id
);
472 static const VMStateDescription vmstate_spapr_xive
= {
473 .name
= TYPE_SPAPR_XIVE
,
475 .minimum_version_id
= 1,
476 .pre_save
= vmstate_spapr_xive_pre_save
,
477 .post_load
= NULL
, /* handled at the machine level */
478 .fields
= (VMStateField
[]) {
479 VMSTATE_UINT32_EQUAL(nr_irqs
, SpaprXive
, NULL
),
480 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, SpaprXive
, nr_irqs
,
481 vmstate_spapr_xive_eas
, XiveEAS
),
482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, SpaprXive
, nr_ends
,
483 vmstate_spapr_xive_end
, XiveEND
),
484 VMSTATE_END_OF_LIST()
488 static Property spapr_xive_properties
[] = {
489 DEFINE_PROP_UINT32("nr-irqs", SpaprXive
, nr_irqs
, 0),
490 DEFINE_PROP_UINT32("nr-ends", SpaprXive
, nr_ends
, 0),
491 DEFINE_PROP_UINT64("vc-base", SpaprXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
492 DEFINE_PROP_UINT64("tm-base", SpaprXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
493 DEFINE_PROP_END_OF_LIST(),
496 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
498 DeviceClass
*dc
= DEVICE_CLASS(klass
);
499 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
501 dc
->desc
= "sPAPR XIVE Interrupt Controller";
502 dc
->props
= spapr_xive_properties
;
503 dc
->realize
= spapr_xive_realize
;
504 dc
->vmsd
= &vmstate_spapr_xive
;
506 xrc
->get_eas
= spapr_xive_get_eas
;
507 xrc
->get_end
= spapr_xive_get_end
;
508 xrc
->write_end
= spapr_xive_write_end
;
509 xrc
->get_nvt
= spapr_xive_get_nvt
;
510 xrc
->write_nvt
= spapr_xive_write_nvt
;
511 xrc
->get_tctx
= spapr_xive_get_tctx
;
514 static const TypeInfo spapr_xive_info
= {
515 .name
= TYPE_SPAPR_XIVE
,
516 .parent
= TYPE_XIVE_ROUTER
,
517 .instance_init
= spapr_xive_instance_init
,
518 .instance_size
= sizeof(SpaprXive
),
519 .class_init
= spapr_xive_class_init
,
522 static void spapr_xive_register_types(void)
524 type_register_static(&spapr_xive_info
);
527 type_init(spapr_xive_register_types
)
529 bool spapr_xive_irq_claim(SpaprXive
*xive
, uint32_t lisn
, bool lsi
)
531 XiveSource
*xsrc
= &xive
->source
;
533 if (lisn
>= xive
->nr_irqs
) {
537 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
);
539 xive_source_irq_set_lsi(xsrc
, lisn
);
542 if (kvm_irqchip_in_kernel()) {
543 Error
*local_err
= NULL
;
545 kvmppc_xive_source_reset_one(xsrc
, lisn
, &local_err
);
547 error_report_err(local_err
);
555 bool spapr_xive_irq_free(SpaprXive
*xive
, uint32_t lisn
)
557 if (lisn
>= xive
->nr_irqs
) {
561 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
568 * The terminology used by the XIVE hcalls is the following :
571 * EQ Event Queue assigned by OS to receive event data
572 * ESB page for source interrupt management
573 * LISN Logical Interrupt Source Number identifying a source in the
575 * EISN Effective Interrupt Source Number used by guest OS to
576 * identify source in the guest
578 * The EAS, END, NVT structures are not exposed.
582 * Linux hosts under OPAL reserve priority 7 for their own escalation
583 * interrupts (DD2.X POWER9). So we only allow the guest to use
586 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
591 case 7: /* OPAL escalation queue */
598 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
599 * real address of the MMIO page through which the Event State Buffer
600 * entry associated with the value of the "lisn" parameter is managed.
606 * - R5: "lisn" is per "interrupts", "interrupt-map", or
607 * "ibm,xive-lisn-ranges" properties, or as returned by the
608 * ibm,query-interrupt-source-number RTAS call, or as returned
609 * by the H_ALLOCATE_VAS_WINDOW hcall
613 * Bits 0-59: Reserved
614 * Bit 60: H_INT_ESB must be used for Event State Buffer
616 * Bit 61: 1 == LSI 0 == MSI
617 * Bit 62: the full function page supports trigger
618 * Bit 63: Store EOI Supported
619 * - R5: Logical Real address of full function Event State Buffer
620 * management page, -1 if H_INT_ESB hcall flag is set to 1.
621 * - R6: Logical Real Address of trigger only Event State Buffer
622 * management page or -1.
623 * - R7: Power of 2 page size for the ESB management pages returned in
627 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
628 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
629 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
631 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
633 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
634 SpaprMachineState
*spapr
,
638 SpaprXive
*xive
= spapr
->xive
;
639 XiveSource
*xsrc
= &xive
->source
;
640 target_ulong flags
= args
[0];
641 target_ulong lisn
= args
[1];
643 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
651 if (lisn
>= xive
->nr_irqs
) {
652 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
657 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
658 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
664 * All sources are emulated under the main XIVE object and share
665 * the same characteristics.
668 if (!xive_source_esb_has_2page(xsrc
)) {
669 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
671 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
672 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
676 * Force the use of the H_INT_ESB hcall in case of an LSI
677 * interrupt. This is necessary under KVM to re-trigger the
678 * interrupt if the level is still asserted
680 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
681 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
684 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
685 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
690 if (xive_source_esb_has_2page(xsrc
) &&
691 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
692 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
697 if (xive_source_esb_has_2page(xsrc
)) {
698 args
[3] = xsrc
->esb_shift
- 1;
700 args
[3] = xsrc
->esb_shift
;
707 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
708 * Interrupt Source to a target. The Logical Interrupt Source is
709 * designated with the "lisn" parameter and the target is designated
710 * with the "target" and "priority" parameters. Upon return from the
711 * hcall(), no additional interrupts will be directed to the old EQ.
716 * Bits 0-61: Reserved
717 * Bit 62: set the "eisn" in the EAS
718 * Bit 63: masks the interrupt source in the hardware interrupt
719 * control structure. An interrupt masked by this mechanism will
720 * be dropped, but it's source state bits will still be
721 * set. There is no race-free way of unmasking and restoring the
722 * source. Thus this should only be used in interrupts that are
723 * also masked at the source, and only in cases where the
724 * interrupt is not meant to be used for a large amount of time
725 * because no valid target exists for it for example
726 * - R5: "lisn" is per "interrupts", "interrupt-map", or
727 * "ibm,xive-lisn-ranges" properties, or as returned by the
728 * ibm,query-interrupt-source-number RTAS call, or as returned by
729 * the H_ALLOCATE_VAS_WINDOW hcall
730 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
731 * "ibm,ppc-interrupt-gserver#s"
732 * - R7: "priority" is a valid priority not in
733 * "ibm,plat-res-int-priorities"
734 * - R8: "eisn" is the guest EISN associated with the "lisn"
740 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
741 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
743 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
744 SpaprMachineState
*spapr
,
748 SpaprXive
*xive
= spapr
->xive
;
749 XiveEAS eas
, new_eas
;
750 target_ulong flags
= args
[0];
751 target_ulong lisn
= args
[1];
752 target_ulong target
= args
[2];
753 target_ulong priority
= args
[3];
754 target_ulong eisn
= args
[4];
758 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
762 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
766 if (lisn
>= xive
->nr_irqs
) {
767 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
772 eas
= xive
->eat
[lisn
];
773 if (!xive_eas_is_valid(&eas
)) {
774 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
779 /* priority 0xff is used to reset the EAS */
780 if (priority
== 0xff) {
781 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
785 if (flags
& SPAPR_XIVE_SRC_MASK
) {
786 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
788 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
791 if (spapr_xive_priority_is_reserved(priority
)) {
792 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
793 " is reserved\n", priority
);
798 * Validate that "target" is part of the list of threads allocated
799 * to the partition. For that, find the END corresponding to the
802 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
806 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
807 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
809 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
810 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
813 if (kvm_irqchip_in_kernel()) {
814 Error
*local_err
= NULL
;
816 kvmppc_xive_set_source_config(xive
, lisn
, &new_eas
, &local_err
);
818 error_report_err(local_err
);
824 xive
->eat
[lisn
] = new_eas
;
829 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
830 * target/priority pair is assigned to the specified Logical Interrupt
837 * - R5: "lisn" is per "interrupts", "interrupt-map", or
838 * "ibm,xive-lisn-ranges" properties, or as returned by the
839 * ibm,query-interrupt-source-number RTAS call, or as
840 * returned by the H_ALLOCATE_VAS_WINDOW hcall
843 * - R4: Target to which the specified Logical Interrupt Source is
845 * - R5: Priority to which the specified Logical Interrupt Source is
847 * - R6: EISN for the specified Logical Interrupt Source (this will be
848 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
850 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
851 SpaprMachineState
*spapr
,
855 SpaprXive
*xive
= spapr
->xive
;
856 target_ulong flags
= args
[0];
857 target_ulong lisn
= args
[1];
861 uint32_t end_idx
, nvt_idx
;
863 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
871 if (lisn
>= xive
->nr_irqs
) {
872 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
877 eas
= xive
->eat
[lisn
];
878 if (!xive_eas_is_valid(&eas
)) {
879 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
884 /* EAS_END_BLOCK is unused on sPAPR */
885 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
887 assert(end_idx
< xive
->nr_ends
);
888 end
= &xive
->endt
[end_idx
];
890 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
891 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
892 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
894 if (xive_eas_is_masked(&eas
)) {
897 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
900 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
906 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
907 * address of the notification management page associated with the
908 * specified target and priority.
914 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
915 * "ibm,ppc-interrupt-gserver#s"
916 * - R6: "priority" is a valid priority not in
917 * "ibm,plat-res-int-priorities"
920 * - R4: Logical real address of notification page
921 * - R5: Power of 2 page size of the notification page
923 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
924 SpaprMachineState
*spapr
,
928 SpaprXive
*xive
= spapr
->xive
;
929 XiveENDSource
*end_xsrc
= &xive
->end_source
;
930 target_ulong flags
= args
[0];
931 target_ulong target
= args
[1];
932 target_ulong priority
= args
[2];
937 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
946 * H_STATE should be returned if a H_INT_RESET is in progress.
947 * This is not needed when running the emulation under QEMU
950 if (spapr_xive_priority_is_reserved(priority
)) {
951 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
952 " is reserved\n", priority
);
957 * Validate that "target" is part of the list of threads allocated
958 * to the partition. For that, find the END corresponding to the
961 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
965 assert(end_idx
< xive
->nr_ends
);
966 end
= &xive
->endt
[end_idx
];
968 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
969 if (xive_end_is_enqueue(end
)) {
970 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
979 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
980 * a given "target" and "priority". It is also used to set the
981 * notification config associated with the EQ. An EQ size of 0 is
982 * used to reset the EQ config for a given target and priority. If
983 * resetting the EQ config, the END associated with the given "target"
984 * and "priority" will be changed to disable queueing.
986 * Upon return from the hcall(), no additional interrupts will be
987 * directed to the old EQ (if one was set). The old EQ (if one was
988 * set) should be investigated for interrupts that occurred prior to
989 * or during the hcall().
994 * Bits 0-62: Reserved
995 * Bit 63: Unconditional Notify (n) per the XIVE spec
996 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
997 * "ibm,ppc-interrupt-gserver#s"
998 * - R6: "priority" is a valid priority not in
999 * "ibm,plat-res-int-priorities"
1000 * - R7: "eventQueue": The logical real address of the start of the EQ
1001 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1007 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1009 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
1010 SpaprMachineState
*spapr
,
1011 target_ulong opcode
,
1014 SpaprXive
*xive
= spapr
->xive
;
1015 target_ulong flags
= args
[0];
1016 target_ulong target
= args
[1];
1017 target_ulong priority
= args
[2];
1018 target_ulong qpage
= args
[3];
1019 target_ulong qsize
= args
[4];
1021 uint8_t end_blk
, nvt_blk
;
1022 uint32_t end_idx
, nvt_idx
;
1024 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1028 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1033 * H_STATE should be returned if a H_INT_RESET is in progress.
1034 * This is not needed when running the emulation under QEMU
1037 if (spapr_xive_priority_is_reserved(priority
)) {
1038 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1039 " is reserved\n", priority
);
1044 * Validate that "target" is part of the list of threads allocated
1045 * to the partition. For that, find the END corresponding to the
1049 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1053 assert(end_idx
< xive
->nr_ends
);
1054 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
1061 if (!QEMU_IS_ALIGNED(qpage
, 1ul << qsize
)) {
1062 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: EQ @0x%" HWADDR_PRIx
1063 " is not naturally aligned with %" HWADDR_PRIx
"\n",
1064 qpage
, (hwaddr
)1 << qsize
);
1067 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
1068 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
1069 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
1070 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1073 /* reset queue and disable queueing */
1074 spapr_xive_end_reset(&end
);
1078 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1084 hwaddr plen
= 1 << qsize
;
1088 * Validate the guest EQ. We should also check that the queue
1089 * has been zeroed by the OS.
1091 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1092 MEMTXATTRS_UNSPECIFIED
);
1093 if (plen
!= 1 << qsize
) {
1094 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1095 HWADDR_PRIx
"\n", qpage
);
1098 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1101 /* "target" should have been validated above */
1102 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1103 g_assert_not_reached();
1107 * Ensure the priority and target are correctly set (they will not
1108 * be right after allocation)
1110 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1111 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1112 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1114 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1115 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1117 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1121 * The generation bit for the END starts at 1 and The END page
1122 * offset counter starts at 0.
1124 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1125 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1126 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1129 * TODO: issue syncs required to ensure all in-flight interrupts
1130 * are complete on the old END
1134 if (kvm_irqchip_in_kernel()) {
1135 Error
*local_err
= NULL
;
1137 kvmppc_xive_set_queue_config(xive
, end_blk
, end_idx
, &end
, &local_err
);
1139 error_report_err(local_err
);
1145 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1150 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1151 * target and priority.
1156 * Bits 0-62: Reserved
1157 * Bit 63: Debug: Return debug data
1158 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1159 * "ibm,ppc-interrupt-gserver#s"
1160 * - R6: "priority" is a valid priority not in
1161 * "ibm,plat-res-int-priorities"
1165 * Bits 0-61: Reserved
1166 * Bit 62: The value of Event Queue Generation Number (g) per
1167 * the XIVE spec if "Debug" = 1
1168 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1169 * - R5: The logical real address of the start of the EQ
1170 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1171 * - R7: The value of Event Queue Offset Counter per XIVE spec
1172 * if "Debug" = 1, else 0
1176 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1178 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1179 SpaprMachineState
*spapr
,
1180 target_ulong opcode
,
1183 SpaprXive
*xive
= spapr
->xive
;
1184 target_ulong flags
= args
[0];
1185 target_ulong target
= args
[1];
1186 target_ulong priority
= args
[2];
1191 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1195 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1200 * H_STATE should be returned if a H_INT_RESET is in progress.
1201 * This is not needed when running the emulation under QEMU
1204 if (spapr_xive_priority_is_reserved(priority
)) {
1205 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1206 " is reserved\n", priority
);
1211 * Validate that "target" is part of the list of threads allocated
1212 * to the partition. For that, find the END corresponding to the
1215 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1219 assert(end_idx
< xive
->nr_ends
);
1220 end
= &xive
->endt
[end_idx
];
1223 if (xive_end_is_notify(end
)) {
1224 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1227 if (xive_end_is_enqueue(end
)) {
1228 args
[1] = xive_end_qaddr(end
);
1229 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1235 if (kvm_irqchip_in_kernel()) {
1236 Error
*local_err
= NULL
;
1238 kvmppc_xive_get_queue_config(xive
, end_blk
, end_idx
, end
, &local_err
);
1240 error_report_err(local_err
);
1245 /* TODO: do we need any locking on the END ? */
1246 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1247 /* Load the event queue generation number into the return flags */
1248 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1250 /* Load R7 with the event queue offset counter */
1251 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1260 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1261 * reporting cache line pair for the calling thread. The reporting
1262 * cache lines will contain the OS interrupt context when the OS
1263 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1264 * interrupt. The reporting cache lines can be reset by inputting -1
1265 * in "reportingLine". Issuing the CI store byte without reporting
1266 * cache lines registered will result in the data not being accessible
1272 * Bits 0-63: Reserved
1273 * - R5: "reportingLine": The logical real address of the reporting cache
1279 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1280 SpaprMachineState
*spapr
,
1281 target_ulong opcode
,
1284 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1289 * H_STATE should be returned if a H_INT_RESET is in progress.
1290 * This is not needed when running the emulation under QEMU
1293 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1298 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1299 * real address of the reporting cache line pair set for the input
1300 * "target". If no reporting cache line pair has been set, -1 is
1306 * Bits 0-63: Reserved
1307 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1308 * "ibm,ppc-interrupt-gserver#s"
1309 * - R6: "reportingLine": The logical real address of the reporting
1313 * - R4: The logical real address of the reporting line if set, else -1
1315 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1316 SpaprMachineState
*spapr
,
1317 target_ulong opcode
,
1320 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1325 * H_STATE should be returned if a H_INT_RESET is in progress.
1326 * This is not needed when running the emulation under QEMU
1329 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1334 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1335 * page for the input "lisn". This hcall is only supported for LISNs
1336 * that have the ESB hcall flag set to 1 when returned from hcall()
1337 * H_INT_GET_SOURCE_INFO.
1342 * Bits 0-62: Reserved
1343 * bit 63: Store: Store=1, store operation, else load operation
1344 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1345 * "ibm,xive-lisn-ranges" properties, or as returned by the
1346 * ibm,query-interrupt-source-number RTAS call, or as
1347 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1348 * - R6: "esbOffset" is the offset into the ESB page for the load or
1350 * - R7: "storeData" is the data to write for a store operation
1353 * - R4: The value of the load if load operation, else -1
1356 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1358 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1359 SpaprMachineState
*spapr
,
1360 target_ulong opcode
,
1363 SpaprXive
*xive
= spapr
->xive
;
1365 target_ulong flags
= args
[0];
1366 target_ulong lisn
= args
[1];
1367 target_ulong offset
= args
[2];
1368 target_ulong data
= args
[3];
1370 XiveSource
*xsrc
= &xive
->source
;
1372 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1376 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1380 if (lisn
>= xive
->nr_irqs
) {
1381 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1386 eas
= xive
->eat
[lisn
];
1387 if (!xive_eas_is_valid(&eas
)) {
1388 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1393 if (offset
> (1ull << xsrc
->esb_shift
)) {
1397 if (kvm_irqchip_in_kernel()) {
1398 args
[0] = kvmppc_xive_esb_rw(xsrc
, lisn
, offset
, data
,
1399 flags
& SPAPR_XIVE_ESB_STORE
);
1401 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1403 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1404 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1405 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1406 HWADDR_PRIx
"\n", mmio_addr
);
1409 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1415 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1416 * ensure any in flight events for the input lisn are in the event
1422 * Bits 0-63: Reserved
1423 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1424 * "ibm,xive-lisn-ranges" properties, or as returned by the
1425 * ibm,query-interrupt-source-number RTAS call, or as
1426 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1431 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1432 SpaprMachineState
*spapr
,
1433 target_ulong opcode
,
1436 SpaprXive
*xive
= spapr
->xive
;
1438 target_ulong flags
= args
[0];
1439 target_ulong lisn
= args
[1];
1441 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1449 if (lisn
>= xive
->nr_irqs
) {
1450 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1455 eas
= xive
->eat
[lisn
];
1456 if (!xive_eas_is_valid(&eas
)) {
1457 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1463 * H_STATE should be returned if a H_INT_RESET is in progress.
1464 * This is not needed when running the emulation under QEMU
1468 * This is not real hardware. Nothing to be done unless when
1472 if (kvm_irqchip_in_kernel()) {
1473 Error
*local_err
= NULL
;
1475 kvmppc_xive_sync_source(xive
, lisn
, &local_err
);
1477 error_report_err(local_err
);
1485 * The H_INT_RESET hcall() is used to reset all of the partition's
1486 * interrupt exploitation structures to their initial state. This
1487 * means losing all previously set interrupt state set via
1488 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1493 * Bits 0-63: Reserved
1498 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1499 SpaprMachineState
*spapr
,
1500 target_ulong opcode
,
1503 SpaprXive
*xive
= spapr
->xive
;
1504 target_ulong flags
= args
[0];
1506 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1514 device_reset(DEVICE(xive
));
1516 if (kvm_irqchip_in_kernel()) {
1517 Error
*local_err
= NULL
;
1519 kvmppc_xive_reset(xive
, &local_err
);
1521 error_report_err(local_err
);
1528 void spapr_xive_hcall_init(SpaprMachineState
*spapr
)
1530 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1531 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1532 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1533 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1534 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1535 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1536 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1537 h_int_set_os_reporting_line
);
1538 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1539 h_int_get_os_reporting_line
);
1540 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1541 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1542 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1545 void spapr_dt_xive(SpaprMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1548 SpaprXive
*xive
= spapr
->xive
;
1550 uint64_t timas
[2 * 2];
1551 /* Interrupt number ranges for the IPIs */
1552 uint32_t lisn_ranges
[] = {
1554 cpu_to_be32(nr_servers
),
1557 * EQ size - the sizes of pages supported by the system 4K, 64K,
1558 * 2M, 16M. We only advertise 64K for the moment.
1560 uint32_t eq_sizes
[] = {
1561 cpu_to_be32(16), /* 64K */
1564 * The following array is in sync with the reserved priorities
1565 * defined by the 'spapr_xive_priority_is_reserved' routine.
1567 uint32_t plat_res_int_priorities
[] = {
1568 cpu_to_be32(7), /* start */
1569 cpu_to_be32(0xf8), /* count */
1572 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1573 timas
[0] = cpu_to_be64(xive
->tm_base
+
1574 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1575 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1576 timas
[2] = cpu_to_be64(xive
->tm_base
+
1577 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1578 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1580 _FDT(node
= fdt_add_subnode(fdt
, 0, xive
->nodename
));
1582 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1583 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1585 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1586 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1588 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1589 sizeof(lisn_ranges
)));
1591 /* For Linux to link the LSIs to the interrupt controller. */
1592 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1593 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1596 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1597 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1600 * The "ibm,plat-res-int-priorities" property defines the priority
1601 * ranges reserved by the hypervisor
1603 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1604 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));