hw/dma/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Modifications:
   7  *  2010-Feb-14 Artyom Tarasenko : reworked irq generation
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "hw/hw.h"
  29 #include "hw/sparc/sparc32_dma.h"
  30 #include "hw/sparc/sun4m.h"
  31 #include "hw/sysbus.h"
  32 #include "trace.h"
  33
  34 /*
  35  * This is the DMA controller part of chip STP2000 (Master I/O), also
  36  * produced as NCR89C100. See
  37  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  38  * and
  39  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  40  */
  41
  42 #define DMA_REGS 4
  43 #define DMA_SIZE (4 * sizeof(uint32_t))
  44 /* We need the mask, because one instance of the device is not page
  45    aligned (ledma, start address 0x0010) */
  46 #define DMA_MASK (DMA_SIZE - 1)
  47 /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
  48 #define DMA_ETH_SIZE (8 * sizeof(uint32_t))
  49 #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
  50
  51 #define DMA_VER 0xa0000000
  52 #define DMA_INTR 1
  53 #define DMA_INTREN 0x10
  54 #define DMA_WRITE_MEM 0x100
  55 #define DMA_EN 0x200
  56 #define DMA_LOADED 0x04000000
  57 #define DMA_DRAIN_FIFO 0x40
  58 #define DMA_RESET 0x80
  59
  60 /* XXX SCSI and ethernet should have different read-only bit masks */
  61 #define DMA_CSR_RO_MASK 0xfe000007
  62
  63 #define TYPE_SPARC32_DMA "sparc32_dma"
  64 #define SPARC32_DMA(obj) OBJECT_CHECK(DMAState, (obj), TYPE_SPARC32_DMA)
  65
  66 typedef struct DMAState DMAState;
  67
  68 struct DMAState {
  69     SysBusDevice parent_obj;
  70
  71     MemoryRegion iomem;
  72     uint32_t dmaregs[DMA_REGS];
  73     qemu_irq irq;
  74     void *iommu;
  75     qemu_irq gpio[2];
  76     uint32_t is_ledma;
  77 };
  78
  79 enum {
  80     GPIO_RESET = 0,
  81     GPIO_DMA,
  82 };
  83
  84 /* Note: on sparc, the lance 16 bit bus is swapped */
  85 void ledma_memory_read(void *opaque, hwaddr addr,
  86                        uint8_t *buf, int len, int do_bswap)
  87 {
  88     DMAState *s = opaque;
  89     int i;
  90
  91     addr |= s->dmaregs[3];
  92     trace_ledma_memory_read(addr);
  93     if (do_bswap) {
  94         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  95     } else {
  96         addr &= ~1;
  97         len &= ~1;
  98         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  99         for(i = 0; i < len; i += 2) {
 100             bswap16s((uint16_t *)(buf + i));
 101         }
 102     }
 103 }
 104
 105 void ledma_memory_write(void *opaque, hwaddr addr,
 106                         uint8_t *buf, int len, int do_bswap)
 107 {
 108     DMAState *s = opaque;
 109     int l, i;
 110     uint16_t tmp_buf[32];
 111
 112     addr |= s->dmaregs[3];
 113     trace_ledma_memory_write(addr);
 114     if (do_bswap) {
 115         sparc_iommu_memory_write(s->iommu, addr, buf, len);
 116     } else {
 117         addr &= ~1;
 118         len &= ~1;
 119         while (len > 0) {
 120             l = len;
 121             if (l > sizeof(tmp_buf))
 122                 l = sizeof(tmp_buf);
 123             for(i = 0; i < l; i += 2) {
 124                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 125             }
 126             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 127             len -= l;
 128             buf += l;
 129             addr += l;
 130         }
 131     }
 132 }
 133
 134 static void dma_set_irq(void *opaque, int irq, int level)
 135 {
 136     DMAState *s = opaque;
 137     if (level) {
 138         s->dmaregs[0] |= DMA_INTR;
 139         if (s->dmaregs[0] & DMA_INTREN) {
 140             trace_sparc32_dma_set_irq_raise();
 141             qemu_irq_raise(s->irq);
 142         }
 143     } else {
 144         if (s->dmaregs[0] & DMA_INTR) {
 145             s->dmaregs[0] &= ~DMA_INTR;
 146             if (s->dmaregs[0] & DMA_INTREN) {
 147                 trace_sparc32_dma_set_irq_lower();
 148                 qemu_irq_lower(s->irq);
 149             }
 150         }
 151     }
 152 }
 153
 154 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 155 {
 156     DMAState *s = opaque;
 157
 158     trace_espdma_memory_read(s->dmaregs[1]);
 159     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 160     s->dmaregs[1] += len;
 161 }
 162
 163 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 164 {
 165     DMAState *s = opaque;
 166
 167     trace_espdma_memory_write(s->dmaregs[1]);
 168     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 169     s->dmaregs[1] += len;
 170 }
 171
 172 static uint64_t dma_mem_read(void *opaque, hwaddr addr,
 173                              unsigned size)
 174 {
 175     DMAState *s = opaque;
 176     uint32_t saddr;
 177
 178     if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
 179         /* aliased to espdma, but we can't get there from here */
 180         /* buggy driver if using undocumented behavior, just return 0 */
 181         trace_sparc32_dma_mem_readl(addr, 0);
 182         return 0;
 183     }
 184     saddr = (addr & DMA_MASK) >> 2;
 185     trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
 186     return s->dmaregs[saddr];
 187 }
 188
 189 static void dma_mem_write(void *opaque, hwaddr addr,
 190                           uint64_t val, unsigned size)
 191 {
 192     DMAState *s = opaque;
 193     uint32_t saddr;
 194
 195     if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
 196         /* aliased to espdma, but we can't get there from here */
 197         trace_sparc32_dma_mem_writel(addr, 0, val);
 198         return;
 199     }
 200     saddr = (addr & DMA_MASK) >> 2;
 201     trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
 202     switch (saddr) {
 203     case 0:
 204         if (val & DMA_INTREN) {
 205             if (s->dmaregs[0] & DMA_INTR) {
 206                 trace_sparc32_dma_set_irq_raise();
 207                 qemu_irq_raise(s->irq);
 208             }
 209         } else {
 210             if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
 211                 trace_sparc32_dma_set_irq_lower();
 212                 qemu_irq_lower(s->irq);
 213             }
 214         }
 215         if (val & DMA_RESET) {
 216             qemu_irq_raise(s->gpio[GPIO_RESET]);
 217             qemu_irq_lower(s->gpio[GPIO_RESET]);
 218         } else if (val & DMA_DRAIN_FIFO) {
 219             val &= ~DMA_DRAIN_FIFO;
 220         } else if (val == 0)
 221             val = DMA_DRAIN_FIFO;
 222
 223         if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
 224             trace_sparc32_dma_enable_raise();
 225             qemu_irq_raise(s->gpio[GPIO_DMA]);
 226         } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
 227             trace_sparc32_dma_enable_lower();
 228             qemu_irq_lower(s->gpio[GPIO_DMA]);
 229         }
 230
 231         val &= ~DMA_CSR_RO_MASK;
 232         val |= DMA_VER;
 233         s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
 234         break;
 235     case 1:
 236         s->dmaregs[0] |= DMA_LOADED;
 237         /* fall through */
 238     default:
 239         s->dmaregs[saddr] = val;
 240         break;
 241     }
 242 }
 243
 244 static const MemoryRegionOps dma_mem_ops = {
 245     .read = dma_mem_read,
 246     .write = dma_mem_write,
 247     .endianness = DEVICE_NATIVE_ENDIAN,
 248     .valid = {
 249         .min_access_size = 4,
 250         .max_access_size = 4,
 251     },
 252 };
 253
 254 static void dma_reset(DeviceState *d)
 255 {
 256     DMAState *s = SPARC32_DMA(d);
 257
 258     memset(s->dmaregs, 0, DMA_SIZE);
 259     s->dmaregs[0] = DMA_VER;
 260 }
 261
 262 static const VMStateDescription vmstate_dma = {
 263     .name ="sparc32_dma",
 264     .version_id = 2,
 265     .minimum_version_id = 2,
 266     .fields = (VMStateField[]) {
 267         VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS),
 268         VMSTATE_END_OF_LIST()
 269     }
 270 };
 271
 272 static int sparc32_dma_init1(SysBusDevice *sbd)
 273 {
 274     DeviceState *dev = DEVICE(sbd);
 275     DMAState *s = SPARC32_DMA(dev);
 276     int reg_size;
 277
 278     sysbus_init_irq(sbd, &s->irq);
 279
 280     reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
 281     memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
 282                           "dma", reg_size);
 283     sysbus_init_mmio(sbd, &s->iomem);
 284
 285     qdev_init_gpio_in(dev, dma_set_irq, 1);
 286     qdev_init_gpio_out(dev, s->gpio, 2);
 287
 288     return 0;
 289 }
 290
 291 static Property sparc32_dma_properties[] = {
 292     DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
 293     DEFINE_PROP_UINT32("is_ledma", DMAState, is_ledma, 0),
 294     DEFINE_PROP_END_OF_LIST(),
 295 };
 296
 297 static void sparc32_dma_class_init(ObjectClass *klass, void *data)
 298 {
 299     DeviceClass *dc = DEVICE_CLASS(klass);
 300     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 301
 302     k->init = sparc32_dma_init1;
 303     dc->reset = dma_reset;
 304     dc->vmsd = &vmstate_dma;
 305     dc->props = sparc32_dma_properties;
 306     /* Reason: pointer property "iommu_opaque" */
 307     dc->cannot_instantiate_with_device_add_yet = true;
 308 }
 309
 310 static const TypeInfo sparc32_dma_info = {
 311     .name          = TYPE_SPARC32_DMA,
 312     .parent        = TYPE_SYS_BUS_DEVICE,
 313     .instance_size = sizeof(DMAState),
 314     .class_init    = sparc32_dma_class_init,
 315 };
 316
 317 static void sparc32_dma_register_types(void)
 318 {
 319     type_register_static(&sparc32_dma_info);
 320 }
 321
 322 type_init(sparc32_dma_register_types)