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aspeed/smc: reset flash after each test
[qemu/ar7.git] / hw / ssi / aspeed_smc.c
blobae1ad2dba6ffff93d663f07f29656d8213a826a8
1 /*
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/sysemu.h"
28 #include "qemu/log.h"
29 #include "include/qemu/error-report.h"
30 #include "exec/address-spaces.h"
31
32 #include "hw/ssi/aspeed_smc.h"
33
34 /* CE Type Setting Register */
35 #define R_CONF (0x00 / 4)
36 #define CONF_LEGACY_DISABLE (1 << 31)
37 #define CONF_ENABLE_W4 20
38 #define CONF_ENABLE_W3 19
39 #define CONF_ENABLE_W2 18
40 #define CONF_ENABLE_W1 17
41 #define CONF_ENABLE_W0 16
42 #define CONF_FLASH_TYPE4 8
43 #define CONF_FLASH_TYPE3 6
44 #define CONF_FLASH_TYPE2 4
45 #define CONF_FLASH_TYPE1 2
46 #define CONF_FLASH_TYPE0 0
47 #define CONF_FLASH_TYPE_NOR 0x0
48 #define CONF_FLASH_TYPE_NAND 0x1
49 #define CONF_FLASH_TYPE_SPI 0x2
50
51 /* CE Control Register */
52 #define R_CE_CTRL (0x04 / 4)
53 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
54 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
55 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
56 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
57 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
58
59 /* Interrupt Control and Status Register */
60 #define R_INTR_CTRL (0x08 / 4)
61 #define INTR_CTRL_DMA_STATUS (1 << 11)
62 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
63 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
64 #define INTR_CTRL_DMA_EN (1 << 3)
65 #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
66 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
67
68 /* CEx Control Register */
69 #define R_CTRL0 (0x10 / 4)
70 #define CTRL_CMD_SHIFT 16
71 #define CTRL_CMD_MASK 0xff
72 #define CTRL_AST2400_SPI_4BYTE (1 << 13)
73 #define CTRL_CE_STOP_ACTIVE (1 << 2)
74 #define CTRL_CMD_MODE_MASK 0x3
75 #define CTRL_READMODE 0x0
76 #define CTRL_FREADMODE 0x1
77 #define CTRL_WRITEMODE 0x2
78 #define CTRL_USERMODE 0x3
79 #define R_CTRL1 (0x14 / 4)
80 #define R_CTRL2 (0x18 / 4)
81 #define R_CTRL3 (0x1C / 4)
82 #define R_CTRL4 (0x20 / 4)
83
84 /* CEx Segment Address Register */
85 #define R_SEG_ADDR0 (0x30 / 4)
86 #define SEG_END_SHIFT 24 /* 8MB units */
87 #define SEG_END_MASK 0xff
88 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
89 #define SEG_START_MASK 0xff
90 #define R_SEG_ADDR1 (0x34 / 4)
91 #define R_SEG_ADDR2 (0x38 / 4)
92 #define R_SEG_ADDR3 (0x3C / 4)
93 #define R_SEG_ADDR4 (0x40 / 4)
94
95 /* Misc Control Register #1 */
96 #define R_MISC_CTRL1 (0x50 / 4)
97
98 /* Misc Control Register #2 */
99 #define R_MISC_CTRL2 (0x54 / 4)
100
101 /* DMA Control/Status Register */
102 #define R_DMA_CTRL (0x80 / 4)
103 #define DMA_CTRL_DELAY_MASK 0xf
104 #define DMA_CTRL_DELAY_SHIFT 8
105 #define DMA_CTRL_FREQ_MASK 0xf
106 #define DMA_CTRL_FREQ_SHIFT 4
107 #define DMA_CTRL_MODE (1 << 3)
108 #define DMA_CTRL_CKSUM (1 << 2)
109 #define DMA_CTRL_DIR (1 << 1)
110 #define DMA_CTRL_EN (1 << 0)
111
112 /* DMA Flash Side Address */
113 #define R_DMA_FLASH_ADDR (0x84 / 4)
114
115 /* DMA DRAM Side Address */
116 #define R_DMA_DRAM_ADDR (0x88 / 4)
117
118 /* DMA Length Register */
119 #define R_DMA_LEN (0x8C / 4)
120
121 /* Checksum Calculation Result */
122 #define R_DMA_CHECKSUM (0x90 / 4)
123
124 /* Misc Control Register #2 */
125 #define R_TIMINGS (0x94 / 4)
126
127 /* SPI controller registers and bits */
128 #define R_SPI_CONF (0x00 / 4)
129 #define SPI_CONF_ENABLE_W0 0
130 #define R_SPI_CTRL0 (0x4 / 4)
131 #define R_SPI_MISC_CTRL (0x10 / 4)
132 #define R_SPI_TIMINGS (0x14 / 4)
133
134 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
135 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
136
137 #define ASPEED_SOC_SMC_FLASH_BASE 0x10000000
138 #define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
139 #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
140 #define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000
141
142 /* Flash opcodes. */
143 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
144
145 /*
146 * Default segments mapping addresses and size for each slave per
147 * controller. These can be changed when board is initialized with the
148 * Segment Address Registers.
149 */
150 static const AspeedSegments aspeed_segments_legacy[] = {
151 { 0x10000000, 32 * 1024 * 1024 },
152 };
153
154 static const AspeedSegments aspeed_segments_fmc[] = {
155 { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */
156 { 0x24000000, 32 * 1024 * 1024 },
157 { 0x26000000, 32 * 1024 * 1024 },
158 { 0x28000000, 32 * 1024 * 1024 },
159 { 0x2A000000, 32 * 1024 * 1024 }
160 };
161
162 static const AspeedSegments aspeed_segments_spi[] = {
163 { 0x30000000, 64 * 1024 * 1024 },
164 };
165
166 static const AspeedSegments aspeed_segments_ast2500_fmc[] = {
167 { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */
168 { 0x28000000, 32 * 1024 * 1024 },
169 { 0x2A000000, 32 * 1024 * 1024 },
170 };
171
172 static const AspeedSegments aspeed_segments_ast2500_spi1[] = {
173 { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */
174 { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */
175 };
176
177 static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
178 { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
179 { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
180 };
181
182 static const AspeedSMCController controllers[] = {
183 {
184 .name = "aspeed.smc.smc",
185 .r_conf = R_CONF,
186 .r_ce_ctrl = R_CE_CTRL,
187 .r_ctrl0 = R_CTRL0,
188 .r_timings = R_TIMINGS,
189 .conf_enable_w0 = CONF_ENABLE_W0,
190 .max_slaves = 5,
191 .segments = aspeed_segments_legacy,
192 .flash_window_base = ASPEED_SOC_SMC_FLASH_BASE,
193 .flash_window_size = 0x6000000,
194 .has_dma = false,
195 .nregs = ASPEED_SMC_R_SMC_MAX,
196 }, {
197 .name = "aspeed.smc.fmc",
198 .r_conf = R_CONF,
199 .r_ce_ctrl = R_CE_CTRL,
200 .r_ctrl0 = R_CTRL0,
201 .r_timings = R_TIMINGS,
202 .conf_enable_w0 = CONF_ENABLE_W0,
203 .max_slaves = 5,
204 .segments = aspeed_segments_fmc,
205 .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
206 .flash_window_size = 0x10000000,
207 .has_dma = true,
208 .nregs = ASPEED_SMC_R_MAX,
209 }, {
210 .name = "aspeed.smc.spi",
211 .r_conf = R_SPI_CONF,
212 .r_ce_ctrl = 0xff,
213 .r_ctrl0 = R_SPI_CTRL0,
214 .r_timings = R_SPI_TIMINGS,
215 .conf_enable_w0 = SPI_CONF_ENABLE_W0,
216 .max_slaves = 1,
217 .segments = aspeed_segments_spi,
218 .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
219 .flash_window_size = 0x10000000,
220 .has_dma = false,
221 .nregs = ASPEED_SMC_R_SPI_MAX,
222 }, {
223 .name = "aspeed.smc.ast2500-fmc",
224 .r_conf = R_CONF,
225 .r_ce_ctrl = R_CE_CTRL,
226 .r_ctrl0 = R_CTRL0,
227 .r_timings = R_TIMINGS,
228 .conf_enable_w0 = CONF_ENABLE_W0,
229 .max_slaves = 3,
230 .segments = aspeed_segments_ast2500_fmc,
231 .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
232 .flash_window_size = 0x10000000,
233 .has_dma = true,
234 .nregs = ASPEED_SMC_R_MAX,
235 }, {
236 .name = "aspeed.smc.ast2500-spi1",
237 .r_conf = R_CONF,
238 .r_ce_ctrl = R_CE_CTRL,
239 .r_ctrl0 = R_CTRL0,
240 .r_timings = R_TIMINGS,
241 .conf_enable_w0 = CONF_ENABLE_W0,
242 .max_slaves = 2,
243 .segments = aspeed_segments_ast2500_spi1,
244 .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
245 .flash_window_size = 0x8000000,
246 .has_dma = false,
247 .nregs = ASPEED_SMC_R_MAX,
248 }, {
249 .name = "aspeed.smc.ast2500-spi2",
250 .r_conf = R_CONF,
251 .r_ce_ctrl = R_CE_CTRL,
252 .r_ctrl0 = R_CTRL0,
253 .r_timings = R_TIMINGS,
254 .conf_enable_w0 = CONF_ENABLE_W0,
255 .max_slaves = 2,
256 .segments = aspeed_segments_ast2500_spi2,
257 .flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE,
258 .flash_window_size = 0x8000000,
259 .has_dma = false,
260 .nregs = ASPEED_SMC_R_MAX,
261 },
262 };
263
264 /*
265 * The Segment Register uses a 8MB unit to encode the start address
266 * and the end address of the mapping window of a flash SPI slave :
267 *
268 * | byte 1 | byte 2 | byte 3 | byte 4 |
269 * +--------+--------+--------+--------+
270 * | end | start | 0 | 0 |
271 *
272 */
273 static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg)
274 {
275 uint32_t reg = 0;
276 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
277 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
278 return reg;
279 }
280
281 static inline void aspeed_smc_reg_to_segment(uint32_t reg, AspeedSegments *seg)
282 {
283 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
284 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
285 }
286
287 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
288 const AspeedSegments *new,
289 int cs)
290 {
291 AspeedSegments seg;
292 int i;
293
294 for (i = 0; i < s->ctrl->max_slaves; i++) {
295 if (i == cs) {
296 continue;
297 }
298
299 aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + i], &seg);
300
301 if (new->addr + new->size > seg.addr &&
302 new->addr < seg.addr + seg.size) {
303 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment CS%d [ 0x%"
304 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
305 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
306 s->ctrl->name, cs, new->addr, new->addr + new->size,
307 i, seg.addr, seg.addr + seg.size);
308 return true;
309 }
310 }
311 return false;
312 }
313
314 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
315 uint64_t new)
316 {
317 AspeedSMCFlash *fl = &s->flashes[cs];
318 AspeedSegments seg;
319
320 aspeed_smc_reg_to_segment(new, &seg);
321
322 /* The start address of CS0 is read-only */
323 if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
324 qemu_log_mask(LOG_GUEST_ERROR,
325 "%s: Tried to change CS0 start address to 0x%"
326 HWADDR_PRIx "\n", s->ctrl->name, seg.addr);
327 seg.addr = s->ctrl->flash_window_base;
328 new = aspeed_smc_segment_to_reg(&seg);
329 }
330
331 /*
332 * The end address of the AST2500 spi controllers is also
333 * read-only.
334 */
335 if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 ||
336 s->ctrl->segments == aspeed_segments_ast2500_spi2) &&
337 cs == s->ctrl->max_slaves &&
338 seg.addr + seg.size != s->ctrl->segments[cs].addr +
339 s->ctrl->segments[cs].size) {
340 qemu_log_mask(LOG_GUEST_ERROR,
341 "%s: Tried to change CS%d end address to 0x%"
342 HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.size);
343 seg.size = s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size -
344 seg.addr;
345 new = aspeed_smc_segment_to_reg(&seg);
346 }
347
348 /* Keep the segment in the overall flash window */
349 if (seg.addr + seg.size <= s->ctrl->flash_window_base ||
350 seg.addr > s->ctrl->flash_window_base + s->ctrl->flash_window_size) {
351 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is invalid : "
352 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
353 s->ctrl->name, cs, seg.addr, seg.addr + seg.size);
354 return;
355 }
356
357 /* Check start address vs. alignment */
358 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
359 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is not "
360 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
361 s->ctrl->name, cs, seg.addr, seg.addr + seg.size);
362 }
363
364 /* And segments should not overlap (in the specs) */
365 aspeed_smc_flash_overlap(s, &seg, cs);
366
367 /* All should be fine now to move the region */
368 memory_region_transaction_begin();
369 memory_region_set_size(&fl->mmio, seg.size);
370 memory_region_set_address(&fl->mmio, seg.addr - s->ctrl->flash_window_base);
371 memory_region_set_enabled(&fl->mmio, true);
372 memory_region_transaction_commit();
373
374 s->regs[R_SEG_ADDR0 + cs] = new;
375 }
376
377 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
378 unsigned size)
379 {
380 qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u"
381 PRIx64 "\n", __func__, addr, size);
382 return 0;
383 }
384
385 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
386 uint64_t data, unsigned size)
387 {
388 qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"
389 PRIx64 "\n", __func__, addr, size, data);
390 }
391
392 static const MemoryRegionOps aspeed_smc_flash_default_ops = {
393 .read = aspeed_smc_flash_default_read,
394 .write = aspeed_smc_flash_default_write,
395 .endianness = DEVICE_LITTLE_ENDIAN,
396 .valid = {
397 .min_access_size = 1,
398 .max_access_size = 4,
399 },
400 };
401
402 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
403 {
404 const AspeedSMCState *s = fl->controller;
405
406 return s->regs[s->r_ctrl0 + fl->id] & CTRL_CMD_MODE_MASK;
407 }
408
409 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
410 {
411 const AspeedSMCState *s = fl->controller;
412
413 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->id));
414 }
415
416 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
417 {
418 const AspeedSMCState *s = fl->controller;
419 int cmd = (s->regs[s->r_ctrl0 + fl->id] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK;
420
421 /* In read mode, the default SPI command is READ (0x3). In other
422 * modes, the command should necessarily be defined */
423 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) {
424 cmd = SPI_OP_READ;
425 }
426
427 if (!cmd) {
428 qemu_log_mask(LOG_GUEST_ERROR, "%s: no command defined for mode %d\n",
429 __func__, aspeed_smc_flash_mode(fl));
430 }
431
432 return cmd;
433 }
434
435 static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
436 {
437 const AspeedSMCState *s = fl->controller;
438
439 if (s->ctrl->segments == aspeed_segments_spi) {
440 return s->regs[s->r_ctrl0] & CTRL_AST2400_SPI_4BYTE;
441 } else {
442 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->id));
443 }
444 }
445
446 static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
447 {
448 const AspeedSMCState *s = fl->controller;
449
450 return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
451 }
452
453 static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
454 {
455 AspeedSMCState *s = fl->controller;
456
457 s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE;
458 qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
459 }
460
461 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
462 {
463 AspeedSMCState *s = fl->controller;
464
465 s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE;
466 qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
467 }
468
469 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
470 uint32_t addr)
471 {
472 const AspeedSMCState *s = fl->controller;
473 AspeedSegments seg;
474
475 aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg);
476 if ((addr & (seg.size - 1)) != addr) {
477 qemu_log_mask(LOG_GUEST_ERROR,
478 "%s: invalid address 0x%08x for CS%d segment : "
479 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
480 s->ctrl->name, addr, fl->id, seg.addr,
481 seg.addr + seg.size);
482 }
483
484 addr &= seg.size - 1;
485 return addr;
486 }
487
488 static void aspeed_smc_flash_send_addr(AspeedSMCFlash *fl, uint32_t addr)
489 {
490 const AspeedSMCState *s = fl->controller;
491 uint8_t cmd = aspeed_smc_flash_cmd(fl);
492
493 /* Flash access can not exceed CS segment */
494 addr = aspeed_smc_check_segment_addr(fl, addr);
495
496 ssi_transfer(s->spi, cmd);
497
498 if (aspeed_smc_flash_is_4byte(fl)) {
499 ssi_transfer(s->spi, (addr >> 24) & 0xff);
500 }
501 ssi_transfer(s->spi, (addr >> 16) & 0xff);
502 ssi_transfer(s->spi, (addr >> 8) & 0xff);
503 ssi_transfer(s->spi, (addr & 0xff));
504 }
505
506 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
507 {
508 AspeedSMCFlash *fl = opaque;
509 AspeedSMCState *s = fl->controller;
510 uint64_t ret = 0;
511 int i;
512
513 switch (aspeed_smc_flash_mode(fl)) {
514 case CTRL_USERMODE:
515 for (i = 0; i < size; i++) {
516 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
517 }
518 break;
519 case CTRL_READMODE:
520 case CTRL_FREADMODE:
521 aspeed_smc_flash_select(fl);
522 aspeed_smc_flash_send_addr(fl, addr);
523
524 for (i = 0; i < size; i++) {
525 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
526 }
527
528 aspeed_smc_flash_unselect(fl);
529 break;
530 default:
531 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid flash mode %d\n",
532 __func__, aspeed_smc_flash_mode(fl));
533 }
534
535 return ret;
536 }
537
538 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
539 unsigned size)
540 {
541 AspeedSMCFlash *fl = opaque;
542 AspeedSMCState *s = fl->controller;
543 int i;
544
545 if (!aspeed_smc_is_writable(fl)) {
546 qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
547 HWADDR_PRIx "\n", __func__, addr);
548 return;
549 }
550
551 switch (aspeed_smc_flash_mode(fl)) {
552 case CTRL_USERMODE:
553 for (i = 0; i < size; i++) {
554 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
555 }
556 break;
557 case CTRL_WRITEMODE:
558 aspeed_smc_flash_select(fl);
559 aspeed_smc_flash_send_addr(fl, addr);
560
561 for (i = 0; i < size; i++) {
562 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
563 }
564
565 aspeed_smc_flash_unselect(fl);
566 break;
567 default:
568 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid flash mode %d\n",
569 __func__, aspeed_smc_flash_mode(fl));
570 }
571 }
572
573 static const MemoryRegionOps aspeed_smc_flash_ops = {
574 .read = aspeed_smc_flash_read,
575 .write = aspeed_smc_flash_write,
576 .endianness = DEVICE_LITTLE_ENDIAN,
577 .valid = {
578 .min_access_size = 1,
579 .max_access_size = 4,
580 },
581 };
582
583 static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
584 {
585 const AspeedSMCState *s = fl->controller;
586
587 qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
588 }
589
590 static void aspeed_smc_reset(DeviceState *d)
591 {
592 AspeedSMCState *s = ASPEED_SMC(d);
593 int i;
594
595 memset(s->regs, 0, sizeof s->regs);
596
597 /* Pretend DMA is done (u-boot initialization) */
598 s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS;
599
600 /* Unselect all slaves */
601 for (i = 0; i < s->num_cs; ++i) {
602 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
603 qemu_set_irq(s->cs_lines[i], true);
604 }
605
606 /* setup default segment register values for all */
607 for (i = 0; i < s->ctrl->max_slaves; ++i) {
608 s->regs[R_SEG_ADDR0 + i] =
609 aspeed_smc_segment_to_reg(&s->ctrl->segments[i]);
610 }
611
612 /* HW strapping for AST2500 FMC controllers */
613 if (s->ctrl->segments == aspeed_segments_ast2500_fmc) {
614 /* flash type is fixed to SPI for CE0 and CE1 */
615 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
616 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1);
617
618 /* 4BYTE mode is autodetected for CE0. Let's force it to 1 for
619 * now */
620 s->regs[s->r_ce_ctrl] |= (1 << (CTRL_EXTENDED0));
621 }
622
623 /* HW strapping for AST2400 FMC controllers (SCU70). Let's use the
624 * configuration of the palmetto-bmc machine */
625 if (s->ctrl->segments == aspeed_segments_fmc) {
626 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
627
628 s->regs[s->r_ce_ctrl] |= (1 << (CTRL_EXTENDED0));
629 }
630 }
631
632 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
633 {
634 AspeedSMCState *s = ASPEED_SMC(opaque);
635
636 addr >>= 2;
637
638 if (addr == s->r_conf ||
639 addr == s->r_timings ||
640 addr == s->r_ce_ctrl ||
641 addr == R_INTR_CTRL ||
642 (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
643 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) {
644 return s->regs[addr];
645 } else {
646 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
647 __func__, addr);
648 return 0;
649 }
650 }
651
652 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
653 unsigned int size)
654 {
655 AspeedSMCState *s = ASPEED_SMC(opaque);
656 uint32_t value = data;
657
658 addr >>= 2;
659
660 if (addr == s->r_conf ||
661 addr == s->r_timings ||
662 addr == s->r_ce_ctrl) {
663 s->regs[addr] = value;
664 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
665 int cs = addr - s->r_ctrl0;
666 s->regs[addr] = value;
667 aspeed_smc_flash_update_cs(&s->flashes[cs]);
668 } else if (addr >= R_SEG_ADDR0 &&
669 addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
670 int cs = addr - R_SEG_ADDR0;
671
672 if (value != s->regs[R_SEG_ADDR0 + cs]) {
673 aspeed_smc_flash_set_segment(s, cs, value);
674 }
675 } else {
676 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
677 __func__, addr);
678 return;
679 }
680 }
681
682 static const MemoryRegionOps aspeed_smc_ops = {
683 .read = aspeed_smc_read,
684 .write = aspeed_smc_write,
685 .endianness = DEVICE_LITTLE_ENDIAN,
686 .valid.unaligned = true,
687 };
688
689 static void aspeed_smc_realize(DeviceState *dev, Error **errp)
690 {
691 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
692 AspeedSMCState *s = ASPEED_SMC(dev);
693 AspeedSMCClass *mc = ASPEED_SMC_GET_CLASS(s);
694 int i;
695 char name[32];
696 hwaddr offset = 0;
697
698 s->ctrl = mc->ctrl;
699
700 /* keep a copy under AspeedSMCState to speed up accesses */
701 s->r_conf = s->ctrl->r_conf;
702 s->r_ce_ctrl = s->ctrl->r_ce_ctrl;
703 s->r_ctrl0 = s->ctrl->r_ctrl0;
704 s->r_timings = s->ctrl->r_timings;
705 s->conf_enable_w0 = s->ctrl->conf_enable_w0;
706
707 /* Enforce some real HW limits */
708 if (s->num_cs > s->ctrl->max_slaves) {
709 qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
710 __func__, s->ctrl->max_slaves);
711 s->num_cs = s->ctrl->max_slaves;
712 }
713
714 s->spi = ssi_create_bus(dev, "spi");
715
716 /* Setup cs_lines for slaves */
717 sysbus_init_irq(sbd, &s->irq);
718 s->cs_lines = g_new0(qemu_irq, s->num_cs);
719 ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
720
721 for (i = 0; i < s->num_cs; ++i) {
722 sysbus_init_irq(sbd, &s->cs_lines[i]);
723 }
724
725 /* The memory region for the controller registers */
726 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
727 s->ctrl->name, s->ctrl->nregs * 4);
728 sysbus_init_mmio(sbd, &s->mmio);
729
730 /*
731 * The container memory region representing the address space
732 * window in which the flash modules are mapped. The size and
733 * address depends on the SoC model and controller type.
734 */
735 snprintf(name, sizeof(name), "%s.flash", s->ctrl->name);
736
737 memory_region_init_io(&s->mmio_flash, OBJECT(s),
738 &aspeed_smc_flash_default_ops, s, name,
739 s->ctrl->flash_window_size);
740 sysbus_init_mmio(sbd, &s->mmio_flash);
741
742 s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves);
743
744 /*
745 * Let's create a sub memory region for each possible slave. All
746 * have a configurable memory segment in the overall flash mapping
747 * window of the controller but, there is not necessarily a flash
748 * module behind to handle the memory accesses. This depends on
749 * the board configuration.
750 */
751 for (i = 0; i < s->ctrl->max_slaves; ++i) {
752 AspeedSMCFlash *fl = &s->flashes[i];
753
754 snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);
755
756 fl->id = i;
757 fl->controller = s;
758 fl->size = s->ctrl->segments[i].size;
759 memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_ops,
760 fl, name, fl->size);
761 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
762 offset += fl->size;
763 }
764 }
765
766 static const VMStateDescription vmstate_aspeed_smc = {
767 .name = "aspeed.smc",
768 .version_id = 1,
769 .minimum_version_id = 1,
770 .fields = (VMStateField[]) {
771 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
772 VMSTATE_END_OF_LIST()
773 }
774 };
775
776 static Property aspeed_smc_properties[] = {
777 DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
778 DEFINE_PROP_END_OF_LIST(),
779 };
780
781 static void aspeed_smc_class_init(ObjectClass *klass, void *data)
782 {
783 DeviceClass *dc = DEVICE_CLASS(klass);
784 AspeedSMCClass *mc = ASPEED_SMC_CLASS(klass);
785
786 dc->realize = aspeed_smc_realize;
787 dc->reset = aspeed_smc_reset;
788 dc->props = aspeed_smc_properties;
789 dc->vmsd = &vmstate_aspeed_smc;
790 mc->ctrl = data;
791 }
792
793 static const TypeInfo aspeed_smc_info = {
794 .name = TYPE_ASPEED_SMC,
795 .parent = TYPE_SYS_BUS_DEVICE,
796 .instance_size = sizeof(AspeedSMCState),
797 .class_size = sizeof(AspeedSMCClass),
798 .abstract = true,
799 };
800
801 static void aspeed_smc_register_types(void)
802 {
803 int i;
804
805 type_register_static(&aspeed_smc_info);
806 for (i = 0; i < ARRAY_SIZE(controllers); ++i) {
807 TypeInfo ti = {
808 .name = controllers[i].name,
809 .parent = TYPE_ASPEED_SMC,
810 .class_init = aspeed_smc_class_init,
811 .class_data = (void *)&controllers[i],
812 };
813 type_register(&ti);
814 }
815 }
816
817 type_init(aspeed_smc_register_types)
AR7 emulation for QEMU