include/hw/misc/mips_cmgcr.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2015 Imagination Technologies
   7  *
   8  */
   9
  10 #ifndef MIPS_CMGCR_H
  11 #define MIPS_CMGCR_H
  12
  13 #define TYPE_MIPS_GCR "mips-gcr"
  14 #define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
  15
  16 #define GCR_BASE_ADDR           0x1fbf8000ULL
  17 #define GCR_ADDRSPACE_SZ        0x8000
  18
  19 /* Offsets to register blocks */
  20 #define MIPS_GCB_OFS        0x0000 /* Global Control Block */
  21 #define MIPS_CLCB_OFS       0x2000 /* Core Local Control Block */
  22 #define MIPS_COCB_OFS       0x4000 /* Core Other Control Block */
  23 #define MIPS_GDB_OFS        0x6000 /* Global Debug Block */
  24
  25 /* Global Control Block Register Map */
  26 #define GCR_CONFIG_OFS      0x0000
  27 #define GCR_BASE_OFS        0x0008
  28 #define GCR_REV_OFS         0x0030
  29 #define GCR_GIC_BASE_OFS    0x0080
  30 #define GCR_CPC_BASE_OFS    0x0088
  31 #define GCR_GIC_STATUS_OFS  0x00D0
  32 #define GCR_CPC_STATUS_OFS  0x00F0
  33 #define GCR_L2_CONFIG_OFS   0x0130
  34
  35 /* Core Local and Core Other Block Register Map */
  36 #define GCR_CL_CONFIG_OFS   0x0010
  37 #define GCR_CL_OTHER_OFS    0x0018
  38 #define GCR_CL_RESETBASE_OFS 0x0020
  39
  40 /* GCR_L2_CONFIG register fields */
  41 #define GCR_L2_CONFIG_BYPASS_SHF    20
  42 #define GCR_L2_CONFIG_BYPASS_MSK    ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
  43
  44 /* GCR_GIC_BASE register fields */
  45 #define GCR_GIC_BASE_GICEN_MSK   1
  46 #define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
  47 #define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK)
  48
  49 /* GCR_CPC_BASE register fields */
  50 #define GCR_CPC_BASE_CPCEN_MSK   1
  51 #define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
  52 #define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
  53
  54 /* GCR_CL_OTHER_OFS register fields */
  55 #define GCR_CL_OTHER_VPOTHER_MSK 0x7
  56 #define GCR_CL_OTHER_MSK GCR_CL_OTHER_VPOTHER_MSK
  57
  58 /* GCR_CL_RESETBASE_OFS register fields */
  59 #define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFF000U
  60 #define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK
  61
  62 typedef struct MIPSGCRVPState MIPSGCRVPState;
  63 struct MIPSGCRVPState {
  64     uint32_t other;
  65     uint64_t reset_base;
  66 };
  67
  68 typedef struct MIPSGCRState MIPSGCRState;
  69 struct MIPSGCRState {
  70     SysBusDevice parent_obj;
  71
  72     int32_t gcr_rev;
  73     int32_t num_vps;
  74     hwaddr gcr_base;
  75     MemoryRegion iomem;
  76     MemoryRegion *cpc_mr;
  77     MemoryRegion *gic_mr;
  78
  79     uint64_t cpc_base;
  80     uint64_t gic_base;
  81
  82     /* VP Local/Other Registers */
  83     MIPSGCRVPState *vps;
  84 };
  85
  86 #endif /* MIPS_CMGCR_H */