2 * ARM VFP floating-point operations
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
26 #include "fpu/softfloat.h"
29 /* VFP support. We follow the convention used for VFP instructions:
30 Single precision routines have a "s" suffix, double precision a
35 /* Convert host exception flags to vfp form. */
36 static inline int vfp_exceptbits_from_host(int host_bits
)
40 if (host_bits
& float_flag_invalid
) {
43 if (host_bits
& float_flag_divbyzero
) {
46 if (host_bits
& float_flag_overflow
) {
49 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
)) {
52 if (host_bits
& float_flag_inexact
) {
55 if (host_bits
& float_flag_input_denormal
) {
61 /* Convert vfp exception flags to target form. */
62 static inline int vfp_exceptbits_to_host(int target_bits
)
66 if (target_bits
& 1) {
67 host_bits
|= float_flag_invalid
;
69 if (target_bits
& 2) {
70 host_bits
|= float_flag_divbyzero
;
72 if (target_bits
& 4) {
73 host_bits
|= float_flag_overflow
;
75 if (target_bits
& 8) {
76 host_bits
|= float_flag_underflow
;
78 if (target_bits
& 0x10) {
79 host_bits
|= float_flag_inexact
;
81 if (target_bits
& 0x80) {
82 host_bits
|= float_flag_input_denormal
;
87 static uint32_t vfp_get_fpscr_from_host(CPUARMState
*env
)
91 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
92 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
93 /* FZ16 does not generate an input denormal exception. */
94 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
95 & ~float_flag_input_denormal
);
96 i
|= (get_float_exception_flags(&env
->vfp
.standard_fp_status_f16
)
97 & ~float_flag_input_denormal
);
98 return vfp_exceptbits_from_host(i
);
101 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
104 uint32_t changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
107 if (changed
& (3 << 22)) {
110 case FPROUNDING_TIEEVEN
:
111 i
= float_round_nearest_even
;
113 case FPROUNDING_POSINF
:
116 case FPROUNDING_NEGINF
:
117 i
= float_round_down
;
119 case FPROUNDING_ZERO
:
120 i
= float_round_to_zero
;
123 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
124 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
126 if (changed
& FPCR_FZ16
) {
127 bool ftz_enabled
= val
& FPCR_FZ16
;
128 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
129 set_flush_to_zero(ftz_enabled
, &env
->vfp
.standard_fp_status_f16
);
130 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
131 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.standard_fp_status_f16
);
133 if (changed
& FPCR_FZ
) {
134 bool ftz_enabled
= val
& FPCR_FZ
;
135 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
136 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
138 if (changed
& FPCR_DN
) {
139 bool dnan_enabled
= val
& FPCR_DN
;
140 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
141 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
145 * The exception flags are ORed together when we read fpscr so we
146 * only need to preserve the current state in one of our
147 * float_status values.
149 i
= vfp_exceptbits_to_host(val
);
150 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
151 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
152 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
153 set_float_exception_flags(0, &env
->vfp
.standard_fp_status_f16
);
158 static uint32_t vfp_get_fpscr_from_host(CPUARMState
*env
)
163 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
169 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
173 fpscr
= env
->vfp
.xregs
[ARM_VFP_FPSCR
]
174 | (env
->vfp
.vec_len
<< 16)
175 | (env
->vfp
.vec_stride
<< 20);
177 fpscr
|= vfp_get_fpscr_from_host(env
);
179 i
= env
->vfp
.qc
[0] | env
->vfp
.qc
[1] | env
->vfp
.qc
[2] | env
->vfp
.qc
[3];
180 fpscr
|= i
? FPCR_QC
: 0;
185 uint32_t vfp_get_fpscr(CPUARMState
*env
)
187 return HELPER(vfp_get_fpscr
)(env
);
190 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
192 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
193 if (!cpu_isar_feature(any_fp16
, env_archcpu(env
))) {
197 if (arm_feature(env
, ARM_FEATURE_M
)) {
199 * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
200 * and also for the trapped-exception-handling bits IxE.
205 vfp_set_fpscr_to_host(env
, val
);
208 * We don't implement trapped exception handling, so the
209 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
211 * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
212 * (which are stored in fp_status), and the other RES0 bits
213 * in between, then we clear all of the low 16 bits.
215 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = val
& 0xf7c80000;
216 env
->vfp
.vec_len
= (val
>> 16) & 7;
217 env
->vfp
.vec_stride
= (val
>> 20) & 3;
220 * The bit we set within fpscr_q is arbitrary; the register as a
221 * whole being zero/non-zero is what counts.
223 env
->vfp
.qc
[0] = val
& FPCR_QC
;
229 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
231 HELPER(vfp_set_fpscr
)(env
, val
);
236 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
238 #define VFP_BINOP(name) \
239 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
241 float_status *fpst = fpstp; \
242 return float32_ ## name(a, b, fpst); \
244 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
246 float_status *fpst = fpstp; \
247 return float64_ ## name(a, b, fpst); \
259 float32
VFP_HELPER(neg
, s
)(float32 a
)
261 return float32_chs(a
);
264 float64
VFP_HELPER(neg
, d
)(float64 a
)
266 return float64_chs(a
);
269 float32
VFP_HELPER(abs
, s
)(float32 a
)
271 return float32_abs(a
);
274 float64
VFP_HELPER(abs
, d
)(float64 a
)
276 return float64_abs(a
);
279 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
281 return float32_sqrt(a
, &env
->vfp
.fp_status
);
284 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
286 return float64_sqrt(a
, &env
->vfp
.fp_status
);
289 static void softfloat_to_vfp_compare(CPUARMState
*env
, FloatRelation cmp
)
293 case float_relation_equal
:
296 case float_relation_less
:
299 case float_relation_greater
:
302 case float_relation_unordered
:
306 g_assert_not_reached();
308 env
->vfp
.xregs
[ARM_VFP_FPSCR
] =
309 deposit32(env
->vfp
.xregs
[ARM_VFP_FPSCR
], 28, 4, flags
);
312 /* XXX: check quiet/signaling case */
313 #define DO_VFP_cmp(p, type) \
314 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
316 softfloat_to_vfp_compare(env, \
317 type ## _compare_quiet(a, b, &env->vfp.fp_status)); \
319 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
321 softfloat_to_vfp_compare(env, \
322 type ## _compare(a, b, &env->vfp.fp_status)); \
324 DO_VFP_cmp(s
, float32
)
325 DO_VFP_cmp(d
, float64
)
328 /* Integer to float and float to integer conversions */
330 #define CONV_ITOF(name, ftype, fsz, sign) \
331 ftype HELPER(name)(uint32_t x, void *fpstp) \
333 float_status *fpst = fpstp; \
334 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
337 #define CONV_FTOI(name, ftype, fsz, sign, round) \
338 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
340 float_status *fpst = fpstp; \
341 if (float##fsz##_is_any_nan(x)) { \
342 float_raise(float_flag_invalid, fpst); \
345 return float##fsz##_to_##sign##int32##round(x, fpst); \
348 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
349 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
350 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
351 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
353 FLOAT_CONVS(si
, h
, uint32_t, 16, )
354 FLOAT_CONVS(si
, s
, float32
, 32, )
355 FLOAT_CONVS(si
, d
, float64
, 64, )
356 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
357 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
358 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
364 /* floating point conversion */
365 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
367 return float32_to_float64(x
, &env
->vfp
.fp_status
);
370 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
372 return float64_to_float32(x
, &env
->vfp
.fp_status
);
375 /* VFP3 fixed point conversion. */
376 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
377 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
379 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
381 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
382 uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
385 if (unlikely(float##fsz##_is_any_nan(x))) { \
386 float_raise(float_flag_invalid, fpst); \
389 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
392 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
393 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
394 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
395 float_round_to_zero, _round_to_zero) \
396 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
397 get_float_rounding_mode(fpst), )
399 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
400 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
401 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
402 get_float_rounding_mode(fpst), )
404 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
405 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
406 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
407 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
408 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
409 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
410 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
411 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
412 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
413 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
414 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
415 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
418 #undef VFP_CONV_FIX_FLOAT
419 #undef VFP_CONV_FLOAT_FIX_ROUND
420 #undef VFP_CONV_FIX_A64
422 uint32_t HELPER(vfp_sltoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
424 return int32_to_float16_scalbn(x
, -shift
, fpst
);
427 uint32_t HELPER(vfp_ultoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
429 return uint32_to_float16_scalbn(x
, -shift
, fpst
);
432 uint32_t HELPER(vfp_sqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
434 return int64_to_float16_scalbn(x
, -shift
, fpst
);
437 uint32_t HELPER(vfp_uqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
439 return uint64_to_float16_scalbn(x
, -shift
, fpst
);
442 uint32_t HELPER(vfp_toshh
)(uint32_t x
, uint32_t shift
, void *fpst
)
444 if (unlikely(float16_is_any_nan(x
))) {
445 float_raise(float_flag_invalid
, fpst
);
448 return float16_to_int16_scalbn(x
, get_float_rounding_mode(fpst
),
452 uint32_t HELPER(vfp_touhh
)(uint32_t x
, uint32_t shift
, void *fpst
)
454 if (unlikely(float16_is_any_nan(x
))) {
455 float_raise(float_flag_invalid
, fpst
);
458 return float16_to_uint16_scalbn(x
, get_float_rounding_mode(fpst
),
462 uint32_t HELPER(vfp_toslh
)(uint32_t x
, uint32_t shift
, void *fpst
)
464 if (unlikely(float16_is_any_nan(x
))) {
465 float_raise(float_flag_invalid
, fpst
);
468 return float16_to_int32_scalbn(x
, get_float_rounding_mode(fpst
),
472 uint32_t HELPER(vfp_toulh
)(uint32_t x
, uint32_t shift
, void *fpst
)
474 if (unlikely(float16_is_any_nan(x
))) {
475 float_raise(float_flag_invalid
, fpst
);
478 return float16_to_uint32_scalbn(x
, get_float_rounding_mode(fpst
),
482 uint64_t HELPER(vfp_tosqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
484 if (unlikely(float16_is_any_nan(x
))) {
485 float_raise(float_flag_invalid
, fpst
);
488 return float16_to_int64_scalbn(x
, get_float_rounding_mode(fpst
),
492 uint64_t HELPER(vfp_touqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
494 if (unlikely(float16_is_any_nan(x
))) {
495 float_raise(float_flag_invalid
, fpst
);
498 return float16_to_uint64_scalbn(x
, get_float_rounding_mode(fpst
),
502 /* Set the current fp rounding mode and return the old one.
503 * The argument is a softfloat float_round_ value.
505 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
507 float_status
*fp_status
= fpstp
;
509 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
510 set_float_rounding_mode(rmode
, fp_status
);
515 /* Set the current fp rounding mode in the standard fp status and return
516 * the old one. This is for NEON instructions that need to change the
517 * rounding mode but wish to use the standard FPSCR values for everything
518 * else. Always set the rounding mode back to the correct value after
520 * The argument is a softfloat float_round_ value.
522 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
524 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
526 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
527 set_float_rounding_mode(rmode
, fp_status
);
532 /* Half precision conversions. */
533 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
535 /* Squash FZ16 to 0 for the duration of conversion. In this case,
536 * it would affect flushing input denormals.
538 float_status
*fpst
= fpstp
;
539 bool save
= get_flush_inputs_to_zero(fpst
);
540 set_flush_inputs_to_zero(false, fpst
);
541 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
542 set_flush_inputs_to_zero(save
, fpst
);
546 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
548 /* Squash FZ16 to 0 for the duration of conversion. In this case,
549 * it would affect flushing output denormals.
551 float_status
*fpst
= fpstp
;
552 bool save
= get_flush_to_zero(fpst
);
553 set_flush_to_zero(false, fpst
);
554 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
555 set_flush_to_zero(save
, fpst
);
559 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
561 /* Squash FZ16 to 0 for the duration of conversion. In this case,
562 * it would affect flushing input denormals.
564 float_status
*fpst
= fpstp
;
565 bool save
= get_flush_inputs_to_zero(fpst
);
566 set_flush_inputs_to_zero(false, fpst
);
567 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
568 set_flush_inputs_to_zero(save
, fpst
);
572 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
574 /* Squash FZ16 to 0 for the duration of conversion. In this case,
575 * it would affect flushing output denormals.
577 float_status
*fpst
= fpstp
;
578 bool save
= get_flush_to_zero(fpst
);
579 set_flush_to_zero(false, fpst
);
580 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
581 set_flush_to_zero(save
, fpst
);
585 #define float32_two make_float32(0x40000000)
586 #define float32_three make_float32(0x40400000)
587 #define float32_one_point_five make_float32(0x3fc00000)
589 float32
HELPER(recps_f32
)(CPUARMState
*env
, float32 a
, float32 b
)
591 float_status
*s
= &env
->vfp
.standard_fp_status
;
592 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
593 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
594 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
595 float_raise(float_flag_input_denormal
, s
);
599 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
602 float32
HELPER(rsqrts_f32
)(CPUARMState
*env
, float32 a
, float32 b
)
604 float_status
*s
= &env
->vfp
.standard_fp_status
;
606 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
607 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
608 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
609 float_raise(float_flag_input_denormal
, s
);
611 return float32_one_point_five
;
613 product
= float32_mul(a
, b
, s
);
614 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
619 /* Constants 256 and 512 are used in some helpers; we avoid relying on
620 * int->float conversions at run-time. */
621 #define float64_256 make_float64(0x4070000000000000LL)
622 #define float64_512 make_float64(0x4080000000000000LL)
623 #define float16_maxnorm make_float16(0x7bff)
624 #define float32_maxnorm make_float32(0x7f7fffff)
625 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
627 /* Reciprocal functions
629 * The algorithm that must be used to calculate the estimate
630 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
633 /* See RecipEstimate()
635 * input is a 9 bit fixed point number
636 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
637 * result range 256 .. 511 for a number from 1.0 to 511/256.
640 static int recip_estimate(int input
)
643 assert(256 <= input
&& input
< 512);
647 assert(256 <= r
&& r
< 512);
652 * Common wrapper to call recip_estimate
654 * The parameters are exponent and 64 bit fraction (without implicit
655 * bit) where the binary point is nominally at bit 52. Returns a
656 * float64 which can then be rounded to the appropriate size by the
660 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
662 uint32_t scaled
, estimate
;
663 uint64_t result_frac
;
666 /* Handle sub-normals */
668 if (extract64(frac
, 51, 1) == 0) {
676 /* scaled = UInt('1':fraction<51:44>) */
677 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
678 estimate
= recip_estimate(scaled
);
680 result_exp
= exp_off
- *exp
;
681 result_frac
= deposit64(0, 44, 8, estimate
);
682 if (result_exp
== 0) {
683 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
684 } else if (result_exp
== -1) {
685 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
694 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
696 switch (fpst
->float_rounding_mode
) {
697 case float_round_nearest_even
: /* Round to Nearest */
699 case float_round_up
: /* Round to +Inf */
701 case float_round_down
: /* Round to -Inf */
703 case float_round_to_zero
: /* Round to Zero */
706 g_assert_not_reached();
710 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
712 float_status
*fpst
= fpstp
;
713 float16 f16
= float16_squash_input_denormal(input
, fpst
);
714 uint32_t f16_val
= float16_val(f16
);
715 uint32_t f16_sign
= float16_is_neg(f16
);
716 int f16_exp
= extract32(f16_val
, 10, 5);
717 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
720 if (float16_is_any_nan(f16
)) {
722 if (float16_is_signaling_nan(f16
, fpst
)) {
723 float_raise(float_flag_invalid
, fpst
);
724 nan
= float16_silence_nan(f16
, fpst
);
726 if (fpst
->default_nan_mode
) {
727 nan
= float16_default_nan(fpst
);
730 } else if (float16_is_infinity(f16
)) {
731 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
732 } else if (float16_is_zero(f16
)) {
733 float_raise(float_flag_divbyzero
, fpst
);
734 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
735 } else if (float16_abs(f16
) < (1 << 8)) {
736 /* Abs(value) < 2.0^-16 */
737 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
738 if (round_to_inf(fpst
, f16_sign
)) {
739 return float16_set_sign(float16_infinity
, f16_sign
);
741 return float16_set_sign(float16_maxnorm
, f16_sign
);
743 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
744 float_raise(float_flag_underflow
, fpst
);
745 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
748 f64_frac
= call_recip_estimate(&f16_exp
, 29,
749 ((uint64_t) f16_frac
) << (52 - 10));
751 /* result = sign : result_exp<4:0> : fraction<51:42> */
752 f16_val
= deposit32(0, 15, 1, f16_sign
);
753 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
754 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
755 return make_float16(f16_val
);
758 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
760 float_status
*fpst
= fpstp
;
761 float32 f32
= float32_squash_input_denormal(input
, fpst
);
762 uint32_t f32_val
= float32_val(f32
);
763 bool f32_sign
= float32_is_neg(f32
);
764 int f32_exp
= extract32(f32_val
, 23, 8);
765 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
768 if (float32_is_any_nan(f32
)) {
770 if (float32_is_signaling_nan(f32
, fpst
)) {
771 float_raise(float_flag_invalid
, fpst
);
772 nan
= float32_silence_nan(f32
, fpst
);
774 if (fpst
->default_nan_mode
) {
775 nan
= float32_default_nan(fpst
);
778 } else if (float32_is_infinity(f32
)) {
779 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
780 } else if (float32_is_zero(f32
)) {
781 float_raise(float_flag_divbyzero
, fpst
);
782 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
783 } else if (float32_abs(f32
) < (1ULL << 21)) {
784 /* Abs(value) < 2.0^-128 */
785 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
786 if (round_to_inf(fpst
, f32_sign
)) {
787 return float32_set_sign(float32_infinity
, f32_sign
);
789 return float32_set_sign(float32_maxnorm
, f32_sign
);
791 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
792 float_raise(float_flag_underflow
, fpst
);
793 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
796 f64_frac
= call_recip_estimate(&f32_exp
, 253,
797 ((uint64_t) f32_frac
) << (52 - 23));
799 /* result = sign : result_exp<7:0> : fraction<51:29> */
800 f32_val
= deposit32(0, 31, 1, f32_sign
);
801 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
802 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
803 return make_float32(f32_val
);
806 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
808 float_status
*fpst
= fpstp
;
809 float64 f64
= float64_squash_input_denormal(input
, fpst
);
810 uint64_t f64_val
= float64_val(f64
);
811 bool f64_sign
= float64_is_neg(f64
);
812 int f64_exp
= extract64(f64_val
, 52, 11);
813 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
815 /* Deal with any special cases */
816 if (float64_is_any_nan(f64
)) {
818 if (float64_is_signaling_nan(f64
, fpst
)) {
819 float_raise(float_flag_invalid
, fpst
);
820 nan
= float64_silence_nan(f64
, fpst
);
822 if (fpst
->default_nan_mode
) {
823 nan
= float64_default_nan(fpst
);
826 } else if (float64_is_infinity(f64
)) {
827 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
828 } else if (float64_is_zero(f64
)) {
829 float_raise(float_flag_divbyzero
, fpst
);
830 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
831 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
832 /* Abs(value) < 2.0^-1024 */
833 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
834 if (round_to_inf(fpst
, f64_sign
)) {
835 return float64_set_sign(float64_infinity
, f64_sign
);
837 return float64_set_sign(float64_maxnorm
, f64_sign
);
839 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
840 float_raise(float_flag_underflow
, fpst
);
841 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
844 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
846 /* result = sign : result_exp<10:0> : fraction<51:0>; */
847 f64_val
= deposit64(0, 63, 1, f64_sign
);
848 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
849 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
850 return make_float64(f64_val
);
853 /* The algorithm that must be used to calculate the estimate
854 * is specified by the ARM ARM.
857 static int do_recip_sqrt_estimate(int a
)
861 assert(128 <= a
&& a
< 512);
869 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
872 estimate
= (b
+ 1) / 2;
873 assert(256 <= estimate
&& estimate
< 512);
879 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
885 while (extract64(frac
, 51, 1) == 0) {
889 frac
= extract64(frac
, 0, 51) << 1;
893 /* scaled = UInt('01':fraction<51:45>) */
894 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
896 /* scaled = UInt('1':fraction<51:44>) */
897 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
899 estimate
= do_recip_sqrt_estimate(scaled
);
901 *exp
= (exp_off
- *exp
) / 2;
902 return extract64(estimate
, 0, 8) << 44;
905 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
907 float_status
*s
= fpstp
;
908 float16 f16
= float16_squash_input_denormal(input
, s
);
909 uint16_t val
= float16_val(f16
);
910 bool f16_sign
= float16_is_neg(f16
);
911 int f16_exp
= extract32(val
, 10, 5);
912 uint16_t f16_frac
= extract32(val
, 0, 10);
915 if (float16_is_any_nan(f16
)) {
917 if (float16_is_signaling_nan(f16
, s
)) {
918 float_raise(float_flag_invalid
, s
);
919 nan
= float16_silence_nan(f16
, s
);
921 if (s
->default_nan_mode
) {
922 nan
= float16_default_nan(s
);
925 } else if (float16_is_zero(f16
)) {
926 float_raise(float_flag_divbyzero
, s
);
927 return float16_set_sign(float16_infinity
, f16_sign
);
928 } else if (f16_sign
) {
929 float_raise(float_flag_invalid
, s
);
930 return float16_default_nan(s
);
931 } else if (float16_is_infinity(f16
)) {
935 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
936 * preserving the parity of the exponent. */
938 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
940 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
942 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
943 val
= deposit32(0, 15, 1, f16_sign
);
944 val
= deposit32(val
, 10, 5, f16_exp
);
945 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
946 return make_float16(val
);
949 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
951 float_status
*s
= fpstp
;
952 float32 f32
= float32_squash_input_denormal(input
, s
);
953 uint32_t val
= float32_val(f32
);
954 uint32_t f32_sign
= float32_is_neg(f32
);
955 int f32_exp
= extract32(val
, 23, 8);
956 uint32_t f32_frac
= extract32(val
, 0, 23);
959 if (float32_is_any_nan(f32
)) {
961 if (float32_is_signaling_nan(f32
, s
)) {
962 float_raise(float_flag_invalid
, s
);
963 nan
= float32_silence_nan(f32
, s
);
965 if (s
->default_nan_mode
) {
966 nan
= float32_default_nan(s
);
969 } else if (float32_is_zero(f32
)) {
970 float_raise(float_flag_divbyzero
, s
);
971 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
972 } else if (float32_is_neg(f32
)) {
973 float_raise(float_flag_invalid
, s
);
974 return float32_default_nan(s
);
975 } else if (float32_is_infinity(f32
)) {
979 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
980 * preserving the parity of the exponent. */
982 f64_frac
= ((uint64_t) f32_frac
) << 29;
984 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
986 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
987 val
= deposit32(0, 31, 1, f32_sign
);
988 val
= deposit32(val
, 23, 8, f32_exp
);
989 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
990 return make_float32(val
);
993 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
995 float_status
*s
= fpstp
;
996 float64 f64
= float64_squash_input_denormal(input
, s
);
997 uint64_t val
= float64_val(f64
);
998 bool f64_sign
= float64_is_neg(f64
);
999 int f64_exp
= extract64(val
, 52, 11);
1000 uint64_t f64_frac
= extract64(val
, 0, 52);
1002 if (float64_is_any_nan(f64
)) {
1004 if (float64_is_signaling_nan(f64
, s
)) {
1005 float_raise(float_flag_invalid
, s
);
1006 nan
= float64_silence_nan(f64
, s
);
1008 if (s
->default_nan_mode
) {
1009 nan
= float64_default_nan(s
);
1012 } else if (float64_is_zero(f64
)) {
1013 float_raise(float_flag_divbyzero
, s
);
1014 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
1015 } else if (float64_is_neg(f64
)) {
1016 float_raise(float_flag_invalid
, s
);
1017 return float64_default_nan(s
);
1018 } else if (float64_is_infinity(f64
)) {
1019 return float64_zero
;
1022 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
1024 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
1025 val
= deposit64(0, 61, 1, f64_sign
);
1026 val
= deposit64(val
, 52, 11, f64_exp
);
1027 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
1028 return make_float64(val
);
1031 uint32_t HELPER(recpe_u32
)(uint32_t a
)
1033 int input
, estimate
;
1035 if ((a
& 0x80000000) == 0) {
1039 input
= extract32(a
, 23, 9);
1040 estimate
= recip_estimate(input
);
1042 return deposit32(0, (32 - 9), 9, estimate
);
1045 uint32_t HELPER(rsqrte_u32
)(uint32_t a
)
1049 if ((a
& 0xc0000000) == 0) {
1053 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
1055 return deposit32(0, 23, 9, estimate
);
1058 /* VFPv4 fused multiply-accumulate */
1059 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
1061 float_status
*fpst
= fpstp
;
1062 return float32_muladd(a
, b
, c
, 0, fpst
);
1065 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
1067 float_status
*fpst
= fpstp
;
1068 return float64_muladd(a
, b
, c
, 0, fpst
);
1071 /* ARMv8 round to integral */
1072 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
1074 return float32_round_to_int(x
, fp_status
);
1077 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
1079 return float64_round_to_int(x
, fp_status
);
1082 float32
HELPER(rints
)(float32 x
, void *fp_status
)
1084 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1087 ret
= float32_round_to_int(x
, fp_status
);
1089 /* Suppress any inexact exceptions the conversion produced */
1090 if (!(old_flags
& float_flag_inexact
)) {
1091 new_flags
= get_float_exception_flags(fp_status
);
1092 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1098 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
1100 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1103 ret
= float64_round_to_int(x
, fp_status
);
1105 new_flags
= get_float_exception_flags(fp_status
);
1107 /* Suppress any inexact exceptions the conversion produced */
1108 if (!(old_flags
& float_flag_inexact
)) {
1109 new_flags
= get_float_exception_flags(fp_status
);
1110 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1116 /* Convert ARM rounding mode to softfloat */
1117 int arm_rmode_to_sf(int rmode
)
1120 case FPROUNDING_TIEAWAY
:
1121 rmode
= float_round_ties_away
;
1123 case FPROUNDING_ODD
:
1124 /* FIXME: add support for TIEAWAY and ODD */
1125 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
1127 /* fall through for now */
1128 case FPROUNDING_TIEEVEN
:
1130 rmode
= float_round_nearest_even
;
1132 case FPROUNDING_POSINF
:
1133 rmode
= float_round_up
;
1135 case FPROUNDING_NEGINF
:
1136 rmode
= float_round_down
;
1138 case FPROUNDING_ZERO
:
1139 rmode
= float_round_to_zero
;
1146 * Implement float64 to int32_t conversion without saturation;
1147 * the result is supplied modulo 2^32.
1149 uint64_t HELPER(fjcvtzs
)(float64 value
, void *vstatus
)
1151 float_status
*status
= vstatus
;
1154 uint32_t inexact
= 1; /* !Z */
1156 sign
= extract64(value
, 63, 1);
1157 exp
= extract64(value
, 52, 11);
1158 frac
= extract64(value
, 0, 52);
1161 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1164 if (status
->flush_inputs_to_zero
) {
1165 float_raise(float_flag_input_denormal
, status
);
1167 float_raise(float_flag_inexact
, status
);
1172 } else if (exp
== 0x7ff) {
1173 /* This operation raises Invalid for both NaN and overflow (Inf). */
1174 float_raise(float_flag_invalid
, status
);
1177 int true_exp
= exp
- 1023;
1178 int shift
= true_exp
- 52;
1180 /* Restore implicit bit. */
1183 /* Shift the fraction into place. */
1185 /* The number is so large we must shift the fraction left. */
1187 /* The fraction is shifted out entirely. */
1192 } else if (shift
> -64) {
1193 /* Normal case -- shift right and notice if bits shift out. */
1194 inexact
= (frac
<< (64 + shift
)) != 0;
1197 /* The fraction is shifted out entirely. */
1201 /* Notice overflow or inexact exceptions. */
1202 if (true_exp
> 31 || frac
> (sign
? 0x80000000ull
: 0x7fffffff)) {
1203 /* Overflow, for which this operation raises invalid. */
1204 float_raise(float_flag_invalid
, status
);
1206 } else if (inexact
) {
1207 float_raise(float_flag_inexact
, status
);
1210 /* Honor the sign. */
1216 /* Pack the result and the env->ZF representation of Z together. */
1217 return deposit64(frac
, 32, 32, inexact
);
1220 uint32_t HELPER(vjcvt
)(float64 value
, CPUARMState
*env
)
1222 uint64_t pair
= HELPER(fjcvtzs
)(value
, &env
->vfp
.fp_status
);
1223 uint32_t result
= pair
;
1224 uint32_t z
= (pair
>> 32) == 0;
1226 /* Store Z, clear NCV, in FPSCR.NZCV. */
1227 env
->vfp
.xregs
[ARM_VFP_FPSCR
]
1228 = (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & ~CPSR_NZCV
) | (z
* CPSR_Z
);
1233 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1234 static float32
frint_s(float32 f
, float_status
*fpst
, int intsize
)
1236 int old_flags
= get_float_exception_flags(fpst
);
1237 uint32_t exp
= extract32(f
, 23, 8);
1239 if (unlikely(exp
== 0xff)) {
1244 /* Round and re-extract the exponent. */
1245 f
= float32_round_to_int(f
, fpst
);
1246 exp
= extract32(f
, 23, 8);
1248 /* Validate the range of the result. */
1249 if (exp
< 126 + intsize
) {
1250 /* abs(F) <= INT{N}_MAX */
1253 if (exp
== 126 + intsize
) {
1254 uint32_t sign
= extract32(f
, 31, 1);
1255 uint32_t frac
= extract32(f
, 0, 23);
1256 if (sign
&& frac
== 0) {
1257 /* F == INT{N}_MIN */
1264 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1265 * inexact exception float32_round_to_int may have raised.
1267 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1268 return (0x100u
+ 126u + intsize
) << 23;
1271 float32
HELPER(frint32_s
)(float32 f
, void *fpst
)
1273 return frint_s(f
, fpst
, 32);
1276 float32
HELPER(frint64_s
)(float32 f
, void *fpst
)
1278 return frint_s(f
, fpst
, 64);
1281 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1282 static float64
frint_d(float64 f
, float_status
*fpst
, int intsize
)
1284 int old_flags
= get_float_exception_flags(fpst
);
1285 uint32_t exp
= extract64(f
, 52, 11);
1287 if (unlikely(exp
== 0x7ff)) {
1292 /* Round and re-extract the exponent. */
1293 f
= float64_round_to_int(f
, fpst
);
1294 exp
= extract64(f
, 52, 11);
1296 /* Validate the range of the result. */
1297 if (exp
< 1022 + intsize
) {
1298 /* abs(F) <= INT{N}_MAX */
1301 if (exp
== 1022 + intsize
) {
1302 uint64_t sign
= extract64(f
, 63, 1);
1303 uint64_t frac
= extract64(f
, 0, 52);
1304 if (sign
&& frac
== 0) {
1305 /* F == INT{N}_MIN */
1312 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1313 * inexact exception float64_round_to_int may have raised.
1315 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1316 return (uint64_t)(0x800 + 1022 + intsize
) << 52;
1319 float64
HELPER(frint32_d
)(float64 f
, void *fpst
)
1321 return frint_d(f
, fpst
, 32);
1324 float64
HELPER(frint64_d
)(float64 f
, void *fpst
)
1326 return frint_d(f
, fpst
, 64);
1329 void HELPER(check_hcr_el2_trap
)(CPUARMState
*env
, uint32_t rt
, uint32_t reg
)
1337 if (!(arm_hcr_el2_eff(env
) & HCR_TID3
)) {
1342 if (!(arm_hcr_el2_eff(env
) & HCR_TID0
)) {
1347 g_assert_not_reached();
1350 syndrome
= ((EC_FPIDTRAP
<< ARM_EL_EC_SHIFT
)
1352 | (1 << 24) | (0xe << 20) | (7 << 14)
1353 | (reg
<< 10) | (rt
<< 5) | 1);
1355 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);