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aspeed/smc: Add some tracing
[qemu/ar7.git] / hw / ssi / aspeed_smc.c
blobe5621bf728ca8f51d65ad28ed2b952546ec42d54
1 /*
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "migration/vmstate.h"
28 #include "qemu/log.h"
29 #include "qemu/module.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
32 #include "exec/address-spaces.h"
33 #include "qemu/units.h"
34 #include "trace.h"
35
36 #include "hw/irq.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ssi/aspeed_smc.h"
39
40 /* CE Type Setting Register */
41 #define R_CONF (0x00 / 4)
42 #define CONF_LEGACY_DISABLE (1 << 31)
43 #define CONF_ENABLE_W4 20
44 #define CONF_ENABLE_W3 19
45 #define CONF_ENABLE_W2 18
46 #define CONF_ENABLE_W1 17
47 #define CONF_ENABLE_W0 16
48 #define CONF_FLASH_TYPE4 8
49 #define CONF_FLASH_TYPE3 6
50 #define CONF_FLASH_TYPE2 4
51 #define CONF_FLASH_TYPE1 2
52 #define CONF_FLASH_TYPE0 0
53 #define CONF_FLASH_TYPE_NOR 0x0
54 #define CONF_FLASH_TYPE_NAND 0x1
55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
56
57 /* CE Control Register */
58 #define R_CE_CTRL (0x04 / 4)
59 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
60 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
61 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
62 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
64
65 /* Interrupt Control and Status Register */
66 #define R_INTR_CTRL (0x08 / 4)
67 #define INTR_CTRL_DMA_STATUS (1 << 11)
68 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
69 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
70 #define INTR_CTRL_DMA_EN (1 << 3)
71 #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
72 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
73
74 /* CEx Control Register */
75 #define R_CTRL0 (0x10 / 4)
76 #define CTRL_IO_QPI (1 << 31)
77 #define CTRL_IO_QUAD_DATA (1 << 30)
78 #define CTRL_IO_DUAL_DATA (1 << 29)
79 #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */
80 #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */
81 #define CTRL_CMD_SHIFT 16
82 #define CTRL_CMD_MASK 0xff
83 #define CTRL_DUMMY_HIGH_SHIFT 14
84 #define CTRL_AST2400_SPI_4BYTE (1 << 13)
85 #define CE_CTRL_CLOCK_FREQ_SHIFT 8
86 #define CE_CTRL_CLOCK_FREQ_MASK 0xf
87 #define CE_CTRL_CLOCK_FREQ(div) \
88 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
89 #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
90 #define CTRL_CE_STOP_ACTIVE (1 << 2)
91 #define CTRL_CMD_MODE_MASK 0x3
92 #define CTRL_READMODE 0x0
93 #define CTRL_FREADMODE 0x1
94 #define CTRL_WRITEMODE 0x2
95 #define CTRL_USERMODE 0x3
96 #define R_CTRL1 (0x14 / 4)
97 #define R_CTRL2 (0x18 / 4)
98 #define R_CTRL3 (0x1C / 4)
99 #define R_CTRL4 (0x20 / 4)
100
101 /* CEx Segment Address Register */
102 #define R_SEG_ADDR0 (0x30 / 4)
103 #define SEG_END_SHIFT 24 /* 8MB units */
104 #define SEG_END_MASK 0xff
105 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
106 #define SEG_START_MASK 0xff
107 #define R_SEG_ADDR1 (0x34 / 4)
108 #define R_SEG_ADDR2 (0x38 / 4)
109 #define R_SEG_ADDR3 (0x3C / 4)
110 #define R_SEG_ADDR4 (0x40 / 4)
111
112 /* Misc Control Register #1 */
113 #define R_MISC_CTRL1 (0x50 / 4)
114
115 /* SPI dummy cycle data */
116 #define R_DUMMY_DATA (0x54 / 4)
117
118 /* DMA Control/Status Register */
119 #define R_DMA_CTRL (0x80 / 4)
120 #define DMA_CTRL_DELAY_MASK 0xf
121 #define DMA_CTRL_DELAY_SHIFT 8
122 #define DMA_CTRL_FREQ_MASK 0xf
123 #define DMA_CTRL_FREQ_SHIFT 4
124 #define DMA_CTRL_CALIB (1 << 3)
125 #define DMA_CTRL_CKSUM (1 << 2)
126 #define DMA_CTRL_WRITE (1 << 1)
127 #define DMA_CTRL_ENABLE (1 << 0)
128
129 /* DMA Flash Side Address */
130 #define R_DMA_FLASH_ADDR (0x84 / 4)
131
132 /* DMA DRAM Side Address */
133 #define R_DMA_DRAM_ADDR (0x88 / 4)
134
135 /* DMA Length Register */
136 #define R_DMA_LEN (0x8C / 4)
137
138 /* Checksum Calculation Result */
139 #define R_DMA_CHECKSUM (0x90 / 4)
140
141 /* Read Timing Compensation Register */
142 #define R_TIMINGS (0x94 / 4)
143
144 /* SPI controller registers and bits (AST2400) */
145 #define R_SPI_CONF (0x00 / 4)
146 #define SPI_CONF_ENABLE_W0 0
147 #define R_SPI_CTRL0 (0x4 / 4)
148 #define R_SPI_MISC_CTRL (0x10 / 4)
149 #define R_SPI_TIMINGS (0x14 / 4)
150
151 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
152 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
153
154 #define ASPEED_SOC_SMC_FLASH_BASE 0x10000000
155 #define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
156 #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
157 #define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000
158
159 /*
160 * DMA DRAM addresses should be 4 bytes aligned and the valid address
161 * range is 0x40000000 - 0x5FFFFFFF (AST2400)
162 * 0x80000000 - 0xBFFFFFFF (AST2500)
163 *
164 * DMA flash addresses should be 4 bytes aligned and the valid address
165 * range is 0x20000000 - 0x2FFFFFFF.
166 *
167 * DMA length is from 4 bytes to 32MB
168 * 0: 4 bytes
169 * 0x7FFFFF: 32M bytes
170 */
171 #define DMA_DRAM_ADDR(s, val) ((s)->sdram_base | \
172 ((val) & (s)->ctrl->dma_dram_mask))
173 #define DMA_FLASH_ADDR(s, val) ((s)->ctrl->flash_window_base | \
174 ((val) & (s)->ctrl->dma_flash_mask))
175 #define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
176
177 /* Flash opcodes. */
178 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
179
180 #define SNOOP_OFF 0xFF
181 #define SNOOP_START 0x0
182
183 /*
184 * Default segments mapping addresses and size for each slave per
185 * controller. These can be changed when board is initialized with the
186 * Segment Address Registers.
187 */
188 static const AspeedSegments aspeed_segments_legacy[] = {
189 { 0x10000000, 32 * 1024 * 1024 },
190 };
191
192 static const AspeedSegments aspeed_segments_fmc[] = {
193 { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */
194 { 0x24000000, 32 * 1024 * 1024 },
195 { 0x26000000, 32 * 1024 * 1024 },
196 { 0x28000000, 32 * 1024 * 1024 },
197 { 0x2A000000, 32 * 1024 * 1024 }
198 };
199
200 static const AspeedSegments aspeed_segments_spi[] = {
201 { 0x30000000, 64 * 1024 * 1024 },
202 };
203
204 static const AspeedSegments aspeed_segments_ast2500_fmc[] = {
205 { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */
206 { 0x28000000, 32 * 1024 * 1024 },
207 { 0x2A000000, 32 * 1024 * 1024 },
208 };
209
210 static const AspeedSegments aspeed_segments_ast2500_spi1[] = {
211 { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */
212 { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */
213 };
214
215 static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
216 { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
217 { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
218 };
219 static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
220 const AspeedSegments *seg);
221 static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg,
222 AspeedSegments *seg);
223
224 /*
225 * AST2600 definitions
226 */
227 #define ASPEED26_SOC_FMC_FLASH_BASE 0x20000000
228 #define ASPEED26_SOC_SPI_FLASH_BASE 0x30000000
229 #define ASPEED26_SOC_SPI2_FLASH_BASE 0x50000000
230
231 static const AspeedSegments aspeed_segments_ast2600_fmc[] = {
232 { 0x0, 128 * MiB }, /* start address is readonly */
233 { 0x0, 0 }, /* disabled */
234 { 0x0, 0 }, /* disabled */
235 };
236
237 static const AspeedSegments aspeed_segments_ast2600_spi1[] = {
238 { 0x0, 128 * MiB }, /* start address is readonly */
239 { 0x0, 0 }, /* disabled */
240 };
241
242 static const AspeedSegments aspeed_segments_ast2600_spi2[] = {
243 { 0x0, 128 * MiB }, /* start address is readonly */
244 { 0x0, 0 }, /* disabled */
245 { 0x0, 0 }, /* disabled */
246 };
247
248 static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
249 const AspeedSegments *seg);
250 static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
251 uint32_t reg, AspeedSegments *seg);
252
253 static const AspeedSMCController controllers[] = {
254 {
255 .name = "aspeed.smc-ast2400",
256 .r_conf = R_CONF,
257 .r_ce_ctrl = R_CE_CTRL,
258 .r_ctrl0 = R_CTRL0,
259 .r_timings = R_TIMINGS,
260 .nregs_timings = 1,
261 .conf_enable_w0 = CONF_ENABLE_W0,
262 .max_slaves = 5,
263 .segments = aspeed_segments_legacy,
264 .flash_window_base = ASPEED_SOC_SMC_FLASH_BASE,
265 .flash_window_size = 0x6000000,
266 .has_dma = false,
267 .nregs = ASPEED_SMC_R_SMC_MAX,
268 .segment_to_reg = aspeed_smc_segment_to_reg,
269 .reg_to_segment = aspeed_smc_reg_to_segment,
270 }, {
271 .name = "aspeed.fmc-ast2400",
272 .r_conf = R_CONF,
273 .r_ce_ctrl = R_CE_CTRL,
274 .r_ctrl0 = R_CTRL0,
275 .r_timings = R_TIMINGS,
276 .nregs_timings = 1,
277 .conf_enable_w0 = CONF_ENABLE_W0,
278 .max_slaves = 5,
279 .segments = aspeed_segments_fmc,
280 .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
281 .flash_window_size = 0x10000000,
282 .has_dma = true,
283 .dma_flash_mask = 0x0FFFFFFC,
284 .dma_dram_mask = 0x1FFFFFFC,
285 .nregs = ASPEED_SMC_R_MAX,
286 .segment_to_reg = aspeed_smc_segment_to_reg,
287 .reg_to_segment = aspeed_smc_reg_to_segment,
288 }, {
289 .name = "aspeed.spi1-ast2400",
290 .r_conf = R_SPI_CONF,
291 .r_ce_ctrl = 0xff,
292 .r_ctrl0 = R_SPI_CTRL0,
293 .r_timings = R_SPI_TIMINGS,
294 .nregs_timings = 1,
295 .conf_enable_w0 = SPI_CONF_ENABLE_W0,
296 .max_slaves = 1,
297 .segments = aspeed_segments_spi,
298 .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
299 .flash_window_size = 0x10000000,
300 .has_dma = false,
301 .nregs = ASPEED_SMC_R_SPI_MAX,
302 .segment_to_reg = aspeed_smc_segment_to_reg,
303 .reg_to_segment = aspeed_smc_reg_to_segment,
304 }, {
305 .name = "aspeed.fmc-ast2500",
306 .r_conf = R_CONF,
307 .r_ce_ctrl = R_CE_CTRL,
308 .r_ctrl0 = R_CTRL0,
309 .r_timings = R_TIMINGS,
310 .nregs_timings = 1,
311 .conf_enable_w0 = CONF_ENABLE_W0,
312 .max_slaves = 3,
313 .segments = aspeed_segments_ast2500_fmc,
314 .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
315 .flash_window_size = 0x10000000,
316 .has_dma = true,
317 .dma_flash_mask = 0x0FFFFFFC,
318 .dma_dram_mask = 0x3FFFFFFC,
319 .nregs = ASPEED_SMC_R_MAX,
320 .segment_to_reg = aspeed_smc_segment_to_reg,
321 .reg_to_segment = aspeed_smc_reg_to_segment,
322 }, {
323 .name = "aspeed.spi1-ast2500",
324 .r_conf = R_CONF,
325 .r_ce_ctrl = R_CE_CTRL,
326 .r_ctrl0 = R_CTRL0,
327 .r_timings = R_TIMINGS,
328 .nregs_timings = 1,
329 .conf_enable_w0 = CONF_ENABLE_W0,
330 .max_slaves = 2,
331 .segments = aspeed_segments_ast2500_spi1,
332 .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
333 .flash_window_size = 0x8000000,
334 .has_dma = false,
335 .nregs = ASPEED_SMC_R_MAX,
336 .segment_to_reg = aspeed_smc_segment_to_reg,
337 .reg_to_segment = aspeed_smc_reg_to_segment,
338 }, {
339 .name = "aspeed.spi2-ast2500",
340 .r_conf = R_CONF,
341 .r_ce_ctrl = R_CE_CTRL,
342 .r_ctrl0 = R_CTRL0,
343 .r_timings = R_TIMINGS,
344 .nregs_timings = 1,
345 .conf_enable_w0 = CONF_ENABLE_W0,
346 .max_slaves = 2,
347 .segments = aspeed_segments_ast2500_spi2,
348 .flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE,
349 .flash_window_size = 0x8000000,
350 .has_dma = false,
351 .nregs = ASPEED_SMC_R_MAX,
352 .segment_to_reg = aspeed_smc_segment_to_reg,
353 .reg_to_segment = aspeed_smc_reg_to_segment,
354 }, {
355 .name = "aspeed.fmc-ast2600",
356 .r_conf = R_CONF,
357 .r_ce_ctrl = R_CE_CTRL,
358 .r_ctrl0 = R_CTRL0,
359 .r_timings = R_TIMINGS,
360 .nregs_timings = 1,
361 .conf_enable_w0 = CONF_ENABLE_W0,
362 .max_slaves = 3,
363 .segments = aspeed_segments_ast2600_fmc,
364 .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE,
365 .flash_window_size = 0x10000000,
366 .has_dma = true,
367 .nregs = ASPEED_SMC_R_MAX,
368 .segment_to_reg = aspeed_2600_smc_segment_to_reg,
369 .reg_to_segment = aspeed_2600_smc_reg_to_segment,
370 }, {
371 .name = "aspeed.spi1-ast2600",
372 .r_conf = R_CONF,
373 .r_ce_ctrl = R_CE_CTRL,
374 .r_ctrl0 = R_CTRL0,
375 .r_timings = R_TIMINGS,
376 .nregs_timings = 2,
377 .conf_enable_w0 = CONF_ENABLE_W0,
378 .max_slaves = 2,
379 .segments = aspeed_segments_ast2600_spi1,
380 .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE,
381 .flash_window_size = 0x10000000,
382 .has_dma = false,
383 .nregs = ASPEED_SMC_R_MAX,
384 .segment_to_reg = aspeed_2600_smc_segment_to_reg,
385 .reg_to_segment = aspeed_2600_smc_reg_to_segment,
386 }, {
387 .name = "aspeed.spi2-ast2600",
388 .r_conf = R_CONF,
389 .r_ce_ctrl = R_CE_CTRL,
390 .r_ctrl0 = R_CTRL0,
391 .r_timings = R_TIMINGS,
392 .nregs_timings = 3,
393 .conf_enable_w0 = CONF_ENABLE_W0,
394 .max_slaves = 3,
395 .segments = aspeed_segments_ast2600_spi2,
396 .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE,
397 .flash_window_size = 0x10000000,
398 .has_dma = false,
399 .nregs = ASPEED_SMC_R_MAX,
400 .segment_to_reg = aspeed_2600_smc_segment_to_reg,
401 .reg_to_segment = aspeed_2600_smc_reg_to_segment,
402 },
403 };
404
405 /*
406 * The Segment Registers of the AST2400 and AST2500 have a 8MB
407 * unit. The address range of a flash SPI slave is encoded with
408 * absolute addresses which should be part of the overall controller
409 * window.
410 */
411 static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
412 const AspeedSegments *seg)
413 {
414 uint32_t reg = 0;
415 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
416 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
417 return reg;
418 }
419
420 static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
421 uint32_t reg, AspeedSegments *seg)
422 {
423 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
424 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
425 }
426
427 /*
428 * The Segment Registers of the AST2600 have a 1MB unit. The address
429 * range of a flash SPI slave is encoded with offsets in the overall
430 * controller window. The previous SoC AST2400 and AST2500 used
431 * absolute addresses. Only bits [27:20] are relevant and the end
432 * address is an upper bound limit.
433 */
434 #define AST2600_SEG_ADDR_MASK 0x0ff00000
435
436 static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
437 const AspeedSegments *seg)
438 {
439 uint32_t reg = 0;
440
441 /* Disabled segments have a nil register */
442 if (!seg->size) {
443 return 0;
444 }
445
446 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */
447 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */
448 return reg;
449 }
450
451 static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
452 uint32_t reg, AspeedSegments *seg)
453 {
454 uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
455 uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK;
456
457 if (reg) {
458 seg->addr = s->ctrl->flash_window_base + start_offset;
459 seg->size = end_offset + MiB - start_offset;
460 } else {
461 seg->addr = s->ctrl->flash_window_base;
462 seg->size = 0;
463 }
464 }
465
466 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
467 const AspeedSegments *new,
468 int cs)
469 {
470 AspeedSegments seg;
471 int i;
472
473 for (i = 0; i < s->ctrl->max_slaves; i++) {
474 if (i == cs) {
475 continue;
476 }
477
478 s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg);
479
480 if (new->addr + new->size > seg.addr &&
481 new->addr < seg.addr + seg.size) {
482 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment CS%d [ 0x%"
483 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
484 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
485 s->ctrl->name, cs, new->addr, new->addr + new->size,
486 i, seg.addr, seg.addr + seg.size);
487 return true;
488 }
489 }
490 return false;
491 }
492
493 static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
494 uint64_t regval)
495 {
496 AspeedSMCFlash *fl = &s->flashes[cs];
497 AspeedSegments seg;
498
499 s->ctrl->reg_to_segment(s, regval, &seg);
500
501 memory_region_transaction_begin();
502 memory_region_set_size(&fl->mmio, seg.size);
503 memory_region_set_address(&fl->mmio, seg.addr - s->ctrl->flash_window_base);
504 memory_region_set_enabled(&fl->mmio, !!seg.size);
505 memory_region_transaction_commit();
506
507 s->regs[R_SEG_ADDR0 + cs] = regval;
508 }
509
510 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
511 uint64_t new)
512 {
513 AspeedSegments seg;
514
515 s->ctrl->reg_to_segment(s, new, &seg);
516
517 trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
518
519 /* The start address of CS0 is read-only */
520 if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
521 qemu_log_mask(LOG_GUEST_ERROR,
522 "%s: Tried to change CS0 start address to 0x%"
523 HWADDR_PRIx "\n", s->ctrl->name, seg.addr);
524 seg.addr = s->ctrl->flash_window_base;
525 new = s->ctrl->segment_to_reg(s, &seg);
526 }
527
528 /*
529 * The end address of the AST2500 spi controllers is also
530 * read-only.
531 */
532 if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 ||
533 s->ctrl->segments == aspeed_segments_ast2500_spi2) &&
534 cs == s->ctrl->max_slaves &&
535 seg.addr + seg.size != s->ctrl->segments[cs].addr +
536 s->ctrl->segments[cs].size) {
537 qemu_log_mask(LOG_GUEST_ERROR,
538 "%s: Tried to change CS%d end address to 0x%"
539 HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.size);
540 seg.size = s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size -
541 seg.addr;
542 new = s->ctrl->segment_to_reg(s, &seg);
543 }
544
545 /* Keep the segment in the overall flash window */
546 if (seg.size &&
547 (seg.addr + seg.size <= s->ctrl->flash_window_base ||
548 seg.addr > s->ctrl->flash_window_base + s->ctrl->flash_window_size)) {
549 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is invalid : "
550 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
551 s->ctrl->name, cs, seg.addr, seg.addr + seg.size);
552 return;
553 }
554
555 /* Check start address vs. alignment */
556 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
557 qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is not "
558 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
559 s->ctrl->name, cs, seg.addr, seg.addr + seg.size);
560 }
561
562 /* And segments should not overlap (in the specs) */
563 aspeed_smc_flash_overlap(s, &seg, cs);
564
565 /* All should be fine now to move the region */
566 aspeed_smc_flash_set_segment_region(s, cs, new);
567 }
568
569 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
570 unsigned size)
571 {
572 qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u"
573 PRIx64 "\n", __func__, addr, size);
574 return 0;
575 }
576
577 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
578 uint64_t data, unsigned size)
579 {
580 qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"
581 PRIx64 "\n", __func__, addr, size, data);
582 }
583
584 static const MemoryRegionOps aspeed_smc_flash_default_ops = {
585 .read = aspeed_smc_flash_default_read,
586 .write = aspeed_smc_flash_default_write,
587 .endianness = DEVICE_LITTLE_ENDIAN,
588 .valid = {
589 .min_access_size = 1,
590 .max_access_size = 4,
591 },
592 };
593
594 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
595 {
596 const AspeedSMCState *s = fl->controller;
597
598 return s->regs[s->r_ctrl0 + fl->id] & CTRL_CMD_MODE_MASK;
599 }
600
601 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
602 {
603 const AspeedSMCState *s = fl->controller;
604
605 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->id));
606 }
607
608 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
609 {
610 const AspeedSMCState *s = fl->controller;
611 int cmd = (s->regs[s->r_ctrl0 + fl->id] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK;
612
613 /*
614 * In read mode, the default SPI command is READ (0x3). In other
615 * modes, the command should necessarily be defined
616 *
617 * TODO: add support for READ4 (0x13) on AST2600
618 */
619 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) {
620 cmd = SPI_OP_READ;
621 }
622
623 if (!cmd) {
624 qemu_log_mask(LOG_GUEST_ERROR, "%s: no command defined for mode %d\n",
625 __func__, aspeed_smc_flash_mode(fl));
626 }
627
628 return cmd;
629 }
630
631 static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
632 {
633 const AspeedSMCState *s = fl->controller;
634
635 if (s->ctrl->segments == aspeed_segments_spi) {
636 return s->regs[s->r_ctrl0] & CTRL_AST2400_SPI_4BYTE;
637 } else {
638 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->id));
639 }
640 }
641
642 static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
643 {
644 const AspeedSMCState *s = fl->controller;
645
646 return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
647 }
648
649 static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
650 {
651 AspeedSMCState *s = fl->controller;
652
653 s->regs[s->r_ctrl0 + fl->id] &= ~CTRL_CE_STOP_ACTIVE;
654 qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
655 }
656
657 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
658 {
659 AspeedSMCState *s = fl->controller;
660
661 s->regs[s->r_ctrl0 + fl->id] |= CTRL_CE_STOP_ACTIVE;
662 qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
663 }
664
665 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
666 uint32_t addr)
667 {
668 const AspeedSMCState *s = fl->controller;
669 AspeedSegments seg;
670
671 s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->id], &seg);
672 if ((addr % seg.size) != addr) {
673 qemu_log_mask(LOG_GUEST_ERROR,
674 "%s: invalid address 0x%08x for CS%d segment : "
675 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
676 s->ctrl->name, addr, fl->id, seg.addr,
677 seg.addr + seg.size);
678 addr %= seg.size;
679 }
680
681 return addr;
682 }
683
684 static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl)
685 {
686 const AspeedSMCState *s = fl->controller;
687 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->id];
688 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1;
689 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3;
690 uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8;
691
692 if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) {
693 dummies /= 2;
694 }
695
696 return dummies;
697 }
698
699 static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
700 {
701 const AspeedSMCState *s = fl->controller;
702 uint8_t cmd = aspeed_smc_flash_cmd(fl);
703 int i;
704
705 /* Flash access can not exceed CS segment */
706 addr = aspeed_smc_check_segment_addr(fl, addr);
707
708 ssi_transfer(s->spi, cmd);
709
710 if (aspeed_smc_flash_is_4byte(fl)) {
711 ssi_transfer(s->spi, (addr >> 24) & 0xff);
712 }
713 ssi_transfer(s->spi, (addr >> 16) & 0xff);
714 ssi_transfer(s->spi, (addr >> 8) & 0xff);
715 ssi_transfer(s->spi, (addr & 0xff));
716
717 /*
718 * Use fake transfers to model dummy bytes. The value should
719 * be configured to some non-zero value in fast read mode and
720 * zero in read mode. But, as the HW allows inconsistent
721 * settings, let's check for fast read mode.
722 */
723 if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
724 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
725 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff);
726 }
727 }
728 }
729
730 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
731 {
732 AspeedSMCFlash *fl = opaque;
733 AspeedSMCState *s = fl->controller;
734 uint64_t ret = 0;
735 int i;
736
737 switch (aspeed_smc_flash_mode(fl)) {
738 case CTRL_USERMODE:
739 for (i = 0; i < size; i++) {
740 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
741 }
742 break;
743 case CTRL_READMODE:
744 case CTRL_FREADMODE:
745 aspeed_smc_flash_select(fl);
746 aspeed_smc_flash_setup(fl, addr);
747
748 for (i = 0; i < size; i++) {
749 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
750 }
751
752 aspeed_smc_flash_unselect(fl);
753 break;
754 default:
755 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid flash mode %d\n",
756 __func__, aspeed_smc_flash_mode(fl));
757 }
758
759 trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
760 aspeed_smc_flash_mode(fl));
761 return ret;
762 }
763
764 /*
765 * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a
766 * common include header.
767 */
768 typedef enum {
769 READ = 0x3, READ_4 = 0x13,
770 FAST_READ = 0xb, FAST_READ_4 = 0x0c,
771 DOR = 0x3b, DOR_4 = 0x3c,
772 QOR = 0x6b, QOR_4 = 0x6c,
773 DIOR = 0xbb, DIOR_4 = 0xbc,
774 QIOR = 0xeb, QIOR_4 = 0xec,
775
776 PP = 0x2, PP_4 = 0x12,
777 DPP = 0xa2,
778 QPP = 0x32, QPP_4 = 0x34,
779 } FlashCMD;
780
781 static int aspeed_smc_num_dummies(uint8_t command)
782 {
783 switch (command) { /* check for dummies */
784 case READ: /* no dummy bytes/cycles */
785 case PP:
786 case DPP:
787 case QPP:
788 case READ_4:
789 case PP_4:
790 case QPP_4:
791 return 0;
792 case FAST_READ:
793 case DOR:
794 case QOR:
795 case DOR_4:
796 case QOR_4:
797 return 1;
798 case DIOR:
799 case FAST_READ_4:
800 case DIOR_4:
801 return 2;
802 case QIOR:
803 case QIOR_4:
804 return 4;
805 default:
806 return -1;
807 }
808 }
809
810 static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
811 unsigned size)
812 {
813 AspeedSMCState *s = fl->controller;
814 uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
815
816 trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
817 (uint8_t) data & 0xff);
818
819 if (s->snoop_index == SNOOP_OFF) {
820 return false; /* Do nothing */
821
822 } else if (s->snoop_index == SNOOP_START) {
823 uint8_t cmd = data & 0xff;
824 int ndummies = aspeed_smc_num_dummies(cmd);
825
826 /*
827 * No dummy cycles are expected with the current command. Turn
828 * off snooping and let the transfer proceed normally.
829 */
830 if (ndummies <= 0) {
831 s->snoop_index = SNOOP_OFF;
832 return false;
833 }
834
835 s->snoop_dummies = ndummies * 8;
836
837 } else if (s->snoop_index >= addr_width + 1) {
838
839 /* The SPI transfer has reached the dummy cycles sequence */
840 for (; s->snoop_dummies; s->snoop_dummies--) {
841 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff);
842 }
843
844 /* If no more dummy cycles are expected, turn off snooping */
845 if (!s->snoop_dummies) {
846 s->snoop_index = SNOOP_OFF;
847 } else {
848 s->snoop_index += size;
849 }
850
851 /*
852 * Dummy cycles have been faked already. Ignore the current
853 * SPI transfer
854 */
855 return true;
856 }
857
858 s->snoop_index += size;
859 return false;
860 }
861
862 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
863 unsigned size)
864 {
865 AspeedSMCFlash *fl = opaque;
866 AspeedSMCState *s = fl->controller;
867 int i;
868
869 trace_aspeed_smc_flash_write(fl->id, addr, size, data,
870 aspeed_smc_flash_mode(fl));
871
872 if (!aspeed_smc_is_writable(fl)) {
873 qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
874 HWADDR_PRIx "\n", __func__, addr);
875 return;
876 }
877
878 switch (aspeed_smc_flash_mode(fl)) {
879 case CTRL_USERMODE:
880 if (aspeed_smc_do_snoop(fl, data, size)) {
881 break;
882 }
883
884 for (i = 0; i < size; i++) {
885 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
886 }
887 break;
888 case CTRL_WRITEMODE:
889 aspeed_smc_flash_select(fl);
890 aspeed_smc_flash_setup(fl, addr);
891
892 for (i = 0; i < size; i++) {
893 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
894 }
895
896 aspeed_smc_flash_unselect(fl);
897 break;
898 default:
899 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid flash mode %d\n",
900 __func__, aspeed_smc_flash_mode(fl));
901 }
902 }
903
904 static const MemoryRegionOps aspeed_smc_flash_ops = {
905 .read = aspeed_smc_flash_read,
906 .write = aspeed_smc_flash_write,
907 .endianness = DEVICE_LITTLE_ENDIAN,
908 .valid = {
909 .min_access_size = 1,
910 .max_access_size = 4,
911 },
912 };
913
914 static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
915 {
916 AspeedSMCState *s = fl->controller;
917
918 s->snoop_index = aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOOP_START;
919
920 qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
921 }
922
923 static void aspeed_smc_reset(DeviceState *d)
924 {
925 AspeedSMCState *s = ASPEED_SMC(d);
926 int i;
927
928 memset(s->regs, 0, sizeof s->regs);
929
930 /* Unselect all slaves */
931 for (i = 0; i < s->num_cs; ++i) {
932 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
933 qemu_set_irq(s->cs_lines[i], true);
934 }
935
936 /* setup the default segment register values and regions for all */
937 for (i = 0; i < s->ctrl->max_slaves; ++i) {
938 aspeed_smc_flash_set_segment_region(s, i,
939 s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]));
940 }
941
942 /* HW strapping flash type for the AST2600 controllers */
943 if (s->ctrl->segments == aspeed_segments_ast2600_fmc) {
944 /* flash type is fixed to SPI for all */
945 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
946 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1);
947 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2);
948 }
949
950 /* HW strapping flash type for FMC controllers */
951 if (s->ctrl->segments == aspeed_segments_ast2500_fmc) {
952 /* flash type is fixed to SPI for CE0 and CE1 */
953 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
954 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1);
955 }
956
957 /* HW strapping for AST2400 FMC controllers (SCU70). Let's use the
958 * configuration of the palmetto-bmc machine */
959 if (s->ctrl->segments == aspeed_segments_fmc) {
960 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
961 }
962
963 s->snoop_index = SNOOP_OFF;
964 s->snoop_dummies = 0;
965 }
966
967 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
968 {
969 AspeedSMCState *s = ASPEED_SMC(opaque);
970
971 addr >>= 2;
972
973 if (addr == s->r_conf ||
974 (addr >= s->r_timings &&
975 addr < s->r_timings + s->ctrl->nregs_timings) ||
976 addr == s->r_ce_ctrl ||
977 addr == R_INTR_CTRL ||
978 addr == R_DUMMY_DATA ||
979 (s->ctrl->has_dma && addr == R_DMA_CTRL) ||
980 (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) ||
981 (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) ||
982 (s->ctrl->has_dma && addr == R_DMA_LEN) ||
983 (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
984 (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
985 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
986
987 trace_aspeed_smc_read(addr, size, s->regs[addr]);
988
989 return s->regs[addr];
990 } else {
991 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
992 __func__, addr);
993 return -1;
994 }
995 }
996
997 static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
998 {
999 /* HCLK/1 .. HCLK/16 */
1000 const uint8_t hclk_divisors[] = {
1001 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
1002 };
1003 int i;
1004
1005 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) {
1006 if (hclk_mask == hclk_divisors[i]) {
1007 return i + 1;
1008 }
1009 }
1010
1011 qemu_log_mask(LOG_GUEST_ERROR, "invalid HCLK mask %x", hclk_mask);
1012 return 0;
1013 }
1014
1015 /*
1016 * When doing calibration, the SPI clock rate in the CE0 Control
1017 * Register and the read delay cycles in the Read Timing Compensation
1018 * Register are set using bit[11:4] of the DMA Control Register.
1019 */
1020 static void aspeed_smc_dma_calibration(AspeedSMCState *s)
1021 {
1022 uint8_t delay =
1023 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
1024 uint8_t hclk_mask =
1025 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
1026 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask);
1027 uint32_t hclk_shift = (hclk_div - 1) << 2;
1028 uint8_t cs;
1029
1030 /*
1031 * The Read Timing Compensation Register values apply to all CS on
1032 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays
1033 */
1034 if (hclk_div && hclk_div < 6) {
1035 s->regs[s->r_timings] &= ~(0xf << hclk_shift);
1036 s->regs[s->r_timings] |= delay << hclk_shift;
1037 }
1038
1039 /*
1040 * TODO: compute the CS from the DMA address and the segment
1041 * registers. This is not really a problem for now because the
1042 * Timing Register values apply to all CS and software uses CS0 to
1043 * do calibration.
1044 */
1045 cs = 0;
1046 s->regs[s->r_ctrl0 + cs] &=
1047 ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT);
1048 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
1049 }
1050
1051 /*
1052 * Emulate read errors in the DMA Checksum Register for high
1053 * frequencies and optimistic settings of the Read Timing Compensation
1054 * Register. This will help in tuning the SPI timing calibration
1055 * algorithm.
1056 */
1057 static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
1058 {
1059 uint8_t delay =
1060 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
1061 uint8_t hclk_mask =
1062 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
1063
1064 /*
1065 * Typical values of a palmetto-bmc machine.
1066 */
1067 switch (aspeed_smc_hclk_divisor(hclk_mask)) {
1068 case 4 ... 16:
1069 return false;
1070 case 3: /* at least one HCLK cycle delay */
1071 return (delay & 0x7) < 1;
1072 case 2: /* at least two HCLK cycle delay */
1073 return (delay & 0x7) < 2;
1074 case 1: /* (> 100MHz) is above the max freq of the controller */
1075 return true;
1076 default:
1077 g_assert_not_reached();
1078 }
1079 }
1080
1081 /*
1082 * Accumulate the result of the reads to provide a checksum that will
1083 * be used to validate the read timing settings.
1084 */
1085 static void aspeed_smc_dma_checksum(AspeedSMCState *s)
1086 {
1087 MemTxResult result;
1088 uint32_t data;
1089
1090 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
1091 qemu_log_mask(LOG_GUEST_ERROR,
1092 "%s: invalid direction for DMA checksum\n", __func__);
1093 return;
1094 }
1095
1096 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {
1097 aspeed_smc_dma_calibration(s);
1098 }
1099
1100 while (s->regs[R_DMA_LEN]) {
1101 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
1102 MEMTXATTRS_UNSPECIFIED, &result);
1103 if (result != MEMTX_OK) {
1104 qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n",
1105 __func__, s->regs[R_DMA_FLASH_ADDR]);
1106 return;
1107 }
1108 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
1109
1110 /*
1111 * When the DMA is on-going, the DMA registers are updated
1112 * with the current working addresses and length.
1113 */
1114 s->regs[R_DMA_CHECKSUM] += data;
1115 s->regs[R_DMA_FLASH_ADDR] += 4;
1116 s->regs[R_DMA_LEN] -= 4;
1117 }
1118
1119 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
1120 s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
1121 }
1122
1123 }
1124
1125 static void aspeed_smc_dma_rw(AspeedSMCState *s)
1126 {
1127 MemTxResult result;
1128 uint32_t data;
1129
1130 while (s->regs[R_DMA_LEN]) {
1131 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
1132 data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
1133 MEMTXATTRS_UNSPECIFIED, &result);
1134 if (result != MEMTX_OK) {
1135 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n",
1136 __func__, s->regs[R_DMA_DRAM_ADDR]);
1137 return;
1138 }
1139
1140 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
1141 data, MEMTXATTRS_UNSPECIFIED, &result);
1142 if (result != MEMTX_OK) {
1143 qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash write failed @%08x\n",
1144 __func__, s->regs[R_DMA_FLASH_ADDR]);
1145 return;
1146 }
1147 } else {
1148 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
1149 MEMTXATTRS_UNSPECIFIED, &result);
1150 if (result != MEMTX_OK) {
1151 qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n",
1152 __func__, s->regs[R_DMA_FLASH_ADDR]);
1153 return;
1154 }
1155
1156 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
1157 data, MEMTXATTRS_UNSPECIFIED, &result);
1158 if (result != MEMTX_OK) {
1159 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n",
1160 __func__, s->regs[R_DMA_DRAM_ADDR]);
1161 return;
1162 }
1163 }
1164
1165 /*
1166 * When the DMA is on-going, the DMA registers are updated
1167 * with the current working addresses and length.
1168 */
1169 s->regs[R_DMA_FLASH_ADDR] += 4;
1170 s->regs[R_DMA_DRAM_ADDR] += 4;
1171 s->regs[R_DMA_LEN] -= 4;
1172 s->regs[R_DMA_CHECKSUM] += data;
1173 }
1174 }
1175
1176 static void aspeed_smc_dma_stop(AspeedSMCState *s)
1177 {
1178 /*
1179 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the
1180 * engine is idle
1181 */
1182 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
1183 s->regs[R_DMA_CHECKSUM] = 0;
1184
1185 /*
1186 * Lower the DMA irq in any case. The IRQ control register could
1187 * have been cleared before disabling the DMA.
1188 */
1189 qemu_irq_lower(s->irq);
1190 }
1191
1192 /*
1193 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
1194 * can start even if the result of the previous was not collected.
1195 */
1196 static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
1197 {
1198 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
1199 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
1200 }
1201
1202 static void aspeed_smc_dma_done(AspeedSMCState *s)
1203 {
1204 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
1205 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
1206 qemu_irq_raise(s->irq);
1207 }
1208 }
1209
1210 static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
1211 {
1212 if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
1213 s->regs[R_DMA_CTRL] = dma_ctrl;
1214
1215 aspeed_smc_dma_stop(s);
1216 return;
1217 }
1218
1219 if (aspeed_smc_dma_in_progress(s)) {
1220 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA in progress\n", __func__);
1221 return;
1222 }
1223
1224 s->regs[R_DMA_CTRL] = dma_ctrl;
1225
1226 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
1227 aspeed_smc_dma_checksum(s);
1228 } else {
1229 aspeed_smc_dma_rw(s);
1230 }
1231
1232 aspeed_smc_dma_done(s);
1233 }
1234
1235 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
1236 unsigned int size)
1237 {
1238 AspeedSMCState *s = ASPEED_SMC(opaque);
1239 uint32_t value = data;
1240
1241 addr >>= 2;
1242
1243 trace_aspeed_smc_write(addr, size, data);
1244
1245 if (addr == s->r_conf ||
1246 (addr >= s->r_timings &&
1247 addr < s->r_timings + s->ctrl->nregs_timings) ||
1248 addr == s->r_ce_ctrl) {
1249 s->regs[addr] = value;
1250 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
1251 int cs = addr - s->r_ctrl0;
1252 s->regs[addr] = value;
1253 aspeed_smc_flash_update_cs(&s->flashes[cs]);
1254 } else if (addr >= R_SEG_ADDR0 &&
1255 addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
1256 int cs = addr - R_SEG_ADDR0;
1257
1258 if (value != s->regs[R_SEG_ADDR0 + cs]) {
1259 aspeed_smc_flash_set_segment(s, cs, value);
1260 }
1261 } else if (addr == R_DUMMY_DATA) {
1262 s->regs[addr] = value & 0xff;
1263 } else if (addr == R_INTR_CTRL) {
1264 s->regs[addr] = value;
1265 } else if (s->ctrl->has_dma && addr == R_DMA_CTRL) {
1266 aspeed_smc_dma_ctrl(s, value);
1267 } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) {
1268 s->regs[addr] = DMA_DRAM_ADDR(s, value);
1269 } else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) {
1270 s->regs[addr] = DMA_FLASH_ADDR(s, value);
1271 } else if (s->ctrl->has_dma && addr == R_DMA_LEN) {
1272 s->regs[addr] = DMA_LENGTH(value);
1273 } else {
1274 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
1275 __func__, addr);
1276 return;
1277 }
1278 }
1279
1280 static const MemoryRegionOps aspeed_smc_ops = {
1281 .read = aspeed_smc_read,
1282 .write = aspeed_smc_write,
1283 .endianness = DEVICE_LITTLE_ENDIAN,
1284 .valid.unaligned = true,
1285 };
1286
1287
1288 /*
1289 * Initialize the custom address spaces for DMAs
1290 */
1291 static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
1292 {
1293 char *name;
1294
1295 if (!s->dram_mr) {
1296 error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
1297 return;
1298 }
1299
1300 name = g_strdup_printf("%s-dma-flash", s->ctrl->name);
1301 address_space_init(&s->flash_as, &s->mmio_flash, name);
1302 g_free(name);
1303
1304 name = g_strdup_printf("%s-dma-dram", s->ctrl->name);
1305 address_space_init(&s->dram_as, s->dram_mr, name);
1306 g_free(name);
1307 }
1308
1309 static void aspeed_smc_realize(DeviceState *dev, Error **errp)
1310 {
1311 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1312 AspeedSMCState *s = ASPEED_SMC(dev);
1313 AspeedSMCClass *mc = ASPEED_SMC_GET_CLASS(s);
1314 int i;
1315 char name[32];
1316 hwaddr offset = 0;
1317
1318 s->ctrl = mc->ctrl;
1319
1320 /* keep a copy under AspeedSMCState to speed up accesses */
1321 s->r_conf = s->ctrl->r_conf;
1322 s->r_ce_ctrl = s->ctrl->r_ce_ctrl;
1323 s->r_ctrl0 = s->ctrl->r_ctrl0;
1324 s->r_timings = s->ctrl->r_timings;
1325 s->conf_enable_w0 = s->ctrl->conf_enable_w0;
1326
1327 /* Enforce some real HW limits */
1328 if (s->num_cs > s->ctrl->max_slaves) {
1329 qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
1330 __func__, s->ctrl->max_slaves);
1331 s->num_cs = s->ctrl->max_slaves;
1332 }
1333
1334 /* DMA irq. Keep it first for the initialization in the SoC */
1335 sysbus_init_irq(sbd, &s->irq);
1336
1337 s->spi = ssi_create_bus(dev, "spi");
1338
1339 /* Setup cs_lines for slaves */
1340 s->cs_lines = g_new0(qemu_irq, s->num_cs);
1341 ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
1342
1343 for (i = 0; i < s->num_cs; ++i) {
1344 sysbus_init_irq(sbd, &s->cs_lines[i]);
1345 }
1346
1347 /* The memory region for the controller registers */
1348 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
1349 s->ctrl->name, s->ctrl->nregs * 4);
1350 sysbus_init_mmio(sbd, &s->mmio);
1351
1352 /*
1353 * The container memory region representing the address space
1354 * window in which the flash modules are mapped. The size and
1355 * address depends on the SoC model and controller type.
1356 */
1357 snprintf(name, sizeof(name), "%s.flash", s->ctrl->name);
1358
1359 memory_region_init_io(&s->mmio_flash, OBJECT(s),
1360 &aspeed_smc_flash_default_ops, s, name,
1361 s->ctrl->flash_window_size);
1362 sysbus_init_mmio(sbd, &s->mmio_flash);
1363
1364 s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves);
1365
1366 /*
1367 * Let's create a sub memory region for each possible slave. All
1368 * have a configurable memory segment in the overall flash mapping
1369 * window of the controller but, there is not necessarily a flash
1370 * module behind to handle the memory accesses. This depends on
1371 * the board configuration.
1372 */
1373 for (i = 0; i < s->ctrl->max_slaves; ++i) {
1374 AspeedSMCFlash *fl = &s->flashes[i];
1375
1376 snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);
1377
1378 fl->id = i;
1379 fl->controller = s;
1380 fl->size = s->ctrl->segments[i].size;
1381 memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_ops,
1382 fl, name, fl->size);
1383 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
1384 offset += fl->size;
1385 }
1386
1387 /* DMA support */
1388 if (s->ctrl->has_dma) {
1389 aspeed_smc_dma_setup(s, errp);
1390 }
1391 }
1392
1393 static const VMStateDescription vmstate_aspeed_smc = {
1394 .name = "aspeed.smc",
1395 .version_id = 2,
1396 .minimum_version_id = 2,
1397 .fields = (VMStateField[]) {
1398 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
1399 VMSTATE_UINT8(snoop_index, AspeedSMCState),
1400 VMSTATE_UINT8(snoop_dummies, AspeedSMCState),
1401 VMSTATE_END_OF_LIST()
1402 }
1403 };
1404
1405 static Property aspeed_smc_properties[] = {
1406 DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
1407 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
1408 DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
1409 DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
1410 TYPE_MEMORY_REGION, MemoryRegion *),
1411 DEFINE_PROP_END_OF_LIST(),
1412 };
1413
1414 static void aspeed_smc_class_init(ObjectClass *klass, void *data)
1415 {
1416 DeviceClass *dc = DEVICE_CLASS(klass);
1417 AspeedSMCClass *mc = ASPEED_SMC_CLASS(klass);
1418
1419 dc->realize = aspeed_smc_realize;
1420 dc->reset = aspeed_smc_reset;
1421 device_class_set_props(dc, aspeed_smc_properties);
1422 dc->vmsd = &vmstate_aspeed_smc;
1423 mc->ctrl = data;
1424 }
1425
1426 static const TypeInfo aspeed_smc_info = {
1427 .name = TYPE_ASPEED_SMC,
1428 .parent = TYPE_SYS_BUS_DEVICE,
1429 .instance_size = sizeof(AspeedSMCState),
1430 .class_size = sizeof(AspeedSMCClass),
1431 .abstract = true,
1432 };
1433
1434 static void aspeed_smc_register_types(void)
1435 {
1436 int i;
1437
1438 type_register_static(&aspeed_smc_info);
1439 for (i = 0; i < ARRAY_SIZE(controllers); ++i) {
1440 TypeInfo ti = {
1441 .name = controllers[i].name,
1442 .parent = TYPE_ASPEED_SMC,
1443 .class_init = aspeed_smc_class_init,
1444 .class_data = (void *)&controllers[i],
1445 };
1446 type_register(&ti);
1447 }
1448 }
1449
1450 type_init(aspeed_smc_register_types)
AR7 emulation for QEMU