4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009, 2010, 2011
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on piix.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu/osdep.h"
34 #include "qapi/visitor.h"
35 #include "qemu/range.h"
36 #include "hw/isa/isa.h"
37 #include "hw/sysbus.h"
38 #include "migration/vmstate.h"
40 #include "hw/isa/apm.h"
41 #include "hw/pci/pci.h"
42 #include "hw/pci/pci_bridge.h"
43 #include "hw/i386/ich9.h"
44 #include "hw/acpi/acpi.h"
45 #include "hw/acpi/ich9.h"
46 #include "hw/pci/pci_bus.h"
47 #include "hw/qdev-properties.h"
48 #include "exec/address-spaces.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/sysemu.h"
51 #include "hw/core/cpu.h"
52 #include "hw/nvram/fw_cfg.h"
53 #include "qemu/cutils.h"
55 /*****************************************************************************/
56 /* ICH9 LPC PCI to ISA bridge */
58 static void ich9_lpc_reset(DeviceState
*qdev
);
60 /* chipset configuration register
61 * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
63 * Although it's not pci configuration space, it's little endian as Intel.
66 static void ich9_cc_update_ir(uint8_t irr
[PCI_NUM_PINS
], uint16_t ir
)
69 for (intx
= 0; intx
< PCI_NUM_PINS
; intx
++) {
70 irr
[intx
] = (ir
>> (intx
* ICH9_CC_DIR_SHIFT
)) & ICH9_CC_DIR_MASK
;
74 static void ich9_cc_update(ICH9LPCState
*lpc
)
79 const int reg_offsets
[] = {
90 /* D{25 - 31}IR, but D30IR is read only to 0. */
91 for (slot
= 25, offset
= reg_offsets
; slot
< 32; slot
++, offset
++) {
95 ich9_cc_update_ir(lpc
->irr
[slot
],
96 pci_get_word(lpc
->chip_config
+ *offset
));
100 * D30: DMI2PCI bridge
101 * It is arbitrarily decided how INTx lines of PCI devices behind
102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
103 * INT[A-D] are connected to PIRQ[E-H]
105 for (pci_intx
= 0; pci_intx
< PCI_NUM_PINS
; pci_intx
++) {
106 lpc
->irr
[30][pci_intx
] = pci_intx
+ 4;
110 static void ich9_cc_init(ICH9LPCState
*lpc
)
115 /* the default irq routing is arbitrary as long as it matches with
116 * acpi irq routing table.
117 * The one that is incompatible with piix_pci(= bochs) one is
118 * intentionally chosen to let the users know that the different
121 * int[A-D] -> pirq[E-F]
122 * avoid pirq A-D because they are used for pci express port
124 for (slot
= 0; slot
< PCI_SLOT_MAX
; slot
++) {
125 for (intx
= 0; intx
< PCI_NUM_PINS
; intx
++) {
126 lpc
->irr
[slot
][intx
] = (slot
+ intx
) % 4 + 4;
132 static void ich9_cc_reset(ICH9LPCState
*lpc
)
134 uint8_t *c
= lpc
->chip_config
;
136 memset(lpc
->chip_config
, 0, sizeof(lpc
->chip_config
));
138 pci_set_long(c
+ ICH9_CC_D31IR
, ICH9_CC_DIR_DEFAULT
);
139 pci_set_long(c
+ ICH9_CC_D30IR
, ICH9_CC_D30IR_DEFAULT
);
140 pci_set_long(c
+ ICH9_CC_D29IR
, ICH9_CC_DIR_DEFAULT
);
141 pci_set_long(c
+ ICH9_CC_D28IR
, ICH9_CC_DIR_DEFAULT
);
142 pci_set_long(c
+ ICH9_CC_D27IR
, ICH9_CC_DIR_DEFAULT
);
143 pci_set_long(c
+ ICH9_CC_D26IR
, ICH9_CC_DIR_DEFAULT
);
144 pci_set_long(c
+ ICH9_CC_D25IR
, ICH9_CC_DIR_DEFAULT
);
145 pci_set_long(c
+ ICH9_CC_GCS
, ICH9_CC_GCS_DEFAULT
);
150 static void ich9_cc_addr_len(uint64_t *addr
, unsigned *len
)
152 *addr
&= ICH9_CC_ADDR_MASK
;
153 if (*addr
+ *len
>= ICH9_CC_SIZE
) {
154 *len
= ICH9_CC_SIZE
- *addr
;
158 /* val: little endian */
159 static void ich9_cc_write(void *opaque
, hwaddr addr
,
160 uint64_t val
, unsigned len
)
162 ICH9LPCState
*lpc
= (ICH9LPCState
*)opaque
;
164 ich9_cc_addr_len(&addr
, &len
);
165 memcpy(lpc
->chip_config
+ addr
, &val
, len
);
166 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc
->d
));
170 /* return value: little endian */
171 static uint64_t ich9_cc_read(void *opaque
, hwaddr addr
,
174 ICH9LPCState
*lpc
= (ICH9LPCState
*)opaque
;
177 ich9_cc_addr_len(&addr
, &len
);
178 memcpy(&val
, lpc
->chip_config
+ addr
, len
);
184 static void ich9_lpc_rout(uint8_t pirq_rout
, int *pic_irq
, int *pic_dis
)
186 *pic_irq
= pirq_rout
& ICH9_LPC_PIRQ_ROUT_MASK
;
187 *pic_dis
= pirq_rout
& ICH9_LPC_PIRQ_ROUT_IRQEN
;
190 static void ich9_lpc_pic_irq(ICH9LPCState
*lpc
, int pirq_num
,
191 int *pic_irq
, int *pic_dis
)
194 case 0 ... 3: /* A-D */
195 ich9_lpc_rout(lpc
->d
.config
[ICH9_LPC_PIRQA_ROUT
+ pirq_num
],
198 case 4 ... 7: /* E-H */
199 ich9_lpc_rout(lpc
->d
.config
[ICH9_LPC_PIRQE_ROUT
+ (pirq_num
- 4)],
208 /* gsi: i8259+ioapic irq 0-15, otherwise assert */
209 static void ich9_lpc_update_pic(ICH9LPCState
*lpc
, int gsi
)
213 assert(gsi
< ICH9_LPC_PIC_NUM_PINS
);
215 /* The pic level is the logical OR of all the PCI irqs mapped to it */
217 for (i
= 0; i
< ICH9_LPC_NB_PIRQS
; i
++) {
220 ich9_lpc_pic_irq(lpc
, i
, &tmp_irq
, &tmp_dis
);
221 if (!tmp_dis
&& tmp_irq
== gsi
) {
222 pic_level
|= pci_bus_get_irq_level(pci_get_bus(&lpc
->d
), i
);
225 if (gsi
== lpc
->sci_gsi
) {
226 pic_level
|= lpc
->sci_level
;
229 qemu_set_irq(lpc
->gsi
[gsi
], pic_level
);
232 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
233 static int ich9_pirq_to_gsi(int pirq
)
235 return pirq
+ ICH9_LPC_PIC_NUM_PINS
;
238 static int ich9_gsi_to_pirq(int gsi
)
240 return gsi
- ICH9_LPC_PIC_NUM_PINS
;
243 /* gsi: ioapic irq 16-23, otherwise assert */
244 static void ich9_lpc_update_apic(ICH9LPCState
*lpc
, int gsi
)
248 assert(gsi
>= ICH9_LPC_PIC_NUM_PINS
);
250 level
|= pci_bus_get_irq_level(pci_get_bus(&lpc
->d
), ich9_gsi_to_pirq(gsi
));
251 if (gsi
== lpc
->sci_gsi
) {
252 level
|= lpc
->sci_level
;
255 qemu_set_irq(lpc
->gsi
[gsi
], level
);
258 void ich9_lpc_set_irq(void *opaque
, int pirq
, int level
)
260 ICH9LPCState
*lpc
= opaque
;
261 int pic_irq
, pic_dis
;
264 assert(pirq
< ICH9_LPC_NB_PIRQS
);
266 ich9_lpc_update_apic(lpc
, ich9_pirq_to_gsi(pirq
));
267 ich9_lpc_pic_irq(lpc
, pirq
, &pic_irq
, &pic_dis
);
268 ich9_lpc_update_pic(lpc
, pic_irq
);
271 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to
272 * a given device irq pin.
274 int ich9_lpc_map_irq(PCIDevice
*pci_dev
, int intx
)
276 BusState
*bus
= qdev_get_parent_bus(&pci_dev
->qdev
);
277 PCIBus
*pci_bus
= PCI_BUS(bus
);
278 PCIDevice
*lpc_pdev
=
279 pci_bus
->devices
[PCI_DEVFN(ICH9_LPC_DEV
, ICH9_LPC_FUNC
)];
280 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(lpc_pdev
);
282 return lpc
->irr
[PCI_SLOT(pci_dev
->devfn
)][intx
];
285 PCIINTxRoute
ich9_route_intx_pin_to_irq(void *opaque
, int pirq_pin
)
287 ICH9LPCState
*lpc
= opaque
;
292 assert(0 <= pirq_pin
);
293 assert(pirq_pin
< ICH9_LPC_NB_PIRQS
);
295 route
.mode
= PCI_INTX_ENABLED
;
296 ich9_lpc_pic_irq(lpc
, pirq_pin
, &pic_irq
, &pic_dis
);
298 if (pic_irq
< ICH9_LPC_PIC_NUM_PINS
) {
301 route
.mode
= PCI_INTX_DISABLED
;
305 route
.irq
= ich9_pirq_to_gsi(pirq_pin
);
311 void ich9_generate_smi(void)
313 cpu_interrupt(first_cpu
, CPU_INTERRUPT_SMI
);
316 /* Returns -1 on error, IRQ number on success */
317 static int ich9_lpc_sci_irq(ICH9LPCState
*lpc
)
319 uint8_t sel
= lpc
->d
.config
[ICH9_LPC_ACPI_CTRL
] &
320 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK
;
322 case ICH9_LPC_ACPI_CTRL_9
:
324 case ICH9_LPC_ACPI_CTRL_10
:
326 case ICH9_LPC_ACPI_CTRL_11
:
328 case ICH9_LPC_ACPI_CTRL_20
:
330 case ICH9_LPC_ACPI_CTRL_21
:
334 qemu_log_mask(LOG_GUEST_ERROR
,
335 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel
);
341 static void ich9_set_sci(void *opaque
, int irq_num
, int level
)
343 ICH9LPCState
*lpc
= opaque
;
346 assert(irq_num
== 0);
348 if (level
== lpc
->sci_level
) {
351 lpc
->sci_level
= level
;
358 if (irq
>= ICH9_LPC_PIC_NUM_PINS
) {
359 ich9_lpc_update_apic(lpc
, irq
);
361 ich9_lpc_update_pic(lpc
, irq
);
365 static void smi_features_ok_callback(void *opaque
)
367 ICH9LPCState
*lpc
= opaque
;
368 uint64_t guest_features
;
369 uint64_t guest_cpu_hotplug_features
;
371 if (lpc
->smi_features_ok
) {
372 /* negotiation already complete, features locked */
376 memcpy(&guest_features
, lpc
->smi_guest_features_le
, sizeof guest_features
);
377 le64_to_cpus(&guest_features
);
378 if (guest_features
& ~lpc
->smi_host_features
) {
379 /* guest requests invalid features, leave @features_ok at zero */
383 guest_cpu_hotplug_features
= guest_features
&
384 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT
) |
385 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
));
386 if (!(guest_features
& BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT
)) &&
387 guest_cpu_hotplug_features
) {
389 * cpu hot-[un]plug with SMI requires SMI broadcast,
390 * leave @features_ok at zero
395 if (guest_cpu_hotplug_features
==
396 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
)) {
397 /* cpu hot-unplug is unsupported without cpu-hotplug */
401 /* valid feature subset requested, lock it down, report success */
402 lpc
->smi_negotiated_features
= guest_features
;
403 lpc
->smi_features_ok
= 1;
406 void ich9_lpc_pm_init(PCIDevice
*lpc_pci
, bool smm_enabled
)
408 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(lpc_pci
);
410 FWCfgState
*fw_cfg
= fw_cfg_find();
412 sci_irq
= qemu_allocate_irq(ich9_set_sci
, lpc
, 0);
413 ich9_pm_init(lpc_pci
, &lpc
->pm
, smm_enabled
, sci_irq
);
415 if (lpc
->smi_host_features
&& fw_cfg
) {
416 uint64_t host_features_le
;
418 host_features_le
= cpu_to_le64(lpc
->smi_host_features
);
419 memcpy(lpc
->smi_host_features_le
, &host_features_le
,
420 sizeof host_features_le
);
421 fw_cfg_add_file(fw_cfg
, "etc/smi/supported-features",
422 lpc
->smi_host_features_le
,
423 sizeof lpc
->smi_host_features_le
);
425 /* The other two guest-visible fields are cleared on device reset, we
426 * just link them into fw_cfg here.
428 fw_cfg_add_file_callback(fw_cfg
, "etc/smi/requested-features",
430 lpc
->smi_guest_features_le
,
431 sizeof lpc
->smi_guest_features_le
,
433 fw_cfg_add_file_callback(fw_cfg
, "etc/smi/features-ok",
434 smi_features_ok_callback
, NULL
, lpc
,
435 &lpc
->smi_features_ok
,
436 sizeof lpc
->smi_features_ok
,
440 ich9_lpc_reset(DEVICE(lpc
));
445 static void ich9_apm_ctrl_changed(uint32_t val
, void *arg
)
447 ICH9LPCState
*lpc
= arg
;
449 /* ACPI specs 3.0, 4.7.2.5 */
450 acpi_pm1_cnt_update(&lpc
->pm
.acpi_regs
,
451 val
== ICH9_APM_ACPI_ENABLE
,
452 val
== ICH9_APM_ACPI_DISABLE
);
453 if (val
== ICH9_APM_ACPI_ENABLE
|| val
== ICH9_APM_ACPI_DISABLE
) {
457 /* SMI_EN = PMBASE + 30. SMI control and enable register */
458 if (lpc
->pm
.smi_en
& ICH9_PMIO_SMI_EN_APMC_EN
) {
459 if (lpc
->smi_negotiated_features
&
460 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT
)) {
463 cpu_interrupt(cs
, CPU_INTERRUPT_SMI
);
466 cpu_interrupt(current_cpu
, CPU_INTERRUPT_SMI
);
473 ich9_lpc_pmbase_sci_update(ICH9LPCState
*lpc
)
475 uint32_t pm_io_base
= pci_get_long(lpc
->d
.config
+ ICH9_LPC_PMBASE
);
476 uint8_t acpi_cntl
= pci_get_long(lpc
->d
.config
+ ICH9_LPC_ACPI_CTRL
);
479 if (acpi_cntl
& ICH9_LPC_ACPI_CTRL_ACPI_EN
) {
480 pm_io_base
&= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK
;
485 ich9_pm_iospace_update(&lpc
->pm
, pm_io_base
);
487 new_gsi
= ich9_lpc_sci_irq(lpc
);
491 if (lpc
->sci_level
&& new_gsi
!= lpc
->sci_gsi
) {
492 qemu_set_irq(lpc
->pm
.irq
, 0);
493 lpc
->sci_gsi
= new_gsi
;
494 qemu_set_irq(lpc
->pm
.irq
, 1);
496 lpc
->sci_gsi
= new_gsi
;
500 static void ich9_lpc_rcba_update(ICH9LPCState
*lpc
, uint32_t rcba_old
)
502 uint32_t rcba
= pci_get_long(lpc
->d
.config
+ ICH9_LPC_RCBA
);
504 if (rcba_old
& ICH9_LPC_RCBA_EN
) {
505 memory_region_del_subregion(get_system_memory(), &lpc
->rcrb_mem
);
507 if (rcba
& ICH9_LPC_RCBA_EN
) {
508 memory_region_add_subregion_overlap(get_system_memory(),
509 rcba
& ICH9_LPC_RCBA_BA_MASK
,
514 /* config:GEN_PMCON* */
516 ich9_lpc_pmcon_update(ICH9LPCState
*lpc
)
518 uint16_t gen_pmcon_1
= pci_get_word(lpc
->d
.config
+ ICH9_LPC_GEN_PMCON_1
);
521 if (gen_pmcon_1
& ICH9_LPC_GEN_PMCON_1_SMI_LOCK
) {
522 wmask
= pci_get_word(lpc
->d
.wmask
+ ICH9_LPC_GEN_PMCON_1
);
523 wmask
&= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK
;
524 pci_set_word(lpc
->d
.wmask
+ ICH9_LPC_GEN_PMCON_1
, wmask
);
525 lpc
->pm
.smi_en_wmask
&= ~1;
529 static int ich9_lpc_post_load(void *opaque
, int version_id
)
531 ICH9LPCState
*lpc
= opaque
;
533 ich9_lpc_pmbase_sci_update(lpc
);
534 ich9_lpc_rcba_update(lpc
, 0 /* disabled ICH9_LPC_RCBA_EN */);
535 ich9_lpc_pmcon_update(lpc
);
539 static void ich9_lpc_config_write(PCIDevice
*d
,
540 uint32_t addr
, uint32_t val
, int len
)
542 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(d
);
543 uint32_t rcba_old
= pci_get_long(d
->config
+ ICH9_LPC_RCBA
);
545 pci_default_write_config(d
, addr
, val
, len
);
546 if (ranges_overlap(addr
, len
, ICH9_LPC_PMBASE
, 4) ||
547 ranges_overlap(addr
, len
, ICH9_LPC_ACPI_CTRL
, 1)) {
548 ich9_lpc_pmbase_sci_update(lpc
);
550 if (ranges_overlap(addr
, len
, ICH9_LPC_RCBA
, 4)) {
551 ich9_lpc_rcba_update(lpc
, rcba_old
);
553 if (ranges_overlap(addr
, len
, ICH9_LPC_PIRQA_ROUT
, 4)) {
554 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc
->d
));
556 if (ranges_overlap(addr
, len
, ICH9_LPC_PIRQE_ROUT
, 4)) {
557 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc
->d
));
559 if (ranges_overlap(addr
, len
, ICH9_LPC_GEN_PMCON_1
, 8)) {
560 ich9_lpc_pmcon_update(lpc
);
564 static void ich9_lpc_reset(DeviceState
*qdev
)
566 PCIDevice
*d
= PCI_DEVICE(qdev
);
567 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(d
);
568 uint32_t rcba_old
= pci_get_long(d
->config
+ ICH9_LPC_RCBA
);
571 for (i
= 0; i
< 4; i
++) {
572 pci_set_byte(d
->config
+ ICH9_LPC_PIRQA_ROUT
+ i
,
573 ICH9_LPC_PIRQ_ROUT_DEFAULT
);
575 for (i
= 0; i
< 4; i
++) {
576 pci_set_byte(d
->config
+ ICH9_LPC_PIRQE_ROUT
+ i
,
577 ICH9_LPC_PIRQ_ROUT_DEFAULT
);
579 pci_set_byte(d
->config
+ ICH9_LPC_ACPI_CTRL
, ICH9_LPC_ACPI_CTRL_DEFAULT
);
581 pci_set_long(d
->config
+ ICH9_LPC_PMBASE
, ICH9_LPC_PMBASE_DEFAULT
);
582 pci_set_long(d
->config
+ ICH9_LPC_RCBA
, ICH9_LPC_RCBA_DEFAULT
);
586 ich9_lpc_pmbase_sci_update(lpc
);
587 ich9_lpc_rcba_update(lpc
, rcba_old
);
592 memset(lpc
->smi_guest_features_le
, 0, sizeof lpc
->smi_guest_features_le
);
593 lpc
->smi_features_ok
= 0;
594 lpc
->smi_negotiated_features
= 0;
597 /* root complex register block is mapped into memory space */
598 static const MemoryRegionOps rcrb_mmio_ops
= {
599 .read
= ich9_cc_read
,
600 .write
= ich9_cc_write
,
601 .endianness
= DEVICE_LITTLE_ENDIAN
,
604 static void ich9_lpc_machine_ready(Notifier
*n
, void *opaque
)
606 ICH9LPCState
*s
= container_of(n
, ICH9LPCState
, machine_ready
);
607 MemoryRegion
*io_as
= pci_address_space_io(&s
->d
);
610 pci_conf
= s
->d
.config
;
611 if (memory_region_present(io_as
, 0x3f8)) {
613 pci_conf
[0x82] |= 0x01;
615 if (memory_region_present(io_as
, 0x2f8)) {
617 pci_conf
[0x82] |= 0x02;
619 if (memory_region_present(io_as
, 0x378)) {
621 pci_conf
[0x82] |= 0x04;
623 if (memory_region_present(io_as
, 0x3f2)) {
625 pci_conf
[0x82] |= 0x08;
630 static void ich9_rst_cnt_write(void *opaque
, hwaddr addr
, uint64_t val
,
633 ICH9LPCState
*lpc
= opaque
;
636 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
639 lpc
->rst_cnt
= val
& 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
642 static uint64_t ich9_rst_cnt_read(void *opaque
, hwaddr addr
, unsigned len
)
644 ICH9LPCState
*lpc
= opaque
;
649 static const MemoryRegionOps ich9_rst_cnt_ops
= {
650 .read
= ich9_rst_cnt_read
,
651 .write
= ich9_rst_cnt_write
,
652 .endianness
= DEVICE_LITTLE_ENDIAN
655 static void ich9_lpc_initfn(Object
*obj
)
657 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(obj
);
659 static const uint8_t acpi_enable_cmd
= ICH9_APM_ACPI_ENABLE
;
660 static const uint8_t acpi_disable_cmd
= ICH9_APM_ACPI_DISABLE
;
662 object_property_add_uint8_ptr(obj
, ACPI_PM_PROP_SCI_INT
,
663 &lpc
->sci_gsi
, OBJ_PROP_FLAG_READ
);
664 object_property_add_uint8_ptr(OBJECT(lpc
), ACPI_PM_PROP_ACPI_ENABLE_CMD
,
665 &acpi_enable_cmd
, OBJ_PROP_FLAG_READ
);
666 object_property_add_uint8_ptr(OBJECT(lpc
), ACPI_PM_PROP_ACPI_DISABLE_CMD
,
667 &acpi_disable_cmd
, OBJ_PROP_FLAG_READ
);
668 object_property_add_uint64_ptr(obj
, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP
,
669 &lpc
->smi_negotiated_features
,
672 ich9_pm_add_properties(obj
, &lpc
->pm
);
675 static void ich9_lpc_realize(PCIDevice
*d
, Error
**errp
)
677 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(d
);
678 DeviceState
*dev
= DEVICE(d
);
681 isa_bus
= isa_bus_new(DEVICE(d
), get_system_memory(), get_system_io(),
687 pci_set_long(d
->wmask
+ ICH9_LPC_PMBASE
,
688 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK
);
689 pci_set_byte(d
->wmask
+ ICH9_LPC_PMBASE
,
690 ICH9_LPC_ACPI_CTRL_ACPI_EN
|
691 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK
);
693 memory_region_init_io(&lpc
->rcrb_mem
, OBJECT(d
), &rcrb_mmio_ops
, lpc
,
694 "lpc-rcrb-mmio", ICH9_CC_SIZE
);
696 lpc
->isa_bus
= isa_bus
;
699 apm_init(d
, &lpc
->apm
, ich9_apm_ctrl_changed
, lpc
);
701 lpc
->machine_ready
.notify
= ich9_lpc_machine_ready
;
702 qemu_add_machine_init_done_notifier(&lpc
->machine_ready
);
704 memory_region_init_io(&lpc
->rst_cnt_mem
, OBJECT(d
), &ich9_rst_cnt_ops
, lpc
,
705 "lpc-reset-control", 1);
706 memory_region_add_subregion_overlap(pci_address_space_io(d
),
707 ICH9_RST_CNT_IOPORT
, &lpc
->rst_cnt_mem
,
710 qdev_init_gpio_out_named(dev
, lpc
->gsi
, ICH9_GPIO_GSI
, GSI_NUM_PINS
);
712 isa_bus_irqs(isa_bus
, lpc
->gsi
);
715 static bool ich9_rst_cnt_needed(void *opaque
)
717 ICH9LPCState
*lpc
= opaque
;
719 return (lpc
->rst_cnt
!= 0);
722 static const VMStateDescription vmstate_ich9_rst_cnt
= {
723 .name
= "ICH9LPC/rst_cnt",
725 .minimum_version_id
= 1,
726 .needed
= ich9_rst_cnt_needed
,
727 .fields
= (VMStateField
[]) {
728 VMSTATE_UINT8(rst_cnt
, ICH9LPCState
),
729 VMSTATE_END_OF_LIST()
733 static bool ich9_smi_feat_needed(void *opaque
)
735 ICH9LPCState
*lpc
= opaque
;
737 return !buffer_is_zero(lpc
->smi_guest_features_le
,
738 sizeof lpc
->smi_guest_features_le
) ||
739 lpc
->smi_features_ok
;
742 static const VMStateDescription vmstate_ich9_smi_feat
= {
743 .name
= "ICH9LPC/smi_feat",
745 .minimum_version_id
= 1,
746 .needed
= ich9_smi_feat_needed
,
747 .fields
= (VMStateField
[]) {
748 VMSTATE_UINT8_ARRAY(smi_guest_features_le
, ICH9LPCState
,
750 VMSTATE_UINT8(smi_features_ok
, ICH9LPCState
),
751 VMSTATE_UINT64(smi_negotiated_features
, ICH9LPCState
),
752 VMSTATE_END_OF_LIST()
756 static const VMStateDescription vmstate_ich9_lpc
= {
759 .minimum_version_id
= 1,
760 .post_load
= ich9_lpc_post_load
,
761 .fields
= (VMStateField
[]) {
762 VMSTATE_PCI_DEVICE(d
, ICH9LPCState
),
763 VMSTATE_STRUCT(apm
, ICH9LPCState
, 0, vmstate_apm
, APMState
),
764 VMSTATE_STRUCT(pm
, ICH9LPCState
, 0, vmstate_ich9_pm
, ICH9LPCPMRegs
),
765 VMSTATE_UINT8_ARRAY(chip_config
, ICH9LPCState
, ICH9_CC_SIZE
),
766 VMSTATE_UINT32(sci_level
, ICH9LPCState
),
767 VMSTATE_END_OF_LIST()
769 .subsections
= (const VMStateDescription
*[]) {
770 &vmstate_ich9_rst_cnt
,
771 &vmstate_ich9_smi_feat
,
776 static Property ich9_lpc_properties
[] = {
777 DEFINE_PROP_BOOL("noreboot", ICH9LPCState
, pin_strap
.spkr_hi
, true),
778 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState
, smi_host_features
,
779 ICH9_LPC_SMI_F_BROADCAST_BIT
, true),
780 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState
, smi_host_features
,
781 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT
, true),
782 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState
, smi_host_features
,
783 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
, true),
784 DEFINE_PROP_END_OF_LIST(),
787 static void ich9_send_gpe(AcpiDeviceIf
*adev
, AcpiEventStatusBits ev
)
789 ICH9LPCState
*s
= ICH9_LPC_DEVICE(adev
);
791 acpi_send_gpe_event(&s
->pm
.acpi_regs
, s
->pm
.irq
, ev
);
794 static void ich9_lpc_class_init(ObjectClass
*klass
, void *data
)
796 DeviceClass
*dc
= DEVICE_CLASS(klass
);
797 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
798 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(klass
);
799 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_CLASS(klass
);
801 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
802 dc
->reset
= ich9_lpc_reset
;
803 k
->realize
= ich9_lpc_realize
;
804 dc
->vmsd
= &vmstate_ich9_lpc
;
805 device_class_set_props(dc
, ich9_lpc_properties
);
806 k
->config_write
= ich9_lpc_config_write
;
807 dc
->desc
= "ICH9 LPC bridge";
808 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
809 k
->device_id
= PCI_DEVICE_ID_INTEL_ICH9_8
;
810 k
->revision
= ICH9_A2_LPC_REVISION
;
811 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
813 * Reason: part of ICH9 southbridge, needs to be wired up by
816 dc
->user_creatable
= false;
817 hc
->pre_plug
= ich9_pm_device_pre_plug_cb
;
818 hc
->plug
= ich9_pm_device_plug_cb
;
819 hc
->unplug_request
= ich9_pm_device_unplug_request_cb
;
820 hc
->unplug
= ich9_pm_device_unplug_cb
;
821 adevc
->ospm_status
= ich9_pm_ospm_status
;
822 adevc
->send_event
= ich9_send_gpe
;
823 adevc
->madt_cpu
= pc_madt_cpu_entry
;
826 static const TypeInfo ich9_lpc_info
= {
827 .name
= TYPE_ICH9_LPC_DEVICE
,
828 .parent
= TYPE_PCI_DEVICE
,
829 .instance_size
= sizeof(ICH9LPCState
),
830 .instance_init
= ich9_lpc_initfn
,
831 .class_init
= ich9_lpc_class_init
,
832 .interfaces
= (InterfaceInfo
[]) {
833 { TYPE_HOTPLUG_HANDLER
},
834 { TYPE_ACPI_DEVICE_IF
},
835 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
840 static void ich9_lpc_register(void)
842 type_register_static(&ich9_lpc_info
);
845 type_init(ich9_lpc_register
);