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hw/riscv: spike: Remove compile time XLEN checks
[qemu/ar7.git] / hw / i386 / acpi-build.c
blobf18b71dea90e272acd1a6809e629f6bbe4e8ee21
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/boards.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/rtc/mc146818rtc_regs.h"
49 #include "migration/vmstate.h"
50 #include "hw/mem/memory-device.h"
51 #include "hw/mem/nvdimm.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/reset.h"
54 #include "hw/hyperv/vmbus-bridge.h"
55
56 /* Supported chipsets: */
57 #include "hw/southbridge/piix.h"
58 #include "hw/acpi/pcihp.h"
59 #include "hw/i386/fw_cfg.h"
60 #include "hw/i386/ich9.h"
61 #include "hw/pci/pci_bus.h"
62 #include "hw/pci-host/q35.h"
63 #include "hw/i386/x86-iommu.h"
64
65 #include "hw/acpi/aml-build.h"
66 #include "hw/acpi/utils.h"
67 #include "hw/acpi/pci.h"
68
69 #include "qom/qom-qobject.h"
70 #include "hw/i386/amd_iommu.h"
71 #include "hw/i386/intel_iommu.h"
72
73 #include "hw/acpi/ipmi.h"
74 #include "hw/acpi/hmat.h"
75
76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
78 * a little bit, there should be plenty of free space since the DSDT
79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
80 */
81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
82 #define ACPI_BUILD_ALIGN_SIZE 0x1000
83
84 #define ACPI_BUILD_TABLE_SIZE 0x20000
85
86 /* #define DEBUG_ACPI_BUILD */
87 #ifdef DEBUG_ACPI_BUILD
88 #define ACPI_BUILD_DPRINTF(fmt, ...) \
89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
90 #else
91 #define ACPI_BUILD_DPRINTF(fmt, ...)
92 #endif
93
94 typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 bool smi_on_cpuhp;
99 bool smi_on_cpu_unplug;
100 bool pcihp_root_en;
101 uint8_t s4_val;
102 AcpiFadtData fadt;
103 uint16_t cpu_hp_io_base;
104 uint16_t pcihp_io_base;
105 uint16_t pcihp_io_len;
106 } AcpiPmInfo;
107
108 typedef struct AcpiMiscInfo {
109 bool is_piix4;
110 bool has_hpet;
111 TPMVersion tpm_version;
112 const unsigned char *dsdt_code;
113 unsigned dsdt_size;
114 uint16_t pvpanic_port;
115 uint16_t applesmc_io_base;
116 } AcpiMiscInfo;
117
118 typedef struct AcpiBuildPciBusHotplugState {
119 GArray *device_table;
120 GArray *notify_table;
121 struct AcpiBuildPciBusHotplugState *parent;
122 bool pcihp_bridge_en;
123 } AcpiBuildPciBusHotplugState;
124
125 typedef struct FwCfgTPMConfig {
126 uint32_t tpmppi_address;
127 uint8_t tpm_version;
128 uint8_t tpmppi_version;
129 } QEMU_PACKED FwCfgTPMConfig;
130
131 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
132
133 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
134 .space_id = AML_AS_SYSTEM_IO,
135 .address = NVDIMM_ACPI_IO_BASE,
136 .bit_width = NVDIMM_ACPI_IO_LEN << 3
137 };
138
139 static void init_common_fadt_data(MachineState *ms, Object *o,
140 AcpiFadtData *data)
141 {
142 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
143 AmlAddressSpace as = AML_AS_SYSTEM_IO;
144 AcpiFadtData fadt = {
145 .rev = 3,
146 .flags =
147 (1 << ACPI_FADT_F_WBINVD) |
148 (1 << ACPI_FADT_F_PROC_C1) |
149 (1 << ACPI_FADT_F_SLP_BUTTON) |
150 (1 << ACPI_FADT_F_RTC_S4) |
151 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
152 /* APIC destination mode ("Flat Logical") has an upper limit of 8
153 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
154 * used
155 */
156 ((ms->smp.max_cpus > 8) ?
157 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
158 .int_model = 1 /* Multiple APIC */,
159 .rtc_century = RTC_CENTURY,
160 .plvl2_lat = 0xfff /* C2 state not supported */,
161 .plvl3_lat = 0xfff /* C3 state not supported */,
162 .smi_cmd = ACPI_PORT_SMI_CMD,
163 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
164 .acpi_enable_cmd =
165 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
166 .acpi_disable_cmd =
167 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
168 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
169 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
170 .address = io + 0x04 },
171 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
172 .gpe0_blk = { .space_id = as, .bit_width =
173 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
174 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
175 },
176 };
177 *data = fadt;
178 }
179
180 static Object *object_resolve_type_unambiguous(const char *typename)
181 {
182 bool ambig;
183 Object *o = object_resolve_path_type("", typename, &ambig);
184
185 if (ambig || !o) {
186 return NULL;
187 }
188 return o;
189 }
190
191 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
192 {
193 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
194 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
195 Object *obj = piix ? piix : lpc;
196 QObject *o;
197 pm->cpu_hp_io_base = 0;
198 pm->pcihp_io_base = 0;
199 pm->pcihp_io_len = 0;
200 pm->smi_on_cpuhp = false;
201 pm->smi_on_cpu_unplug = false;
202
203 assert(obj);
204 init_common_fadt_data(machine, obj, &pm->fadt);
205 if (piix) {
206 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
207 pm->fadt.rev = 1;
208 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
209 pm->pcihp_io_base =
210 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
211 pm->pcihp_io_len =
212 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
213 }
214 if (lpc) {
215 uint64_t smi_features = object_property_get_uint(lpc,
216 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
217 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
218 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
219 pm->fadt.reset_reg = r;
220 pm->fadt.reset_val = 0xf;
221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
223 pm->smi_on_cpuhp =
224 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
225 pm->smi_on_cpu_unplug =
226 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
227 }
228
229 /* The above need not be conditional on machine type because the reset port
230 * happens to be the same on PIIX (pc) and ICH9 (q35). */
231 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
232
233 /* Fill in optional s3/s4 related properties */
234 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
235 if (o) {
236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
237 } else {
238 pm->s3_disabled = false;
239 }
240 qobject_unref(o);
241 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
242 if (o) {
243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
244 } else {
245 pm->s4_disabled = false;
246 }
247 qobject_unref(o);
248 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
249 if (o) {
250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
251 } else {
252 pm->s4_val = false;
253 }
254 qobject_unref(o);
255
256 pm->pcihp_bridge_en =
257 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
258 NULL);
259 pm->pcihp_root_en =
260 object_property_get_bool(obj, "acpi-root-pci-hotplug",
261 NULL);
262 }
263
264 static void acpi_get_misc_info(AcpiMiscInfo *info)
265 {
266 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
267 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
268 assert(!!piix != !!lpc);
269
270 if (piix) {
271 info->is_piix4 = true;
272 }
273 if (lpc) {
274 info->is_piix4 = false;
275 }
276
277 info->has_hpet = hpet_find();
278 info->tpm_version = tpm_get_version(tpm_find());
279 info->pvpanic_port = pvpanic_port();
280 info->applesmc_io_base = applesmc_port();
281 }
282
283 /*
284 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
285 * On i386 arch we only have two pci hosts, so we can look only for them.
286 */
287 static Object *acpi_get_i386_pci_host(void)
288 {
289 PCIHostState *host;
290
291 host = OBJECT_CHECK(PCIHostState,
292 object_resolve_path("/machine/i440fx", NULL),
293 TYPE_PCI_HOST_BRIDGE);
294 if (!host) {
295 host = OBJECT_CHECK(PCIHostState,
296 object_resolve_path("/machine/q35", NULL),
297 TYPE_PCI_HOST_BRIDGE);
298 }
299
300 return OBJECT(host);
301 }
302
303 static void acpi_get_pci_holes(Range *hole, Range *hole64)
304 {
305 Object *pci_host;
306
307 pci_host = acpi_get_i386_pci_host();
308 g_assert(pci_host);
309
310 range_set_bounds1(hole,
311 object_property_get_uint(pci_host,
312 PCI_HOST_PROP_PCI_HOLE_START,
313 NULL),
314 object_property_get_uint(pci_host,
315 PCI_HOST_PROP_PCI_HOLE_END,
316 NULL));
317 range_set_bounds1(hole64,
318 object_property_get_uint(pci_host,
319 PCI_HOST_PROP_PCI_HOLE64_START,
320 NULL),
321 object_property_get_uint(pci_host,
322 PCI_HOST_PROP_PCI_HOLE64_END,
323 NULL));
324 }
325
326 static void acpi_align_size(GArray *blob, unsigned align)
327 {
328 /* Align size to multiple of given size. This reduces the chance
329 * we need to change size in the future (breaking cross version migration).
330 */
331 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
332 }
333
334 /* FACS */
335 static void
336 build_facs(GArray *table_data)
337 {
338 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
339 memcpy(&facs->signature, "FACS", 4);
340 facs->length = cpu_to_le32(sizeof(*facs));
341 }
342
343 static void build_append_pcihp_notify_entry(Aml *method, int slot)
344 {
345 Aml *if_ctx;
346 int32_t devfn = PCI_DEVFN(slot, 0);
347
348 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
349 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
350 aml_append(method, if_ctx);
351 }
352
353 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
354 bool pcihp_bridge_en)
355 {
356 Aml *dev, *notify_method = NULL, *method;
357 QObject *bsel;
358 PCIBus *sec;
359 int i;
360
361 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
362 if (bsel) {
363 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
364
365 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
366 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
367 }
368
369 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
370 DeviceClass *dc;
371 PCIDeviceClass *pc;
372 PCIDevice *pdev = bus->devices[i];
373 int slot = PCI_SLOT(i);
374 bool hotplug_enabled_dev;
375 bool bridge_in_acpi;
376 bool cold_plugged_bridge;
377
378 if (!pdev) {
379 if (bsel) { /* add hotplug slots for non present devices */
380 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
381 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
382 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
383 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
384 aml_append(method,
385 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
386 );
387 aml_append(dev, method);
388 aml_append(parent_scope, dev);
389
390 build_append_pcihp_notify_entry(notify_method, slot);
391 }
392 continue;
393 }
394
395 pc = PCI_DEVICE_GET_CLASS(pdev);
396 dc = DEVICE_GET_CLASS(pdev);
397
398 /*
399 * Cold plugged bridges aren't themselves hot-pluggable.
400 * Hotplugged bridges *are* hot-pluggable.
401 */
402 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
403 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
404
405 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
406
407 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
408 continue;
409 }
410
411 /* start to compose PCI slot descriptor */
412 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
413 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
414
415 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
416 /* add VGA specific AML methods */
417 int s3d;
418
419 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
420 s3d = 3;
421 } else {
422 s3d = 0;
423 }
424
425 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
426 aml_append(method, aml_return(aml_int(0)));
427 aml_append(dev, method);
428
429 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
430 aml_append(method, aml_return(aml_int(0)));
431 aml_append(dev, method);
432
433 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
434 aml_append(method, aml_return(aml_int(s3d)));
435 aml_append(dev, method);
436 } else if (hotplug_enabled_dev) {
437 /* add _SUN/_EJ0 to make slot hotpluggable */
438 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
439
440 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
441 aml_append(method,
442 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
443 );
444 aml_append(dev, method);
445
446 if (bsel) {
447 build_append_pcihp_notify_entry(notify_method, slot);
448 }
449 } else if (bridge_in_acpi) {
450 /*
451 * device is coldplugged bridge,
452 * add child device descriptions into its scope
453 */
454 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
455
456 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
457 }
458 /* slot descriptor has been composed, add it into parent context */
459 aml_append(parent_scope, dev);
460 }
461
462 if (bsel) {
463 aml_append(parent_scope, notify_method);
464 }
465
466 /* Append PCNT method to notify about events on local and child buses.
467 * Add this method for root bus only when hotplug is enabled since DSDT
468 * expects it.
469 */
470 if (bsel || pcihp_bridge_en) {
471 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
472
473 /* If bus supports hotplug select it and notify about local events */
474 if (bsel) {
475 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
476
477 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
478 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
479 aml_int(1))); /* Device Check */
480 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
481 aml_int(3))); /* Eject Request */
482 }
483
484 /* Notify about child bus events in any case */
485 if (pcihp_bridge_en) {
486 QLIST_FOREACH(sec, &bus->child, sibling) {
487 int32_t devfn = sec->parent_dev->devfn;
488
489 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
490 continue;
491 }
492
493 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
494 }
495 }
496
497 aml_append(parent_scope, method);
498 }
499 qobject_unref(bsel);
500 }
501
502 /**
503 * build_prt_entry:
504 * @link_name: link name for PCI route entry
505 *
506 * build AML package containing a PCI route entry for @link_name
507 */
508 static Aml *build_prt_entry(const char *link_name)
509 {
510 Aml *a_zero = aml_int(0);
511 Aml *pkg = aml_package(4);
512 aml_append(pkg, a_zero);
513 aml_append(pkg, a_zero);
514 aml_append(pkg, aml_name("%s", link_name));
515 aml_append(pkg, a_zero);
516 return pkg;
517 }
518
519 /*
520 * initialize_route - Initialize the interrupt routing rule
521 * through a specific LINK:
522 * if (lnk_idx == idx)
523 * route using link 'link_name'
524 */
525 static Aml *initialize_route(Aml *route, const char *link_name,
526 Aml *lnk_idx, int idx)
527 {
528 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
529 Aml *pkg = build_prt_entry(link_name);
530
531 aml_append(if_ctx, aml_store(pkg, route));
532
533 return if_ctx;
534 }
535
536 /*
537 * build_prt - Define interrupt rounting rules
538 *
539 * Returns an array of 128 routes, one for each device,
540 * based on device location.
541 * The main goal is to equaly distribute the interrupts
542 * over the 4 existing ACPI links (works only for i440fx).
543 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
544 *
545 */
546 static Aml *build_prt(bool is_pci0_prt)
547 {
548 Aml *method, *while_ctx, *pin, *res;
549
550 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
551 res = aml_local(0);
552 pin = aml_local(1);
553 aml_append(method, aml_store(aml_package(128), res));
554 aml_append(method, aml_store(aml_int(0), pin));
555
556 /* while (pin < 128) */
557 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
558 {
559 Aml *slot = aml_local(2);
560 Aml *lnk_idx = aml_local(3);
561 Aml *route = aml_local(4);
562
563 /* slot = pin >> 2 */
564 aml_append(while_ctx,
565 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
566 /* lnk_idx = (slot + pin) & 3 */
567 aml_append(while_ctx,
568 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
569 lnk_idx));
570
571 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
572 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
573 if (is_pci0_prt) {
574 Aml *if_device_1, *if_pin_4, *else_pin_4;
575
576 /* device 1 is the power-management device, needs SCI */
577 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
578 {
579 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
580 {
581 aml_append(if_pin_4,
582 aml_store(build_prt_entry("LNKS"), route));
583 }
584 aml_append(if_device_1, if_pin_4);
585 else_pin_4 = aml_else();
586 {
587 aml_append(else_pin_4,
588 aml_store(build_prt_entry("LNKA"), route));
589 }
590 aml_append(if_device_1, else_pin_4);
591 }
592 aml_append(while_ctx, if_device_1);
593 } else {
594 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
595 }
596 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
597 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
598
599 /* route[0] = 0x[slot]FFFF */
600 aml_append(while_ctx,
601 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
602 NULL),
603 aml_index(route, aml_int(0))));
604 /* route[1] = pin & 3 */
605 aml_append(while_ctx,
606 aml_store(aml_and(pin, aml_int(3), NULL),
607 aml_index(route, aml_int(1))));
608 /* res[pin] = route */
609 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
610 /* pin++ */
611 aml_append(while_ctx, aml_increment(pin));
612 }
613 aml_append(method, while_ctx);
614 /* return res*/
615 aml_append(method, aml_return(res));
616
617 return method;
618 }
619
620 static void build_hpet_aml(Aml *table)
621 {
622 Aml *crs;
623 Aml *field;
624 Aml *method;
625 Aml *if_ctx;
626 Aml *scope = aml_scope("_SB");
627 Aml *dev = aml_device("HPET");
628 Aml *zero = aml_int(0);
629 Aml *id = aml_local(0);
630 Aml *period = aml_local(1);
631
632 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
633 aml_append(dev, aml_name_decl("_UID", zero));
634
635 aml_append(dev,
636 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
637 HPET_LEN));
638 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
639 aml_append(field, aml_named_field("VEND", 32));
640 aml_append(field, aml_named_field("PRD", 32));
641 aml_append(dev, field);
642
643 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
644 aml_append(method, aml_store(aml_name("VEND"), id));
645 aml_append(method, aml_store(aml_name("PRD"), period));
646 aml_append(method, aml_shiftright(id, aml_int(16), id));
647 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
648 aml_equal(id, aml_int(0xffff))));
649 {
650 aml_append(if_ctx, aml_return(zero));
651 }
652 aml_append(method, if_ctx);
653
654 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
655 aml_lgreater(period, aml_int(100000000))));
656 {
657 aml_append(if_ctx, aml_return(zero));
658 }
659 aml_append(method, if_ctx);
660
661 aml_append(method, aml_return(aml_int(0x0F)));
662 aml_append(dev, method);
663
664 crs = aml_resource_template();
665 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
666 aml_append(dev, aml_name_decl("_CRS", crs));
667
668 aml_append(scope, dev);
669 aml_append(table, scope);
670 }
671
672 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
673 {
674 Aml *dev;
675 Aml *method;
676 Aml *crs;
677
678 dev = aml_device("VMBS");
679 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
680 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
681 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
682 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
683
684 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
685 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
686 aml_name("STA")));
687 aml_append(dev, method);
688
689 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
690 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
691 aml_name("STA")));
692 aml_append(dev, method);
693
694 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
695 aml_append(method, aml_return(aml_name("STA")));
696 aml_append(dev, method);
697
698 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
699
700 crs = aml_resource_template();
701 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
702 aml_append(dev, aml_name_decl("_CRS", crs));
703
704 return dev;
705 }
706
707 static void build_isa_devices_aml(Aml *table)
708 {
709 bool ambiguous;
710 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
711 Aml *scope;
712
713 assert(obj && !ambiguous);
714
715 scope = aml_scope("_SB.PCI0.ISA");
716 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
717 isa_build_aml(ISA_BUS(obj), scope);
718
719 aml_append(table, scope);
720 }
721
722 static void build_dbg_aml(Aml *table)
723 {
724 Aml *field;
725 Aml *method;
726 Aml *while_ctx;
727 Aml *scope = aml_scope("\\");
728 Aml *buf = aml_local(0);
729 Aml *len = aml_local(1);
730 Aml *idx = aml_local(2);
731
732 aml_append(scope,
733 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
734 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
735 aml_append(field, aml_named_field("DBGB", 8));
736 aml_append(scope, field);
737
738 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
739
740 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
741 aml_append(method, aml_to_buffer(buf, buf));
742 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
743 aml_append(method, aml_store(aml_int(0), idx));
744
745 while_ctx = aml_while(aml_lless(idx, len));
746 aml_append(while_ctx,
747 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
748 aml_append(while_ctx, aml_increment(idx));
749 aml_append(method, while_ctx);
750
751 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
752 aml_append(scope, method);
753
754 aml_append(table, scope);
755 }
756
757 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
758 {
759 Aml *dev;
760 Aml *crs;
761 Aml *method;
762 uint32_t irqs[] = {5, 10, 11};
763
764 dev = aml_device("%s", name);
765 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
766 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
767
768 crs = aml_resource_template();
769 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
770 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
771 aml_append(dev, aml_name_decl("_PRS", crs));
772
773 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
774 aml_append(method, aml_return(aml_call1("IQST", reg)));
775 aml_append(dev, method);
776
777 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
778 aml_append(method, aml_or(reg, aml_int(0x80), reg));
779 aml_append(dev, method);
780
781 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
782 aml_append(method, aml_return(aml_call1("IQCR", reg)));
783 aml_append(dev, method);
784
785 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
786 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
787 aml_append(method, aml_store(aml_name("PRRI"), reg));
788 aml_append(dev, method);
789
790 return dev;
791 }
792
793 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
794 {
795 Aml *dev;
796 Aml *crs;
797 Aml *method;
798 uint32_t irqs;
799
800 dev = aml_device("%s", name);
801 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
802 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
803
804 crs = aml_resource_template();
805 irqs = gsi;
806 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
807 AML_SHARED, &irqs, 1));
808 aml_append(dev, aml_name_decl("_PRS", crs));
809
810 aml_append(dev, aml_name_decl("_CRS", crs));
811
812 /*
813 * _DIS can be no-op because the interrupt cannot be disabled.
814 */
815 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
816 aml_append(dev, method);
817
818 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
819 aml_append(dev, method);
820
821 return dev;
822 }
823
824 /* _CRS method - get current settings */
825 static Aml *build_iqcr_method(bool is_piix4)
826 {
827 Aml *if_ctx;
828 uint32_t irqs;
829 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
830 Aml *crs = aml_resource_template();
831
832 irqs = 0;
833 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
834 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
835 aml_append(method, aml_name_decl("PRR0", crs));
836
837 aml_append(method,
838 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
839
840 if (is_piix4) {
841 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
842 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
843 aml_append(method, if_ctx);
844 } else {
845 aml_append(method,
846 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
847 aml_name("PRRI")));
848 }
849
850 aml_append(method, aml_return(aml_name("PRR0")));
851 return method;
852 }
853
854 /* _STA method - get status */
855 static Aml *build_irq_status_method(void)
856 {
857 Aml *if_ctx;
858 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
859
860 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
861 aml_append(if_ctx, aml_return(aml_int(0x09)));
862 aml_append(method, if_ctx);
863 aml_append(method, aml_return(aml_int(0x0B)));
864 return method;
865 }
866
867 static void build_piix4_pci0_int(Aml *table)
868 {
869 Aml *dev;
870 Aml *crs;
871 Aml *field;
872 Aml *method;
873 uint32_t irqs;
874 Aml *sb_scope = aml_scope("_SB");
875 Aml *pci0_scope = aml_scope("PCI0");
876
877 aml_append(pci0_scope, build_prt(true));
878 aml_append(sb_scope, pci0_scope);
879
880 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
881 aml_append(field, aml_named_field("PRQ0", 8));
882 aml_append(field, aml_named_field("PRQ1", 8));
883 aml_append(field, aml_named_field("PRQ2", 8));
884 aml_append(field, aml_named_field("PRQ3", 8));
885 aml_append(sb_scope, field);
886
887 aml_append(sb_scope, build_irq_status_method());
888 aml_append(sb_scope, build_iqcr_method(true));
889
890 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
891 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
892 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
893 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
894
895 dev = aml_device("LNKS");
896 {
897 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
898 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
899
900 crs = aml_resource_template();
901 irqs = 9;
902 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
903 AML_ACTIVE_HIGH, AML_SHARED,
904 &irqs, 1));
905 aml_append(dev, aml_name_decl("_PRS", crs));
906
907 /* The SCI cannot be disabled and is always attached to GSI 9,
908 * so these are no-ops. We only need this link to override the
909 * polarity to active high and match the content of the MADT.
910 */
911 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
912 aml_append(method, aml_return(aml_int(0x0b)));
913 aml_append(dev, method);
914
915 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
916 aml_append(dev, method);
917
918 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
919 aml_append(method, aml_return(aml_name("_PRS")));
920 aml_append(dev, method);
921
922 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
923 aml_append(dev, method);
924 }
925 aml_append(sb_scope, dev);
926
927 aml_append(table, sb_scope);
928 }
929
930 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
931 {
932 int i;
933 int head;
934 Aml *pkg;
935 char base = name[3] < 'E' ? 'A' : 'E';
936 char *s = g_strdup(name);
937 Aml *a_nr = aml_int((nr << 16) | 0xffff);
938
939 assert(strlen(s) == 4);
940
941 head = name[3] - base;
942 for (i = 0; i < 4; i++) {
943 if (head + i > 3) {
944 head = i * -1;
945 }
946 s[3] = base + head + i;
947 pkg = aml_package(4);
948 aml_append(pkg, a_nr);
949 aml_append(pkg, aml_int(i));
950 aml_append(pkg, aml_name("%s", s));
951 aml_append(pkg, aml_int(0));
952 aml_append(ctx, pkg);
953 }
954 g_free(s);
955 }
956
957 static Aml *build_q35_routing_table(const char *str)
958 {
959 int i;
960 Aml *pkg;
961 char *name = g_strdup_printf("%s ", str);
962
963 pkg = aml_package(128);
964 for (i = 0; i < 0x18; i++) {
965 name[3] = 'E' + (i & 0x3);
966 append_q35_prt_entry(pkg, i, name);
967 }
968
969 name[3] = 'E';
970 append_q35_prt_entry(pkg, 0x18, name);
971
972 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
973 for (i = 0x0019; i < 0x1e; i++) {
974 name[3] = 'A';
975 append_q35_prt_entry(pkg, i, name);
976 }
977
978 /* PCIe->PCI bridge. use PIRQ[E-H] */
979 name[3] = 'E';
980 append_q35_prt_entry(pkg, 0x1e, name);
981 name[3] = 'A';
982 append_q35_prt_entry(pkg, 0x1f, name);
983
984 g_free(name);
985 return pkg;
986 }
987
988 static void build_q35_pci0_int(Aml *table)
989 {
990 Aml *field;
991 Aml *method;
992 Aml *sb_scope = aml_scope("_SB");
993 Aml *pci0_scope = aml_scope("PCI0");
994
995 /* Zero => PIC mode, One => APIC Mode */
996 aml_append(table, aml_name_decl("PICF", aml_int(0)));
997 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
998 {
999 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1000 }
1001 aml_append(table, method);
1002
1003 aml_append(pci0_scope,
1004 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1005 aml_append(pci0_scope,
1006 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1007
1008 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1009 {
1010 Aml *if_ctx;
1011 Aml *else_ctx;
1012
1013 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1014 section 6.2.8.1 */
1015 /* Note: we provide the same info as the PCI routing
1016 table of the Bochs BIOS */
1017 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1018 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1019 aml_append(method, if_ctx);
1020 else_ctx = aml_else();
1021 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1022 aml_append(method, else_ctx);
1023 }
1024 aml_append(pci0_scope, method);
1025 aml_append(sb_scope, pci0_scope);
1026
1027 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1028 aml_append(field, aml_named_field("PRQA", 8));
1029 aml_append(field, aml_named_field("PRQB", 8));
1030 aml_append(field, aml_named_field("PRQC", 8));
1031 aml_append(field, aml_named_field("PRQD", 8));
1032 aml_append(field, aml_reserved_field(0x20));
1033 aml_append(field, aml_named_field("PRQE", 8));
1034 aml_append(field, aml_named_field("PRQF", 8));
1035 aml_append(field, aml_named_field("PRQG", 8));
1036 aml_append(field, aml_named_field("PRQH", 8));
1037 aml_append(sb_scope, field);
1038
1039 aml_append(sb_scope, build_irq_status_method());
1040 aml_append(sb_scope, build_iqcr_method(false));
1041
1042 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1043 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1044 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1045 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1046 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1047 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1048 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1049 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1050
1051 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1052 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1053 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1054 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1055 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1056 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1057 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1058 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1059
1060 aml_append(table, sb_scope);
1061 }
1062
1063 static void build_q35_isa_bridge(Aml *table)
1064 {
1065 Aml *dev;
1066 Aml *scope;
1067
1068 scope = aml_scope("_SB.PCI0");
1069 dev = aml_device("ISA");
1070 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1071
1072 /* ICH9 PCI to ISA irq remapping */
1073 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1074 aml_int(0x60), 0x0C));
1075
1076 aml_append(scope, dev);
1077 aml_append(table, scope);
1078 }
1079
1080 static void build_piix4_isa_bridge(Aml *table)
1081 {
1082 Aml *dev;
1083 Aml *scope;
1084
1085 scope = aml_scope("_SB.PCI0");
1086 dev = aml_device("ISA");
1087 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1088
1089 /* PIIX PCI to ISA irq remapping */
1090 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1091 aml_int(0x60), 0x04));
1092
1093 aml_append(scope, dev);
1094 aml_append(table, scope);
1095 }
1096
1097 static void build_piix4_pci_hotplug(Aml *table)
1098 {
1099 Aml *scope;
1100 Aml *field;
1101 Aml *method;
1102
1103 scope = aml_scope("_SB.PCI0");
1104
1105 aml_append(scope,
1106 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1107 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1108 aml_append(field, aml_named_field("PCIU", 32));
1109 aml_append(field, aml_named_field("PCID", 32));
1110 aml_append(scope, field);
1111
1112 aml_append(scope,
1113 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1114 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1115 aml_append(field, aml_named_field("B0EJ", 32));
1116 aml_append(scope, field);
1117
1118 aml_append(scope,
1119 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1120 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1121 aml_append(field, aml_named_field("BNUM", 32));
1122 aml_append(scope, field);
1123
1124 aml_append(scope, aml_mutex("BLCK", 0));
1125
1126 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1127 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1128 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1129 aml_append(method,
1130 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1131 aml_append(method, aml_release(aml_name("BLCK")));
1132 aml_append(method, aml_return(aml_int(0)));
1133 aml_append(scope, method);
1134
1135 aml_append(table, scope);
1136 }
1137
1138 static Aml *build_q35_osc_method(void)
1139 {
1140 Aml *if_ctx;
1141 Aml *if_ctx2;
1142 Aml *else_ctx;
1143 Aml *method;
1144 Aml *a_cwd1 = aml_name("CDW1");
1145 Aml *a_ctrl = aml_local(0);
1146
1147 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1148 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1149
1150 if_ctx = aml_if(aml_equal(
1151 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1152 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1153 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1154
1155 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1156
1157 /*
1158 * Always allow native PME, AER (no dependencies)
1159 * Allow SHPC (PCI bridges can have SHPC controller)
1160 */
1161 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1162
1163 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1164 /* Unknown revision */
1165 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1166 aml_append(if_ctx, if_ctx2);
1167
1168 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1169 /* Capabilities bits were masked */
1170 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1171 aml_append(if_ctx, if_ctx2);
1172
1173 /* Update DWORD3 in the buffer */
1174 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1175 aml_append(method, if_ctx);
1176
1177 else_ctx = aml_else();
1178 /* Unrecognized UUID */
1179 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1180 aml_append(method, else_ctx);
1181
1182 aml_append(method, aml_return(aml_arg(3)));
1183 return method;
1184 }
1185
1186 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1187 {
1188 Aml *scope = aml_scope("_SB.PCI0");
1189 Aml *dev = aml_device("SMB0");
1190
1191 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1192 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1193 aml_append(scope, dev);
1194 aml_append(table, scope);
1195 }
1196
1197 static void
1198 build_dsdt(GArray *table_data, BIOSLinker *linker,
1199 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1200 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1201 {
1202 CrsRangeEntry *entry;
1203 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1204 CrsRangeSet crs_range_set;
1205 PCMachineState *pcms = PC_MACHINE(machine);
1206 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1207 X86MachineState *x86ms = X86_MACHINE(machine);
1208 AcpiMcfgInfo mcfg;
1209 uint32_t nr_mem = machine->ram_slots;
1210 int root_bus_limit = 0xFF;
1211 PCIBus *bus = NULL;
1212 TPMIf *tpm = tpm_find();
1213 int i;
1214 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1215
1216 dsdt = init_aml_allocator();
1217
1218 /* Reserve space for header */
1219 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1220
1221 build_dbg_aml(dsdt);
1222 if (misc->is_piix4) {
1223 sb_scope = aml_scope("_SB");
1224 dev = aml_device("PCI0");
1225 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1226 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1227 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1228 aml_append(sb_scope, dev);
1229 aml_append(dsdt, sb_scope);
1230
1231 build_hpet_aml(dsdt);
1232 build_piix4_isa_bridge(dsdt);
1233 build_isa_devices_aml(dsdt);
1234 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1235 build_piix4_pci_hotplug(dsdt);
1236 }
1237 build_piix4_pci0_int(dsdt);
1238 } else {
1239 sb_scope = aml_scope("_SB");
1240 dev = aml_device("PCI0");
1241 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1242 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1243 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1244 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1245 aml_append(dev, build_q35_osc_method());
1246 aml_append(sb_scope, dev);
1247
1248 if (pm->smi_on_cpuhp) {
1249 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1250 dev = aml_device("PCI0.SMI0");
1251 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1252 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1253 crs = aml_resource_template();
1254 aml_append(crs,
1255 aml_io(
1256 AML_DECODE16,
1257 ACPI_PORT_SMI_CMD,
1258 ACPI_PORT_SMI_CMD,
1259 1,
1260 2)
1261 );
1262 aml_append(dev, aml_name_decl("_CRS", crs));
1263 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1264 aml_int(ACPI_PORT_SMI_CMD), 2));
1265 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1266 AML_WRITE_AS_ZEROS);
1267 aml_append(field, aml_named_field("SMIC", 8));
1268 aml_append(field, aml_reserved_field(8));
1269 aml_append(dev, field);
1270 aml_append(sb_scope, dev);
1271 }
1272
1273 aml_append(dsdt, sb_scope);
1274
1275 build_hpet_aml(dsdt);
1276 build_q35_isa_bridge(dsdt);
1277 build_isa_devices_aml(dsdt);
1278 build_q35_pci0_int(dsdt);
1279 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1280 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1281 }
1282 }
1283
1284 if (vmbus_bridge) {
1285 sb_scope = aml_scope("_SB");
1286 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1287 aml_append(dsdt, sb_scope);
1288 }
1289
1290 if (pcmc->legacy_cpu_hotplug) {
1291 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1292 } else {
1293 CPUHotplugFeatures opts = {
1294 .acpi_1_compatible = true, .has_legacy_cphp = true,
1295 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1296 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1297 };
1298 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1299 "\\_SB.PCI0", "\\_GPE._E02");
1300 }
1301
1302 if (pcms->memhp_io_base && nr_mem) {
1303 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1304 "\\_GPE._E03", AML_SYSTEM_IO,
1305 pcms->memhp_io_base);
1306 }
1307
1308 scope = aml_scope("_GPE");
1309 {
1310 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1311
1312 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1313 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1314 aml_append(method,
1315 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1316 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1317 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1318 aml_append(scope, method);
1319 }
1320
1321 if (machine->nvdimms_state->is_enabled) {
1322 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1323 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1324 aml_int(0x80)));
1325 aml_append(scope, method);
1326 }
1327 }
1328 aml_append(dsdt, scope);
1329
1330 crs_range_set_init(&crs_range_set);
1331 bus = PC_MACHINE(machine)->bus;
1332 if (bus) {
1333 QLIST_FOREACH(bus, &bus->child, sibling) {
1334 uint8_t bus_num = pci_bus_num(bus);
1335 uint8_t numa_node = pci_bus_numa_node(bus);
1336
1337 /* look only for expander root buses */
1338 if (!pci_bus_is_root(bus)) {
1339 continue;
1340 }
1341
1342 if (bus_num < root_bus_limit) {
1343 root_bus_limit = bus_num - 1;
1344 }
1345
1346 scope = aml_scope("\\_SB");
1347 dev = aml_device("PC%.02X", bus_num);
1348 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1349 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1350 if (pci_bus_is_express(bus)) {
1351 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1352 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1353 aml_append(dev, build_q35_osc_method());
1354 } else {
1355 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1356 }
1357
1358 if (numa_node != NUMA_NODE_UNASSIGNED) {
1359 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1360 }
1361
1362 aml_append(dev, build_prt(false));
1363 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1364 aml_append(dev, aml_name_decl("_CRS", crs));
1365 aml_append(scope, dev);
1366 aml_append(dsdt, scope);
1367 }
1368 }
1369
1370 /*
1371 * At this point crs_range_set has all the ranges used by pci
1372 * busses *other* than PCI0. These ranges will be excluded from
1373 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1374 * too.
1375 */
1376 if (acpi_get_mcfg(&mcfg)) {
1377 crs_range_insert(crs_range_set.mem_ranges,
1378 mcfg.base, mcfg.base + mcfg.size - 1);
1379 }
1380
1381 scope = aml_scope("\\_SB.PCI0");
1382 /* build PCI0._CRS */
1383 crs = aml_resource_template();
1384 aml_append(crs,
1385 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1386 0x0000, 0x0, root_bus_limit,
1387 0x0000, root_bus_limit + 1));
1388 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1389
1390 aml_append(crs,
1391 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1392 AML_POS_DECODE, AML_ENTIRE_RANGE,
1393 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1394
1395 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1396 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1397 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1398 aml_append(crs,
1399 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1400 AML_POS_DECODE, AML_ENTIRE_RANGE,
1401 0x0000, entry->base, entry->limit,
1402 0x0000, entry->limit - entry->base + 1));
1403 }
1404
1405 aml_append(crs,
1406 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1407 AML_CACHEABLE, AML_READ_WRITE,
1408 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1409
1410 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1411 range_lob(pci_hole),
1412 range_upb(pci_hole));
1413 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1414 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1415 aml_append(crs,
1416 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1417 AML_NON_CACHEABLE, AML_READ_WRITE,
1418 0, entry->base, entry->limit,
1419 0, entry->limit - entry->base + 1));
1420 }
1421
1422 if (!range_is_empty(pci_hole64)) {
1423 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1424 range_lob(pci_hole64),
1425 range_upb(pci_hole64));
1426 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1427 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1428 aml_append(crs,
1429 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1430 AML_MAX_FIXED,
1431 AML_CACHEABLE, AML_READ_WRITE,
1432 0, entry->base, entry->limit,
1433 0, entry->limit - entry->base + 1));
1434 }
1435 }
1436
1437 if (TPM_IS_TIS_ISA(tpm_find())) {
1438 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1439 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1440 }
1441 aml_append(scope, aml_name_decl("_CRS", crs));
1442
1443 /* reserve GPE0 block resources */
1444 dev = aml_device("GPE0");
1445 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1446 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1447 /* device present, functioning, decoding, not shown in UI */
1448 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1449 crs = aml_resource_template();
1450 aml_append(crs,
1451 aml_io(
1452 AML_DECODE16,
1453 pm->fadt.gpe0_blk.address,
1454 pm->fadt.gpe0_blk.address,
1455 1,
1456 pm->fadt.gpe0_blk.bit_width / 8)
1457 );
1458 aml_append(dev, aml_name_decl("_CRS", crs));
1459 aml_append(scope, dev);
1460
1461 crs_range_set_free(&crs_range_set);
1462
1463 /* reserve PCIHP resources */
1464 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1465 dev = aml_device("PHPR");
1466 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1467 aml_append(dev,
1468 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1469 /* device present, functioning, decoding, not shown in UI */
1470 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1471 crs = aml_resource_template();
1472 aml_append(crs,
1473 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1474 pm->pcihp_io_len)
1475 );
1476 aml_append(dev, aml_name_decl("_CRS", crs));
1477 aml_append(scope, dev);
1478 }
1479 aml_append(dsdt, scope);
1480
1481 /* create S3_ / S4_ / S5_ packages if necessary */
1482 scope = aml_scope("\\");
1483 if (!pm->s3_disabled) {
1484 pkg = aml_package(4);
1485 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1486 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1487 aml_append(pkg, aml_int(0)); /* reserved */
1488 aml_append(pkg, aml_int(0)); /* reserved */
1489 aml_append(scope, aml_name_decl("_S3", pkg));
1490 }
1491
1492 if (!pm->s4_disabled) {
1493 pkg = aml_package(4);
1494 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1495 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1496 aml_append(pkg, aml_int(pm->s4_val));
1497 aml_append(pkg, aml_int(0)); /* reserved */
1498 aml_append(pkg, aml_int(0)); /* reserved */
1499 aml_append(scope, aml_name_decl("_S4", pkg));
1500 }
1501
1502 pkg = aml_package(4);
1503 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1504 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1505 aml_append(pkg, aml_int(0)); /* reserved */
1506 aml_append(pkg, aml_int(0)); /* reserved */
1507 aml_append(scope, aml_name_decl("_S5", pkg));
1508 aml_append(dsdt, scope);
1509
1510 /* create fw_cfg node, unconditionally */
1511 {
1512 scope = aml_scope("\\_SB.PCI0");
1513 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1514 aml_append(dsdt, scope);
1515 }
1516
1517 if (misc->applesmc_io_base) {
1518 scope = aml_scope("\\_SB.PCI0.ISA");
1519 dev = aml_device("SMC");
1520
1521 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1522 /* device present, functioning, decoding, not shown in UI */
1523 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1524
1525 crs = aml_resource_template();
1526 aml_append(crs,
1527 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1528 0x01, APPLESMC_MAX_DATA_LENGTH)
1529 );
1530 aml_append(crs, aml_irq_no_flags(6));
1531 aml_append(dev, aml_name_decl("_CRS", crs));
1532
1533 aml_append(scope, dev);
1534 aml_append(dsdt, scope);
1535 }
1536
1537 if (misc->pvpanic_port) {
1538 scope = aml_scope("\\_SB.PCI0.ISA");
1539
1540 dev = aml_device("PEVT");
1541 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1542
1543 crs = aml_resource_template();
1544 aml_append(crs,
1545 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1546 );
1547 aml_append(dev, aml_name_decl("_CRS", crs));
1548
1549 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1550 aml_int(misc->pvpanic_port), 1));
1551 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1552 aml_append(field, aml_named_field("PEPT", 8));
1553 aml_append(dev, field);
1554
1555 /* device present, functioning, decoding, shown in UI */
1556 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1557
1558 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1559 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1560 aml_append(method, aml_return(aml_local(0)));
1561 aml_append(dev, method);
1562
1563 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1564 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1565 aml_append(dev, method);
1566
1567 aml_append(scope, dev);
1568 aml_append(dsdt, scope);
1569 }
1570
1571 sb_scope = aml_scope("\\_SB");
1572 {
1573 Object *pci_host;
1574 PCIBus *bus = NULL;
1575
1576 pci_host = acpi_get_i386_pci_host();
1577 if (pci_host) {
1578 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1579 }
1580
1581 if (bus) {
1582 Aml *scope = aml_scope("PCI0");
1583 /* Scan all PCI buses. Generate tables to support hotplug. */
1584 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1585
1586 if (TPM_IS_TIS_ISA(tpm)) {
1587 if (misc->tpm_version == TPM_VERSION_2_0) {
1588 dev = aml_device("TPM");
1589 aml_append(dev, aml_name_decl("_HID",
1590 aml_string("MSFT0101")));
1591 } else {
1592 dev = aml_device("ISA.TPM");
1593 aml_append(dev, aml_name_decl("_HID",
1594 aml_eisaid("PNP0C31")));
1595 }
1596
1597 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1598 crs = aml_resource_template();
1599 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1600 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1601 /*
1602 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1603 Rewrite to take IRQ from TPM device model and
1604 fix default IRQ value there to use some unused IRQ
1605 */
1606 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1607 aml_append(dev, aml_name_decl("_CRS", crs));
1608
1609 tpm_build_ppi_acpi(tpm, dev);
1610
1611 aml_append(scope, dev);
1612 }
1613
1614 aml_append(sb_scope, scope);
1615 }
1616 }
1617
1618 if (TPM_IS_CRB(tpm)) {
1619 dev = aml_device("TPM");
1620 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1621 crs = aml_resource_template();
1622 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1623 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1624 aml_append(dev, aml_name_decl("_CRS", crs));
1625
1626 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1627
1628 tpm_build_ppi_acpi(tpm, dev);
1629
1630 aml_append(sb_scope, dev);
1631 }
1632
1633 aml_append(dsdt, sb_scope);
1634
1635 /* copy AML table into ACPI tables blob and patch header there */
1636 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1637 build_header(linker, table_data,
1638 (void *)(table_data->data + table_data->len - dsdt->buf->len),
1639 "DSDT", dsdt->buf->len, 1, NULL, NULL);
1640 free_aml_allocator();
1641 }
1642
1643 static void
1644 build_hpet(GArray *table_data, BIOSLinker *linker)
1645 {
1646 Acpi20Hpet *hpet;
1647
1648 hpet = acpi_data_push(table_data, sizeof(*hpet));
1649 /* Note timer_block_id value must be kept in sync with value advertised by
1650 * emulated hpet
1651 */
1652 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1653 hpet->addr.address = cpu_to_le64(HPET_BASE);
1654 build_header(linker, table_data,
1655 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
1656 }
1657
1658 static void
1659 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
1660 {
1661 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1662 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
1663 unsigned log_addr_offset =
1664 (char *)&tcpa->log_area_start_address - table_data->data;
1665
1666 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1667 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1668 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
1669
1670 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1671 false /* high memory */);
1672
1673 /* log area start address to be filled by Guest linker */
1674 bios_linker_loader_add_pointer(linker,
1675 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
1676 ACPI_BUILD_TPMLOG_FILE, 0);
1677
1678 build_header(linker, table_data,
1679 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
1680 }
1681
1682 #define HOLE_640K_START (640 * KiB)
1683 #define HOLE_640K_END (1 * MiB)
1684
1685 static void
1686 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1687 {
1688 AcpiSystemResourceAffinityTable *srat;
1689 AcpiSratMemoryAffinity *numamem;
1690
1691 int i;
1692 int srat_start, numa_start, slots;
1693 uint64_t mem_len, mem_base, next_base;
1694 MachineClass *mc = MACHINE_GET_CLASS(machine);
1695 X86MachineState *x86ms = X86_MACHINE(machine);
1696 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1697 PCMachineState *pcms = PC_MACHINE(machine);
1698 ram_addr_t hotplugabble_address_space_size =
1699 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1700 NULL);
1701
1702 srat_start = table_data->len;
1703
1704 srat = acpi_data_push(table_data, sizeof *srat);
1705 srat->reserved1 = cpu_to_le32(1);
1706
1707 for (i = 0; i < apic_ids->len; i++) {
1708 int node_id = apic_ids->cpus[i].props.node_id;
1709 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1710
1711 if (apic_id < 255) {
1712 AcpiSratProcessorAffinity *core;
1713
1714 core = acpi_data_push(table_data, sizeof *core);
1715 core->type = ACPI_SRAT_PROCESSOR_APIC;
1716 core->length = sizeof(*core);
1717 core->local_apic_id = apic_id;
1718 core->proximity_lo = node_id;
1719 memset(core->proximity_hi, 0, 3);
1720 core->local_sapic_eid = 0;
1721 core->flags = cpu_to_le32(1);
1722 } else {
1723 AcpiSratProcessorX2ApicAffinity *core;
1724
1725 core = acpi_data_push(table_data, sizeof *core);
1726 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
1727 core->length = sizeof(*core);
1728 core->x2apic_id = cpu_to_le32(apic_id);
1729 core->proximity_domain = cpu_to_le32(node_id);
1730 core->flags = cpu_to_le32(1);
1731 }
1732 }
1733
1734
1735 /* the memory map is a bit tricky, it contains at least one hole
1736 * from 640k-1M and possibly another one from 3.5G-4G.
1737 */
1738 next_base = 0;
1739 numa_start = table_data->len;
1740
1741 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
1742 mem_base = next_base;
1743 mem_len = pcms->node_mem[i - 1];
1744 next_base = mem_base + mem_len;
1745
1746 /* Cut out the 640K hole */
1747 if (mem_base <= HOLE_640K_START &&
1748 next_base > HOLE_640K_START) {
1749 mem_len -= next_base - HOLE_640K_START;
1750 if (mem_len > 0) {
1751 numamem = acpi_data_push(table_data, sizeof *numamem);
1752 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1753 MEM_AFFINITY_ENABLED);
1754 }
1755
1756 /* Check for the rare case: 640K < RAM < 1M */
1757 if (next_base <= HOLE_640K_END) {
1758 next_base = HOLE_640K_END;
1759 continue;
1760 }
1761 mem_base = HOLE_640K_END;
1762 mem_len = next_base - HOLE_640K_END;
1763 }
1764
1765 /* Cut out the ACPI_PCI hole */
1766 if (mem_base <= x86ms->below_4g_mem_size &&
1767 next_base > x86ms->below_4g_mem_size) {
1768 mem_len -= next_base - x86ms->below_4g_mem_size;
1769 if (mem_len > 0) {
1770 numamem = acpi_data_push(table_data, sizeof *numamem);
1771 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1772 MEM_AFFINITY_ENABLED);
1773 }
1774 mem_base = 1ULL << 32;
1775 mem_len = next_base - x86ms->below_4g_mem_size;
1776 next_base = mem_base + mem_len;
1777 }
1778
1779 if (mem_len > 0) {
1780 numamem = acpi_data_push(table_data, sizeof *numamem);
1781 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1782 MEM_AFFINITY_ENABLED);
1783 }
1784 }
1785
1786 if (machine->nvdimms_state->is_enabled) {
1787 nvdimm_build_srat(table_data);
1788 }
1789
1790 slots = (table_data->len - numa_start) / sizeof *numamem;
1791 for (; slots < pcms->numa_nodes + 2; slots++) {
1792 numamem = acpi_data_push(table_data, sizeof *numamem);
1793 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1794 }
1795
1796 /*
1797 * Entry is required for Windows to enable memory hotplug in OS
1798 * and for Linux to enable SWIOTLB when booted with less than
1799 * 4G of RAM. Windows works better if the entry sets proximity
1800 * to the highest NUMA node in the machine.
1801 * Memory devices may override proximity set by this entry,
1802 * providing _PXM method if necessary.
1803 */
1804 if (hotplugabble_address_space_size) {
1805 numamem = acpi_data_push(table_data, sizeof *numamem);
1806 build_srat_memory(numamem, machine->device_memory->base,
1807 hotplugabble_address_space_size, pcms->numa_nodes - 1,
1808 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
1809 }
1810
1811 build_header(linker, table_data,
1812 (void *)(table_data->data + srat_start),
1813 "SRAT",
1814 table_data->len - srat_start, 1, NULL, NULL);
1815 }
1816
1817 /*
1818 * VT-d spec 8.1 DMA Remapping Reporting Structure
1819 * (version Oct. 2014 or later)
1820 */
1821 static void
1822 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
1823 {
1824 int dmar_start = table_data->len;
1825
1826 AcpiTableDmar *dmar;
1827 AcpiDmarHardwareUnit *drhd;
1828 AcpiDmarRootPortATS *atsr;
1829 uint8_t dmar_flags = 0;
1830 X86IOMMUState *iommu = x86_iommu_get_default();
1831 AcpiDmarDeviceScope *scope = NULL;
1832 /* Root complex IOAPIC use one path[0] only */
1833 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
1834 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1835
1836 assert(iommu);
1837 if (x86_iommu_ir_supported(iommu)) {
1838 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
1839 }
1840
1841 dmar = acpi_data_push(table_data, sizeof(*dmar));
1842 dmar->host_address_width = intel_iommu->aw_bits - 1;
1843 dmar->flags = dmar_flags;
1844
1845 /* DMAR Remapping Hardware Unit Definition structure */
1846 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
1847 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1848 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
1849 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1850 drhd->pci_segment = cpu_to_le16(0);
1851 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1852
1853 /* Scope definition for the root-complex IOAPIC. See VT-d spec
1854 * 8.3.1 (version Oct. 2014 or later). */
1855 scope = &drhd->scope[0];
1856 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
1857 scope->length = ioapic_scope_size;
1858 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
1859 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
1860 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
1861 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
1862
1863 if (iommu->dt_supported) {
1864 atsr = acpi_data_push(table_data, sizeof(*atsr));
1865 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
1866 atsr->length = cpu_to_le16(sizeof(*atsr));
1867 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
1868 atsr->pci_segment = cpu_to_le16(0);
1869 }
1870
1871 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1872 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
1873 }
1874
1875 /*
1876 * Windows ACPI Emulated Devices Table
1877 * (Version 1.0 - April 6, 2009)
1878 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
1879 *
1880 * Helpful to speedup Windows guests and ignored by others.
1881 */
1882 static void
1883 build_waet(GArray *table_data, BIOSLinker *linker)
1884 {
1885 int waet_start = table_data->len;
1886
1887 /* WAET header */
1888 acpi_data_push(table_data, sizeof(AcpiTableHeader));
1889 /*
1890 * Set "ACPI PM timer good" flag.
1891 *
1892 * Tells Windows guests that our ACPI PM timer is reliable in the
1893 * sense that guest can read it only once to obtain a reliable value.
1894 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
1895 */
1896 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
1897
1898 build_header(linker, table_data, (void *)(table_data->data + waet_start),
1899 "WAET", table_data->len - waet_start, 1, NULL, NULL);
1900 }
1901
1902 /*
1903 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
1904 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
1905 */
1906 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
1907
1908 /*
1909 * Insert IVHD entry for device and recurse, insert alias, or insert range as
1910 * necessary for the PCI topology.
1911 */
1912 static void
1913 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
1914 {
1915 GArray *table_data = opaque;
1916 uint32_t entry;
1917
1918 /* "Select" IVHD entry, type 0x2 */
1919 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
1920 build_append_int_noprefix(table_data, entry, 4);
1921
1922 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1923 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1924 uint8_t sec = pci_bus_num(sec_bus);
1925 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
1926
1927 if (pci_bus_is_express(sec_bus)) {
1928 /*
1929 * Walk the bus if there are subordinates, otherwise use a range
1930 * to cover an entire leaf bus. We could potentially also use a
1931 * range for traversed buses, but we'd need to take care not to
1932 * create both Select and Range entries covering the same device.
1933 * This is easier and potentially more compact.
1934 *
1935 * An example bare metal system seems to use Select entries for
1936 * root ports without a slot (ie. built-ins) and Range entries
1937 * when there is a slot. The same system also only hard-codes
1938 * the alias range for an onboard PCIe-to-PCI bridge, apparently
1939 * making no effort to support nested bridges. We attempt to
1940 * be more thorough here.
1941 */
1942 if (sec == sub) { /* leaf bus */
1943 /* "Start of Range" IVHD entry, type 0x3 */
1944 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
1945 build_append_int_noprefix(table_data, entry, 4);
1946 /* "End of Range" IVHD entry, type 0x4 */
1947 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
1948 build_append_int_noprefix(table_data, entry, 4);
1949 } else {
1950 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
1951 }
1952 } else {
1953 /*
1954 * If the secondary bus is conventional, then we need to create an
1955 * Alias range for everything downstream. The range covers the
1956 * first devfn on the secondary bus to the last devfn on the
1957 * subordinate bus. The alias target depends on legacy versus
1958 * express bridges, just as in pci_device_iommu_address_space().
1959 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
1960 */
1961 uint16_t dev_id_a, dev_id_b;
1962
1963 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
1964
1965 if (pci_is_express(dev) &&
1966 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
1967 dev_id_b = dev_id_a;
1968 } else {
1969 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
1970 }
1971
1972 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
1973 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
1974 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
1975
1976 /* "End of Range" IVHD entry, type 0x4 */
1977 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
1978 build_append_int_noprefix(table_data, entry, 4);
1979 }
1980 }
1981 }
1982
1983 /* For all PCI host bridges, walk and insert IVHD entries */
1984 static int
1985 ivrs_host_bridges(Object *obj, void *opaque)
1986 {
1987 GArray *ivhd_blob = opaque;
1988
1989 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
1990 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
1991
1992 if (bus) {
1993 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
1994 }
1995 }
1996
1997 return 0;
1998 }
1999
2000 static void
2001 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2002 {
2003 int ivhd_table_len = 24;
2004 int iommu_start = table_data->len;
2005 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2006 GArray *ivhd_blob = g_array_new(false, true, 1);
2007
2008 /* IVRS header */
2009 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2010 /* IVinfo - IO virtualization information common to all
2011 * IOMMU units in a system
2012 */
2013 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2014 /* reserved */
2015 build_append_int_noprefix(table_data, 0, 8);
2016
2017 /* IVHD definition - type 10h */
2018 build_append_int_noprefix(table_data, 0x10, 1);
2019 /* virtualization flags */
2020 build_append_int_noprefix(table_data,
2021 (1UL << 0) | /* HtTunEn */
2022 (1UL << 4) | /* iotblSup */
2023 (1UL << 6) | /* PrefSup */
2024 (1UL << 7), /* PPRSup */
2025 1);
2026
2027 /*
2028 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2029 * complete set of IVHD entries. Do this into a separate blob so that we
2030 * can calculate the total IVRS table length here and then append the new
2031 * blob further below. Fall back to an entry covering all devices, which
2032 * is sufficient when no aliases are present.
2033 */
2034 object_child_foreach_recursive(object_get_root(),
2035 ivrs_host_bridges, ivhd_blob);
2036
2037 if (!ivhd_blob->len) {
2038 /*
2039 * Type 1 device entry reporting all devices
2040 * These are 4-byte device entries currently reporting the range of
2041 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2042 */
2043 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2044 }
2045
2046 ivhd_table_len += ivhd_blob->len;
2047
2048 /*
2049 * When interrupt remapping is supported, we add a special IVHD device
2050 * for type IO-APIC.
2051 */
2052 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2053 ivhd_table_len += 8;
2054 }
2055
2056 /* IVHD length */
2057 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2058 /* DeviceID */
2059 build_append_int_noprefix(table_data, s->devid, 2);
2060 /* Capability offset */
2061 build_append_int_noprefix(table_data, s->capab_offset, 2);
2062 /* IOMMU base address */
2063 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2064 /* PCI Segment Group */
2065 build_append_int_noprefix(table_data, 0, 2);
2066 /* IOMMU info */
2067 build_append_int_noprefix(table_data, 0, 2);
2068 /* IOMMU Feature Reporting */
2069 build_append_int_noprefix(table_data,
2070 (48UL << 30) | /* HATS */
2071 (48UL << 28) | /* GATS */
2072 (1UL << 2) | /* GTSup */
2073 (1UL << 6), /* GASup */
2074 4);
2075
2076 /* IVHD entries as found above */
2077 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2078 g_array_free(ivhd_blob, TRUE);
2079
2080 /*
2081 * Add a special IVHD device type.
2082 * Refer to spec - Table 95: IVHD device entry type codes
2083 *
2084 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2085 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2086 */
2087 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2088 build_append_int_noprefix(table_data,
2089 (0x1ull << 56) | /* type IOAPIC */
2090 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2091 0x48, /* special device */
2092 8);
2093 }
2094
2095 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2096 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2097 }
2098
2099 typedef
2100 struct AcpiBuildState {
2101 /* Copy of table in RAM (for patching). */
2102 MemoryRegion *table_mr;
2103 /* Is table patched? */
2104 uint8_t patched;
2105 void *rsdp;
2106 MemoryRegion *rsdp_mr;
2107 MemoryRegion *linker_mr;
2108 } AcpiBuildState;
2109
2110 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2111 {
2112 Object *pci_host;
2113 QObject *o;
2114
2115 pci_host = acpi_get_i386_pci_host();
2116 g_assert(pci_host);
2117
2118 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2119 if (!o) {
2120 return false;
2121 }
2122 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2123 qobject_unref(o);
2124 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2125 return false;
2126 }
2127
2128 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2129 assert(o);
2130 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2131 qobject_unref(o);
2132 return true;
2133 }
2134
2135 static
2136 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2137 {
2138 PCMachineState *pcms = PC_MACHINE(machine);
2139 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2140 X86MachineState *x86ms = X86_MACHINE(machine);
2141 GArray *table_offsets;
2142 unsigned facs, dsdt, rsdt, fadt;
2143 AcpiPmInfo pm;
2144 AcpiMiscInfo misc;
2145 AcpiMcfgInfo mcfg;
2146 Range pci_hole, pci_hole64;
2147 uint8_t *u;
2148 size_t aml_len = 0;
2149 GArray *tables_blob = tables->table_data;
2150 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2151 Object *vmgenid_dev;
2152
2153 acpi_get_pm_info(machine, &pm);
2154 acpi_get_misc_info(&misc);
2155 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2156 acpi_get_slic_oem(&slic_oem);
2157
2158 table_offsets = g_array_new(false, true /* clear */,
2159 sizeof(uint32_t));
2160 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2161
2162 bios_linker_loader_alloc(tables->linker,
2163 ACPI_BUILD_TABLE_FILE, tables_blob,
2164 64 /* Ensure FACS is aligned */,
2165 false /* high memory */);
2166
2167 /*
2168 * FACS is pointed to by FADT.
2169 * We place it first since it's the only table that has alignment
2170 * requirements.
2171 */
2172 facs = tables_blob->len;
2173 build_facs(tables_blob);
2174
2175 /* DSDT is pointed to by FADT */
2176 dsdt = tables_blob->len;
2177 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2178 &pci_hole, &pci_hole64, machine);
2179
2180 /* Count the size of the DSDT and SSDT, we will need it for legacy
2181 * sizing of ACPI tables.
2182 */
2183 aml_len += tables_blob->len - dsdt;
2184
2185 /* ACPI tables pointed to by RSDT */
2186 fadt = tables_blob->len;
2187 acpi_add_table(table_offsets, tables_blob);
2188 pm.fadt.facs_tbl_offset = &facs;
2189 pm.fadt.dsdt_tbl_offset = &dsdt;
2190 pm.fadt.xdsdt_tbl_offset = &dsdt;
2191 build_fadt(tables_blob, tables->linker, &pm.fadt,
2192 slic_oem.id, slic_oem.table_id);
2193 aml_len += tables_blob->len - fadt;
2194
2195 acpi_add_table(table_offsets, tables_blob);
2196 acpi_build_madt(tables_blob, tables->linker, x86ms,
2197 ACPI_DEVICE_IF(x86ms->acpi_dev));
2198
2199 vmgenid_dev = find_vmgenid_dev();
2200 if (vmgenid_dev) {
2201 acpi_add_table(table_offsets, tables_blob);
2202 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2203 tables->vmgenid, tables->linker);
2204 }
2205
2206 if (misc.has_hpet) {
2207 acpi_add_table(table_offsets, tables_blob);
2208 build_hpet(tables_blob, tables->linker);
2209 }
2210 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2211 if (misc.tpm_version == TPM_VERSION_1_2) {
2212 acpi_add_table(table_offsets, tables_blob);
2213 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2214 } else { /* TPM_VERSION_2_0 */
2215 acpi_add_table(table_offsets, tables_blob);
2216 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2217 }
2218 }
2219 if (pcms->numa_nodes) {
2220 acpi_add_table(table_offsets, tables_blob);
2221 build_srat(tables_blob, tables->linker, machine);
2222 if (machine->numa_state->have_numa_distance) {
2223 acpi_add_table(table_offsets, tables_blob);
2224 build_slit(tables_blob, tables->linker, machine);
2225 }
2226 if (machine->numa_state->hmat_enabled) {
2227 acpi_add_table(table_offsets, tables_blob);
2228 build_hmat(tables_blob, tables->linker, machine->numa_state);
2229 }
2230 }
2231 if (acpi_get_mcfg(&mcfg)) {
2232 acpi_add_table(table_offsets, tables_blob);
2233 build_mcfg(tables_blob, tables->linker, &mcfg);
2234 }
2235 if (x86_iommu_get_default()) {
2236 IommuType IOMMUType = x86_iommu_get_type();
2237 if (IOMMUType == TYPE_AMD) {
2238 acpi_add_table(table_offsets, tables_blob);
2239 build_amd_iommu(tables_blob, tables->linker);
2240 } else if (IOMMUType == TYPE_INTEL) {
2241 acpi_add_table(table_offsets, tables_blob);
2242 build_dmar_q35(tables_blob, tables->linker);
2243 }
2244 }
2245 if (machine->nvdimms_state->is_enabled) {
2246 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2247 machine->nvdimms_state, machine->ram_slots);
2248 }
2249
2250 acpi_add_table(table_offsets, tables_blob);
2251 build_waet(tables_blob, tables->linker);
2252
2253 /* Add tables supplied by user (if any) */
2254 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2255 unsigned len = acpi_table_len(u);
2256
2257 acpi_add_table(table_offsets, tables_blob);
2258 g_array_append_vals(tables_blob, u, len);
2259 }
2260
2261 /* RSDT is pointed to by RSDP */
2262 rsdt = tables_blob->len;
2263 build_rsdt(tables_blob, tables->linker, table_offsets,
2264 slic_oem.id, slic_oem.table_id);
2265
2266 /* RSDP is in FSEG memory, so allocate it separately */
2267 {
2268 AcpiRsdpData rsdp_data = {
2269 .revision = 0,
2270 .oem_id = ACPI_BUILD_APPNAME6,
2271 .xsdt_tbl_offset = NULL,
2272 .rsdt_tbl_offset = &rsdt,
2273 };
2274 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2275 if (!pcmc->rsdp_in_ram) {
2276 /* We used to allocate some extra space for RSDP revision 2 but
2277 * only used the RSDP revision 0 space. The extra bytes were
2278 * zeroed out and not used.
2279 * Here we continue wasting those extra 16 bytes to make sure we
2280 * don't break migration for machine types 2.2 and older due to
2281 * RSDP blob size mismatch.
2282 */
2283 build_append_int_noprefix(tables->rsdp, 0, 16);
2284 }
2285 }
2286
2287 /* We'll expose it all to Guest so we want to reduce
2288 * chance of size changes.
2289 *
2290 * We used to align the tables to 4k, but of course this would
2291 * too simple to be enough. 4k turned out to be too small an
2292 * alignment very soon, and in fact it is almost impossible to
2293 * keep the table size stable for all (max_cpus, max_memory_slots)
2294 * combinations. So the table size is always 64k for pc-i440fx-2.1
2295 * and we give an error if the table grows beyond that limit.
2296 *
2297 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2298 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2299 * than 2.0 and we can always pad the smaller tables with zeros. We can
2300 * then use the exact size of the 2.0 tables.
2301 *
2302 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2303 */
2304 if (pcmc->legacy_acpi_table_size) {
2305 /* Subtracting aml_len gives the size of fixed tables. Then add the
2306 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2307 */
2308 int legacy_aml_len =
2309 pcmc->legacy_acpi_table_size +
2310 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2311 int legacy_table_size =
2312 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2313 ACPI_BUILD_ALIGN_SIZE);
2314 if (tables_blob->len > legacy_table_size) {
2315 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2316 warn_report("ACPI table size %u exceeds %d bytes,"
2317 " migration may not work",
2318 tables_blob->len, legacy_table_size);
2319 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2320 " or PCI bridges.");
2321 }
2322 g_array_set_size(tables_blob, legacy_table_size);
2323 } else {
2324 /* Make sure we have a buffer in case we need to resize the tables. */
2325 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2326 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2327 warn_report("ACPI table size %u exceeds %d bytes,"
2328 " migration may not work",
2329 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2330 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2331 " or PCI bridges.");
2332 }
2333 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2334 }
2335
2336 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2337
2338 /* Cleanup memory that's no longer used. */
2339 g_array_free(table_offsets, true);
2340 }
2341
2342 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2343 {
2344 uint32_t size = acpi_data_len(data);
2345
2346 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2347 memory_region_ram_resize(mr, size, &error_abort);
2348
2349 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2350 memory_region_set_dirty(mr, 0, size);
2351 }
2352
2353 static void acpi_build_update(void *build_opaque)
2354 {
2355 AcpiBuildState *build_state = build_opaque;
2356 AcpiBuildTables tables;
2357
2358 /* No state to update or already patched? Nothing to do. */
2359 if (!build_state || build_state->patched) {
2360 return;
2361 }
2362 build_state->patched = 1;
2363
2364 acpi_build_tables_init(&tables);
2365
2366 acpi_build(&tables, MACHINE(qdev_get_machine()));
2367
2368 acpi_ram_update(build_state->table_mr, tables.table_data);
2369
2370 if (build_state->rsdp) {
2371 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2372 } else {
2373 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2374 }
2375
2376 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2377 acpi_build_tables_cleanup(&tables, true);
2378 }
2379
2380 static void acpi_build_reset(void *build_opaque)
2381 {
2382 AcpiBuildState *build_state = build_opaque;
2383 build_state->patched = 0;
2384 }
2385
2386 static const VMStateDescription vmstate_acpi_build = {
2387 .name = "acpi_build",
2388 .version_id = 1,
2389 .minimum_version_id = 1,
2390 .fields = (VMStateField[]) {
2391 VMSTATE_UINT8(patched, AcpiBuildState),
2392 VMSTATE_END_OF_LIST()
2393 },
2394 };
2395
2396 void acpi_setup(void)
2397 {
2398 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2399 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2400 X86MachineState *x86ms = X86_MACHINE(pcms);
2401 AcpiBuildTables tables;
2402 AcpiBuildState *build_state;
2403 Object *vmgenid_dev;
2404 TPMIf *tpm;
2405 static FwCfgTPMConfig tpm_config;
2406
2407 if (!x86ms->fw_cfg) {
2408 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2409 return;
2410 }
2411
2412 if (!pcms->acpi_build_enabled) {
2413 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2414 return;
2415 }
2416
2417 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2418 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2419 return;
2420 }
2421
2422 build_state = g_malloc0(sizeof *build_state);
2423
2424 acpi_build_tables_init(&tables);
2425 acpi_build(&tables, MACHINE(pcms));
2426
2427 /* Now expose it all to Guest */
2428 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2429 build_state, tables.table_data,
2430 ACPI_BUILD_TABLE_FILE,
2431 ACPI_BUILD_TABLE_MAX_SIZE);
2432 assert(build_state->table_mr != NULL);
2433
2434 build_state->linker_mr =
2435 acpi_add_rom_blob(acpi_build_update, build_state,
2436 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
2437
2438 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2439 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2440
2441 tpm = tpm_find();
2442 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2443 tpm_config = (FwCfgTPMConfig) {
2444 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2445 .tpm_version = tpm_get_version(tpm),
2446 .tpmppi_version = TPM_PPI_VERSION_1_30
2447 };
2448 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2449 &tpm_config, sizeof tpm_config);
2450 }
2451
2452 vmgenid_dev = find_vmgenid_dev();
2453 if (vmgenid_dev) {
2454 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2455 tables.vmgenid);
2456 }
2457
2458 if (!pcmc->rsdp_in_ram) {
2459 /*
2460 * Keep for compatibility with old machine types.
2461 * Though RSDP is small, its contents isn't immutable, so
2462 * we'll update it along with the rest of tables on guest access.
2463 */
2464 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2465
2466 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2467 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2468 acpi_build_update, NULL, build_state,
2469 build_state->rsdp, rsdp_size, true);
2470 build_state->rsdp_mr = NULL;
2471 } else {
2472 build_state->rsdp = NULL;
2473 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2474 build_state, tables.rsdp,
2475 ACPI_BUILD_RSDP_FILE, 0);
2476 }
2477
2478 qemu_register_reset(acpi_build_reset, build_state);
2479 acpi_build_reset(build_state);
2480 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2481
2482 /* Cleanup tables but don't free the memory: we track it
2483 * in build_state.
2484 */
2485 acpi_build_tables_cleanup(&tables, false);
2486 }
AR7 emulation for QEMU