hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "hw/sysbus.h"
  13 #include "hw/ssi/ssi.h"
  14 #include "hw/arm/boot.h"
  15 #include "qemu/timer.h"
  16 #include "hw/i2c/i2c.h"
  17 #include "net/net.h"
  18 #include "hw/boards.h"
  19 #include "qemu/log.h"
  20 #include "exec/address-spaces.h"
  21 #include "sysemu/sysemu.h"
  22 #include "hw/arm/armv7m.h"
  23 #include "hw/char/pl011.h"
  24 #include "hw/input/gamepad.h"
  25 #include "hw/irq.h"
  26 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  27 #include "migration/vmstate.h"
  28 #include "hw/misc/unimp.h"
  29 #include "cpu.h"
  30 #include "qom/object.h"
  31
  32 #define GPIO_A 0
  33 #define GPIO_B 1
  34 #define GPIO_C 2
  35 #define GPIO_D 3
  36 #define GPIO_E 4
  37 #define GPIO_F 5
  38 #define GPIO_G 6
  39
  40 #define BP_OLED_I2C  0x01
  41 #define BP_OLED_SSI  0x02
  42 #define BP_GAMEPAD   0x04
  43
  44 #define NUM_IRQ_LINES 64
  45
  46 typedef const struct {
  47     const char *name;
  48     uint32_t did0;
  49     uint32_t did1;
  50     uint32_t dc0;
  51     uint32_t dc1;
  52     uint32_t dc2;
  53     uint32_t dc3;
  54     uint32_t dc4;
  55     uint32_t peripherals;
  56 } stellaris_board_info;
  57
  58 /* General purpose timer module.  */
  59
  60 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  61 OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
  62
  63 struct gptm_state {
  64     SysBusDevice parent_obj;
  65
  66     MemoryRegion iomem;
  67     uint32_t config;
  68     uint32_t mode[2];
  69     uint32_t control;
  70     uint32_t state;
  71     uint32_t mask;
  72     uint32_t load[2];
  73     uint32_t match[2];
  74     uint32_t prescale[2];
  75     uint32_t match_prescale[2];
  76     uint32_t rtc;
  77     int64_t tick[2];
  78     struct gptm_state *opaque[2];
  79     QEMUTimer *timer[2];
  80     /* The timers have an alternate output used to trigger the ADC.  */
  81     qemu_irq trigger;
  82     qemu_irq irq;
  83 };
  84
  85 static void gptm_update_irq(gptm_state *s)
  86 {
  87     int level;
  88     level = (s->state & s->mask) != 0;
  89     qemu_set_irq(s->irq, level);
  90 }
  91
  92 static void gptm_stop(gptm_state *s, int n)
  93 {
  94     timer_del(s->timer[n]);
  95 }
  96
  97 static void gptm_reload(gptm_state *s, int n, int reset)
  98 {
  99     int64_t tick;
 100     if (reset)
 101         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 102     else
 103         tick = s->tick[n];
 104
 105     if (s->config == 0) {
 106         /* 32-bit CountDown.  */
 107         uint32_t count;
 108         count = s->load[0] | (s->load[1] << 16);
 109         tick += (int64_t)count * system_clock_scale;
 110     } else if (s->config == 1) {
 111         /* 32-bit RTC.  1Hz tick.  */
 112         tick += NANOSECONDS_PER_SECOND;
 113     } else if (s->mode[n] == 0xa) {
 114         /* PWM mode.  Not implemented.  */
 115     } else {
 116         qemu_log_mask(LOG_UNIMP,
 117                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 118                       s->mode[n]);
 119         return;
 120     }
 121     s->tick[n] = tick;
 122     timer_mod(s->timer[n], tick);
 123 }
 124
 125 static void gptm_tick(void *opaque)
 126 {
 127     gptm_state **p = (gptm_state **)opaque;
 128     gptm_state *s;
 129     int n;
 130
 131     s = *p;
 132     n = p - s->opaque;
 133     if (s->config == 0) {
 134         s->state |= 1;
 135         if ((s->control & 0x20)) {
 136             /* Output trigger.  */
 137             qemu_irq_pulse(s->trigger);
 138         }
 139         if (s->mode[0] & 1) {
 140             /* One-shot.  */
 141             s->control &= ~1;
 142         } else {
 143             /* Periodic.  */
 144             gptm_reload(s, 0, 0);
 145         }
 146     } else if (s->config == 1) {
 147         /* RTC.  */
 148         uint32_t match;
 149         s->rtc++;
 150         match = s->match[0] | (s->match[1] << 16);
 151         if (s->rtc > match)
 152             s->rtc = 0;
 153         if (s->rtc == 0) {
 154             s->state |= 8;
 155         }
 156         gptm_reload(s, 0, 0);
 157     } else if (s->mode[n] == 0xa) {
 158         /* PWM mode.  Not implemented.  */
 159     } else {
 160         qemu_log_mask(LOG_UNIMP,
 161                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 162                       s->mode[n]);
 163     }
 164     gptm_update_irq(s);
 165 }
 166
 167 static uint64_t gptm_read(void *opaque, hwaddr offset,
 168                           unsigned size)
 169 {
 170     gptm_state *s = (gptm_state *)opaque;
 171
 172     switch (offset) {
 173     case 0x00: /* CFG */
 174         return s->config;
 175     case 0x04: /* TAMR */
 176         return s->mode[0];
 177     case 0x08: /* TBMR */
 178         return s->mode[1];
 179     case 0x0c: /* CTL */
 180         return s->control;
 181     case 0x18: /* IMR */
 182         return s->mask;
 183     case 0x1c: /* RIS */
 184         return s->state;
 185     case 0x20: /* MIS */
 186         return s->state & s->mask;
 187     case 0x24: /* CR */
 188         return 0;
 189     case 0x28: /* TAILR */
 190         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 191     case 0x2c: /* TBILR */
 192         return s->load[1];
 193     case 0x30: /* TAMARCHR */
 194         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 195     case 0x34: /* TBMATCHR */
 196         return s->match[1];
 197     case 0x38: /* TAPR */
 198         return s->prescale[0];
 199     case 0x3c: /* TBPR */
 200         return s->prescale[1];
 201     case 0x40: /* TAPMR */
 202         return s->match_prescale[0];
 203     case 0x44: /* TBPMR */
 204         return s->match_prescale[1];
 205     case 0x48: /* TAR */
 206         if (s->config == 1) {
 207             return s->rtc;
 208         }
 209         qemu_log_mask(LOG_UNIMP,
 210                       "GPTM: read of TAR but timer read not supported\n");
 211         return 0;
 212     case 0x4c: /* TBR */
 213         qemu_log_mask(LOG_UNIMP,
 214                       "GPTM: read of TBR but timer read not supported\n");
 215         return 0;
 216     default:
 217         qemu_log_mask(LOG_GUEST_ERROR,
 218                       "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
 219                       offset);
 220         return 0;
 221     }
 222 }
 223
 224 static void gptm_write(void *opaque, hwaddr offset,
 225                        uint64_t value, unsigned size)
 226 {
 227     gptm_state *s = (gptm_state *)opaque;
 228     uint32_t oldval;
 229
 230     /* The timers should be disabled before changing the configuration.
 231        We take advantage of this and defer everything until the timer
 232        is enabled.  */
 233     switch (offset) {
 234     case 0x00: /* CFG */
 235         s->config = value;
 236         break;
 237     case 0x04: /* TAMR */
 238         s->mode[0] = value;
 239         break;
 240     case 0x08: /* TBMR */
 241         s->mode[1] = value;
 242         break;
 243     case 0x0c: /* CTL */
 244         oldval = s->control;
 245         s->control = value;
 246         /* TODO: Implement pause.  */
 247         if ((oldval ^ value) & 1) {
 248             if (value & 1) {
 249                 gptm_reload(s, 0, 1);
 250             } else {
 251                 gptm_stop(s, 0);
 252             }
 253         }
 254         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 255             if (value & 0x100) {
 256                 gptm_reload(s, 1, 1);
 257             } else {
 258                 gptm_stop(s, 1);
 259             }
 260         }
 261         break;
 262     case 0x18: /* IMR */
 263         s->mask = value & 0x77;
 264         gptm_update_irq(s);
 265         break;
 266     case 0x24: /* CR */
 267         s->state &= ~value;
 268         break;
 269     case 0x28: /* TAILR */
 270         s->load[0] = value & 0xffff;
 271         if (s->config < 4) {
 272             s->load[1] = value >> 16;
 273         }
 274         break;
 275     case 0x2c: /* TBILR */
 276         s->load[1] = value & 0xffff;
 277         break;
 278     case 0x30: /* TAMARCHR */
 279         s->match[0] = value & 0xffff;
 280         if (s->config < 4) {
 281             s->match[1] = value >> 16;
 282         }
 283         break;
 284     case 0x34: /* TBMATCHR */
 285         s->match[1] = value >> 16;
 286         break;
 287     case 0x38: /* TAPR */
 288         s->prescale[0] = value;
 289         break;
 290     case 0x3c: /* TBPR */
 291         s->prescale[1] = value;
 292         break;
 293     case 0x40: /* TAPMR */
 294         s->match_prescale[0] = value;
 295         break;
 296     case 0x44: /* TBPMR */
 297         s->match_prescale[0] = value;
 298         break;
 299     default:
 300         qemu_log_mask(LOG_GUEST_ERROR,
 301                       "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
 302                       offset);
 303     }
 304     gptm_update_irq(s);
 305 }
 306
 307 static const MemoryRegionOps gptm_ops = {
 308     .read = gptm_read,
 309     .write = gptm_write,
 310     .endianness = DEVICE_NATIVE_ENDIAN,
 311 };
 312
 313 static const VMStateDescription vmstate_stellaris_gptm = {
 314     .name = "stellaris_gptm",
 315     .version_id = 1,
 316     .minimum_version_id = 1,
 317     .fields = (VMStateField[]) {
 318         VMSTATE_UINT32(config, gptm_state),
 319         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 320         VMSTATE_UINT32(control, gptm_state),
 321         VMSTATE_UINT32(state, gptm_state),
 322         VMSTATE_UINT32(mask, gptm_state),
 323         VMSTATE_UNUSED(8),
 324         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 325         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 326         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 327         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 328         VMSTATE_UINT32(rtc, gptm_state),
 329         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 330         VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
 331         VMSTATE_END_OF_LIST()
 332     }
 333 };
 334
 335 static void stellaris_gptm_init(Object *obj)
 336 {
 337     DeviceState *dev = DEVICE(obj);
 338     gptm_state *s = STELLARIS_GPTM(obj);
 339     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 340
 341     sysbus_init_irq(sbd, &s->irq);
 342     qdev_init_gpio_out(dev, &s->trigger, 1);
 343
 344     memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
 345                           "gptm", 0x1000);
 346     sysbus_init_mmio(sbd, &s->iomem);
 347
 348     s->opaque[0] = s->opaque[1] = s;
 349 }
 350
 351 static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
 352 {
 353     gptm_state *s = STELLARIS_GPTM(dev);
 354     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 355     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 356 }
 357
 358 /* System controller.  */
 359
 360 typedef struct {
 361     MemoryRegion iomem;
 362     uint32_t pborctl;
 363     uint32_t ldopctl;
 364     uint32_t int_status;
 365     uint32_t int_mask;
 366     uint32_t resc;
 367     uint32_t rcc;
 368     uint32_t rcc2;
 369     uint32_t rcgc[3];
 370     uint32_t scgc[3];
 371     uint32_t dcgc[3];
 372     uint32_t clkvclr;
 373     uint32_t ldoarst;
 374     uint32_t user0;
 375     uint32_t user1;
 376     qemu_irq irq;
 377     stellaris_board_info *board;
 378 } ssys_state;
 379
 380 static void ssys_update(ssys_state *s)
 381 {
 382   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 383 }
 384
 385 static uint32_t pllcfg_sandstorm[16] = {
 386     0x31c0, /* 1 Mhz */
 387     0x1ae0, /* 1.8432 Mhz */
 388     0x18c0, /* 2 Mhz */
 389     0xd573, /* 2.4576 Mhz */
 390     0x37a6, /* 3.57954 Mhz */
 391     0x1ae2, /* 3.6864 Mhz */
 392     0x0c40, /* 4 Mhz */
 393     0x98bc, /* 4.906 Mhz */
 394     0x935b, /* 4.9152 Mhz */
 395     0x09c0, /* 5 Mhz */
 396     0x4dee, /* 5.12 Mhz */
 397     0x0c41, /* 6 Mhz */
 398     0x75db, /* 6.144 Mhz */
 399     0x1ae6, /* 7.3728 Mhz */
 400     0x0600, /* 8 Mhz */
 401     0x585b /* 8.192 Mhz */
 402 };
 403
 404 static uint32_t pllcfg_fury[16] = {
 405     0x3200, /* 1 Mhz */
 406     0x1b20, /* 1.8432 Mhz */
 407     0x1900, /* 2 Mhz */
 408     0xf42b, /* 2.4576 Mhz */
 409     0x37e3, /* 3.57954 Mhz */
 410     0x1b21, /* 3.6864 Mhz */
 411     0x0c80, /* 4 Mhz */
 412     0x98ee, /* 4.906 Mhz */
 413     0xd5b4, /* 4.9152 Mhz */
 414     0x0a00, /* 5 Mhz */
 415     0x4e27, /* 5.12 Mhz */
 416     0x1902, /* 6 Mhz */
 417     0xec1c, /* 6.144 Mhz */
 418     0x1b23, /* 7.3728 Mhz */
 419     0x0640, /* 8 Mhz */
 420     0xb11c /* 8.192 Mhz */
 421 };
 422
 423 #define DID0_VER_MASK        0x70000000
 424 #define DID0_VER_0           0x00000000
 425 #define DID0_VER_1           0x10000000
 426
 427 #define DID0_CLASS_MASK      0x00FF0000
 428 #define DID0_CLASS_SANDSTORM 0x00000000
 429 #define DID0_CLASS_FURY      0x00010000
 430
 431 static int ssys_board_class(const ssys_state *s)
 432 {
 433     uint32_t did0 = s->board->did0;
 434     switch (did0 & DID0_VER_MASK) {
 435     case DID0_VER_0:
 436         return DID0_CLASS_SANDSTORM;
 437     case DID0_VER_1:
 438         switch (did0 & DID0_CLASS_MASK) {
 439         case DID0_CLASS_SANDSTORM:
 440         case DID0_CLASS_FURY:
 441             return did0 & DID0_CLASS_MASK;
 442         }
 443         /* for unknown classes, fall through */
 444     default:
 445         /* This can only happen if the hardwired constant did0 value
 446          * in this board's stellaris_board_info struct is wrong.
 447          */
 448         g_assert_not_reached();
 449     }
 450 }
 451
 452 static uint64_t ssys_read(void *opaque, hwaddr offset,
 453                           unsigned size)
 454 {
 455     ssys_state *s = (ssys_state *)opaque;
 456
 457     switch (offset) {
 458     case 0x000: /* DID0 */
 459         return s->board->did0;
 460     case 0x004: /* DID1 */
 461         return s->board->did1;
 462     case 0x008: /* DC0 */
 463         return s->board->dc0;
 464     case 0x010: /* DC1 */
 465         return s->board->dc1;
 466     case 0x014: /* DC2 */
 467         return s->board->dc2;
 468     case 0x018: /* DC3 */
 469         return s->board->dc3;
 470     case 0x01c: /* DC4 */
 471         return s->board->dc4;
 472     case 0x030: /* PBORCTL */
 473         return s->pborctl;
 474     case 0x034: /* LDOPCTL */
 475         return s->ldopctl;
 476     case 0x040: /* SRCR0 */
 477         return 0;
 478     case 0x044: /* SRCR1 */
 479         return 0;
 480     case 0x048: /* SRCR2 */
 481         return 0;
 482     case 0x050: /* RIS */
 483         return s->int_status;
 484     case 0x054: /* IMC */
 485         return s->int_mask;
 486     case 0x058: /* MISC */
 487         return s->int_status & s->int_mask;
 488     case 0x05c: /* RESC */
 489         return s->resc;
 490     case 0x060: /* RCC */
 491         return s->rcc;
 492     case 0x064: /* PLLCFG */
 493         {
 494             int xtal;
 495             xtal = (s->rcc >> 6) & 0xf;
 496             switch (ssys_board_class(s)) {
 497             case DID0_CLASS_FURY:
 498                 return pllcfg_fury[xtal];
 499             case DID0_CLASS_SANDSTORM:
 500                 return pllcfg_sandstorm[xtal];
 501             default:
 502                 g_assert_not_reached();
 503             }
 504         }
 505     case 0x070: /* RCC2 */
 506         return s->rcc2;
 507     case 0x100: /* RCGC0 */
 508         return s->rcgc[0];
 509     case 0x104: /* RCGC1 */
 510         return s->rcgc[1];
 511     case 0x108: /* RCGC2 */
 512         return s->rcgc[2];
 513     case 0x110: /* SCGC0 */
 514         return s->scgc[0];
 515     case 0x114: /* SCGC1 */
 516         return s->scgc[1];
 517     case 0x118: /* SCGC2 */
 518         return s->scgc[2];
 519     case 0x120: /* DCGC0 */
 520         return s->dcgc[0];
 521     case 0x124: /* DCGC1 */
 522         return s->dcgc[1];
 523     case 0x128: /* DCGC2 */
 524         return s->dcgc[2];
 525     case 0x150: /* CLKVCLR */
 526         return s->clkvclr;
 527     case 0x160: /* LDOARST */
 528         return s->ldoarst;
 529     case 0x1e0: /* USER0 */
 530         return s->user0;
 531     case 0x1e4: /* USER1 */
 532         return s->user1;
 533     default:
 534         qemu_log_mask(LOG_GUEST_ERROR,
 535                       "SSYS: read at bad offset 0x%x\n", (int)offset);
 536         return 0;
 537     }
 538 }
 539
 540 static bool ssys_use_rcc2(ssys_state *s)
 541 {
 542     return (s->rcc2 >> 31) & 0x1;
 543 }
 544
 545 /*
 546  * Caculate the sys. clock period in ms.
 547  */
 548 static void ssys_calculate_system_clock(ssys_state *s)
 549 {
 550     if (ssys_use_rcc2(s)) {
 551         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 552     } else {
 553         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 554     }
 555 }
 556
 557 static void ssys_write(void *opaque, hwaddr offset,
 558                        uint64_t value, unsigned size)
 559 {
 560     ssys_state *s = (ssys_state *)opaque;
 561
 562     switch (offset) {
 563     case 0x030: /* PBORCTL */
 564         s->pborctl = value & 0xffff;
 565         break;
 566     case 0x034: /* LDOPCTL */
 567         s->ldopctl = value & 0x1f;
 568         break;
 569     case 0x040: /* SRCR0 */
 570     case 0x044: /* SRCR1 */
 571     case 0x048: /* SRCR2 */
 572         qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
 573         break;
 574     case 0x054: /* IMC */
 575         s->int_mask = value & 0x7f;
 576         break;
 577     case 0x058: /* MISC */
 578         s->int_status &= ~value;
 579         break;
 580     case 0x05c: /* RESC */
 581         s->resc = value & 0x3f;
 582         break;
 583     case 0x060: /* RCC */
 584         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 585             /* PLL enable.  */
 586             s->int_status |= (1 << 6);
 587         }
 588         s->rcc = value;
 589         ssys_calculate_system_clock(s);
 590         break;
 591     case 0x070: /* RCC2 */
 592         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 593             break;
 594         }
 595
 596         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 597             /* PLL enable.  */
 598             s->int_status |= (1 << 6);
 599         }
 600         s->rcc2 = value;
 601         ssys_calculate_system_clock(s);
 602         break;
 603     case 0x100: /* RCGC0 */
 604         s->rcgc[0] = value;
 605         break;
 606     case 0x104: /* RCGC1 */
 607         s->rcgc[1] = value;
 608         break;
 609     case 0x108: /* RCGC2 */
 610         s->rcgc[2] = value;
 611         break;
 612     case 0x110: /* SCGC0 */
 613         s->scgc[0] = value;
 614         break;
 615     case 0x114: /* SCGC1 */
 616         s->scgc[1] = value;
 617         break;
 618     case 0x118: /* SCGC2 */
 619         s->scgc[2] = value;
 620         break;
 621     case 0x120: /* DCGC0 */
 622         s->dcgc[0] = value;
 623         break;
 624     case 0x124: /* DCGC1 */
 625         s->dcgc[1] = value;
 626         break;
 627     case 0x128: /* DCGC2 */
 628         s->dcgc[2] = value;
 629         break;
 630     case 0x150: /* CLKVCLR */
 631         s->clkvclr = value;
 632         break;
 633     case 0x160: /* LDOARST */
 634         s->ldoarst = value;
 635         break;
 636     default:
 637         qemu_log_mask(LOG_GUEST_ERROR,
 638                       "SSYS: write at bad offset 0x%x\n", (int)offset);
 639     }
 640     ssys_update(s);
 641 }
 642
 643 static const MemoryRegionOps ssys_ops = {
 644     .read = ssys_read,
 645     .write = ssys_write,
 646     .endianness = DEVICE_NATIVE_ENDIAN,
 647 };
 648
 649 static void ssys_reset(void *opaque)
 650 {
 651     ssys_state *s = (ssys_state *)opaque;
 652
 653     s->pborctl = 0x7ffd;
 654     s->rcc = 0x078e3ac0;
 655
 656     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 657         s->rcc2 = 0;
 658     } else {
 659         s->rcc2 = 0x07802810;
 660     }
 661     s->rcgc[0] = 1;
 662     s->scgc[0] = 1;
 663     s->dcgc[0] = 1;
 664     ssys_calculate_system_clock(s);
 665 }
 666
 667 static int stellaris_sys_post_load(void *opaque, int version_id)
 668 {
 669     ssys_state *s = opaque;
 670
 671     ssys_calculate_system_clock(s);
 672
 673     return 0;
 674 }
 675
 676 static const VMStateDescription vmstate_stellaris_sys = {
 677     .name = "stellaris_sys",
 678     .version_id = 2,
 679     .minimum_version_id = 1,
 680     .post_load = stellaris_sys_post_load,
 681     .fields = (VMStateField[]) {
 682         VMSTATE_UINT32(pborctl, ssys_state),
 683         VMSTATE_UINT32(ldopctl, ssys_state),
 684         VMSTATE_UINT32(int_mask, ssys_state),
 685         VMSTATE_UINT32(int_status, ssys_state),
 686         VMSTATE_UINT32(resc, ssys_state),
 687         VMSTATE_UINT32(rcc, ssys_state),
 688         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 689         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 690         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 691         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 692         VMSTATE_UINT32(clkvclr, ssys_state),
 693         VMSTATE_UINT32(ldoarst, ssys_state),
 694         VMSTATE_END_OF_LIST()
 695     }
 696 };
 697
 698 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 699                               stellaris_board_info * board,
 700                               uint8_t *macaddr)
 701 {
 702     ssys_state *s;
 703
 704     s = g_new0(ssys_state, 1);
 705     s->irq = irq;
 706     s->board = board;
 707     /* Most devices come preprogrammed with a MAC address in the user data. */
 708     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 709     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 710
 711     memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
 712     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 713     ssys_reset(s);
 714     vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s);
 715     return 0;
 716 }
 717
 718
 719 /* I2C controller.  */
 720
 721 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 722 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
 723
 724 struct stellaris_i2c_state {
 725     SysBusDevice parent_obj;
 726
 727     I2CBus *bus;
 728     qemu_irq irq;
 729     MemoryRegion iomem;
 730     uint32_t msa;
 731     uint32_t mcs;
 732     uint32_t mdr;
 733     uint32_t mtpr;
 734     uint32_t mimr;
 735     uint32_t mris;
 736     uint32_t mcr;
 737 };
 738
 739 #define STELLARIS_I2C_MCS_BUSY    0x01
 740 #define STELLARIS_I2C_MCS_ERROR   0x02
 741 #define STELLARIS_I2C_MCS_ADRACK  0x04
 742 #define STELLARIS_I2C_MCS_DATACK  0x08
 743 #define STELLARIS_I2C_MCS_ARBLST  0x10
 744 #define STELLARIS_I2C_MCS_IDLE    0x20
 745 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 746
 747 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 748                                    unsigned size)
 749 {
 750     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 751
 752     switch (offset) {
 753     case 0x00: /* MSA */
 754         return s->msa;
 755     case 0x04: /* MCS */
 756         /* We don't emulate timing, so the controller is never busy.  */
 757         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 758     case 0x08: /* MDR */
 759         return s->mdr;
 760     case 0x0c: /* MTPR */
 761         return s->mtpr;
 762     case 0x10: /* MIMR */
 763         return s->mimr;
 764     case 0x14: /* MRIS */
 765         return s->mris;
 766     case 0x18: /* MMIS */
 767         return s->mris & s->mimr;
 768     case 0x20: /* MCR */
 769         return s->mcr;
 770     default:
 771         qemu_log_mask(LOG_GUEST_ERROR,
 772                       "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
 773         return 0;
 774     }
 775 }
 776
 777 static void stellaris_i2c_update(stellaris_i2c_state *s)
 778 {
 779     int level;
 780
 781     level = (s->mris & s->mimr) != 0;
 782     qemu_set_irq(s->irq, level);
 783 }
 784
 785 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 786                                 uint64_t value, unsigned size)
 787 {
 788     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 789
 790     switch (offset) {
 791     case 0x00: /* MSA */
 792         s->msa = value & 0xff;
 793         break;
 794     case 0x04: /* MCS */
 795         if ((s->mcr & 0x10) == 0) {
 796             /* Disabled.  Do nothing.  */
 797             break;
 798         }
 799         /* Grab the bus if this is starting a transfer.  */
 800         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 801             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 802                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 803             } else {
 804                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 805                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 806             }
 807         }
 808         /* If we don't have the bus then indicate an error.  */
 809         if (!i2c_bus_busy(s->bus)
 810                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 811             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 812             break;
 813         }
 814         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 815         if (value & 1) {
 816             /* Transfer a byte.  */
 817             /* TODO: Handle errors.  */
 818             if (s->msa & 1) {
 819                 /* Recv */
 820                 s->mdr = i2c_recv(s->bus);
 821             } else {
 822                 /* Send */
 823                 i2c_send(s->bus, s->mdr);
 824             }
 825             /* Raise an interrupt.  */
 826             s->mris |= 1;
 827         }
 828         if (value & 4) {
 829             /* Finish transfer.  */
 830             i2c_end_transfer(s->bus);
 831             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 832         }
 833         break;
 834     case 0x08: /* MDR */
 835         s->mdr = value & 0xff;
 836         break;
 837     case 0x0c: /* MTPR */
 838         s->mtpr = value & 0xff;
 839         break;
 840     case 0x10: /* MIMR */
 841         s->mimr = 1;
 842         break;
 843     case 0x1c: /* MICR */
 844         s->mris &= ~value;
 845         break;
 846     case 0x20: /* MCR */
 847         if (value & 1) {
 848             qemu_log_mask(LOG_UNIMP,
 849                           "stellaris_i2c: Loopback not implemented\n");
 850         }
 851         if (value & 0x20) {
 852             qemu_log_mask(LOG_UNIMP,
 853                           "stellaris_i2c: Slave mode not implemented\n");
 854         }
 855         s->mcr = value & 0x31;
 856         break;
 857     default:
 858         qemu_log_mask(LOG_GUEST_ERROR,
 859                       "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
 860     }
 861     stellaris_i2c_update(s);
 862 }
 863
 864 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 865 {
 866     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 867         i2c_end_transfer(s->bus);
 868
 869     s->msa = 0;
 870     s->mcs = 0;
 871     s->mdr = 0;
 872     s->mtpr = 1;
 873     s->mimr = 0;
 874     s->mris = 0;
 875     s->mcr = 0;
 876     stellaris_i2c_update(s);
 877 }
 878
 879 static const MemoryRegionOps stellaris_i2c_ops = {
 880     .read = stellaris_i2c_read,
 881     .write = stellaris_i2c_write,
 882     .endianness = DEVICE_NATIVE_ENDIAN,
 883 };
 884
 885 static const VMStateDescription vmstate_stellaris_i2c = {
 886     .name = "stellaris_i2c",
 887     .version_id = 1,
 888     .minimum_version_id = 1,
 889     .fields = (VMStateField[]) {
 890         VMSTATE_UINT32(msa, stellaris_i2c_state),
 891         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 892         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 893         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 894         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 895         VMSTATE_UINT32(mris, stellaris_i2c_state),
 896         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 897         VMSTATE_END_OF_LIST()
 898     }
 899 };
 900
 901 static void stellaris_i2c_init(Object *obj)
 902 {
 903     DeviceState *dev = DEVICE(obj);
 904     stellaris_i2c_state *s = STELLARIS_I2C(obj);
 905     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 906     I2CBus *bus;
 907
 908     sysbus_init_irq(sbd, &s->irq);
 909     bus = i2c_init_bus(dev, "i2c");
 910     s->bus = bus;
 911
 912     memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
 913                           "i2c", 0x1000);
 914     sysbus_init_mmio(sbd, &s->iomem);
 915     /* ??? For now we only implement the master interface.  */
 916     stellaris_i2c_reset(s);
 917 }
 918
 919 /* Analogue to Digital Converter.  This is only partially implemented,
 920    enough for applications that use a combined ADC and timer tick.  */
 921
 922 #define STELLARIS_ADC_EM_CONTROLLER 0
 923 #define STELLARIS_ADC_EM_COMP       1
 924 #define STELLARIS_ADC_EM_EXTERNAL   4
 925 #define STELLARIS_ADC_EM_TIMER      5
 926 #define STELLARIS_ADC_EM_PWM0       6
 927 #define STELLARIS_ADC_EM_PWM1       7
 928 #define STELLARIS_ADC_EM_PWM2       8
 929
 930 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 931 #define STELLARIS_ADC_FIFO_FULL     0x1000
 932
 933 #define TYPE_STELLARIS_ADC "stellaris-adc"
 934 typedef struct StellarisADCState stellaris_adc_state;
 935 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
 936                          TYPE_STELLARIS_ADC)
 937
 938 struct StellarisADCState {
 939     SysBusDevice parent_obj;
 940
 941     MemoryRegion iomem;
 942     uint32_t actss;
 943     uint32_t ris;
 944     uint32_t im;
 945     uint32_t emux;
 946     uint32_t ostat;
 947     uint32_t ustat;
 948     uint32_t sspri;
 949     uint32_t sac;
 950     struct {
 951         uint32_t state;
 952         uint32_t data[16];
 953     } fifo[4];
 954     uint32_t ssmux[4];
 955     uint32_t ssctl[4];
 956     uint32_t noise;
 957     qemu_irq irq[4];
 958 };
 959
 960 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 961 {
 962     int tail;
 963
 964     tail = s->fifo[n].state & 0xf;
 965     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 966         s->ustat |= 1 << n;
 967     } else {
 968         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 969         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 970         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 971             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 972     }
 973     return s->fifo[n].data[tail];
 974 }
 975
 976 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 977                                      uint32_t value)
 978 {
 979     int head;
 980
 981     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 982        FIFO fir each sequencer.  */
 983     head = (s->fifo[n].state >> 4) & 0xf;
 984     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 985         s->ostat |= 1 << n;
 986         return;
 987     }
 988     s->fifo[n].data[head] = value;
 989     head = (head + 1) & 0xf;
 990     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 991     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 992     if ((s->fifo[n].state & 0xf) == head)
 993         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 994 }
 995
 996 static void stellaris_adc_update(stellaris_adc_state *s)
 997 {
 998     int level;
 999     int n;
1000
1001     for (n = 0; n < 4; n++) {
1002         level = (s->ris & s->im & (1 << n)) != 0;
1003         qemu_set_irq(s->irq[n], level);
1004     }
1005 }
1006
1007 static void stellaris_adc_trigger(void *opaque, int irq, int level)
1008 {
1009     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1010     int n;
1011
1012     for (n = 0; n < 4; n++) {
1013         if ((s->actss & (1 << n)) == 0) {
1014             continue;
1015         }
1016
1017         if (((s->emux >> (n * 4)) & 0xff) != 5) {
1018             continue;
1019         }
1020
1021         /* Some applications use the ADC as a random number source, so introduce
1022            some variation into the signal.  */
1023         s->noise = s->noise * 314159 + 1;
1024         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
1025         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1026         s->ris |= (1 << n);
1027         stellaris_adc_update(s);
1028     }
1029 }
1030
1031 static void stellaris_adc_reset(stellaris_adc_state *s)
1032 {
1033     int n;
1034
1035     for (n = 0; n < 4; n++) {
1036         s->ssmux[n] = 0;
1037         s->ssctl[n] = 0;
1038         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1039     }
1040 }
1041
1042 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1043                                    unsigned size)
1044 {
1045     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1046
1047     /* TODO: Implement this.  */
1048     if (offset >= 0x40 && offset < 0xc0) {
1049         int n;
1050         n = (offset - 0x40) >> 5;
1051         switch (offset & 0x1f) {
1052         case 0x00: /* SSMUX */
1053             return s->ssmux[n];
1054         case 0x04: /* SSCTL */
1055             return s->ssctl[n];
1056         case 0x08: /* SSFIFO */
1057             return stellaris_adc_fifo_read(s, n);
1058         case 0x0c: /* SSFSTAT */
1059             return s->fifo[n].state;
1060         default:
1061             break;
1062         }
1063     }
1064     switch (offset) {
1065     case 0x00: /* ACTSS */
1066         return s->actss;
1067     case 0x04: /* RIS */
1068         return s->ris;
1069     case 0x08: /* IM */
1070         return s->im;
1071     case 0x0c: /* ISC */
1072         return s->ris & s->im;
1073     case 0x10: /* OSTAT */
1074         return s->ostat;
1075     case 0x14: /* EMUX */
1076         return s->emux;
1077     case 0x18: /* USTAT */
1078         return s->ustat;
1079     case 0x20: /* SSPRI */
1080         return s->sspri;
1081     case 0x30: /* SAC */
1082         return s->sac;
1083     default:
1084         qemu_log_mask(LOG_GUEST_ERROR,
1085                       "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
1086         return 0;
1087     }
1088 }
1089
1090 static void stellaris_adc_write(void *opaque, hwaddr offset,
1091                                 uint64_t value, unsigned size)
1092 {
1093     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1094
1095     /* TODO: Implement this.  */
1096     if (offset >= 0x40 && offset < 0xc0) {
1097         int n;
1098         n = (offset - 0x40) >> 5;
1099         switch (offset & 0x1f) {
1100         case 0x00: /* SSMUX */
1101             s->ssmux[n] = value & 0x33333333;
1102             return;
1103         case 0x04: /* SSCTL */
1104             if (value != 6) {
1105                 qemu_log_mask(LOG_UNIMP,
1106                               "ADC: Unimplemented sequence %" PRIx64 "\n",
1107                               value);
1108             }
1109             s->ssctl[n] = value;
1110             return;
1111         default:
1112             break;
1113         }
1114     }
1115     switch (offset) {
1116     case 0x00: /* ACTSS */
1117         s->actss = value & 0xf;
1118         break;
1119     case 0x08: /* IM */
1120         s->im = value;
1121         break;
1122     case 0x0c: /* ISC */
1123         s->ris &= ~value;
1124         break;
1125     case 0x10: /* OSTAT */
1126         s->ostat &= ~value;
1127         break;
1128     case 0x14: /* EMUX */
1129         s->emux = value;
1130         break;
1131     case 0x18: /* USTAT */
1132         s->ustat &= ~value;
1133         break;
1134     case 0x20: /* SSPRI */
1135         s->sspri = value;
1136         break;
1137     case 0x28: /* PSSI */
1138         qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
1139         break;
1140     case 0x30: /* SAC */
1141         s->sac = value;
1142         break;
1143     default:
1144         qemu_log_mask(LOG_GUEST_ERROR,
1145                       "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
1146     }
1147     stellaris_adc_update(s);
1148 }
1149
1150 static const MemoryRegionOps stellaris_adc_ops = {
1151     .read = stellaris_adc_read,
1152     .write = stellaris_adc_write,
1153     .endianness = DEVICE_NATIVE_ENDIAN,
1154 };
1155
1156 static const VMStateDescription vmstate_stellaris_adc = {
1157     .name = "stellaris_adc",
1158     .version_id = 1,
1159     .minimum_version_id = 1,
1160     .fields = (VMStateField[]) {
1161         VMSTATE_UINT32(actss, stellaris_adc_state),
1162         VMSTATE_UINT32(ris, stellaris_adc_state),
1163         VMSTATE_UINT32(im, stellaris_adc_state),
1164         VMSTATE_UINT32(emux, stellaris_adc_state),
1165         VMSTATE_UINT32(ostat, stellaris_adc_state),
1166         VMSTATE_UINT32(ustat, stellaris_adc_state),
1167         VMSTATE_UINT32(sspri, stellaris_adc_state),
1168         VMSTATE_UINT32(sac, stellaris_adc_state),
1169         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1170         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1171         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1172         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1173         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1174         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1175         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1176         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1177         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1178         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1179         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1180         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1181         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1182         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1183         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1184         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1185         VMSTATE_UINT32(noise, stellaris_adc_state),
1186         VMSTATE_END_OF_LIST()
1187     }
1188 };
1189
1190 static void stellaris_adc_init(Object *obj)
1191 {
1192     DeviceState *dev = DEVICE(obj);
1193     stellaris_adc_state *s = STELLARIS_ADC(obj);
1194     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1195     int n;
1196
1197     for (n = 0; n < 4; n++) {
1198         sysbus_init_irq(sbd, &s->irq[n]);
1199     }
1200
1201     memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1202                           "adc", 0x1000);
1203     sysbus_init_mmio(sbd, &s->iomem);
1204     stellaris_adc_reset(s);
1205     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1206 }
1207
1208 /* Board init.  */
1209 static stellaris_board_info stellaris_boards[] = {
1210   { "LM3S811EVB",
1211     0,
1212     0x0032000e,
1213     0x001f001f, /* dc0 */
1214     0x001132bf,
1215     0x01071013,
1216     0x3f0f01ff,
1217     0x0000001f,
1218     BP_OLED_I2C
1219   },
1220   { "LM3S6965EVB",
1221     0x10010002,
1222     0x1073402e,
1223     0x00ff007f, /* dc0 */
1224     0x001133ff,
1225     0x030f5317,
1226     0x0f0f87ff,
1227     0x5000007f,
1228     BP_OLED_SSI | BP_GAMEPAD
1229   }
1230 };
1231
1232 static void stellaris_init(MachineState *ms, stellaris_board_info *board)
1233 {
1234     static const int uart_irq[] = {5, 6, 33, 34};
1235     static const int timer_irq[] = {19, 21, 23, 35};
1236     static const uint32_t gpio_addr[7] =
1237       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1238         0x40024000, 0x40025000, 0x40026000};
1239     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1240
1241     /* Memory map of SoC devices, from
1242      * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1243      * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1244      *
1245      * 40000000 wdtimer
1246      * 40002000 i2c (unimplemented)
1247      * 40004000 GPIO
1248      * 40005000 GPIO
1249      * 40006000 GPIO
1250      * 40007000 GPIO
1251      * 40008000 SSI
1252      * 4000c000 UART
1253      * 4000d000 UART
1254      * 4000e000 UART
1255      * 40020000 i2c
1256      * 40021000 i2c (unimplemented)
1257      * 40024000 GPIO
1258      * 40025000 GPIO
1259      * 40026000 GPIO
1260      * 40028000 PWM (unimplemented)
1261      * 4002c000 QEI (unimplemented)
1262      * 4002d000 QEI (unimplemented)
1263      * 40030000 gptimer
1264      * 40031000 gptimer
1265      * 40032000 gptimer
1266      * 40033000 gptimer
1267      * 40038000 ADC
1268      * 4003c000 analogue comparator (unimplemented)
1269      * 40048000 ethernet
1270      * 400fc000 hibernation module (unimplemented)
1271      * 400fd000 flash memory control (unimplemented)
1272      * 400fe000 system control
1273      */
1274
1275     DeviceState *gpio_dev[7], *nvic;
1276     qemu_irq gpio_in[7][8];
1277     qemu_irq gpio_out[7][8];
1278     qemu_irq adc;
1279     int sram_size;
1280     int flash_size;
1281     I2CBus *i2c;
1282     DeviceState *dev;
1283     int i;
1284     int j;
1285
1286     MemoryRegion *sram = g_new(MemoryRegion, 1);
1287     MemoryRegion *flash = g_new(MemoryRegion, 1);
1288     MemoryRegion *system_memory = get_system_memory();
1289
1290     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1291     sram_size = ((board->dc0 >> 18) + 1) * 1024;
1292
1293     /* Flash programming is done via the SCU, so pretend it is ROM.  */
1294     memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1295                            &error_fatal);
1296     memory_region_add_subregion(system_memory, 0, flash);
1297
1298     memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1299                            &error_fatal);
1300     memory_region_add_subregion(system_memory, 0x20000000, sram);
1301
1302     nvic = qdev_new(TYPE_ARMV7M);
1303     qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1304     qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1305     qdev_prop_set_bit(nvic, "enable-bitband", true);
1306     object_property_set_link(OBJECT(nvic), "memory",
1307                              OBJECT(get_system_memory()), &error_abort);
1308     /* This will exit with an error if the user passed us a bad cpu_type */
1309     sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
1310
1311     if (board->dc1 & (1 << 16)) {
1312         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1313                                     qdev_get_gpio_in(nvic, 14),
1314                                     qdev_get_gpio_in(nvic, 15),
1315                                     qdev_get_gpio_in(nvic, 16),
1316                                     qdev_get_gpio_in(nvic, 17),
1317                                     NULL);
1318         adc = qdev_get_gpio_in(dev, 0);
1319     } else {
1320         adc = NULL;
1321     }
1322     for (i = 0; i < 4; i++) {
1323         if (board->dc2 & (0x10000 << i)) {
1324             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1325                                        0x40030000 + i * 0x1000,
1326                                        qdev_get_gpio_in(nvic, timer_irq[i]));
1327             /* TODO: This is incorrect, but we get away with it because
1328                the ADC output is only ever pulsed.  */
1329             qdev_connect_gpio_out(dev, 0, adc);
1330         }
1331     }
1332
1333     stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1334                        board, nd_table[0].macaddr.a);
1335
1336
1337     if (board->dc1 & (1 << 3)) { /* watchdog present */
1338         dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1339
1340         /* system_clock_scale is valid now */
1341         uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
1342         qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
1343
1344         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1345         sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1346                         0,
1347                         0x40000000u);
1348         sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1349                            0,
1350                            qdev_get_gpio_in(nvic, 18));
1351     }
1352
1353
1354     for (i = 0; i < 7; i++) {
1355         if (board->dc4 & (1 << i)) {
1356             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1357                                                qdev_get_gpio_in(nvic,
1358                                                                 gpio_irq[i]));
1359             for (j = 0; j < 8; j++) {
1360                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1361                 gpio_out[i][j] = NULL;
1362             }
1363         }
1364     }
1365
1366     if (board->dc2 & (1 << 12)) {
1367         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1368                                    qdev_get_gpio_in(nvic, 8));
1369         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1370         if (board->peripherals & BP_OLED_I2C) {
1371             i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
1372         }
1373     }
1374
1375     for (i = 0; i < 4; i++) {
1376         if (board->dc2 & (1 << i)) {
1377             pl011_luminary_create(0x4000c000 + i * 0x1000,
1378                                   qdev_get_gpio_in(nvic, uart_irq[i]),
1379                                   serial_hd(i));
1380         }
1381     }
1382     if (board->dc2 & (1 << 4)) {
1383         dev = sysbus_create_simple("pl022", 0x40008000,
1384                                    qdev_get_gpio_in(nvic, 7));
1385         if (board->peripherals & BP_OLED_SSI) {
1386             void *bus;
1387             DeviceState *sddev;
1388             DeviceState *ssddev;
1389
1390             /* Some boards have both an OLED controller and SD card connected to
1391              * the same SSI port, with the SD card chip select connected to a
1392              * GPIO pin.  Technically the OLED chip select is connected to the
1393              * SSI Fss pin.  We do not bother emulating that as both devices
1394              * should never be selected simultaneously, and our OLED controller
1395              * ignores stray 0xff commands that occur when deselecting the SD
1396              * card.
1397              */
1398             bus = qdev_get_child_bus(dev, "ssi");
1399
1400             sddev = ssi_create_peripheral(bus, "ssi-sd");
1401             ssddev = ssi_create_peripheral(bus, "ssd0323");
1402             gpio_out[GPIO_D][0] = qemu_irq_split(
1403                     qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1404                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1405             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1406
1407             /* Make sure the select pin is high.  */
1408             qemu_irq_raise(gpio_out[GPIO_D][0]);
1409         }
1410     }
1411     if (board->dc4 & (1 << 28)) {
1412         DeviceState *enet;
1413
1414         qemu_check_nic_model(&nd_table[0], "stellaris");
1415
1416         enet = qdev_new("stellaris_enet");
1417         qdev_set_nic_properties(enet, &nd_table[0]);
1418         sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1419         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1420         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1421     }
1422     if (board->peripherals & BP_GAMEPAD) {
1423         qemu_irq gpad_irq[5];
1424         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1425
1426         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1427         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1428         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1429         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1430         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1431
1432         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1433     }
1434     for (i = 0; i < 7; i++) {
1435         if (board->dc4 & (1 << i)) {
1436             for (j = 0; j < 8; j++) {
1437                 if (gpio_out[i][j]) {
1438                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1439                 }
1440             }
1441         }
1442     }
1443
1444     /* Add dummy regions for the devices we don't implement yet,
1445      * so guest accesses don't cause unlogged crashes.
1446      */
1447     create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1448     create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1449     create_unimplemented_device("PWM", 0x40028000, 0x1000);
1450     create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1451     create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1452     create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1453     create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1454     create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1455
1456     armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1457 }
1458
1459 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1460 static void lm3s811evb_init(MachineState *machine)
1461 {
1462     stellaris_init(machine, &stellaris_boards[0]);
1463 }
1464
1465 static void lm3s6965evb_init(MachineState *machine)
1466 {
1467     stellaris_init(machine, &stellaris_boards[1]);
1468 }
1469
1470 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1471 {
1472     MachineClass *mc = MACHINE_CLASS(oc);
1473
1474     mc->desc = "Stellaris LM3S811EVB";
1475     mc->init = lm3s811evb_init;
1476     mc->ignore_memory_transaction_failures = true;
1477     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1478 }
1479
1480 static const TypeInfo lm3s811evb_type = {
1481     .name = MACHINE_TYPE_NAME("lm3s811evb"),
1482     .parent = TYPE_MACHINE,
1483     .class_init = lm3s811evb_class_init,
1484 };
1485
1486 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1487 {
1488     MachineClass *mc = MACHINE_CLASS(oc);
1489
1490     mc->desc = "Stellaris LM3S6965EVB";
1491     mc->init = lm3s6965evb_init;
1492     mc->ignore_memory_transaction_failures = true;
1493     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1494 }
1495
1496 static const TypeInfo lm3s6965evb_type = {
1497     .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1498     .parent = TYPE_MACHINE,
1499     .class_init = lm3s6965evb_class_init,
1500 };
1501
1502 static void stellaris_machine_init(void)
1503 {
1504     type_register_static(&lm3s811evb_type);
1505     type_register_static(&lm3s6965evb_type);
1506 }
1507
1508 type_init(stellaris_machine_init)
1509
1510 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1511 {
1512     DeviceClass *dc = DEVICE_CLASS(klass);
1513
1514     dc->vmsd = &vmstate_stellaris_i2c;
1515 }
1516
1517 static const TypeInfo stellaris_i2c_info = {
1518     .name          = TYPE_STELLARIS_I2C,
1519     .parent        = TYPE_SYS_BUS_DEVICE,
1520     .instance_size = sizeof(stellaris_i2c_state),
1521     .instance_init = stellaris_i2c_init,
1522     .class_init    = stellaris_i2c_class_init,
1523 };
1524
1525 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1526 {
1527     DeviceClass *dc = DEVICE_CLASS(klass);
1528
1529     dc->vmsd = &vmstate_stellaris_gptm;
1530     dc->realize = stellaris_gptm_realize;
1531 }
1532
1533 static const TypeInfo stellaris_gptm_info = {
1534     .name          = TYPE_STELLARIS_GPTM,
1535     .parent        = TYPE_SYS_BUS_DEVICE,
1536     .instance_size = sizeof(gptm_state),
1537     .instance_init = stellaris_gptm_init,
1538     .class_init    = stellaris_gptm_class_init,
1539 };
1540
1541 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1542 {
1543     DeviceClass *dc = DEVICE_CLASS(klass);
1544
1545     dc->vmsd = &vmstate_stellaris_adc;
1546 }
1547
1548 static const TypeInfo stellaris_adc_info = {
1549     .name          = TYPE_STELLARIS_ADC,
1550     .parent        = TYPE_SYS_BUS_DEVICE,
1551     .instance_size = sizeof(stellaris_adc_state),
1552     .instance_init = stellaris_adc_init,
1553     .class_init    = stellaris_adc_class_init,
1554 };
1555
1556 static void stellaris_register_types(void)
1557 {
1558     type_register_static(&stellaris_i2c_info);
1559     type_register_static(&stellaris_gptm_info);
1560     type_register_static(&stellaris_adc_info);
1561 }
1562
1563 type_init(stellaris_register_types)