4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
34 #include "qemu-common.h"
35 #include "migration/vmstate.h"
36 #include "exec/exec-all.h"
39 static void xtensa_cpu_set_pc(CPUState
*cs
, vaddr value
)
41 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
46 static bool xtensa_cpu_has_work(CPUState
*cs
)
48 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
50 return !cpu
->env
.runstall
&& cpu
->env
.pending_irq_level
;
53 /* CPUClass::reset() */
54 static void xtensa_cpu_reset(CPUState
*s
)
56 XtensaCPU
*cpu
= XTENSA_CPU(s
);
57 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(cpu
);
58 CPUXtensaState
*env
= &cpu
->env
;
62 env
->exception_taken
= 0;
63 env
->pc
= env
->config
->exception_vector
[EXC_RESET0
+ env
->static_vectors
];
64 env
->sregs
[LITBASE
] &= ~1;
65 env
->sregs
[PS
] = xtensa_option_enabled(env
->config
,
66 XTENSA_OPTION_INTERRUPT
) ? 0x1f : 0x10;
67 env
->sregs
[VECBASE
] = env
->config
->vecbase
;
68 env
->sregs
[IBREAKENABLE
] = 0;
69 env
->sregs
[MEMCTL
] = MEMCTL_IL0EN
& env
->config
->memctl_mask
;
70 env
->sregs
[CACHEATTR
] = 0x22222222;
71 env
->sregs
[ATOMCTL
] = xtensa_option_enabled(env
->config
,
72 XTENSA_OPTION_ATOMCTL
) ? 0x28 : 0x15;
73 env
->sregs
[CONFIGID0
] = env
->config
->configid
[0];
74 env
->sregs
[CONFIGID1
] = env
->config
->configid
[1];
76 env
->pending_irq_level
= 0;
78 s
->halted
= env
->runstall
;
81 static ObjectClass
*xtensa_cpu_class_by_name(const char *cpu_model
)
86 if (cpu_model
== NULL
) {
90 typename
= g_strdup_printf("%s-" TYPE_XTENSA_CPU
, cpu_model
);
91 oc
= object_class_by_name(typename
);
93 if (oc
== NULL
|| !object_class_dynamic_cast(oc
, TYPE_XTENSA_CPU
) ||
94 object_class_is_abstract(oc
)) {
100 static void xtensa_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
102 CPUState
*cs
= CPU(dev
);
103 XtensaCPU
*cpu
= XTENSA_CPU(dev
);
104 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(dev
);
105 Error
*local_err
= NULL
;
107 xtensa_irq_init(&cpu
->env
);
109 cpu_exec_realizefn(cs
, &local_err
);
110 if (local_err
!= NULL
) {
111 error_propagate(errp
, local_err
);
115 cs
->gdb_num_regs
= xcc
->config
->gdb_regmap
.num_regs
;
119 xcc
->parent_realize(dev
, errp
);
122 static void xtensa_cpu_initfn(Object
*obj
)
124 CPUState
*cs
= CPU(obj
);
125 XtensaCPU
*cpu
= XTENSA_CPU(obj
);
126 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(obj
);
127 CPUXtensaState
*env
= &cpu
->env
;
128 static bool tcg_inited
;
131 env
->config
= xcc
->config
;
133 env
->address_space_er
= g_malloc(sizeof(*env
->address_space_er
));
134 env
->system_er
= g_malloc(sizeof(*env
->system_er
));
135 memory_region_init_io(env
->system_er
, NULL
, NULL
, env
, "er",
136 UINT64_C(0x100000000));
137 address_space_init(env
->address_space_er
, env
->system_er
, "ER");
139 if (tcg_enabled() && !tcg_inited
) {
141 xtensa_translate_init();
145 static const VMStateDescription vmstate_xtensa_cpu
= {
150 static void xtensa_cpu_class_init(ObjectClass
*oc
, void *data
)
152 DeviceClass
*dc
= DEVICE_CLASS(oc
);
153 CPUClass
*cc
= CPU_CLASS(oc
);
154 XtensaCPUClass
*xcc
= XTENSA_CPU_CLASS(cc
);
156 xcc
->parent_realize
= dc
->realize
;
157 dc
->realize
= xtensa_cpu_realizefn
;
159 xcc
->parent_reset
= cc
->reset
;
160 cc
->reset
= xtensa_cpu_reset
;
162 cc
->class_by_name
= xtensa_cpu_class_by_name
;
163 cc
->has_work
= xtensa_cpu_has_work
;
164 cc
->do_interrupt
= xtensa_cpu_do_interrupt
;
165 cc
->cpu_exec_interrupt
= xtensa_cpu_exec_interrupt
;
166 cc
->dump_state
= xtensa_cpu_dump_state
;
167 cc
->set_pc
= xtensa_cpu_set_pc
;
168 cc
->gdb_read_register
= xtensa_cpu_gdb_read_register
;
169 cc
->gdb_write_register
= xtensa_cpu_gdb_write_register
;
170 cc
->gdb_stop_before_watchpoint
= true;
171 #ifndef CONFIG_USER_ONLY
172 cc
->do_unaligned_access
= xtensa_cpu_do_unaligned_access
;
173 cc
->get_phys_page_debug
= xtensa_cpu_get_phys_page_debug
;
174 cc
->do_unassigned_access
= xtensa_cpu_do_unassigned_access
;
176 cc
->debug_excp_handler
= xtensa_breakpoint_handler
;
177 dc
->vmsd
= &vmstate_xtensa_cpu
;
180 static const TypeInfo xtensa_cpu_type_info
= {
181 .name
= TYPE_XTENSA_CPU
,
183 .instance_size
= sizeof(XtensaCPU
),
184 .instance_init
= xtensa_cpu_initfn
,
186 .class_size
= sizeof(XtensaCPUClass
),
187 .class_init
= xtensa_cpu_class_init
,
190 static void xtensa_cpu_register_types(void)
192 type_register_static(&xtensa_cpu_type_info
);
195 type_init(xtensa_cpu_register_types
)