4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/units.h"
22 #include "qemu/main-loop.h"
24 #include "exec/helper-proto.h"
25 #include "internals.h"
26 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
29 #define SIGNBIT (uint32_t)0x80000000
30 #define SIGNBIT64 ((uint64_t)1 << 63)
32 static CPUState
*do_raise_exception(CPUARMState
*env
, uint32_t excp
,
33 uint32_t syndrome
, uint32_t target_el
)
35 CPUState
*cs
= env_cpu(env
);
37 if (target_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
39 * Redirect NS EL1 exceptions to NS EL2. These are reported with
40 * their original syndrome register value, with the exception of
41 * SIMD/FP access traps, which are reported as uncategorized
42 * (see DDI0478C.a D1.10.4)
45 if (syn_get_ec(syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
46 syndrome
= syn_uncategorized();
50 assert(!excp_is_internal(excp
));
51 cs
->exception_index
= excp
;
52 env
->exception
.syndrome
= syndrome
;
53 env
->exception
.target_el
= target_el
;
58 void raise_exception(CPUARMState
*env
, uint32_t excp
,
59 uint32_t syndrome
, uint32_t target_el
)
61 CPUState
*cs
= do_raise_exception(env
, excp
, syndrome
, target_el
);
65 void raise_exception_ra(CPUARMState
*env
, uint32_t excp
, uint32_t syndrome
,
66 uint32_t target_el
, uintptr_t ra
)
68 CPUState
*cs
= do_raise_exception(env
, excp
, syndrome
, target_el
);
69 cpu_loop_exit_restore(cs
, ra
);
72 uint32_t HELPER(neon_tbl
)(uint32_t ireg
, uint32_t def
, void *vn
,
79 for (shift
= 0; shift
< 32; shift
+= 8) {
80 uint32_t index
= (ireg
>> shift
) & 0xff;
81 if (index
< maxindex
) {
82 uint32_t tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
85 val
|= def
& (0xff << shift
);
91 void HELPER(v8m_stackcheck
)(CPUARMState
*env
, uint32_t newvalue
)
94 * Perform the v8M stack limit check for SP updates from translated code,
95 * raising an exception if the limit is breached.
97 if (newvalue
< v7m_sp_limit(env
)) {
98 CPUState
*cs
= env_cpu(env
);
101 * Stack limit exceptions are a rare case, so rather than syncing
102 * PC/condbits before the call, we use cpu_restore_state() to
103 * get them right before raising the exception.
105 cpu_restore_state(cs
, GETPC(), true);
106 raise_exception(env
, EXCP_STKOF
, 0, 1);
110 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
112 uint32_t res
= a
+ b
;
113 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
118 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
120 uint32_t res
= a
+ b
;
121 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
123 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
128 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
130 uint32_t res
= a
- b
;
131 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
133 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
138 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
140 uint32_t res
= a
+ b
;
148 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
150 uint32_t res
= a
- b
;
158 /* Signed saturation. */
159 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
165 mask
= (1u << shift
) - 1;
169 } else if (top
< -1) {
176 /* Unsigned saturation. */
177 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
181 max
= (1u << shift
) - 1;
185 } else if (val
> max
) {
192 /* Signed saturate. */
193 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
195 return do_ssat(env
, x
, shift
);
198 /* Dual halfword signed saturate. */
199 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
203 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
204 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
208 /* Unsigned saturate. */
209 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
211 return do_usat(env
, x
, shift
);
214 /* Dual halfword unsigned saturate. */
215 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
219 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
220 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
224 void HELPER(setend
)(CPUARMState
*env
)
226 env
->uncached_cpsr
^= CPSR_E
;
227 arm_rebuild_hflags(env
);
230 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
231 * The function returns the target EL (1-3) if the instruction is to be trapped;
232 * otherwise it returns 0 indicating it is not trapped.
234 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
236 int cur_el
= arm_current_el(env
);
239 if (arm_feature(env
, ARM_FEATURE_M
)) {
240 /* M profile cores can never trap WFI/WFE. */
244 /* If we are currently in EL0 then we need to check if SCTLR is set up for
245 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
247 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
250 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
251 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
252 /* Secure EL0 and Secure PL1 is at EL3 */
258 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
263 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
264 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
265 * bits will be zero indicating no trap.
268 mask
= is_wfe
? HCR_TWE
: HCR_TWI
;
269 if (arm_hcr_el2_eff(env
) & mask
) {
274 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
276 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
277 if (env
->cp15
.scr_el3
& mask
) {
285 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
287 CPUState
*cs
= env_cpu(env
);
288 int target_el
= check_wfx_trap(env
, false);
290 if (cpu_has_work(cs
)) {
291 /* Don't bother to go into our "low power state" if
292 * we would just wake up immediately.
299 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
303 cs
->exception_index
= EXCP_HLT
;
308 void HELPER(wfe
)(CPUARMState
*env
)
310 /* This is a hint instruction that is semantically different
311 * from YIELD even though we currently implement it identically.
312 * Don't actually halt the CPU, just yield back to top
313 * level loop. This is not going into a "low power state"
314 * (ie halting until some event occurs), so we never take
315 * a configurable trap to a different exception level.
320 void HELPER(yield
)(CPUARMState
*env
)
322 CPUState
*cs
= env_cpu(env
);
324 /* This is a non-trappable hint instruction that generally indicates
325 * that the guest is currently busy-looping. Yield control back to the
326 * top level loop so that a more deserving VCPU has a chance to run.
328 cs
->exception_index
= EXCP_YIELD
;
332 /* Raise an internal-to-QEMU exception. This is limited to only
333 * those EXCP values which are special cases for QEMU to interrupt
334 * execution and not to be used for exceptions which are passed to
335 * the guest (those must all have syndrome information and thus should
336 * use exception_with_syndrome).
338 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
340 CPUState
*cs
= env_cpu(env
);
342 assert(excp_is_internal(excp
));
343 cs
->exception_index
= excp
;
347 /* Raise an exception with the specified syndrome register value */
348 void HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
349 uint32_t syndrome
, uint32_t target_el
)
351 raise_exception(env
, excp
, syndrome
, target_el
);
354 /* Raise an EXCP_BKPT with the specified syndrome register value,
355 * targeting the correct exception level for debug exceptions.
357 void HELPER(exception_bkpt_insn
)(CPUARMState
*env
, uint32_t syndrome
)
359 int debug_el
= arm_debug_target_el(env
);
360 int cur_el
= arm_current_el(env
);
362 /* FSR will only be used if the debug target EL is AArch32. */
363 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
364 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
365 * values to the guest that it shouldn't be able to see at its
366 * exception/security level.
368 env
->exception
.vaddress
= 0;
370 * Other kinds of architectural debug exception are ignored if
371 * they target an exception level below the current one (in QEMU
372 * this is checked by arm_generate_debug_exceptions()). Breakpoint
373 * instructions are special because they always generate an exception
374 * to somewhere: if they can't go to the configured debug exception
375 * level they are taken to the current exception level.
377 if (debug_el
< cur_el
) {
380 raise_exception(env
, EXCP_BKPT
, syndrome
, debug_el
);
383 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
385 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
388 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
390 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
391 /* TODO: Not all cpsr bits are relevant to hflags. */
392 arm_rebuild_hflags(env
);
395 /* Write the CPSR for a 32-bit exception return */
396 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
398 qemu_mutex_lock_iothread();
399 arm_call_pre_el_change_hook(env_archcpu(env
));
400 qemu_mutex_unlock_iothread();
402 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
404 /* Generated code has already stored the new PC value, but
405 * without masking out its low bits, because which bits need
406 * masking depends on whether we're returning to Thumb or ARM
407 * state. Do the masking now.
409 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
410 arm_rebuild_hflags(env
);
412 qemu_mutex_lock_iothread();
413 arm_call_el_change_hook(env_archcpu(env
));
414 qemu_mutex_unlock_iothread();
417 /* Access to user mode registers from privileged modes. */
418 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
423 val
= env
->banked_r13
[BANK_USRSYS
];
424 } else if (regno
== 14) {
425 val
= env
->banked_r14
[BANK_USRSYS
];
426 } else if (regno
>= 8
427 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
428 val
= env
->usr_regs
[regno
- 8];
430 val
= env
->regs
[regno
];
435 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
438 env
->banked_r13
[BANK_USRSYS
] = val
;
439 } else if (regno
== 14) {
440 env
->banked_r14
[BANK_USRSYS
] = val
;
441 } else if (regno
>= 8
442 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
443 env
->usr_regs
[regno
- 8] = val
;
445 env
->regs
[regno
] = val
;
449 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
451 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
454 env
->banked_r13
[bank_number(mode
)] = val
;
458 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
460 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
461 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
462 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
464 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
465 exception_target_el(env
));
468 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
469 return env
->regs
[13];
471 return env
->banked_r13
[bank_number(mode
)];
475 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
478 /* Raise an exception if the requested access is one of the UNPREDICTABLE
479 * cases; otherwise return. This broadly corresponds to the pseudocode
480 * BankedRegisterAccessValid() and SPSRAccessValid(),
481 * except that we have already handled some cases at translate time.
483 int curmode
= env
->uncached_cpsr
& CPSR_M
;
486 /* ELR_Hyp: a special case because access from tgtmode is OK */
487 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
493 if (curmode
== tgtmode
) {
497 if (tgtmode
== ARM_CPU_MODE_USR
) {
500 if (curmode
!= ARM_CPU_MODE_FIQ
) {
505 if (curmode
== ARM_CPU_MODE_SYS
) {
510 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
519 if (tgtmode
== ARM_CPU_MODE_HYP
) {
520 /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
521 if (curmode
!= ARM_CPU_MODE_MON
) {
529 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
530 exception_target_el(env
));
533 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
536 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
540 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
542 case 17: /* ELR_Hyp */
543 env
->elr_el
[2] = value
;
546 env
->banked_r13
[bank_number(tgtmode
)] = value
;
549 env
->banked_r14
[r14_bank_number(tgtmode
)] = value
;
553 case ARM_CPU_MODE_USR
:
554 env
->usr_regs
[regno
- 8] = value
;
556 case ARM_CPU_MODE_FIQ
:
557 env
->fiq_regs
[regno
- 8] = value
;
560 g_assert_not_reached();
564 g_assert_not_reached();
568 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
570 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
574 return env
->banked_spsr
[bank_number(tgtmode
)];
575 case 17: /* ELR_Hyp */
576 return env
->elr_el
[2];
578 return env
->banked_r13
[bank_number(tgtmode
)];
580 return env
->banked_r14
[r14_bank_number(tgtmode
)];
583 case ARM_CPU_MODE_USR
:
584 return env
->usr_regs
[regno
- 8];
585 case ARM_CPU_MODE_FIQ
:
586 return env
->fiq_regs
[regno
- 8];
588 g_assert_not_reached();
591 g_assert_not_reached();
595 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
598 const ARMCPRegInfo
*ri
= rip
;
601 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
602 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
603 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
607 * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
608 * to sysregs non accessible at EL0 to have UNDEF-ed already.
610 if (!is_a64(env
) && arm_current_el(env
) < 2 && ri
->cp
== 15 &&
611 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
612 uint32_t mask
= 1 << ri
->crn
;
614 if (ri
->type
& ARM_CP_64BIT
) {
618 /* T4 and T14 are RES0 */
619 mask
&= ~((1 << 4) | (1 << 14));
621 if (env
->cp15
.hstr_el2
& mask
) {
631 switch (ri
->accessfn(env
, ri
, isread
)) {
635 target_el
= exception_target_el(env
);
637 case CP_ACCESS_TRAP_EL2
:
638 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
639 * a bug in the access function.
641 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
644 case CP_ACCESS_TRAP_EL3
:
647 case CP_ACCESS_TRAP_UNCATEGORIZED
:
648 target_el
= exception_target_el(env
);
649 syndrome
= syn_uncategorized();
651 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
653 syndrome
= syn_uncategorized();
655 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
657 syndrome
= syn_uncategorized();
659 case CP_ACCESS_TRAP_FP_EL2
:
661 /* Since we are an implementation that takes exceptions on a trapped
662 * conditional insn only if the insn has passed its condition code
663 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
664 * (which is also the required value for AArch64 traps).
666 syndrome
= syn_fp_access_trap(1, 0xe, false);
668 case CP_ACCESS_TRAP_FP_EL3
:
670 syndrome
= syn_fp_access_trap(1, 0xe, false);
673 g_assert_not_reached();
677 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
680 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
682 const ARMCPRegInfo
*ri
= rip
;
684 if (ri
->type
& ARM_CP_IO
) {
685 qemu_mutex_lock_iothread();
686 ri
->writefn(env
, ri
, value
);
687 qemu_mutex_unlock_iothread();
689 ri
->writefn(env
, ri
, value
);
693 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
695 const ARMCPRegInfo
*ri
= rip
;
698 if (ri
->type
& ARM_CP_IO
) {
699 qemu_mutex_lock_iothread();
700 res
= ri
->readfn(env
, ri
);
701 qemu_mutex_unlock_iothread();
703 res
= ri
->readfn(env
, ri
);
709 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
711 const ARMCPRegInfo
*ri
= rip
;
713 if (ri
->type
& ARM_CP_IO
) {
714 qemu_mutex_lock_iothread();
715 ri
->writefn(env
, ri
, value
);
716 qemu_mutex_unlock_iothread();
718 ri
->writefn(env
, ri
, value
);
722 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
724 const ARMCPRegInfo
*ri
= rip
;
727 if (ri
->type
& ARM_CP_IO
) {
728 qemu_mutex_lock_iothread();
729 res
= ri
->readfn(env
, ri
);
730 qemu_mutex_unlock_iothread();
732 res
= ri
->readfn(env
, ri
);
738 void HELPER(pre_hvc
)(CPUARMState
*env
)
740 ARMCPU
*cpu
= env_archcpu(env
);
741 int cur_el
= arm_current_el(env
);
742 /* FIXME: Use actual secure state. */
746 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
747 /* If PSCI is enabled and this looks like a valid PSCI call then
748 * that overrides the architecturally mandated HVC behaviour.
753 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
754 /* If EL2 doesn't exist, HVC always UNDEFs */
756 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
757 /* EL3.HCE has priority over EL2.HCD. */
758 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
760 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
763 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
764 * For ARMv8/AArch64, HVC is allowed in EL3.
765 * Note that we've already trapped HVC from EL0 at translation
768 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
773 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
774 exception_target_el(env
));
778 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
780 ARMCPU
*cpu
= env_archcpu(env
);
781 int cur_el
= arm_current_el(env
);
782 bool secure
= arm_is_secure(env
);
783 bool smd_flag
= env
->cp15
.scr_el3
& SCR_SMD
;
786 * SMC behaviour is summarized in the following table.
787 * This helper handles the "Trap to EL2" and "Undef insn" cases.
788 * The "Trap to EL3" and "PSCI call" cases are handled in the exception
791 * -> ARM_FEATURE_EL3 and !SMD
792 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
794 * Conduit SMC, valid call Trap to EL2 PSCI Call
795 * Conduit SMC, inval call Trap to EL2 Trap to EL3
796 * Conduit not SMC Trap to EL2 Trap to EL3
799 * -> ARM_FEATURE_EL3 and SMD
800 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
802 * Conduit SMC, valid call Trap to EL2 PSCI Call
803 * Conduit SMC, inval call Trap to EL2 Undef insn
804 * Conduit not SMC Trap to EL2 Undef insn
807 * -> !ARM_FEATURE_EL3
808 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
810 * Conduit SMC, valid call Trap to EL2 PSCI Call
811 * Conduit SMC, inval call Trap to EL2 Undef insn
812 * Conduit not SMC Undef insn Undef insn
815 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
816 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
817 * extensions, SMD only applies to NS state.
818 * On ARMv7 without the Virtualization extensions, the SMD bit
819 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
820 * so we need not special case this here.
822 bool smd
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd_flag
823 : smd_flag
&& !secure
;
825 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
826 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
827 /* If we have no EL3 then SMC always UNDEFs and can't be
828 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
829 * firmware within QEMU, and we want an EL2 guest to be able
830 * to forbid its EL1 from making PSCI calls into QEMU's
831 * "firmware" via HCR.TSC, so for these purposes treat
832 * PSCI-via-SMC as implying an EL3.
833 * This handles the very last line of the previous table.
835 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
836 exception_target_el(env
));
839 if (cur_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TSC
)) {
840 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
841 * We also want an EL2 guest to be able to forbid its EL1 from
842 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
843 * This handles all the "Trap to EL2" cases of the previous table.
845 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
848 /* Catch the two remaining "Undef insn" cases of the previous table:
849 * - PSCI conduit is SMC but we don't have a valid PCSI call,
850 * - We don't have EL3 or SMD is set.
852 if (!arm_is_psci_call(cpu
, EXCP_SMC
) &&
853 (smd
|| !arm_feature(env
, ARM_FEATURE_EL3
))) {
854 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
855 exception_target_el(env
));
859 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
860 The only way to do that in TCG is a conditional branch, which clobbers
861 all our temporaries. For now implement these as helper functions. */
863 /* Similarly for variable shift instructions. */
865 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
867 int shift
= i
& 0xff;
874 } else if (shift
!= 0) {
875 env
->CF
= (x
>> (32 - shift
)) & 1;
881 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
883 int shift
= i
& 0xff;
886 env
->CF
= (x
>> 31) & 1;
890 } else if (shift
!= 0) {
891 env
->CF
= (x
>> (shift
- 1)) & 1;
897 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
899 int shift
= i
& 0xff;
901 env
->CF
= (x
>> 31) & 1;
902 return (int32_t)x
>> 31;
903 } else if (shift
!= 0) {
904 env
->CF
= (x
>> (shift
- 1)) & 1;
905 return (int32_t)x
>> shift
;
910 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
914 shift
= shift1
& 0x1f;
917 env
->CF
= (x
>> 31) & 1;
920 env
->CF
= (x
>> (shift
- 1)) & 1;
921 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));
925 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
928 * Implement DC ZVA, which zeroes a fixed-length block of memory.
929 * Note that we do not implement the (architecturally mandated)
930 * alignment fault for attempts to use this on Device memory
931 * (which matches the usual QEMU behaviour of not implementing either
932 * alignment faults or any memory attribute handling).
935 ARMCPU
*cpu
= env_archcpu(env
);
936 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
937 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
939 #ifndef CONFIG_USER_ONLY
942 * Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
943 * the block size so we might have to do more than one TLB lookup.
944 * We know that in fact for any v8 CPU the page size is at least 4K
945 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
946 * 1K as an artefact of legacy v5 subpage support being present in the
947 * same QEMU executable. So in practice the hostaddr[] array has
948 * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
950 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
951 void *hostaddr
[DIV_ROUND_UP(2 * KiB
, 1 << TARGET_PAGE_BITS_MIN
)];
953 unsigned mmu_idx
= cpu_mmu_index(env
, false);
954 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
956 assert(maxidx
<= ARRAY_SIZE(hostaddr
));
958 for (try = 0; try < 2; try++) {
960 for (i
= 0; i
< maxidx
; i
++) {
961 hostaddr
[i
] = tlb_vaddr_to_host(env
,
962 vaddr
+ TARGET_PAGE_SIZE
* i
,
970 * If it's all in the TLB it's fair game for just writing to;
971 * we know we don't need to update dirty status, etc.
973 for (i
= 0; i
< maxidx
- 1; i
++) {
974 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
976 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
980 * OK, try a store and see if we can populate the tlb. This
981 * might cause an exception if the memory isn't writable,
982 * in which case we will longjmp out of here. We must for
983 * this purpose use the actual register value passed to us
984 * so that we get the fault address right.
986 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
987 /* Now we can populate the other TLB entries, if any */
988 for (i
= 0; i
< maxidx
; i
++) {
989 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
990 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
991 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
997 * Slow path (probably attempt to do this to an I/O device or
998 * similar, or clearing of a block of code we have translations
999 * cached for). Just do a series of byte writes as the architecture
1000 * demands. It's not worth trying to use a cpu_physical_memory_map(),
1001 * memset(), unmap() sequence here because:
1002 * + we'd need to account for the blocksize being larger than a page
1003 * + the direct-RAM access case is almost always going to be dealt
1004 * with in the fastpath code above, so there's no speed benefit
1005 * + we would have to deal with the map returning NULL because the
1006 * bounce buffer was in use
1008 for (i
= 0; i
< blocklen
; i
++) {
1009 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
1013 memset(g2h(vaddr
), 0, blocklen
);