4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "hw/semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/kvm.h"
28 #include "qemu/range.h"
29 #include "qapi/qapi-commands-machine-target.h"
30 #include "qapi/error.h"
31 #include "qemu/guest-random.h"
34 #include "exec/cpu_ldst.h"
37 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
39 #ifndef CONFIG_USER_ONLY
41 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
42 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
43 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
44 target_ulong
*page_size_ptr
,
45 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
48 static void switch_mode(CPUARMState
*env
, int mode
);
50 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
54 /* VFP data registers are always little-endian. */
55 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
57 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
60 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
61 /* Aliases for Q regs. */
64 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
66 stq_le_p(buf
+ 8, q
[1]);
70 switch (reg
- nregs
) {
71 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
72 case 1: stl_p(buf
, vfp_get_fpscr(env
)); return 4;
73 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
78 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
82 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
84 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
87 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
90 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
92 q
[1] = ldq_le_p(buf
+ 8);
96 switch (reg
- nregs
) {
97 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
98 case 1: vfp_set_fpscr(env
, ldl_p(buf
)); return 4;
99 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
104 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
108 /* 128 bit FP register */
110 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
112 stq_le_p(buf
+ 8, q
[1]);
117 stl_p(buf
, vfp_get_fpsr(env
));
121 stl_p(buf
, vfp_get_fpcr(env
));
128 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
132 /* 128 bit FP register */
134 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
135 q
[0] = ldq_le_p(buf
);
136 q
[1] = ldq_le_p(buf
+ 8);
141 vfp_set_fpsr(env
, ldl_p(buf
));
145 vfp_set_fpcr(env
, ldl_p(buf
));
152 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
154 assert(ri
->fieldoffset
);
155 if (cpreg_field_is_64bit(ri
)) {
156 return CPREG_FIELD64(env
, ri
);
158 return CPREG_FIELD32(env
, ri
);
162 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
165 assert(ri
->fieldoffset
);
166 if (cpreg_field_is_64bit(ri
)) {
167 CPREG_FIELD64(env
, ri
) = value
;
169 CPREG_FIELD32(env
, ri
) = value
;
173 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
175 return (char *)env
+ ri
->fieldoffset
;
178 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
180 /* Raw read of a coprocessor register (as needed for migration, etc). */
181 if (ri
->type
& ARM_CP_CONST
) {
182 return ri
->resetvalue
;
183 } else if (ri
->raw_readfn
) {
184 return ri
->raw_readfn(env
, ri
);
185 } else if (ri
->readfn
) {
186 return ri
->readfn(env
, ri
);
188 return raw_read(env
, ri
);
192 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
195 /* Raw write of a coprocessor register (as needed for migration, etc).
196 * Note that constant registers are treated as write-ignored; the
197 * caller should check for success by whether a readback gives the
200 if (ri
->type
& ARM_CP_CONST
) {
202 } else if (ri
->raw_writefn
) {
203 ri
->raw_writefn(env
, ri
, v
);
204 } else if (ri
->writefn
) {
205 ri
->writefn(env
, ri
, v
);
207 raw_write(env
, ri
, v
);
211 static int arm_gdb_get_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
213 ARMCPU
*cpu
= env_archcpu(env
);
214 const ARMCPRegInfo
*ri
;
217 key
= cpu
->dyn_xml
.cpregs_keys
[reg
];
218 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
220 if (cpreg_field_is_64bit(ri
)) {
221 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
223 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
229 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
234 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
236 /* Return true if the regdef would cause an assertion if you called
237 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
238 * program bug for it not to have the NO_RAW flag).
239 * NB that returning false here doesn't necessarily mean that calling
240 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
241 * read/write access functions which are safe for raw use" from "has
242 * read/write access functions which have side effects but has forgotten
243 * to provide raw access functions".
244 * The tests here line up with the conditions in read/write_raw_cp_reg()
245 * and assertions in raw_read()/raw_write().
247 if ((ri
->type
& ARM_CP_CONST
) ||
249 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
255 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
257 /* Write the coprocessor state from cpu->env to the (index,value) list. */
261 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
262 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
263 const ARMCPRegInfo
*ri
;
266 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
271 if (ri
->type
& ARM_CP_NO_RAW
) {
275 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
278 * Only sync if the previous list->cpustate sync succeeded.
279 * Rather than tracking the success/failure state for every
280 * item in the list, we just recheck "does the raw write we must
281 * have made in write_list_to_cpustate() read back OK" here.
283 uint64_t oldval
= cpu
->cpreg_values
[i
];
285 if (oldval
== newval
) {
289 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
290 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
294 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
296 cpu
->cpreg_values
[i
] = newval
;
301 bool write_list_to_cpustate(ARMCPU
*cpu
)
306 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
307 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
308 uint64_t v
= cpu
->cpreg_values
[i
];
309 const ARMCPRegInfo
*ri
;
311 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
316 if (ri
->type
& ARM_CP_NO_RAW
) {
319 /* Write value and confirm it reads back as written
320 * (to catch read-only registers and partially read-only
321 * registers where the incoming migration value doesn't match)
323 write_raw_cp_reg(&cpu
->env
, ri
, v
);
324 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
331 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
333 ARMCPU
*cpu
= opaque
;
335 const ARMCPRegInfo
*ri
;
337 regidx
= *(uint32_t *)key
;
338 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
340 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
341 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
342 /* The value array need not be initialized at this point */
343 cpu
->cpreg_array_len
++;
347 static void count_cpreg(gpointer key
, gpointer opaque
)
349 ARMCPU
*cpu
= opaque
;
351 const ARMCPRegInfo
*ri
;
353 regidx
= *(uint32_t *)key
;
354 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
356 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
357 cpu
->cpreg_array_len
++;
361 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
363 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
364 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
375 void init_cpreg_list(ARMCPU
*cpu
)
377 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
378 * Note that we require cpreg_tuples[] to be sorted by key ID.
383 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
384 keys
= g_list_sort(keys
, cpreg_key_compare
);
386 cpu
->cpreg_array_len
= 0;
388 g_list_foreach(keys
, count_cpreg
, cpu
);
390 arraylen
= cpu
->cpreg_array_len
;
391 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
392 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
393 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
394 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
395 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
396 cpu
->cpreg_array_len
= 0;
398 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
400 assert(cpu
->cpreg_array_len
== arraylen
);
406 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
407 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
409 * access_el3_aa32ns: Used to check AArch32 register views.
410 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
412 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
413 const ARMCPRegInfo
*ri
,
416 bool secure
= arm_is_secure_below_el3(env
);
418 assert(!arm_el_is_aa64(env
, 3));
420 return CP_ACCESS_TRAP_UNCATEGORIZED
;
425 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
426 const ARMCPRegInfo
*ri
,
429 if (!arm_el_is_aa64(env
, 3)) {
430 return access_el3_aa32ns(env
, ri
, isread
);
435 /* Some secure-only AArch32 registers trap to EL3 if used from
436 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
437 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
438 * We assume that the .access field is set to PL1_RW.
440 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
441 const ARMCPRegInfo
*ri
,
444 if (arm_current_el(env
) == 3) {
447 if (arm_is_secure_below_el3(env
)) {
448 return CP_ACCESS_TRAP_EL3
;
450 /* This will be EL1 NS and EL2 NS, which just UNDEF */
451 return CP_ACCESS_TRAP_UNCATEGORIZED
;
454 /* Check for traps to "powerdown debug" registers, which are controlled
457 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
460 int el
= arm_current_el(env
);
461 bool mdcr_el2_tdosa
= (env
->cp15
.mdcr_el2
& MDCR_TDOSA
) ||
462 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
463 (arm_hcr_el2_eff(env
) & HCR_TGE
);
465 if (el
< 2 && mdcr_el2_tdosa
&& !arm_is_secure_below_el3(env
)) {
466 return CP_ACCESS_TRAP_EL2
;
468 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
469 return CP_ACCESS_TRAP_EL3
;
474 /* Check for traps to "debug ROM" registers, which are controlled
475 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
477 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
480 int el
= arm_current_el(env
);
481 bool mdcr_el2_tdra
= (env
->cp15
.mdcr_el2
& MDCR_TDRA
) ||
482 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
483 (arm_hcr_el2_eff(env
) & HCR_TGE
);
485 if (el
< 2 && mdcr_el2_tdra
&& !arm_is_secure_below_el3(env
)) {
486 return CP_ACCESS_TRAP_EL2
;
488 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
489 return CP_ACCESS_TRAP_EL3
;
494 /* Check for traps to general debug registers, which are controlled
495 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
497 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
500 int el
= arm_current_el(env
);
501 bool mdcr_el2_tda
= (env
->cp15
.mdcr_el2
& MDCR_TDA
) ||
502 (env
->cp15
.mdcr_el2
& MDCR_TDE
) ||
503 (arm_hcr_el2_eff(env
) & HCR_TGE
);
505 if (el
< 2 && mdcr_el2_tda
&& !arm_is_secure_below_el3(env
)) {
506 return CP_ACCESS_TRAP_EL2
;
508 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
509 return CP_ACCESS_TRAP_EL3
;
514 /* Check for traps to performance monitor registers, which are controlled
515 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
517 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
520 int el
= arm_current_el(env
);
522 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
523 && !arm_is_secure_below_el3(env
)) {
524 return CP_ACCESS_TRAP_EL2
;
526 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
527 return CP_ACCESS_TRAP_EL3
;
532 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
534 ARMCPU
*cpu
= env_archcpu(env
);
536 raw_write(env
, ri
, value
);
537 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
540 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
542 ARMCPU
*cpu
= env_archcpu(env
);
544 if (raw_read(env
, ri
) != value
) {
545 /* Unlike real hardware the qemu TLB uses virtual addresses,
546 * not modified virtual addresses, so this causes a TLB flush.
549 raw_write(env
, ri
, value
);
553 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
556 ARMCPU
*cpu
= env_archcpu(env
);
558 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
559 && !extended_addresses_enabled(env
)) {
560 /* For VMSA (when not using the LPAE long descriptor page table
561 * format) this register includes the ASID, so do a TLB flush.
562 * For PMSA it is purely a process ID and no action is needed.
566 raw_write(env
, ri
, value
);
569 /* IS variants of TLB operations must affect all cores */
570 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
573 CPUState
*cs
= env_cpu(env
);
575 tlb_flush_all_cpus_synced(cs
);
578 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
581 CPUState
*cs
= env_cpu(env
);
583 tlb_flush_all_cpus_synced(cs
);
586 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
589 CPUState
*cs
= env_cpu(env
);
591 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
594 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 CPUState
*cs
= env_cpu(env
);
599 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
603 * Non-IS variants of TLB operations are upgraded to
604 * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
605 * force broadcast of these operations.
607 static bool tlb_force_broadcast(CPUARMState
*env
)
609 return (env
->cp15
.hcr_el2
& HCR_FB
) &&
610 arm_current_el(env
) == 1 && arm_is_secure_below_el3(env
);
613 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 /* Invalidate all (TLBIALL) */
617 ARMCPU
*cpu
= env_archcpu(env
);
619 if (tlb_force_broadcast(env
)) {
620 tlbiall_is_write(env
, NULL
, value
);
627 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
630 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
631 ARMCPU
*cpu
= env_archcpu(env
);
633 if (tlb_force_broadcast(env
)) {
634 tlbimva_is_write(env
, NULL
, value
);
638 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
641 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
644 /* Invalidate by ASID (TLBIASID) */
645 ARMCPU
*cpu
= env_archcpu(env
);
647 if (tlb_force_broadcast(env
)) {
648 tlbiasid_is_write(env
, NULL
, value
);
655 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
658 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
659 ARMCPU
*cpu
= env_archcpu(env
);
661 if (tlb_force_broadcast(env
)) {
662 tlbimvaa_is_write(env
, NULL
, value
);
666 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
669 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
672 CPUState
*cs
= env_cpu(env
);
674 tlb_flush_by_mmuidx(cs
,
675 ARMMMUIdxBit_S12NSE1
|
676 ARMMMUIdxBit_S12NSE0
|
680 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
683 CPUState
*cs
= env_cpu(env
);
685 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
686 ARMMMUIdxBit_S12NSE1
|
687 ARMMMUIdxBit_S12NSE0
|
691 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
694 /* Invalidate by IPA. This has to invalidate any structures that
695 * contain only stage 2 translation information, but does not need
696 * to apply to structures that contain combined stage 1 and stage 2
697 * translation information.
698 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
700 CPUState
*cs
= env_cpu(env
);
703 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
707 pageaddr
= sextract64(value
<< 12, 0, 40);
709 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
712 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
715 CPUState
*cs
= env_cpu(env
);
718 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
722 pageaddr
= sextract64(value
<< 12, 0, 40);
724 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
728 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
731 CPUState
*cs
= env_cpu(env
);
733 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
736 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
739 CPUState
*cs
= env_cpu(env
);
741 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
744 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
747 CPUState
*cs
= env_cpu(env
);
748 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
750 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
753 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
756 CPUState
*cs
= env_cpu(env
);
757 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
759 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
763 static const ARMCPRegInfo cp_reginfo
[] = {
764 /* Define the secure and non-secure FCSE identifier CP registers
765 * separately because there is no secure bank in V8 (no _EL3). This allows
766 * the secure register to be properly reset and migrated. There is also no
767 * v8 EL1 version of the register so the non-secure instance stands alone.
770 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
771 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
772 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
773 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
774 { .name
= "FCSEIDR_S",
775 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
776 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
777 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
778 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
779 /* Define the secure and non-secure context identifier CP registers
780 * separately because there is no secure bank in V8 (no _EL3). This allows
781 * the secure register to be properly reset and migrated. In the
782 * non-secure case, the 32-bit register will have reset and migration
783 * disabled during registration as it is handled by the 64-bit instance.
785 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
786 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
787 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
788 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
789 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
790 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
791 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
792 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
793 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
794 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
798 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
799 /* NB: Some of these registers exist in v8 but with more precise
800 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
802 /* MMU Domain access control / MPU write buffer control */
804 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
805 .access
= PL1_RW
, .resetvalue
= 0,
806 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
807 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
808 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
809 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
810 * For v6 and v5, these mappings are overly broad.
812 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
813 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
814 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
815 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
816 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
817 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
818 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
819 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
820 /* Cache maintenance ops; some of this space may be overridden later. */
821 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
822 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
823 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
827 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
828 /* Not all pre-v6 cores implemented this WFI, so this is slightly
831 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
832 .access
= PL1_W
, .type
= ARM_CP_WFI
},
836 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
837 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
838 * is UNPREDICTABLE; we choose to NOP as most implementations do).
840 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
841 .access
= PL1_W
, .type
= ARM_CP_WFI
},
842 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
843 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
844 * OMAPCP will override this space.
846 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
847 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
849 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
850 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
852 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
853 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
854 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
856 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
857 * implementing it as RAZ means the "debug architecture version" bits
858 * will read as a reserved value, which should cause Linux to not try
859 * to use the debug hardware.
861 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
862 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
863 /* MMU TLB control. Note that the wildcarding means we cover not just
864 * the unified TLB ops but also the dside/iside/inner-shareable variants.
866 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
867 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
868 .type
= ARM_CP_NO_RAW
},
869 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
870 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
871 .type
= ARM_CP_NO_RAW
},
872 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
873 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
874 .type
= ARM_CP_NO_RAW
},
875 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
876 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
877 .type
= ARM_CP_NO_RAW
},
878 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
879 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
880 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
881 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
885 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
890 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
891 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
892 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
893 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
894 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
896 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
897 /* VFP coprocessor: cp10 & cp11 [23:20] */
898 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
900 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
901 /* ASEDIS [31] bit is RAO/WI */
905 /* VFPv3 and upwards with NEON implement 32 double precision
906 * registers (D0-D31).
908 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
909 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
910 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
918 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
919 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
921 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
922 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
923 value
&= ~(0xf << 20);
924 value
|= env
->cp15
.cpacr_el1
& (0xf << 20);
927 env
->cp15
.cpacr_el1
= value
;
930 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
933 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
934 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
936 uint64_t value
= env
->cp15
.cpacr_el1
;
938 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
939 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
940 value
&= ~(0xf << 20);
946 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
948 /* Call cpacr_write() so that we reset with the correct RAO bits set
949 * for our CPU features.
951 cpacr_write(env
, ri
, 0);
954 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
957 if (arm_feature(env
, ARM_FEATURE_V8
)) {
958 /* Check if CPACR accesses are to be trapped to EL2 */
959 if (arm_current_el(env
) == 1 &&
960 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
961 return CP_ACCESS_TRAP_EL2
;
962 /* Check if CPACR accesses are to be trapped to EL3 */
963 } else if (arm_current_el(env
) < 3 &&
964 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
965 return CP_ACCESS_TRAP_EL3
;
972 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
975 /* Check if CPTR accesses are set to trap to EL3 */
976 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
977 return CP_ACCESS_TRAP_EL3
;
983 static const ARMCPRegInfo v6_cp_reginfo
[] = {
984 /* prefetch by MVA in v6, NOP in v7 */
985 { .name
= "MVA_prefetch",
986 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
987 .access
= PL1_W
, .type
= ARM_CP_NOP
},
988 /* We need to break the TB after ISB to execute self-modifying code
989 * correctly and also to take any pending interrupts immediately.
990 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
992 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
993 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
994 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
995 .access
= PL0_W
, .type
= ARM_CP_NOP
},
996 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
997 .access
= PL0_W
, .type
= ARM_CP_NOP
},
998 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
1000 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
1001 offsetof(CPUARMState
, cp15
.ifar_ns
) },
1003 /* Watchpoint Fault Address Register : should actually only be present
1004 * for 1136, 1176, 11MPCore.
1006 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1007 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
1008 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
1009 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
1010 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
1011 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
1015 /* Definitions for the PMU registers */
1016 #define PMCRN_MASK 0xf800
1017 #define PMCRN_SHIFT 11
1025 #define PMXEVTYPER_P 0x80000000
1026 #define PMXEVTYPER_U 0x40000000
1027 #define PMXEVTYPER_NSK 0x20000000
1028 #define PMXEVTYPER_NSU 0x10000000
1029 #define PMXEVTYPER_NSH 0x08000000
1030 #define PMXEVTYPER_M 0x04000000
1031 #define PMXEVTYPER_MT 0x02000000
1032 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1033 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1034 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1035 PMXEVTYPER_M | PMXEVTYPER_MT | \
1036 PMXEVTYPER_EVTCOUNT)
1038 #define PMCCFILTR 0xf8000000
1039 #define PMCCFILTR_M PMXEVTYPER_M
1040 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1042 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1044 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1047 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1048 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1050 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1053 typedef struct pm_event
{
1054 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1055 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1056 bool (*supported
)(CPUARMState
*);
1058 * Retrieve the current count of the underlying event. The programmed
1059 * counters hold a difference from the return value from this function
1061 uint64_t (*get_count
)(CPUARMState
*);
1063 * Return how many nanoseconds it will take (at a minimum) for count events
1064 * to occur. A negative value indicates the counter will never overflow, or
1065 * that the counter has otherwise arranged for the overflow bit to be set
1066 * and the PMU interrupt to be raised on overflow.
1068 int64_t (*ns_per_count
)(uint64_t);
1071 static bool event_always_supported(CPUARMState
*env
)
1076 static uint64_t swinc_get_count(CPUARMState
*env
)
1079 * SW_INCR events are written directly to the pmevcntr's by writes to
1080 * PMSWINC, so there is no underlying count maintained by the PMU itself
1085 static int64_t swinc_ns_per(uint64_t ignored
)
1091 * Return the underlying cycle count for the PMU cycle counters. If we're in
1092 * usermode, simply return 0.
1094 static uint64_t cycles_get_count(CPUARMState
*env
)
1096 #ifndef CONFIG_USER_ONLY
1097 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1098 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1100 return cpu_get_host_ticks();
1104 #ifndef CONFIG_USER_ONLY
1105 static int64_t cycles_ns_per(uint64_t cycles
)
1107 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1110 static bool instructions_supported(CPUARMState
*env
)
1112 return use_icount
== 1 /* Precise instruction counting */;
1115 static uint64_t instructions_get_count(CPUARMState
*env
)
1117 return (uint64_t)cpu_get_icount_raw();
1120 static int64_t instructions_ns_per(uint64_t icount
)
1122 return cpu_icount_to_ns((int64_t)icount
);
1126 static const pm_event pm_events
[] = {
1127 { .number
= 0x000, /* SW_INCR */
1128 .supported
= event_always_supported
,
1129 .get_count
= swinc_get_count
,
1130 .ns_per_count
= swinc_ns_per
,
1132 #ifndef CONFIG_USER_ONLY
1133 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1134 .supported
= instructions_supported
,
1135 .get_count
= instructions_get_count
,
1136 .ns_per_count
= instructions_ns_per
,
1138 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1139 .supported
= event_always_supported
,
1140 .get_count
= cycles_get_count
,
1141 .ns_per_count
= cycles_ns_per
,
1147 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1148 * events (i.e. the statistical profiling extension), this implementation
1149 * should first be updated to something sparse instead of the current
1150 * supported_event_map[] array.
1152 #define MAX_EVENT_ID 0x11
1153 #define UNSUPPORTED_EVENT UINT16_MAX
1154 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1157 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1158 * of ARM event numbers to indices in our pm_events array.
1160 * Note: Events in the 0x40XX range are not currently supported.
1162 void pmu_init(ARMCPU
*cpu
)
1167 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1170 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1171 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1176 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1177 const pm_event
*cnt
= &pm_events
[i
];
1178 assert(cnt
->number
<= MAX_EVENT_ID
);
1179 /* We do not currently support events in the 0x40xx range */
1180 assert(cnt
->number
<= 0x3f);
1182 if (cnt
->supported(&cpu
->env
)) {
1183 supported_event_map
[cnt
->number
] = i
;
1184 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1185 if (cnt
->number
& 0x20) {
1186 cpu
->pmceid1
|= event_mask
;
1188 cpu
->pmceid0
|= event_mask
;
1195 * Check at runtime whether a PMU event is supported for the current machine
1197 static bool event_supported(uint16_t number
)
1199 if (number
> MAX_EVENT_ID
) {
1202 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1205 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1208 /* Performance monitor registers user accessibility is controlled
1209 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1210 * trapping to EL2 or EL3 for other accesses.
1212 int el
= arm_current_el(env
);
1214 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1215 return CP_ACCESS_TRAP
;
1217 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
1218 && !arm_is_secure_below_el3(env
)) {
1219 return CP_ACCESS_TRAP_EL2
;
1221 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1222 return CP_ACCESS_TRAP_EL3
;
1225 return CP_ACCESS_OK
;
1228 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1229 const ARMCPRegInfo
*ri
,
1232 /* ER: event counter read trap control */
1233 if (arm_feature(env
, ARM_FEATURE_V8
)
1234 && arm_current_el(env
) == 0
1235 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1237 return CP_ACCESS_OK
;
1240 return pmreg_access(env
, ri
, isread
);
1243 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1244 const ARMCPRegInfo
*ri
,
1247 /* SW: software increment write trap control */
1248 if (arm_feature(env
, ARM_FEATURE_V8
)
1249 && arm_current_el(env
) == 0
1250 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1252 return CP_ACCESS_OK
;
1255 return pmreg_access(env
, ri
, isread
);
1258 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1259 const ARMCPRegInfo
*ri
,
1262 /* ER: event counter read trap control */
1263 if (arm_feature(env
, ARM_FEATURE_V8
)
1264 && arm_current_el(env
) == 0
1265 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1266 return CP_ACCESS_OK
;
1269 return pmreg_access(env
, ri
, isread
);
1272 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1273 const ARMCPRegInfo
*ri
,
1276 /* CR: cycle counter read trap control */
1277 if (arm_feature(env
, ARM_FEATURE_V8
)
1278 && arm_current_el(env
) == 0
1279 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1281 return CP_ACCESS_OK
;
1284 return pmreg_access(env
, ri
, isread
);
1287 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1288 * the current EL, security state, and register configuration.
1290 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1293 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1294 bool enabled
, prohibited
, filtered
;
1295 bool secure
= arm_is_secure(env
);
1296 int el
= arm_current_el(env
);
1297 uint8_t hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1299 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1303 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1304 (counter
< hpmn
|| counter
== 31)) {
1305 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1307 e
= env
->cp15
.mdcr_el2
& MDCR_HPME
;
1309 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1312 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1313 prohibited
= env
->cp15
.mdcr_el2
& MDCR_HPMD
;
1318 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1319 (env
->cp15
.mdcr_el3
& MDCR_SPME
);
1322 if (prohibited
&& counter
== 31) {
1323 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1326 if (counter
== 31) {
1327 filter
= env
->cp15
.pmccfiltr_el0
;
1329 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1332 p
= filter
& PMXEVTYPER_P
;
1333 u
= filter
& PMXEVTYPER_U
;
1334 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1335 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1336 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1337 m
= arm_el_is_aa64(env
, 1) &&
1338 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1341 filtered
= secure
? u
: u
!= nsu
;
1342 } else if (el
== 1) {
1343 filtered
= secure
? p
: p
!= nsk
;
1344 } else if (el
== 2) {
1350 if (counter
!= 31) {
1352 * If not checking PMCCNTR, ensure the counter is setup to an event we
1355 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1356 if (!event_supported(event
)) {
1361 return enabled
&& !prohibited
&& !filtered
;
1364 static void pmu_update_irq(CPUARMState
*env
)
1366 ARMCPU
*cpu
= env_archcpu(env
);
1367 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1368 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1372 * Ensure c15_ccnt is the guest-visible count so that operations such as
1373 * enabling/disabling the counter or filtering, modifying the count itself,
1374 * etc. can be done logically. This is essentially a no-op if the counter is
1375 * not enabled at the time of the call.
1377 static void pmccntr_op_start(CPUARMState
*env
)
1379 uint64_t cycles
= cycles_get_count(env
);
1381 if (pmu_counter_enabled(env
, 31)) {
1382 uint64_t eff_cycles
= cycles
;
1383 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1384 /* Increment once every 64 processor clock cycles */
1388 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1390 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1391 1ull << 63 : 1ull << 31;
1392 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1393 env
->cp15
.c9_pmovsr
|= (1 << 31);
1394 pmu_update_irq(env
);
1397 env
->cp15
.c15_ccnt
= new_pmccntr
;
1399 env
->cp15
.c15_ccnt_delta
= cycles
;
1403 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1404 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1407 static void pmccntr_op_finish(CPUARMState
*env
)
1409 if (pmu_counter_enabled(env
, 31)) {
1410 #ifndef CONFIG_USER_ONLY
1411 /* Calculate when the counter will next overflow */
1412 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1413 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1414 remaining_cycles
= (uint32_t)remaining_cycles
;
1416 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1418 if (overflow_in
> 0) {
1419 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1421 ARMCPU
*cpu
= env_archcpu(env
);
1422 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1426 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1427 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1428 /* Increment once every 64 processor clock cycles */
1431 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1435 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1438 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1440 if (event_supported(event
)) {
1441 uint16_t event_idx
= supported_event_map
[event
];
1442 count
= pm_events
[event_idx
].get_count(env
);
1445 if (pmu_counter_enabled(env
, counter
)) {
1446 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1448 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1449 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1450 pmu_update_irq(env
);
1452 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1454 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1457 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1459 if (pmu_counter_enabled(env
, counter
)) {
1460 #ifndef CONFIG_USER_ONLY
1461 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1462 uint16_t event_idx
= supported_event_map
[event
];
1463 uint64_t delta
= UINT32_MAX
-
1464 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1465 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1467 if (overflow_in
> 0) {
1468 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1470 ARMCPU
*cpu
= env_archcpu(env
);
1471 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1475 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1476 env
->cp15
.c14_pmevcntr
[counter
];
1480 void pmu_op_start(CPUARMState
*env
)
1483 pmccntr_op_start(env
);
1484 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1485 pmevcntr_op_start(env
, i
);
1489 void pmu_op_finish(CPUARMState
*env
)
1492 pmccntr_op_finish(env
);
1493 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1494 pmevcntr_op_finish(env
, i
);
1498 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1500 pmu_op_start(&cpu
->env
);
1503 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1505 pmu_op_finish(&cpu
->env
);
1508 void arm_pmu_timer_cb(void *opaque
)
1510 ARMCPU
*cpu
= opaque
;
1513 * Update all the counter values based on the current underlying counts,
1514 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1515 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1516 * counter may expire.
1518 pmu_op_start(&cpu
->env
);
1519 pmu_op_finish(&cpu
->env
);
1522 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1527 if (value
& PMCRC
) {
1528 /* The counter has been reset */
1529 env
->cp15
.c15_ccnt
= 0;
1532 if (value
& PMCRP
) {
1534 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1535 env
->cp15
.c14_pmevcntr
[i
] = 0;
1539 /* only the DP, X, D and E bits are writable */
1540 env
->cp15
.c9_pmcr
&= ~0x39;
1541 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1546 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1550 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1551 /* Increment a counter's count iff: */
1552 if ((value
& (1 << i
)) && /* counter's bit is set */
1553 /* counter is enabled and not filtered */
1554 pmu_counter_enabled(env
, i
) &&
1555 /* counter is SW_INCR */
1556 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1557 pmevcntr_op_start(env
, i
);
1560 * Detect if this write causes an overflow since we can't predict
1561 * PMSWINC overflows like we can for other events
1563 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1565 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1566 env
->cp15
.c9_pmovsr
|= (1 << i
);
1567 pmu_update_irq(env
);
1570 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1572 pmevcntr_op_finish(env
, i
);
1577 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1580 pmccntr_op_start(env
);
1581 ret
= env
->cp15
.c15_ccnt
;
1582 pmccntr_op_finish(env
);
1586 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1589 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1590 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1591 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1594 env
->cp15
.c9_pmselr
= value
& 0x1f;
1597 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1600 pmccntr_op_start(env
);
1601 env
->cp15
.c15_ccnt
= value
;
1602 pmccntr_op_finish(env
);
1605 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1608 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1610 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1613 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1616 pmccntr_op_start(env
);
1617 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1618 pmccntr_op_finish(env
);
1621 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1624 pmccntr_op_start(env
);
1625 /* M is not accessible from AArch32 */
1626 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1627 (value
& PMCCFILTR
);
1628 pmccntr_op_finish(env
);
1631 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1633 /* M is not visible in AArch32 */
1634 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1637 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1640 value
&= pmu_counter_mask(env
);
1641 env
->cp15
.c9_pmcnten
|= value
;
1644 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1647 value
&= pmu_counter_mask(env
);
1648 env
->cp15
.c9_pmcnten
&= ~value
;
1651 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1654 value
&= pmu_counter_mask(env
);
1655 env
->cp15
.c9_pmovsr
&= ~value
;
1656 pmu_update_irq(env
);
1659 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1662 value
&= pmu_counter_mask(env
);
1663 env
->cp15
.c9_pmovsr
|= value
;
1664 pmu_update_irq(env
);
1667 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1668 uint64_t value
, const uint8_t counter
)
1670 if (counter
== 31) {
1671 pmccfiltr_write(env
, ri
, value
);
1672 } else if (counter
< pmu_num_counters(env
)) {
1673 pmevcntr_op_start(env
, counter
);
1676 * If this counter's event type is changing, store the current
1677 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1678 * pmevcntr_op_finish has the correct baseline when it converts back to
1681 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1682 PMXEVTYPER_EVTCOUNT
;
1683 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1684 if (old_event
!= new_event
) {
1686 if (event_supported(new_event
)) {
1687 uint16_t event_idx
= supported_event_map
[new_event
];
1688 count
= pm_events
[event_idx
].get_count(env
);
1690 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1693 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1694 pmevcntr_op_finish(env
, counter
);
1696 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1697 * PMSELR value is equal to or greater than the number of implemented
1698 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1702 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1703 const uint8_t counter
)
1705 if (counter
== 31) {
1706 return env
->cp15
.pmccfiltr_el0
;
1707 } else if (counter
< pmu_num_counters(env
)) {
1708 return env
->cp15
.c14_pmevtyper
[counter
];
1711 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1712 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1718 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1721 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1722 pmevtyper_write(env
, ri
, value
, counter
);
1725 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1729 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1732 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1733 * pmu_op_finish calls when loading saved state for a migration. Because
1734 * we're potentially updating the type of event here, the value written to
1735 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1736 * different counter type. Therefore, we need to set this value to the
1737 * current count for the counter type we're writing so that pmu_op_finish
1738 * has the correct count for its calculation.
1740 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1741 if (event_supported(event
)) {
1742 uint16_t event_idx
= supported_event_map
[event
];
1743 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1744 pm_events
[event_idx
].get_count(env
);
1748 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1750 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1751 return pmevtyper_read(env
, ri
, counter
);
1754 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1757 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1760 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1762 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1765 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1766 uint64_t value
, uint8_t counter
)
1768 if (counter
< pmu_num_counters(env
)) {
1769 pmevcntr_op_start(env
, counter
);
1770 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1771 pmevcntr_op_finish(env
, counter
);
1774 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1775 * are CONSTRAINED UNPREDICTABLE.
1779 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1782 if (counter
< pmu_num_counters(env
)) {
1784 pmevcntr_op_start(env
, counter
);
1785 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1786 pmevcntr_op_finish(env
, counter
);
1789 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1790 * are CONSTRAINED UNPREDICTABLE. */
1795 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1798 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1799 pmevcntr_write(env
, ri
, value
, counter
);
1802 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1804 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1805 return pmevcntr_read(env
, ri
, counter
);
1808 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1811 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1812 assert(counter
< pmu_num_counters(env
));
1813 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1814 pmevcntr_write(env
, ri
, value
, counter
);
1817 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1819 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1820 assert(counter
< pmu_num_counters(env
));
1821 return env
->cp15
.c14_pmevcntr
[counter
];
1824 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1827 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1830 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1832 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1835 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1838 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1839 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1841 env
->cp15
.c9_pmuserenr
= value
& 1;
1845 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1848 /* We have no event counters so only the C bit can be changed */
1849 value
&= pmu_counter_mask(env
);
1850 env
->cp15
.c9_pminten
|= value
;
1851 pmu_update_irq(env
);
1854 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1857 value
&= pmu_counter_mask(env
);
1858 env
->cp15
.c9_pminten
&= ~value
;
1859 pmu_update_irq(env
);
1862 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1865 /* Note that even though the AArch64 view of this register has bits
1866 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1867 * architectural requirements for bits which are RES0 only in some
1868 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1869 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1871 raw_write(env
, ri
, value
& ~0x1FULL
);
1874 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1876 /* Begin with base v8.0 state. */
1877 uint32_t valid_mask
= 0x3fff;
1878 ARMCPU
*cpu
= env_archcpu(env
);
1880 if (arm_el_is_aa64(env
, 3)) {
1881 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
1882 valid_mask
&= ~SCR_NET
;
1884 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1887 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1888 valid_mask
&= ~SCR_HCE
;
1890 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1891 * supported if EL2 exists. The bit is UNK/SBZP when
1892 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1893 * when EL2 is unavailable.
1894 * On ARMv8, this bit is always available.
1896 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1897 !arm_feature(env
, ARM_FEATURE_V8
)) {
1898 valid_mask
&= ~SCR_SMD
;
1901 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1902 valid_mask
|= SCR_TLOR
;
1904 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1905 valid_mask
|= SCR_API
| SCR_APK
;
1908 /* Clear all-context RES0 bits. */
1909 value
&= valid_mask
;
1910 raw_write(env
, ri
, value
);
1913 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
1914 const ARMCPRegInfo
*ri
,
1917 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
1918 return CP_ACCESS_TRAP_EL2
;
1921 return CP_ACCESS_OK
;
1924 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1926 ARMCPU
*cpu
= env_archcpu(env
);
1928 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1931 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1932 ri
->secure
& ARM_CP_SECSTATE_S
);
1934 return cpu
->ccsidr
[index
];
1937 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1940 raw_write(env
, ri
, value
& 0xf);
1943 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1945 CPUState
*cs
= env_cpu(env
);
1946 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
1948 bool allow_virt
= (arm_current_el(env
) == 1 &&
1949 (!arm_is_secure_below_el3(env
) ||
1950 (env
->cp15
.scr_el3
& SCR_EEL2
)));
1952 if (allow_virt
&& (hcr_el2
& HCR_IMO
)) {
1953 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1957 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1962 if (allow_virt
&& (hcr_el2
& HCR_FMO
)) {
1963 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1967 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1972 /* External aborts are not possible in QEMU so A bit is always clear */
1976 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1979 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
1980 return CP_ACCESS_TRAP_EL2
;
1983 return CP_ACCESS_OK
;
1986 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1989 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1990 return access_aa64_tid1(env
, ri
, isread
);
1993 return CP_ACCESS_OK
;
1996 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1997 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1998 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1999 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2000 /* Performance monitors are implementation defined in v7,
2001 * but with an ARM recommended set of registers, which we
2004 * Performance registers fall into three categories:
2005 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2006 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2007 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2008 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2009 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2011 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2012 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2013 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2014 .writefn
= pmcntenset_write
,
2015 .accessfn
= pmreg_access
,
2016 .raw_writefn
= raw_write
},
2017 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
2018 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2019 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2020 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2021 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2022 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2024 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2025 .accessfn
= pmreg_access
,
2026 .writefn
= pmcntenclr_write
,
2027 .type
= ARM_CP_ALIAS
},
2028 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2029 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2030 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2031 .type
= ARM_CP_ALIAS
,
2032 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2033 .writefn
= pmcntenclr_write
},
2034 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2035 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2036 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2037 .accessfn
= pmreg_access
,
2038 .writefn
= pmovsr_write
,
2039 .raw_writefn
= raw_write
},
2040 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2041 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2042 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2043 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2044 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2045 .writefn
= pmovsr_write
,
2046 .raw_writefn
= raw_write
},
2047 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2048 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2049 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2050 .writefn
= pmswinc_write
},
2051 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2052 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2053 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2054 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2055 .writefn
= pmswinc_write
},
2056 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2057 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2058 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2059 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2060 .raw_writefn
= raw_write
},
2061 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2062 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2063 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2064 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2065 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2066 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2067 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2068 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2069 .accessfn
= pmreg_access_ccntr
},
2070 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2071 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2072 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2074 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2075 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2076 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2077 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2078 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2079 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2080 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2082 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2083 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2084 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2085 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2087 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2089 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2090 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2091 .accessfn
= pmreg_access
,
2092 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2093 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2094 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2095 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2096 .accessfn
= pmreg_access
,
2097 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2098 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2099 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2100 .accessfn
= pmreg_access_xevcntr
,
2101 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2102 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2103 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2104 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2105 .accessfn
= pmreg_access_xevcntr
,
2106 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2107 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2108 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2109 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2111 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2112 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2113 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2114 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2115 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2117 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2118 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2119 .access
= PL1_RW
, .accessfn
= access_tpm
,
2120 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2121 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2123 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2124 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2125 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2126 .access
= PL1_RW
, .accessfn
= access_tpm
,
2128 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2129 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2130 .resetvalue
= 0x0 },
2131 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2132 .access
= PL1_RW
, .accessfn
= access_tpm
,
2133 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2134 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2135 .writefn
= pmintenclr_write
, },
2136 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2137 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2138 .access
= PL1_RW
, .accessfn
= access_tpm
,
2139 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2140 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2141 .writefn
= pmintenclr_write
},
2142 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2143 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2145 .accessfn
= access_aa64_tid2
,
2146 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2147 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2148 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2150 .accessfn
= access_aa64_tid2
,
2151 .writefn
= csselr_write
, .resetvalue
= 0,
2152 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2153 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2154 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2155 * just RAZ for all cores:
2157 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2158 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2159 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2160 .accessfn
= access_aa64_tid1
,
2162 /* Auxiliary fault status registers: these also are IMPDEF, and we
2163 * choose to RAZ/WI for all cores.
2165 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2166 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2167 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2168 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2169 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2170 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2171 /* MAIR can just read-as-written because we don't implement caches
2172 * and so don't need to care about memory attributes.
2174 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2175 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2176 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2178 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2179 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2180 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2182 /* For non-long-descriptor page tables these are PRRR and NMRR;
2183 * regardless they still act as reads-as-written for QEMU.
2185 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2186 * allows them to assign the correct fieldoffset based on the endianness
2187 * handled in the field definitions.
2189 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2190 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
2191 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2192 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2193 .resetfn
= arm_cp_reset_ignore
},
2194 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2195 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
2196 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2197 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2198 .resetfn
= arm_cp_reset_ignore
},
2199 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2200 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2201 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2202 /* 32 bit ITLB invalidates */
2203 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2204 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2205 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2206 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2207 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2208 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2209 /* 32 bit DTLB invalidates */
2210 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2211 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2212 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2213 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2214 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2215 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2216 /* 32 bit TLB invalidates */
2217 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2218 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
2219 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2220 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
2221 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2222 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
2223 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2224 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
2228 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2229 /* 32 bit TLB invalidates, Inner Shareable */
2230 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2231 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
2232 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2233 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
2234 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2235 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2236 .writefn
= tlbiasid_is_write
},
2237 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2238 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
2239 .writefn
= tlbimvaa_is_write
},
2243 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2244 /* PMOVSSET is not implemented in v7 before v7ve */
2245 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2246 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2247 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2248 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2249 .writefn
= pmovsset_write
,
2250 .raw_writefn
= raw_write
},
2251 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2252 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2253 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2254 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2255 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2256 .writefn
= pmovsset_write
,
2257 .raw_writefn
= raw_write
},
2261 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2268 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2271 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2272 return CP_ACCESS_TRAP
;
2274 return CP_ACCESS_OK
;
2277 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2278 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2279 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2281 .writefn
= teecr_write
},
2282 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2283 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2284 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2288 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2289 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2290 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2292 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2293 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2295 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2296 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2297 .resetfn
= arm_cp_reset_ignore
},
2298 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2299 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2300 .access
= PL0_R
|PL1_W
,
2301 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2303 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2304 .access
= PL0_R
|PL1_W
,
2305 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2306 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2307 .resetfn
= arm_cp_reset_ignore
},
2308 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2309 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2311 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2312 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2314 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2315 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2320 #ifndef CONFIG_USER_ONLY
2322 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2325 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2326 * Writable only at the highest implemented exception level.
2328 int el
= arm_current_el(env
);
2332 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
2333 return CP_ACCESS_TRAP
;
2337 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2338 arm_is_secure_below_el3(env
)) {
2339 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2340 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2348 if (!isread
&& el
< arm_highest_el(env
)) {
2349 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2352 return CP_ACCESS_OK
;
2355 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2358 unsigned int cur_el
= arm_current_el(env
);
2359 bool secure
= arm_is_secure(env
);
2361 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
2363 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2364 return CP_ACCESS_TRAP
;
2367 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2368 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
2369 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
2370 return CP_ACCESS_TRAP_EL2
;
2372 return CP_ACCESS_OK
;
2375 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2378 unsigned int cur_el
= arm_current_el(env
);
2379 bool secure
= arm_is_secure(env
);
2381 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
2382 * EL0[PV]TEN is zero.
2385 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2386 return CP_ACCESS_TRAP
;
2389 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2390 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
2391 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2392 return CP_ACCESS_TRAP_EL2
;
2394 return CP_ACCESS_OK
;
2397 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2398 const ARMCPRegInfo
*ri
,
2401 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2404 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2405 const ARMCPRegInfo
*ri
,
2408 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2411 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2414 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2417 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2420 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2423 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2424 const ARMCPRegInfo
*ri
,
2427 /* The AArch64 register view of the secure physical timer is
2428 * always accessible from EL3, and configurably accessible from
2431 switch (arm_current_el(env
)) {
2433 if (!arm_is_secure(env
)) {
2434 return CP_ACCESS_TRAP
;
2436 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2437 return CP_ACCESS_TRAP_EL3
;
2439 return CP_ACCESS_OK
;
2442 return CP_ACCESS_TRAP
;
2444 return CP_ACCESS_OK
;
2446 g_assert_not_reached();
2450 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2452 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
2455 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2457 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2460 /* Timer enabled: calculate and set current ISTATUS, irq, and
2461 * reset timer to when ISTATUS next has to change
2463 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2464 cpu
->env
.cp15
.cntvoff_el2
: 0;
2465 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2466 /* Note that this must be unsigned 64 bit arithmetic: */
2467 int istatus
= count
- offset
>= gt
->cval
;
2471 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2473 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2474 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2477 /* Next transition is when count rolls back over to zero */
2478 nexttick
= UINT64_MAX
;
2480 /* Next transition is when we hit cval */
2481 nexttick
= gt
->cval
+ offset
;
2483 /* Note that the desired next expiry time might be beyond the
2484 * signed-64-bit range of a QEMUTimer -- in this case we just
2485 * set the timer for as far in the future as possible. When the
2486 * timer expires we will reset the timer for any remaining period.
2488 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
2489 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
2491 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2492 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2494 /* Timer disabled: ISTATUS and timer output always clear */
2496 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2497 timer_del(cpu
->gt_timer
[timeridx
]);
2498 trace_arm_gt_recalc_disabled(timeridx
);
2502 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2505 ARMCPU
*cpu
= env_archcpu(env
);
2507 timer_del(cpu
->gt_timer
[timeridx
]);
2510 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2512 return gt_get_countervalue(env
);
2515 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2517 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
2520 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2524 trace_arm_gt_cval_write(timeridx
, value
);
2525 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2526 gt_recalc_timer(env_archcpu(env
), timeridx
);
2529 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2532 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
2534 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2535 (gt_get_countervalue(env
) - offset
));
2538 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2542 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
2544 trace_arm_gt_tval_write(timeridx
, value
);
2545 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2546 sextract64(value
, 0, 32);
2547 gt_recalc_timer(env_archcpu(env
), timeridx
);
2550 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2554 ARMCPU
*cpu
= env_archcpu(env
);
2555 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2557 trace_arm_gt_ctl_write(timeridx
, value
);
2558 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2559 if ((oldval
^ value
) & 1) {
2560 /* Enable toggled */
2561 gt_recalc_timer(cpu
, timeridx
);
2562 } else if ((oldval
^ value
) & 2) {
2563 /* IMASK toggled: don't need to recalculate,
2564 * just set the interrupt line based on ISTATUS
2566 int irqstate
= (oldval
& 4) && !(value
& 2);
2568 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2569 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2573 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2575 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2578 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2581 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2584 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2586 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2589 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2592 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2595 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2598 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2601 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2603 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2606 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2609 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2612 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2614 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2617 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2620 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2623 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2626 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2629 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2632 ARMCPU
*cpu
= env_archcpu(env
);
2634 trace_arm_gt_cntvoff_write(value
);
2635 raw_write(env
, ri
, value
);
2636 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2639 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2641 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2644 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2647 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2650 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2652 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2655 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2658 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2661 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2664 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2667 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2669 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2672 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2675 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2678 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2680 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2683 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2686 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2689 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2692 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2695 void arm_gt_ptimer_cb(void *opaque
)
2697 ARMCPU
*cpu
= opaque
;
2699 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2702 void arm_gt_vtimer_cb(void *opaque
)
2704 ARMCPU
*cpu
= opaque
;
2706 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2709 void arm_gt_htimer_cb(void *opaque
)
2711 ARMCPU
*cpu
= opaque
;
2713 gt_recalc_timer(cpu
, GTIMER_HYP
);
2716 void arm_gt_stimer_cb(void *opaque
)
2718 ARMCPU
*cpu
= opaque
;
2720 gt_recalc_timer(cpu
, GTIMER_SEC
);
2723 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2724 /* Note that CNTFRQ is purely reads-as-written for the benefit
2725 * of software; writing it doesn't actually change the timer frequency.
2726 * Our reset value matches the fixed frequency we implement the timer at.
2728 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2729 .type
= ARM_CP_ALIAS
,
2730 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2731 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2733 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2734 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2735 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2736 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2737 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
2739 /* overall control: mostly access permissions */
2740 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2741 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2743 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2746 /* per-timer control */
2747 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2748 .secure
= ARM_CP_SECSTATE_NS
,
2749 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2750 .accessfn
= gt_ptimer_access
,
2751 .fieldoffset
= offsetoflow32(CPUARMState
,
2752 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2753 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2755 { .name
= "CNTP_CTL_S",
2756 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2757 .secure
= ARM_CP_SECSTATE_S
,
2758 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2759 .accessfn
= gt_ptimer_access
,
2760 .fieldoffset
= offsetoflow32(CPUARMState
,
2761 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2762 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2764 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2765 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2766 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2767 .accessfn
= gt_ptimer_access
,
2768 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2770 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
2772 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2773 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2774 .accessfn
= gt_vtimer_access
,
2775 .fieldoffset
= offsetoflow32(CPUARMState
,
2776 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2777 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2779 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2780 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2781 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2782 .accessfn
= gt_vtimer_access
,
2783 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2785 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2787 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2788 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2789 .secure
= ARM_CP_SECSTATE_NS
,
2790 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2791 .accessfn
= gt_ptimer_access
,
2792 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2794 { .name
= "CNTP_TVAL_S",
2795 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2796 .secure
= ARM_CP_SECSTATE_S
,
2797 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2798 .accessfn
= gt_ptimer_access
,
2799 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2801 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2802 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2803 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2804 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2805 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2807 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2808 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2809 .accessfn
= gt_vtimer_access
,
2810 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2812 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2813 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2814 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2815 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2816 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2818 /* The counter itself */
2819 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2820 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2821 .accessfn
= gt_pct_access
,
2822 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2824 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2825 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2826 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2827 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2829 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2830 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2831 .accessfn
= gt_vct_access
,
2832 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2834 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2835 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2836 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2837 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2839 /* Comparison value, indicating when the timer goes off */
2840 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2841 .secure
= ARM_CP_SECSTATE_NS
,
2843 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2844 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2845 .accessfn
= gt_ptimer_access
,
2846 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2848 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
2849 .secure
= ARM_CP_SECSTATE_S
,
2851 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2852 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2853 .accessfn
= gt_ptimer_access
,
2854 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2856 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2857 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2860 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2861 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2862 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2864 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2866 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2867 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2868 .accessfn
= gt_vtimer_access
,
2869 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2871 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2872 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2875 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2876 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2877 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2879 /* Secure timer -- this is actually restricted to only EL3
2880 * and configurably Secure-EL1 via the accessfn.
2882 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2883 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2884 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2885 .accessfn
= gt_stimer_access
,
2886 .readfn
= gt_sec_tval_read
,
2887 .writefn
= gt_sec_tval_write
,
2888 .resetfn
= gt_sec_timer_reset
,
2890 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2891 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2892 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2893 .accessfn
= gt_stimer_access
,
2894 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2896 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2898 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2899 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2900 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2901 .accessfn
= gt_stimer_access
,
2902 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2903 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2910 /* In user-mode most of the generic timer registers are inaccessible
2911 * however modern kernels (4.12+) allow access to cntvct_el0
2914 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2916 /* Currently we have no support for QEMUTimer in linux-user so we
2917 * can't call gt_get_countervalue(env), instead we directly
2918 * call the lower level functions.
2920 return cpu_get_clock() / GTIMER_SCALE
;
2923 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2924 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2925 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2926 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
2927 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2928 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
2930 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2931 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2932 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2933 .readfn
= gt_virt_cnt_read
,
2940 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2942 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2943 raw_write(env
, ri
, value
);
2944 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2945 raw_write(env
, ri
, value
& 0xfffff6ff);
2947 raw_write(env
, ri
, value
& 0xfffff1ff);
2951 #ifndef CONFIG_USER_ONLY
2952 /* get_phys_addr() isn't present for user-mode-only targets */
2954 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2958 /* The ATS12NSO* operations must trap to EL3 if executed in
2959 * Secure EL1 (which can only happen if EL3 is AArch64).
2960 * They are simply UNDEF if executed from NS EL1.
2961 * They function normally from EL2 or EL3.
2963 if (arm_current_el(env
) == 1) {
2964 if (arm_is_secure_below_el3(env
)) {
2965 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2967 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2970 return CP_ACCESS_OK
;
2973 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2974 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2977 target_ulong page_size
;
2981 bool format64
= false;
2982 MemTxAttrs attrs
= {};
2983 ARMMMUFaultInfo fi
= {};
2984 ARMCacheAttrs cacheattrs
= {};
2986 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
2987 &prot
, &page_size
, &fi
, &cacheattrs
);
2991 * Some kinds of translation fault must cause exceptions rather
2992 * than being reported in the PAR.
2994 int current_el
= arm_current_el(env
);
2996 uint32_t syn
, fsr
, fsc
;
2997 bool take_exc
= false;
2999 if (fi
.s1ptw
&& current_el
== 1 && !arm_is_secure(env
)
3000 && (mmu_idx
== ARMMMUIdx_S1NSE1
|| mmu_idx
== ARMMMUIdx_S1NSE0
)) {
3002 * Synchronous stage 2 fault on an access made as part of the
3003 * translation table walk for AT S1E0* or AT S1E1* insn
3004 * executed from NS EL1. If this is a synchronous external abort
3005 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3006 * to EL3. Otherwise the fault is taken as an exception to EL2,
3007 * and HPFAR_EL2 holds the faulting IPA.
3009 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3010 (env
->cp15
.scr_el3
& SCR_EA
)) {
3013 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3017 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3019 * Synchronous external aborts during a translation table walk
3020 * are taken as Data Abort exceptions.
3023 if (current_el
== 3) {
3029 target_el
= exception_target_el(env
);
3035 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3036 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3037 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3038 fsr
= arm_fi_to_lfsc(&fi
);
3039 fsc
= extract32(fsr
, 0, 6);
3041 fsr
= arm_fi_to_sfsc(&fi
);
3045 * Report exception with ESR indicating a fault due to a
3046 * translation table walk for a cache maintenance instruction.
3048 syn
= syn_data_abort_no_iss(current_el
== target_el
,
3049 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3050 env
->exception
.vaddress
= value
;
3051 env
->exception
.fsr
= fsr
;
3052 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3058 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3061 * * TTBCR.EAE determines whether the result is returned using the
3062 * 32-bit or the 64-bit PAR format
3063 * * Instructions executed in Hyp mode always use the 64bit format
3065 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3066 * * The Non-secure TTBCR.EAE bit is set to 1
3067 * * The implementation includes EL2, and the value of HCR.VM is 1
3069 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3071 * ATS1Hx always uses the 64bit format.
3073 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3075 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3076 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
3077 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3079 format64
|= arm_current_el(env
) == 2;
3085 /* Create a 64-bit PAR */
3086 par64
= (1 << 11); /* LPAE bit always set */
3088 par64
|= phys_addr
& ~0xfffULL
;
3089 if (!attrs
.secure
) {
3090 par64
|= (1 << 9); /* NS */
3092 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3093 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3095 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3098 par64
|= (fsr
& 0x3f) << 1; /* FS */
3100 par64
|= (1 << 9); /* S */
3103 par64
|= (1 << 8); /* PTW */
3107 /* fsr is a DFSR/IFSR value for the short descriptor
3108 * translation table format (with WnR always clear).
3109 * Convert it to a 32-bit PAR.
3112 /* We do not set any attribute bits in the PAR */
3113 if (page_size
== (1 << 24)
3114 && arm_feature(env
, ARM_FEATURE_V7
)) {
3115 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3117 par64
= phys_addr
& 0xfffff000;
3119 if (!attrs
.secure
) {
3120 par64
|= (1 << 9); /* NS */
3123 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3125 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3126 ((fsr
& 0xf) << 1) | 1;
3132 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3134 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3137 int el
= arm_current_el(env
);
3138 bool secure
= arm_is_secure_below_el3(env
);
3140 switch (ri
->opc2
& 6) {
3142 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
3145 mmu_idx
= ARMMMUIdx_S1E3
;
3148 mmu_idx
= ARMMMUIdx_S1NSE1
;
3151 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
3154 g_assert_not_reached();
3158 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3161 mmu_idx
= ARMMMUIdx_S1SE0
;
3164 mmu_idx
= ARMMMUIdx_S1NSE0
;
3167 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
3170 g_assert_not_reached();
3174 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3175 mmu_idx
= ARMMMUIdx_S12NSE1
;
3178 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3179 mmu_idx
= ARMMMUIdx_S12NSE0
;
3182 g_assert_not_reached();
3185 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3187 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3190 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3193 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3196 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S1E2
);
3198 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3201 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3204 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
3205 return CP_ACCESS_TRAP
;
3207 return CP_ACCESS_OK
;
3210 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3213 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3215 int secure
= arm_is_secure_below_el3(env
);
3217 switch (ri
->opc2
& 6) {
3220 case 0: /* AT S1E1R, AT S1E1W */
3221 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
3223 case 4: /* AT S1E2R, AT S1E2W */
3224 mmu_idx
= ARMMMUIdx_S1E2
;
3226 case 6: /* AT S1E3R, AT S1E3W */
3227 mmu_idx
= ARMMMUIdx_S1E3
;
3230 g_assert_not_reached();
3233 case 2: /* AT S1E0R, AT S1E0W */
3234 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
3236 case 4: /* AT S12E1R, AT S12E1W */
3237 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
3239 case 6: /* AT S12E0R, AT S12E0W */
3240 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
3243 g_assert_not_reached();
3246 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3250 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3251 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3252 .access
= PL1_RW
, .resetvalue
= 0,
3253 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3254 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3255 .writefn
= par_write
},
3256 #ifndef CONFIG_USER_ONLY
3257 /* This underdecoding is safe because the reginfo is NO_RAW. */
3258 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3259 .access
= PL1_W
, .accessfn
= ats_access
,
3260 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3265 /* Return basic MPU access permission bits. */
3266 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3273 for (i
= 0; i
< 16; i
+= 2) {
3274 ret
|= (val
>> i
) & mask
;
3280 /* Pad basic MPU access permission bits to extended format. */
3281 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3288 for (i
= 0; i
< 16; i
+= 2) {
3289 ret
|= (val
& mask
) << i
;
3295 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3298 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3301 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3303 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3306 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3309 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3312 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3314 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3317 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3319 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3325 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3329 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3332 ARMCPU
*cpu
= env_archcpu(env
);
3333 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3339 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3340 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3344 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3347 ARMCPU
*cpu
= env_archcpu(env
);
3348 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3350 if (value
>= nrgs
) {
3351 qemu_log_mask(LOG_GUEST_ERROR
,
3352 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3353 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3357 raw_write(env
, ri
, value
);
3360 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3361 /* Reset for all these registers is handled in arm_cpu_reset(),
3362 * because the PMSAv7 is also used by M-profile CPUs, which do
3363 * not register cpregs but still need the state to be reset.
3365 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3366 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3367 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3368 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3369 .resetfn
= arm_cp_reset_ignore
},
3370 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3371 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3372 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3373 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3374 .resetfn
= arm_cp_reset_ignore
},
3375 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3376 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3377 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3378 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3379 .resetfn
= arm_cp_reset_ignore
},
3380 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3382 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3383 .writefn
= pmsav7_rgnr_write
,
3384 .resetfn
= arm_cp_reset_ignore
},
3388 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3389 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3390 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3391 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3392 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3393 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3394 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3395 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3396 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3397 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3399 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3401 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3403 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3405 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3407 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3408 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3410 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3411 /* Protection region base and size registers */
3412 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3413 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3414 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3415 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3416 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3417 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3418 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3419 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3420 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3421 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3422 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3423 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3424 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3425 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3426 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3427 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3428 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3429 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3430 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3431 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3432 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3433 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3434 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3435 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3439 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3442 TCR
*tcr
= raw_ptr(env
, ri
);
3443 int maskshift
= extract32(value
, 0, 3);
3445 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3446 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3447 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3448 * using Long-desciptor translation table format */
3449 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3450 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3451 /* In an implementation that includes the Security Extensions
3452 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3453 * Short-descriptor translation table format.
3455 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3461 /* Update the masks corresponding to the TCR bank being written
3462 * Note that we always calculate mask and base_mask, but
3463 * they are only used for short-descriptor tables (ie if EAE is 0);
3464 * for long-descriptor tables the TCR fields are used differently
3465 * and the mask and base_mask values are meaningless.
3467 tcr
->raw_tcr
= value
;
3468 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3469 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3472 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3475 ARMCPU
*cpu
= env_archcpu(env
);
3476 TCR
*tcr
= raw_ptr(env
, ri
);
3478 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3479 /* With LPAE the TTBCR could result in a change of ASID
3480 * via the TTBCR.A1 bit, so do a TLB flush.
3482 tlb_flush(CPU(cpu
));
3484 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3485 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3486 vmsa_ttbcr_raw_write(env
, ri
, value
);
3489 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3491 TCR
*tcr
= raw_ptr(env
, ri
);
3493 /* Reset both the TCR as well as the masks corresponding to the bank of
3494 * the TCR being reset.
3498 tcr
->base_mask
= 0xffffc000u
;
3501 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3504 ARMCPU
*cpu
= env_archcpu(env
);
3505 TCR
*tcr
= raw_ptr(env
, ri
);
3507 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3508 tlb_flush(CPU(cpu
));
3509 tcr
->raw_tcr
= value
;
3512 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3515 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3516 if (cpreg_field_is_64bit(ri
) &&
3517 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3518 ARMCPU
*cpu
= env_archcpu(env
);
3519 tlb_flush(CPU(cpu
));
3521 raw_write(env
, ri
, value
);
3524 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3527 ARMCPU
*cpu
= env_archcpu(env
);
3528 CPUState
*cs
= CPU(cpu
);
3530 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
3531 if (raw_read(env
, ri
) != value
) {
3532 tlb_flush_by_mmuidx(cs
,
3533 ARMMMUIdxBit_S12NSE1
|
3534 ARMMMUIdxBit_S12NSE0
|
3536 raw_write(env
, ri
, value
);
3540 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3541 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3542 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3543 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3544 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3545 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3546 .access
= PL1_RW
, .resetvalue
= 0,
3547 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3548 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3549 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3550 .access
= PL1_RW
, .resetvalue
= 0,
3551 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3552 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3553 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3554 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3555 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3560 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3561 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3562 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3564 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3565 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3566 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3567 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3568 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3569 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3570 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3571 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3572 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3573 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3574 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3575 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3576 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3577 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
3578 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3579 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3580 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3581 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3582 .raw_writefn
= vmsa_ttbcr_raw_write
,
3583 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
3584 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
3588 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3589 * qemu tlbs nor adjusting cached masks.
3591 static const ARMCPRegInfo ttbcr2_reginfo
= {
3592 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3593 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3594 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
3595 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
3598 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3601 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3602 /* The OS_TYPE bit in this register changes the reported CPUID! */
3603 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3604 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3607 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3610 env
->cp15
.c15_threadid
= value
& 0xffff;
3613 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3616 /* Wait-for-interrupt (deprecated) */
3617 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3620 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3623 /* On OMAP there are registers indicating the max/min index of dcache lines
3624 * containing a dirty line; cache flush operations have to reset these.
3626 env
->cp15
.c15_i_max
= 0x000;
3627 env
->cp15
.c15_i_min
= 0xff0;
3630 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3631 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3632 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3633 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3635 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3636 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3637 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3639 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3640 .writefn
= omap_ticonfig_write
},
3641 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3643 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3644 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3645 .access
= PL1_RW
, .resetvalue
= 0xff0,
3646 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3647 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3649 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3650 .writefn
= omap_threadid_write
},
3651 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3652 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3653 .type
= ARM_CP_NO_RAW
,
3654 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3655 /* TODO: Peripheral port remap register:
3656 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3657 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3660 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3661 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3662 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3663 .writefn
= omap_cachemaint_write
},
3664 { .name
= "C9", .cp
= 15, .crn
= 9,
3665 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3666 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3670 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3673 env
->cp15
.c15_cpar
= value
& 0x3fff;
3676 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3677 { .name
= "XSCALE_CPAR",
3678 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3679 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3680 .writefn
= xscale_cpar_write
, },
3681 { .name
= "XSCALE_AUXCR",
3682 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3683 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3685 /* XScale specific cache-lockdown: since we have no cache we NOP these
3686 * and hope the guest does not really rely on cache behaviour.
3688 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3689 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3690 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3691 { .name
= "XSCALE_UNLOCK_ICACHE",
3692 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3693 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3694 { .name
= "XSCALE_DCACHE_LOCK",
3695 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3696 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3697 { .name
= "XSCALE_UNLOCK_DCACHE",
3698 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3699 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3703 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3704 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3705 * implementation of this implementation-defined space.
3706 * Ideally this should eventually disappear in favour of actually
3707 * implementing the correct behaviour for all cores.
3709 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3710 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3712 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3717 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3718 /* Cache status: RAZ because we have no cache so it's always clean */
3719 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3720 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3725 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3726 /* We never have a a block transfer operation in progress */
3727 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3728 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3730 /* The cache ops themselves: these all NOP for QEMU */
3731 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
3732 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3733 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
3734 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3735 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
3736 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3737 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
3738 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3739 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
3740 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3741 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
3742 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
3746 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
3747 /* The cache test-and-clean instructions always return (1 << 30)
3748 * to indicate that there are no dirty cache lines.
3750 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
3751 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3752 .resetvalue
= (1 << 30) },
3753 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
3754 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3755 .resetvalue
= (1 << 30) },
3759 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
3760 /* Ignore ReadBuffer accesses */
3761 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
3762 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3763 .access
= PL1_RW
, .resetvalue
= 0,
3764 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
3768 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3770 ARMCPU
*cpu
= env_archcpu(env
);
3771 unsigned int cur_el
= arm_current_el(env
);
3772 bool secure
= arm_is_secure(env
);
3774 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
3775 return env
->cp15
.vpidr_el2
;
3777 return raw_read(env
, ri
);
3780 static uint64_t mpidr_read_val(CPUARMState
*env
)
3782 ARMCPU
*cpu
= env_archcpu(env
);
3783 uint64_t mpidr
= cpu
->mp_affinity
;
3785 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
3786 mpidr
|= (1U << 31);
3787 /* Cores which are uniprocessor (non-coherent)
3788 * but still implement the MP extensions set
3789 * bit 30. (For instance, Cortex-R5).
3791 if (cpu
->mp_is_up
) {
3792 mpidr
|= (1u << 30);
3798 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3800 unsigned int cur_el
= arm_current_el(env
);
3801 bool secure
= arm_is_secure(env
);
3803 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
3804 return env
->cp15
.vmpidr_el2
;
3806 return mpidr_read_val(env
);
3809 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
3811 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
3812 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
3813 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3815 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
3816 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
3817 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
3819 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
3820 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
3821 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
3822 offsetof(CPUARMState
, cp15
.par_ns
)} },
3823 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
3824 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3825 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3826 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
3827 .writefn
= vmsa_ttbr_write
, },
3828 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
3829 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3830 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3831 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
3832 .writefn
= vmsa_ttbr_write
, },
3836 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3838 return vfp_get_fpcr(env
);
3841 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3844 vfp_set_fpcr(env
, value
);
3847 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3849 return vfp_get_fpsr(env
);
3852 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3855 vfp_set_fpsr(env
, value
);
3858 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3861 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
3862 return CP_ACCESS_TRAP
;
3864 return CP_ACCESS_OK
;
3867 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3870 env
->daif
= value
& PSTATE_DAIF
;
3873 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
3874 const ARMCPRegInfo
*ri
,
3877 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
3878 * SCTLR_EL1.UCI is set.
3880 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
3881 return CP_ACCESS_TRAP
;
3883 return CP_ACCESS_OK
;
3886 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3887 * Page D4-1736 (DDI0487A.b)
3890 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3893 CPUState
*cs
= env_cpu(env
);
3894 bool sec
= arm_is_secure_below_el3(env
);
3897 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3898 ARMMMUIdxBit_S1SE1
|
3899 ARMMMUIdxBit_S1SE0
);
3901 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3902 ARMMMUIdxBit_S12NSE1
|
3903 ARMMMUIdxBit_S12NSE0
);
3907 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3910 CPUState
*cs
= env_cpu(env
);
3912 if (tlb_force_broadcast(env
)) {
3913 tlbi_aa64_vmalle1is_write(env
, NULL
, value
);
3917 if (arm_is_secure_below_el3(env
)) {
3918 tlb_flush_by_mmuidx(cs
,
3919 ARMMMUIdxBit_S1SE1
|
3920 ARMMMUIdxBit_S1SE0
);
3922 tlb_flush_by_mmuidx(cs
,
3923 ARMMMUIdxBit_S12NSE1
|
3924 ARMMMUIdxBit_S12NSE0
);
3928 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3931 /* Note that the 'ALL' scope must invalidate both stage 1 and
3932 * stage 2 translations, whereas most other scopes only invalidate
3933 * stage 1 translations.
3935 ARMCPU
*cpu
= env_archcpu(env
);
3936 CPUState
*cs
= CPU(cpu
);
3938 if (arm_is_secure_below_el3(env
)) {
3939 tlb_flush_by_mmuidx(cs
,
3940 ARMMMUIdxBit_S1SE1
|
3941 ARMMMUIdxBit_S1SE0
);
3943 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3944 tlb_flush_by_mmuidx(cs
,
3945 ARMMMUIdxBit_S12NSE1
|
3946 ARMMMUIdxBit_S12NSE0
|
3949 tlb_flush_by_mmuidx(cs
,
3950 ARMMMUIdxBit_S12NSE1
|
3951 ARMMMUIdxBit_S12NSE0
);
3956 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3959 ARMCPU
*cpu
= env_archcpu(env
);
3960 CPUState
*cs
= CPU(cpu
);
3962 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3965 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3968 ARMCPU
*cpu
= env_archcpu(env
);
3969 CPUState
*cs
= CPU(cpu
);
3971 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3974 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3977 /* Note that the 'ALL' scope must invalidate both stage 1 and
3978 * stage 2 translations, whereas most other scopes only invalidate
3979 * stage 1 translations.
3981 CPUState
*cs
= env_cpu(env
);
3982 bool sec
= arm_is_secure_below_el3(env
);
3983 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3986 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3987 ARMMMUIdxBit_S1SE1
|
3988 ARMMMUIdxBit_S1SE0
);
3989 } else if (has_el2
) {
3990 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3991 ARMMMUIdxBit_S12NSE1
|
3992 ARMMMUIdxBit_S12NSE0
|
3995 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3996 ARMMMUIdxBit_S12NSE1
|
3997 ARMMMUIdxBit_S12NSE0
);
4001 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4004 CPUState
*cs
= env_cpu(env
);
4006 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
4009 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4012 CPUState
*cs
= env_cpu(env
);
4014 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
4017 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4020 /* Invalidate by VA, EL2
4021 * Currently handles both VAE2 and VALE2, since we don't support
4022 * flush-last-level-only.
4024 ARMCPU
*cpu
= env_archcpu(env
);
4025 CPUState
*cs
= CPU(cpu
);
4026 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4028 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
4031 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4034 /* Invalidate by VA, EL3
4035 * Currently handles both VAE3 and VALE3, since we don't support
4036 * flush-last-level-only.
4038 ARMCPU
*cpu
= env_archcpu(env
);
4039 CPUState
*cs
= CPU(cpu
);
4040 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4042 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
4045 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4048 ARMCPU
*cpu
= env_archcpu(env
);
4049 CPUState
*cs
= CPU(cpu
);
4050 bool sec
= arm_is_secure_below_el3(env
);
4051 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4054 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4055 ARMMMUIdxBit_S1SE1
|
4056 ARMMMUIdxBit_S1SE0
);
4058 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4059 ARMMMUIdxBit_S12NSE1
|
4060 ARMMMUIdxBit_S12NSE0
);
4064 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4067 /* Invalidate by VA, EL1&0 (AArch64 version).
4068 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4069 * since we don't support flush-for-specific-ASID-only or
4070 * flush-last-level-only.
4072 ARMCPU
*cpu
= env_archcpu(env
);
4073 CPUState
*cs
= CPU(cpu
);
4074 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4076 if (tlb_force_broadcast(env
)) {
4077 tlbi_aa64_vae1is_write(env
, NULL
, value
);
4081 if (arm_is_secure_below_el3(env
)) {
4082 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
4083 ARMMMUIdxBit_S1SE1
|
4084 ARMMMUIdxBit_S1SE0
);
4086 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
4087 ARMMMUIdxBit_S12NSE1
|
4088 ARMMMUIdxBit_S12NSE0
);
4092 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4095 CPUState
*cs
= env_cpu(env
);
4096 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4098 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4102 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4105 CPUState
*cs
= env_cpu(env
);
4106 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4108 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4112 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4115 /* Invalidate by IPA. This has to invalidate any structures that
4116 * contain only stage 2 translation information, but does not need
4117 * to apply to structures that contain combined stage 1 and stage 2
4118 * translation information.
4119 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
4121 ARMCPU
*cpu
= env_archcpu(env
);
4122 CPUState
*cs
= CPU(cpu
);
4125 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4129 pageaddr
= sextract64(value
<< 12, 0, 48);
4131 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
4134 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4137 CPUState
*cs
= env_cpu(env
);
4140 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
4144 pageaddr
= sextract64(value
<< 12, 0, 48);
4146 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4150 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4153 /* We don't implement EL2, so the only control on DC ZVA is the
4154 * bit in the SCTLR which can prohibit access for EL0.
4156 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4157 return CP_ACCESS_TRAP
;
4159 return CP_ACCESS_OK
;
4162 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4164 ARMCPU
*cpu
= env_archcpu(env
);
4165 int dzp_bit
= 1 << 4;
4167 /* DZP indicates whether DC ZVA access is allowed */
4168 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4171 return cpu
->dcz_blocksize
| dzp_bit
;
4174 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4177 if (!(env
->pstate
& PSTATE_SP
)) {
4178 /* Access to SP_EL0 is undefined if it's being used as
4179 * the stack pointer.
4181 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4183 return CP_ACCESS_OK
;
4186 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4188 return env
->pstate
& PSTATE_SP
;
4191 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4193 update_spsel(env
, val
);
4196 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4199 ARMCPU
*cpu
= env_archcpu(env
);
4201 if (raw_read(env
, ri
) == value
) {
4202 /* Skip the TLB flush if nothing actually changed; Linux likes
4203 * to do a lot of pointless SCTLR writes.
4208 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4209 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4213 raw_write(env
, ri
, value
);
4214 /* ??? Lots of these bits are not implemented. */
4215 /* This may enable/disable the MMU, so do a TLB flush. */
4216 tlb_flush(CPU(cpu
));
4218 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4220 * Normally we would always end the TB on an SCTLR write; see the
4221 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4222 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4223 * of hflags from the translator, so do it here.
4225 arm_rebuild_hflags(env
);
4229 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4232 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
4233 return CP_ACCESS_TRAP_FP_EL2
;
4235 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
4236 return CP_ACCESS_TRAP_FP_EL3
;
4238 return CP_ACCESS_OK
;
4241 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4244 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4247 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4248 /* Minimal set of EL0-visible registers. This will need to be expanded
4249 * significantly for system emulation of AArch64 CPUs.
4251 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4252 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4253 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4254 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4255 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4256 .type
= ARM_CP_NO_RAW
,
4257 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4258 .fieldoffset
= offsetof(CPUARMState
, daif
),
4259 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4260 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4261 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4262 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4263 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4264 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4265 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4266 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4267 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4268 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4269 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4270 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4271 .readfn
= aa64_dczid_read
},
4272 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4273 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4274 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4275 #ifndef CONFIG_USER_ONLY
4276 /* Avoid overhead of an access check that always passes in user-mode */
4277 .accessfn
= aa64_zva_access
,
4280 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4281 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4282 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4283 /* Cache ops: all NOPs since we don't emulate caches */
4284 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4285 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4286 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4287 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4288 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4289 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4290 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4291 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4292 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4293 .accessfn
= aa64_cacheop_access
},
4294 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4295 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4296 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4297 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4298 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4299 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4300 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4301 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4302 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4303 .accessfn
= aa64_cacheop_access
},
4304 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4305 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4306 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4307 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4308 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4309 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4310 .accessfn
= aa64_cacheop_access
},
4311 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4312 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4313 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4314 .accessfn
= aa64_cacheop_access
},
4315 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4316 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4317 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4318 /* TLBI operations */
4319 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4320 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4321 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4322 .writefn
= tlbi_aa64_vmalle1is_write
},
4323 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4324 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4325 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4326 .writefn
= tlbi_aa64_vae1is_write
},
4327 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4328 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4329 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4330 .writefn
= tlbi_aa64_vmalle1is_write
},
4331 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4332 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4333 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4334 .writefn
= tlbi_aa64_vae1is_write
},
4335 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4336 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4337 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4338 .writefn
= tlbi_aa64_vae1is_write
},
4339 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4340 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4341 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4342 .writefn
= tlbi_aa64_vae1is_write
},
4343 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4344 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4345 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4346 .writefn
= tlbi_aa64_vmalle1_write
},
4347 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4348 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4349 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4350 .writefn
= tlbi_aa64_vae1_write
},
4351 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4352 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4353 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4354 .writefn
= tlbi_aa64_vmalle1_write
},
4355 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4356 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4357 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4358 .writefn
= tlbi_aa64_vae1_write
},
4359 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4360 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4361 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4362 .writefn
= tlbi_aa64_vae1_write
},
4363 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4364 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4365 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4366 .writefn
= tlbi_aa64_vae1_write
},
4367 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4368 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4369 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4370 .writefn
= tlbi_aa64_ipas2e1is_write
},
4371 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4372 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4373 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4374 .writefn
= tlbi_aa64_ipas2e1is_write
},
4375 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4376 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4377 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4378 .writefn
= tlbi_aa64_alle1is_write
},
4379 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4380 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4381 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4382 .writefn
= tlbi_aa64_alle1is_write
},
4383 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4384 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4385 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4386 .writefn
= tlbi_aa64_ipas2e1_write
},
4387 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4388 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4389 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4390 .writefn
= tlbi_aa64_ipas2e1_write
},
4391 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4392 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4393 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4394 .writefn
= tlbi_aa64_alle1_write
},
4395 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4396 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4397 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4398 .writefn
= tlbi_aa64_alle1is_write
},
4399 #ifndef CONFIG_USER_ONLY
4400 /* 64 bit address translation operations */
4401 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4402 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4403 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4404 .writefn
= ats_write64
},
4405 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4406 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4407 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4408 .writefn
= ats_write64
},
4409 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4410 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4411 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4412 .writefn
= ats_write64
},
4413 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4414 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4415 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4416 .writefn
= ats_write64
},
4417 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4418 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4419 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4420 .writefn
= ats_write64
},
4421 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4422 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4423 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4424 .writefn
= ats_write64
},
4425 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4426 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4427 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4428 .writefn
= ats_write64
},
4429 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4430 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4431 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4432 .writefn
= ats_write64
},
4433 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4434 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4435 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4436 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4437 .writefn
= ats_write64
},
4438 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4439 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4440 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4441 .writefn
= ats_write64
},
4442 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4443 .type
= ARM_CP_ALIAS
,
4444 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4445 .access
= PL1_RW
, .resetvalue
= 0,
4446 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4447 .writefn
= par_write
},
4449 /* TLB invalidate last level of translation table walk */
4450 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4451 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
4452 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4453 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
4454 .writefn
= tlbimvaa_is_write
},
4455 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4456 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
4457 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4458 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
4459 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4460 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4461 .writefn
= tlbimva_hyp_write
},
4462 { .name
= "TLBIMVALHIS",
4463 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
4464 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4465 .writefn
= tlbimva_hyp_is_write
},
4466 { .name
= "TLBIIPAS2",
4467 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4468 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4469 .writefn
= tlbiipas2_write
},
4470 { .name
= "TLBIIPAS2IS",
4471 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4472 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4473 .writefn
= tlbiipas2_is_write
},
4474 { .name
= "TLBIIPAS2L",
4475 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4476 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4477 .writefn
= tlbiipas2_write
},
4478 { .name
= "TLBIIPAS2LIS",
4479 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4480 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4481 .writefn
= tlbiipas2_is_write
},
4482 /* 32 bit cache operations */
4483 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4484 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4485 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
4486 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4487 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4488 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4489 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
4490 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4491 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
4492 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4493 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
4494 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4495 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4496 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4497 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4498 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4499 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
4500 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4501 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4502 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4503 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
4504 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4505 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
4506 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4507 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4508 .type
= ARM_CP_NOP
, .access
= PL1_W
},
4509 /* MMU Domain access control / MPU write buffer control */
4510 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
4511 .access
= PL1_RW
, .resetvalue
= 0,
4512 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4513 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
4514 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
4515 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
4516 .type
= ARM_CP_ALIAS
,
4517 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
4519 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
4520 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
4521 .type
= ARM_CP_ALIAS
,
4522 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
4524 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
4525 /* We rely on the access checks not allowing the guest to write to the
4526 * state field when SPSel indicates that it's being used as the stack
4529 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
4530 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
4531 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
4532 .type
= ARM_CP_ALIAS
,
4533 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
4534 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
4535 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
4536 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4537 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
4538 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
4539 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
4540 .type
= ARM_CP_NO_RAW
,
4541 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
4542 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
4543 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
4544 .type
= ARM_CP_ALIAS
,
4545 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
4546 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
4547 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
4548 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
4549 .access
= PL2_RW
, .resetvalue
= 0,
4550 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
4551 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
4552 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
4553 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
4554 .access
= PL2_RW
, .resetvalue
= 0,
4555 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
4556 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
4557 .type
= ARM_CP_ALIAS
,
4558 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
4560 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
4561 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
4562 .type
= ARM_CP_ALIAS
,
4563 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
4565 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
4566 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
4567 .type
= ARM_CP_ALIAS
,
4568 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
4570 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
4571 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
4572 .type
= ARM_CP_ALIAS
,
4573 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
4575 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
4576 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
4577 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
4579 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
4580 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
4581 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
4582 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4583 .writefn
= sdcr_write
,
4584 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
4588 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
4589 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
4590 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4591 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4593 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
4594 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4595 .type
= ARM_CP_NO_RAW
,
4596 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4598 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4599 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
4600 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
4601 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4602 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4603 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4605 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4606 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4607 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4608 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4609 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4610 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4611 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4613 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4614 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4615 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4616 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4617 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4618 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4620 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4621 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4622 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4624 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4625 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4626 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4628 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4629 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4630 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4632 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4633 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4634 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4635 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4636 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4637 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4638 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4639 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4640 .cp
= 15, .opc1
= 6, .crm
= 2,
4641 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4642 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
4643 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4644 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4645 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4646 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4647 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4648 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4649 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4650 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4651 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4652 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4653 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4654 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4655 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4656 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4658 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4659 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
4660 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4661 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
4662 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
4663 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4664 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
4665 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4667 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
4668 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
4669 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4670 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
4671 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
4673 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4674 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4675 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4676 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4677 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4678 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4679 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4680 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4681 .access
= PL2_RW
, .accessfn
= access_tda
,
4682 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4683 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4684 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4685 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4686 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4687 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4688 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4689 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4690 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4691 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
4692 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4693 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
4694 .type
= ARM_CP_CONST
,
4695 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
4696 .access
= PL2_RW
, .resetvalue
= 0 },
4700 /* Ditto, but for registers which exist in ARMv8 but not v7 */
4701 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
4702 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
4703 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
4705 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4709 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
4711 ARMCPU
*cpu
= env_archcpu(env
);
4712 uint64_t valid_mask
= HCR_MASK
;
4714 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4715 valid_mask
&= ~HCR_HCD
;
4716 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
4717 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
4718 * However, if we're using the SMC PSCI conduit then QEMU is
4719 * effectively acting like EL3 firmware and so the guest at
4720 * EL2 should retain the ability to prevent EL1 from being
4721 * able to make SMC calls into the ersatz firmware, so in
4722 * that case HCR.TSC should be read/write.
4724 valid_mask
&= ~HCR_TSC
;
4726 if (cpu_isar_feature(aa64_lor
, cpu
)) {
4727 valid_mask
|= HCR_TLOR
;
4729 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
4730 valid_mask
|= HCR_API
| HCR_APK
;
4733 /* Clear RES0 bits. */
4734 value
&= valid_mask
;
4736 /* These bits change the MMU setup:
4737 * HCR_VM enables stage 2 translation
4738 * HCR_PTW forbids certain page-table setups
4739 * HCR_DC Disables stage1 and enables stage2 translation
4741 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
4742 tlb_flush(CPU(cpu
));
4744 env
->cp15
.hcr_el2
= value
;
4747 * Updates to VI and VF require us to update the status of
4748 * virtual interrupts, which are the logical OR of these bits
4749 * and the state of the input lines from the GIC. (This requires
4750 * that we have the iothread lock, which is done by marking the
4751 * reginfo structs as ARM_CP_IO.)
4752 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
4753 * possible for it to be taken immediately, because VIRQ and
4754 * VFIQ are masked unless running at EL0 or EL1, and HCR
4755 * can only be written at EL2.
4757 g_assert(qemu_mutex_iothread_locked());
4758 arm_cpu_update_virq(cpu
);
4759 arm_cpu_update_vfiq(cpu
);
4762 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4765 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
4766 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
4767 hcr_write(env
, NULL
, value
);
4770 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4773 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
4774 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
4775 hcr_write(env
, NULL
, value
);
4779 * Return the effective value of HCR_EL2.
4780 * Bits that are not included here:
4781 * RW (read from SCR_EL3.RW as needed)
4783 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
4785 uint64_t ret
= env
->cp15
.hcr_el2
;
4787 if (arm_is_secure_below_el3(env
)) {
4789 * "This register has no effect if EL2 is not enabled in the
4790 * current Security state". This is ARMv8.4-SecEL2 speak for
4791 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
4793 * Prior to that, the language was "In an implementation that
4794 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
4795 * as if this field is 0 for all purposes other than a direct
4796 * read or write access of HCR_EL2". With lots of enumeration
4797 * on a per-field basis. In current QEMU, this is condition
4798 * is arm_is_secure_below_el3.
4800 * Since the v8.4 language applies to the entire register, and
4801 * appears to be backward compatible, use that.
4804 } else if (ret
& HCR_TGE
) {
4805 /* These bits are up-to-date as of ARMv8.4. */
4806 if (ret
& HCR_E2H
) {
4807 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
4808 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
4809 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
4810 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
);
4812 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
4814 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
4815 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
4816 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
4823 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4827 * For A-profile AArch32 EL3, if NSACR.CP10
4828 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
4830 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
4831 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
4832 value
&= ~(0x3 << 10);
4833 value
|= env
->cp15
.cptr_el
[2] & (0x3 << 10);
4835 env
->cp15
.cptr_el
[2] = value
;
4838 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4841 * For A-profile AArch32 EL3, if NSACR.CP10
4842 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
4844 uint64_t value
= env
->cp15
.cptr_el
[2];
4846 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
4847 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
4853 static const ARMCPRegInfo el2_cp_reginfo
[] = {
4854 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
4856 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4857 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
4858 .writefn
= hcr_write
},
4859 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
4860 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
4861 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
4862 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
4863 .writefn
= hcr_writelow
},
4864 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
4865 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
4866 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4867 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
4868 .type
= ARM_CP_ALIAS
,
4869 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
4871 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
4872 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
4873 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
4874 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
4875 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4876 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
4877 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
4878 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
4879 .type
= ARM_CP_ALIAS
,
4880 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
4882 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
4883 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
4884 .type
= ARM_CP_ALIAS
,
4885 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
4887 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
4888 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
4889 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
4890 .access
= PL2_RW
, .writefn
= vbar_write
,
4891 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
4893 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
4894 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
4895 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
4896 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
4897 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4898 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
4899 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4900 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
4901 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
4902 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4903 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
4904 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
4906 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
4907 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
4908 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
4909 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
4910 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
4911 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
4912 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4914 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
4915 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
4916 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
4917 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4919 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
4920 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
4921 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4923 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
4924 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
4925 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4927 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4928 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
4930 /* no .writefn needed as this can't cause an ASID change;
4931 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4933 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
4934 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
4935 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4936 .type
= ARM_CP_ALIAS
,
4937 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4938 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4939 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
4940 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
4942 /* no .writefn needed as this can't cause an ASID change;
4943 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
4945 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
4946 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
4947 .cp
= 15, .opc1
= 6, .crm
= 2,
4948 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4949 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4950 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
4951 .writefn
= vttbr_write
},
4952 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
4953 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
4954 .access
= PL2_RW
, .writefn
= vttbr_write
,
4955 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
4956 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4957 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
4958 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
4959 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
4960 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4961 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
4962 .access
= PL2_RW
, .resetvalue
= 0,
4963 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
4964 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
4965 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
4966 .access
= PL2_RW
, .resetvalue
= 0,
4967 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4968 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
4969 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4970 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
4971 { .name
= "TLBIALLNSNH",
4972 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4973 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4974 .writefn
= tlbiall_nsnh_write
},
4975 { .name
= "TLBIALLNSNHIS",
4976 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4977 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4978 .writefn
= tlbiall_nsnh_is_write
},
4979 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4980 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4981 .writefn
= tlbiall_hyp_write
},
4982 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
4983 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4984 .writefn
= tlbiall_hyp_is_write
},
4985 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4986 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4987 .writefn
= tlbimva_hyp_write
},
4988 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
4989 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4990 .writefn
= tlbimva_hyp_is_write
},
4991 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
4992 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
4993 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4994 .writefn
= tlbi_aa64_alle2_write
},
4995 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
4996 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
4997 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4998 .writefn
= tlbi_aa64_vae2_write
},
4999 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5000 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5001 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5002 .writefn
= tlbi_aa64_vae2_write
},
5003 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5004 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5005 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5006 .writefn
= tlbi_aa64_alle2is_write
},
5007 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5008 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5009 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5010 .writefn
= tlbi_aa64_vae2is_write
},
5011 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5012 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5013 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5014 .writefn
= tlbi_aa64_vae2is_write
},
5015 #ifndef CONFIG_USER_ONLY
5016 /* Unlike the other EL2-related AT operations, these must
5017 * UNDEF from EL3 if EL2 is not implemented, which is why we
5018 * define them here rather than with the rest of the AT ops.
5020 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5021 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5022 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5023 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5024 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5025 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5026 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5027 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5028 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5029 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5030 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5031 * to behave as if SCR.NS was 1.
5033 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5035 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5036 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5038 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5039 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5040 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5041 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5042 * reset values as IMPDEF. We choose to reset to 3 to comply with
5043 * both ARMv7 and ARMv8.
5045 .access
= PL2_RW
, .resetvalue
= 3,
5046 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5047 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5048 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5049 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5050 .writefn
= gt_cntvoff_write
,
5051 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5052 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5053 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5054 .writefn
= gt_cntvoff_write
,
5055 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5056 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5057 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5058 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5059 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5060 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5061 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5062 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5063 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5064 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5065 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5066 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5067 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5068 .resetfn
= gt_hyp_timer_reset
,
5069 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5070 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5072 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5074 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5076 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5078 /* The only field of MDCR_EL2 that has a defined architectural reset value
5079 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5080 * don't implement any PMU event counters, so using zero as a reset
5081 * value for MDCR_EL2 is okay
5083 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5084 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5085 .access
= PL2_RW
, .resetvalue
= 0,
5086 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
5087 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5088 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5089 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5090 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5091 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5092 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5094 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5095 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5096 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5098 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5102 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5103 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5104 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5105 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5107 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5108 .writefn
= hcr_writehigh
},
5112 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5115 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5116 * At Secure EL1 it traps to EL3.
5118 if (arm_current_el(env
) == 3) {
5119 return CP_ACCESS_OK
;
5121 if (arm_is_secure_below_el3(env
)) {
5122 return CP_ACCESS_TRAP_EL3
;
5124 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5126 return CP_ACCESS_OK
;
5128 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5131 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5132 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5133 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5134 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5135 .resetvalue
= 0, .writefn
= scr_write
},
5136 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
5137 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5138 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5139 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5140 .writefn
= scr_write
},
5141 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5142 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5143 .access
= PL3_RW
, .resetvalue
= 0,
5144 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5146 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5147 .access
= PL3_RW
, .resetvalue
= 0,
5148 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5149 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5150 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5151 .writefn
= vbar_write
, .resetvalue
= 0,
5152 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5153 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5154 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5155 .access
= PL3_RW
, .resetvalue
= 0,
5156 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5157 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5158 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5160 /* no .writefn needed as this can't cause an ASID change;
5161 * we must provide a .raw_writefn and .resetfn because we handle
5162 * reset and migration for the AArch32 TTBCR(S), which might be
5163 * using mask and base_mask.
5165 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5166 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5167 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5168 .type
= ARM_CP_ALIAS
,
5169 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5171 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5172 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5173 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5174 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5175 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5176 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5177 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5178 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5179 .type
= ARM_CP_ALIAS
,
5180 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5182 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5183 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5184 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5185 .access
= PL3_RW
, .writefn
= vbar_write
,
5186 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5188 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5189 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5190 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5191 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5192 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5193 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5194 .access
= PL3_RW
, .resetvalue
= 0,
5195 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5196 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5197 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5198 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5200 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5201 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5202 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5204 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5205 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5206 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5208 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5209 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5210 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5211 .writefn
= tlbi_aa64_alle3is_write
},
5212 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5213 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5214 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5215 .writefn
= tlbi_aa64_vae3is_write
},
5216 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5217 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5218 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5219 .writefn
= tlbi_aa64_vae3is_write
},
5220 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5221 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5222 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5223 .writefn
= tlbi_aa64_alle3_write
},
5224 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5225 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5226 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5227 .writefn
= tlbi_aa64_vae3_write
},
5228 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5229 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5230 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5231 .writefn
= tlbi_aa64_vae3_write
},
5235 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5238 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
5239 * but the AArch32 CTR has its own reginfo struct)
5241 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5242 return CP_ACCESS_TRAP
;
5245 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5246 return CP_ACCESS_TRAP_EL2
;
5249 return CP_ACCESS_OK
;
5252 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5255 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5256 * read via a bit in OSLSR_EL1.
5260 if (ri
->state
== ARM_CP_STATE_AA32
) {
5261 oslock
= (value
== 0xC5ACCE55);
5266 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5269 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5270 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5271 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
5272 * unlike DBGDRAR it is never accessible from EL0.
5273 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
5276 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
5277 .access
= PL0_R
, .accessfn
= access_tdra
,
5278 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5279 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
5280 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5281 .access
= PL1_R
, .accessfn
= access_tdra
,
5282 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5283 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
5284 .access
= PL0_R
, .accessfn
= access_tdra
,
5285 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5286 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
5287 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
5288 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
5289 .access
= PL1_RW
, .accessfn
= access_tda
,
5290 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
5292 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
5293 * We don't implement the configurable EL0 access.
5295 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
5296 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
5297 .type
= ARM_CP_ALIAS
,
5298 .access
= PL1_R
, .accessfn
= access_tda
,
5299 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
5300 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
5301 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
5302 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
5303 .accessfn
= access_tdosa
,
5304 .writefn
= oslar_write
},
5305 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
5306 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
5307 .access
= PL1_R
, .resetvalue
= 10,
5308 .accessfn
= access_tdosa
,
5309 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
5310 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
5311 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5312 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
5313 .access
= PL1_RW
, .accessfn
= access_tdosa
,
5314 .type
= ARM_CP_NOP
},
5315 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
5316 * implement vector catch debug events yet.
5319 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
5320 .access
= PL1_RW
, .accessfn
= access_tda
,
5321 .type
= ARM_CP_NOP
},
5322 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
5323 * to save and restore a 32-bit guest's DBGVCR)
5325 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
5326 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
5327 .access
= PL2_RW
, .accessfn
= access_tda
,
5328 .type
= ARM_CP_NOP
},
5329 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
5330 * Channel but Linux may try to access this register. The 32-bit
5331 * alias is DBGDCCINT.
5333 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
5334 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
5335 .access
= PL1_RW
, .accessfn
= access_tda
,
5336 .type
= ARM_CP_NOP
},
5340 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
5341 /* 64 bit access versions of the (dummy) debug registers */
5342 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
5343 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5344 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
5345 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
5349 /* Return the exception level to which exceptions should be taken
5350 * via SVEAccessTrap. If an exception should be routed through
5351 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
5352 * take care of raising that exception.
5353 * C.f. the ARM pseudocode function CheckSVEEnabled.
5355 int sve_exception_el(CPUARMState
*env
, int el
)
5357 #ifndef CONFIG_USER_ONLY
5359 bool disabled
= false;
5361 /* The CPACR.ZEN controls traps to EL1:
5362 * 0, 2 : trap EL0 and EL1 accesses
5363 * 1 : trap only EL0 accesses
5364 * 3 : trap no accesses
5366 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
5368 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
5373 return (arm_feature(env
, ARM_FEATURE_EL2
)
5374 && (arm_hcr_el2_eff(env
) & HCR_TGE
) ? 2 : 1);
5377 /* Check CPACR.FPEN. */
5378 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
5380 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
5388 /* CPTR_EL2. Since TZ and TFP are positive,
5389 * they will be zero when EL2 is not present.
5391 if (el
<= 2 && !arm_is_secure_below_el3(env
)) {
5392 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
5395 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
5400 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
5401 if (arm_feature(env
, ARM_FEATURE_EL3
)
5402 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
5409 static uint32_t sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
5413 end_len
= start_len
&= 0xf;
5414 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
5415 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
5416 assert(end_len
< start_len
);
5422 * Given that SVE is enabled, return the vector length for EL.
5424 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
5426 ARMCPU
*cpu
= env_archcpu(env
);
5427 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
5430 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
5432 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
5433 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
5435 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5436 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
5439 return sve_zcr_get_valid_len(cpu
, zcr_len
);
5442 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5445 int cur_el
= arm_current_el(env
);
5446 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
5449 /* Bits other than [3:0] are RAZ/WI. */
5450 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
5451 raw_write(env
, ri
, value
& 0xf);
5454 * Because we arrived here, we know both FP and SVE are enabled;
5455 * otherwise we would have trapped access to the ZCR_ELn register.
5457 new_len
= sve_zcr_len_for_el(env
, cur_el
);
5458 if (new_len
< old_len
) {
5459 aarch64_sve_narrow_vq(env
, new_len
+ 1);
5463 static const ARMCPRegInfo zcr_el1_reginfo
= {
5464 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
5465 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
5466 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
5467 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
5468 .writefn
= zcr_write
, .raw_writefn
= raw_write
5471 static const ARMCPRegInfo zcr_el2_reginfo
= {
5472 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5473 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5474 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5475 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
5476 .writefn
= zcr_write
, .raw_writefn
= raw_write
5479 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
5480 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
5481 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
5482 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
5483 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
5486 static const ARMCPRegInfo zcr_el3_reginfo
= {
5487 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
5488 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
5489 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
5490 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
5491 .writefn
= zcr_write
, .raw_writefn
= raw_write
5494 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
5496 CPUARMState
*env
= &cpu
->env
;
5498 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
5499 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
5501 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
5503 if (env
->cpu_watchpoint
[n
]) {
5504 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
5505 env
->cpu_watchpoint
[n
] = NULL
;
5508 if (!extract64(wcr
, 0, 1)) {
5509 /* E bit clear : watchpoint disabled */
5513 switch (extract64(wcr
, 3, 2)) {
5515 /* LSC 00 is reserved and must behave as if the wp is disabled */
5518 flags
|= BP_MEM_READ
;
5521 flags
|= BP_MEM_WRITE
;
5524 flags
|= BP_MEM_ACCESS
;
5528 /* Attempts to use both MASK and BAS fields simultaneously are
5529 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
5530 * thus generating a watchpoint for every byte in the masked region.
5532 mask
= extract64(wcr
, 24, 4);
5533 if (mask
== 1 || mask
== 2) {
5534 /* Reserved values of MASK; we must act as if the mask value was
5535 * some non-reserved value, or as if the watchpoint were disabled.
5536 * We choose the latter.
5540 /* Watchpoint covers an aligned area up to 2GB in size */
5542 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
5543 * whether the watchpoint fires when the unmasked bits match; we opt
5544 * to generate the exceptions.
5548 /* Watchpoint covers bytes defined by the byte address select bits */
5549 int bas
= extract64(wcr
, 5, 8);
5553 /* This must act as if the watchpoint is disabled */
5557 if (extract64(wvr
, 2, 1)) {
5558 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
5559 * ignored, and BAS[3:0] define which bytes to watch.
5563 /* The BAS bits are supposed to be programmed to indicate a contiguous
5564 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
5565 * we fire for each byte in the word/doubleword addressed by the WVR.
5566 * We choose to ignore any non-zero bits after the first range of 1s.
5568 basstart
= ctz32(bas
);
5569 len
= cto32(bas
>> basstart
);
5573 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
5574 &env
->cpu_watchpoint
[n
]);
5577 void hw_watchpoint_update_all(ARMCPU
*cpu
)
5580 CPUARMState
*env
= &cpu
->env
;
5582 /* Completely clear out existing QEMU watchpoints and our array, to
5583 * avoid possible stale entries following migration load.
5585 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
5586 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
5588 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
5589 hw_watchpoint_update(cpu
, i
);
5593 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5596 ARMCPU
*cpu
= env_archcpu(env
);
5599 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
5600 * register reads and behaves as if values written are sign extended.
5601 * Bits [1:0] are RES0.
5603 value
= sextract64(value
, 0, 49) & ~3ULL;
5605 raw_write(env
, ri
, value
);
5606 hw_watchpoint_update(cpu
, i
);
5609 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5612 ARMCPU
*cpu
= env_archcpu(env
);
5615 raw_write(env
, ri
, value
);
5616 hw_watchpoint_update(cpu
, i
);
5619 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
5621 CPUARMState
*env
= &cpu
->env
;
5622 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
5623 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
5628 if (env
->cpu_breakpoint
[n
]) {
5629 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
5630 env
->cpu_breakpoint
[n
] = NULL
;
5633 if (!extract64(bcr
, 0, 1)) {
5634 /* E bit clear : watchpoint disabled */
5638 bt
= extract64(bcr
, 20, 4);
5641 case 4: /* unlinked address mismatch (reserved if AArch64) */
5642 case 5: /* linked address mismatch (reserved if AArch64) */
5643 qemu_log_mask(LOG_UNIMP
,
5644 "arm: address mismatch breakpoint types not implemented\n");
5646 case 0: /* unlinked address match */
5647 case 1: /* linked address match */
5649 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
5650 * we behave as if the register was sign extended. Bits [1:0] are
5651 * RES0. The BAS field is used to allow setting breakpoints on 16
5652 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
5653 * a bp will fire if the addresses covered by the bp and the addresses
5654 * covered by the insn overlap but the insn doesn't start at the
5655 * start of the bp address range. We choose to require the insn and
5656 * the bp to have the same address. The constraints on writing to
5657 * BAS enforced in dbgbcr_write mean we have only four cases:
5658 * 0b0000 => no breakpoint
5659 * 0b0011 => breakpoint on addr
5660 * 0b1100 => breakpoint on addr + 2
5661 * 0b1111 => breakpoint on addr
5662 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
5664 int bas
= extract64(bcr
, 5, 4);
5665 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
5674 case 2: /* unlinked context ID match */
5675 case 8: /* unlinked VMID match (reserved if no EL2) */
5676 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
5677 qemu_log_mask(LOG_UNIMP
,
5678 "arm: unlinked context breakpoint types not implemented\n");
5680 case 9: /* linked VMID match (reserved if no EL2) */
5681 case 11: /* linked context ID and VMID match (reserved if no EL2) */
5682 case 3: /* linked context ID match */
5684 /* We must generate no events for Linked context matches (unless
5685 * they are linked to by some other bp/wp, which is handled in
5686 * updates for the linking bp/wp). We choose to also generate no events
5687 * for reserved values.
5692 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
5695 void hw_breakpoint_update_all(ARMCPU
*cpu
)
5698 CPUARMState
*env
= &cpu
->env
;
5700 /* Completely clear out existing QEMU breakpoints and our array, to
5701 * avoid possible stale entries following migration load.
5703 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
5704 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
5706 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
5707 hw_breakpoint_update(cpu
, i
);
5711 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5714 ARMCPU
*cpu
= env_archcpu(env
);
5717 raw_write(env
, ri
, value
);
5718 hw_breakpoint_update(cpu
, i
);
5721 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5724 ARMCPU
*cpu
= env_archcpu(env
);
5727 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
5730 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
5731 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
5733 raw_write(env
, ri
, value
);
5734 hw_breakpoint_update(cpu
, i
);
5737 static void define_debug_regs(ARMCPU
*cpu
)
5739 /* Define v7 and v8 architectural debug registers.
5740 * These are just dummy implementations for now.
5743 int wrps
, brps
, ctx_cmps
;
5744 ARMCPRegInfo dbgdidr
= {
5745 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
5746 .access
= PL0_R
, .accessfn
= access_tda
,
5747 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
5750 /* Note that all these register fields hold "number of Xs minus 1". */
5751 brps
= extract32(cpu
->dbgdidr
, 24, 4);
5752 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
5753 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
5755 assert(ctx_cmps
<= brps
);
5757 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
5758 * of the debug registers such as number of breakpoints;
5759 * check that if they both exist then they agree.
5761 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
5762 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
5763 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
5764 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
5767 define_one_arm_cp_reg(cpu
, &dbgdidr
);
5768 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
5770 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
5771 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
5774 for (i
= 0; i
< brps
+ 1; i
++) {
5775 ARMCPRegInfo dbgregs
[] = {
5776 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
5777 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
5778 .access
= PL1_RW
, .accessfn
= access_tda
,
5779 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
5780 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
5782 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
5783 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
5784 .access
= PL1_RW
, .accessfn
= access_tda
,
5785 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
5786 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
5790 define_arm_cp_regs(cpu
, dbgregs
);
5793 for (i
= 0; i
< wrps
+ 1; i
++) {
5794 ARMCPRegInfo dbgregs
[] = {
5795 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
5796 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
5797 .access
= PL1_RW
, .accessfn
= access_tda
,
5798 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
5799 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
5801 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
5802 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
5803 .access
= PL1_RW
, .accessfn
= access_tda
,
5804 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
5805 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
5809 define_arm_cp_regs(cpu
, dbgregs
);
5813 /* We don't know until after realize whether there's a GICv3
5814 * attached, and that is what registers the gicv3 sysregs.
5815 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
5818 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5820 ARMCPU
*cpu
= env_archcpu(env
);
5821 uint64_t pfr1
= cpu
->id_pfr1
;
5823 if (env
->gicv3state
) {
5829 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5831 ARMCPU
*cpu
= env_archcpu(env
);
5832 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
5834 if (env
->gicv3state
) {
5840 /* Shared logic between LORID and the rest of the LOR* registers.
5841 * Secure state has already been delt with.
5843 static CPAccessResult
access_lor_ns(CPUARMState
*env
)
5845 int el
= arm_current_el(env
);
5847 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
5848 return CP_ACCESS_TRAP_EL2
;
5850 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
5851 return CP_ACCESS_TRAP_EL3
;
5853 return CP_ACCESS_OK
;
5856 static CPAccessResult
access_lorid(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5859 if (arm_is_secure_below_el3(env
)) {
5860 /* Access ok in secure mode. */
5861 return CP_ACCESS_OK
;
5863 return access_lor_ns(env
);
5866 static CPAccessResult
access_lor_other(CPUARMState
*env
,
5867 const ARMCPRegInfo
*ri
, bool isread
)
5869 if (arm_is_secure_below_el3(env
)) {
5870 /* Access denied in secure mode. */
5871 return CP_ACCESS_TRAP
;
5873 return access_lor_ns(env
);
5876 #ifdef TARGET_AARCH64
5877 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5880 int el
= arm_current_el(env
);
5883 arm_feature(env
, ARM_FEATURE_EL2
) &&
5884 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
5885 return CP_ACCESS_TRAP_EL2
;
5888 arm_feature(env
, ARM_FEATURE_EL3
) &&
5889 !(env
->cp15
.scr_el3
& SCR_APK
)) {
5890 return CP_ACCESS_TRAP_EL3
;
5892 return CP_ACCESS_OK
;
5895 static const ARMCPRegInfo pauth_reginfo
[] = {
5896 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5897 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
5898 .access
= PL1_RW
, .accessfn
= access_pauth
,
5899 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
5900 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5901 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
5902 .access
= PL1_RW
, .accessfn
= access_pauth
,
5903 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
5904 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5905 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
5906 .access
= PL1_RW
, .accessfn
= access_pauth
,
5907 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
5908 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5909 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
5910 .access
= PL1_RW
, .accessfn
= access_pauth
,
5911 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
5912 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5913 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
5914 .access
= PL1_RW
, .accessfn
= access_pauth
,
5915 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
5916 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5917 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
5918 .access
= PL1_RW
, .accessfn
= access_pauth
,
5919 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
5920 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5921 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
5922 .access
= PL1_RW
, .accessfn
= access_pauth
,
5923 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
5924 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5925 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
5926 .access
= PL1_RW
, .accessfn
= access_pauth
,
5927 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
5928 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
5929 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
5930 .access
= PL1_RW
, .accessfn
= access_pauth
,
5931 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
5932 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
5933 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
5934 .access
= PL1_RW
, .accessfn
= access_pauth
,
5935 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
5939 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5944 /* Success sets NZCV = 0000. */
5945 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
5947 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
5949 * ??? Failed, for unknown reasons in the crypto subsystem.
5950 * The best we can do is log the reason and return the
5951 * timed-out indication to the guest. There is no reason
5952 * we know to expect this failure to be transitory, so the
5953 * guest may well hang retrying the operation.
5955 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
5956 ri
->name
, error_get_pretty(err
));
5959 env
->ZF
= 0; /* NZCF = 0100 */
5965 /* We do not support re-seeding, so the two registers operate the same. */
5966 static const ARMCPRegInfo rndr_reginfo
[] = {
5967 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
5968 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
5969 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
5970 .access
= PL0_R
, .readfn
= rndr_readfn
},
5971 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
5972 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
5973 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
5974 .access
= PL0_R
, .readfn
= rndr_readfn
},
5979 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5982 int el
= arm_current_el(env
);
5985 uint64_t sctlr
= arm_sctlr(env
, el
);
5986 if (!(sctlr
& SCTLR_EnRCTX
)) {
5987 return CP_ACCESS_TRAP
;
5989 } else if (el
== 1) {
5990 uint64_t hcr
= arm_hcr_el2_eff(env
);
5992 return CP_ACCESS_TRAP_EL2
;
5995 return CP_ACCESS_OK
;
5998 static const ARMCPRegInfo predinv_reginfo
[] = {
5999 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
6000 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
6001 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6002 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
6003 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
6004 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6005 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
6006 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
6007 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6009 * Note the AArch32 opcodes have a different OPC1.
6011 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
6012 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
6013 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6014 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
6015 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
6016 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6017 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
6018 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
6019 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
6023 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6026 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
6027 return CP_ACCESS_TRAP_EL2
;
6030 return CP_ACCESS_OK
;
6033 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6036 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6037 return access_aa64_tid3(env
, ri
, isread
);
6040 return CP_ACCESS_OK
;
6043 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6046 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
6047 return CP_ACCESS_TRAP_EL2
;
6050 return CP_ACCESS_OK
;
6053 static const ARMCPRegInfo jazelle_regs
[] = {
6055 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
6056 .access
= PL1_R
, .accessfn
= access_jazelle
,
6057 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6059 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
6060 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6062 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
6063 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6067 void register_cp_regs_for_features(ARMCPU
*cpu
)
6069 /* Register all the coprocessor registers based on feature bits */
6070 CPUARMState
*env
= &cpu
->env
;
6071 if (arm_feature(env
, ARM_FEATURE_M
)) {
6072 /* M profile has no coprocessor registers */
6076 define_arm_cp_regs(cpu
, cp_reginfo
);
6077 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
6078 /* Must go early as it is full of wildcards that may be
6079 * overridden by later definitions.
6081 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
6084 if (arm_feature(env
, ARM_FEATURE_V6
)) {
6085 /* The ID registers all have impdef reset values */
6086 ARMCPRegInfo v6_idregs
[] = {
6087 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
6088 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6089 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6090 .accessfn
= access_aa32_tid3
,
6091 .resetvalue
= cpu
->id_pfr0
},
6092 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
6093 * the value of the GIC field until after we define these regs.
6095 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
6096 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
6097 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
6098 .accessfn
= access_aa32_tid3
,
6099 .readfn
= id_pfr1_read
,
6100 .writefn
= arm_cp_write_ignore
},
6101 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
6102 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
6103 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6104 .accessfn
= access_aa32_tid3
,
6105 .resetvalue
= cpu
->id_dfr0
},
6106 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
6107 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
6108 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6109 .accessfn
= access_aa32_tid3
,
6110 .resetvalue
= cpu
->id_afr0
},
6111 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
6112 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
6113 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6114 .accessfn
= access_aa32_tid3
,
6115 .resetvalue
= cpu
->id_mmfr0
},
6116 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
6117 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
6118 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6119 .accessfn
= access_aa32_tid3
,
6120 .resetvalue
= cpu
->id_mmfr1
},
6121 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
6122 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
6123 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6124 .accessfn
= access_aa32_tid3
,
6125 .resetvalue
= cpu
->id_mmfr2
},
6126 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
6127 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
6128 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6129 .accessfn
= access_aa32_tid3
,
6130 .resetvalue
= cpu
->id_mmfr3
},
6131 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
6132 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6133 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6134 .accessfn
= access_aa32_tid3
,
6135 .resetvalue
= cpu
->isar
.id_isar0
},
6136 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
6137 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
6138 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6139 .accessfn
= access_aa32_tid3
,
6140 .resetvalue
= cpu
->isar
.id_isar1
},
6141 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
6142 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6143 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6144 .accessfn
= access_aa32_tid3
,
6145 .resetvalue
= cpu
->isar
.id_isar2
},
6146 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
6147 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
6148 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6149 .accessfn
= access_aa32_tid3
,
6150 .resetvalue
= cpu
->isar
.id_isar3
},
6151 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
6152 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
6153 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6154 .accessfn
= access_aa32_tid3
,
6155 .resetvalue
= cpu
->isar
.id_isar4
},
6156 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
6157 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
6158 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6159 .accessfn
= access_aa32_tid3
,
6160 .resetvalue
= cpu
->isar
.id_isar5
},
6161 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
6162 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
6163 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6164 .accessfn
= access_aa32_tid3
,
6165 .resetvalue
= cpu
->id_mmfr4
},
6166 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
6167 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
6168 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6169 .accessfn
= access_aa32_tid3
,
6170 .resetvalue
= cpu
->isar
.id_isar6
},
6173 define_arm_cp_regs(cpu
, v6_idregs
);
6174 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
6176 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
6178 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
6179 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
6181 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
6182 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
6183 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
6185 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
6186 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
6188 if (arm_feature(env
, ARM_FEATURE_V7
)) {
6189 /* v7 performance monitor control register: same implementor
6190 * field as main ID register, and we implement four counters in
6191 * addition to the cycle count register.
6193 unsigned int i
, pmcrn
= 4;
6194 ARMCPRegInfo pmcr
= {
6195 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6197 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6198 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6199 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6200 .raw_writefn
= raw_write
,
6202 ARMCPRegInfo pmcr64
= {
6203 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6204 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6205 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6207 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6208 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
),
6209 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6211 define_one_arm_cp_reg(cpu
, &pmcr
);
6212 define_one_arm_cp_reg(cpu
, &pmcr64
);
6213 for (i
= 0; i
< pmcrn
; i
++) {
6214 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6215 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6216 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6217 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6218 ARMCPRegInfo pmev_regs
[] = {
6219 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6220 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6221 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6222 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6223 .accessfn
= pmreg_access
},
6224 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6225 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6226 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6228 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6229 .raw_readfn
= pmevcntr_rawread
,
6230 .raw_writefn
= pmevcntr_rawwrite
},
6231 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6232 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6233 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6234 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6235 .accessfn
= pmreg_access
},
6236 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6237 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6238 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6240 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6241 .raw_writefn
= pmevtyper_rawwrite
},
6244 define_arm_cp_regs(cpu
, pmev_regs
);
6245 g_free(pmevcntr_name
);
6246 g_free(pmevcntr_el0_name
);
6247 g_free(pmevtyper_name
);
6248 g_free(pmevtyper_el0_name
);
6250 ARMCPRegInfo clidr
= {
6251 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
6252 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
6253 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6254 .accessfn
= access_aa64_tid2
,
6255 .resetvalue
= cpu
->clidr
6257 define_one_arm_cp_reg(cpu
, &clidr
);
6258 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
6259 define_debug_regs(cpu
);
6261 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
6263 if (FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) >= 4 &&
6264 FIELD_EX32(cpu
->id_dfr0
, ID_DFR0
, PERFMON
) != 0xf) {
6265 ARMCPRegInfo v81_pmu_regs
[] = {
6266 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6267 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6268 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6269 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6270 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6271 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6272 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6273 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6276 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6278 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6279 /* AArch64 ID registers, which all have impdef reset values.
6280 * Note that within the ID register ranges the unused slots
6281 * must all RAZ, not UNDEF; future architecture versions may
6282 * define new registers here.
6284 ARMCPRegInfo v8_idregs
[] = {
6285 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
6286 * know the right value for the GIC field until after we
6287 * define these regs.
6289 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6290 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
6291 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
6292 .accessfn
= access_aa64_tid3
,
6293 .readfn
= id_aa64pfr0_read
,
6294 .writefn
= arm_cp_write_ignore
},
6295 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6296 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
6297 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6298 .accessfn
= access_aa64_tid3
,
6299 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
6300 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6301 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
6302 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6303 .accessfn
= access_aa64_tid3
,
6305 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6306 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
6307 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6308 .accessfn
= access_aa64_tid3
,
6310 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6311 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
6312 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6313 .accessfn
= access_aa64_tid3
,
6314 /* At present, only SVEver == 0 is defined anyway. */
6316 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6317 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
6318 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6319 .accessfn
= access_aa64_tid3
,
6321 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6322 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
6323 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6324 .accessfn
= access_aa64_tid3
,
6326 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6327 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
6328 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6329 .accessfn
= access_aa64_tid3
,
6331 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6332 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
6333 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6334 .accessfn
= access_aa64_tid3
,
6335 .resetvalue
= cpu
->id_aa64dfr0
},
6336 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6337 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
6338 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6339 .accessfn
= access_aa64_tid3
,
6340 .resetvalue
= cpu
->id_aa64dfr1
},
6341 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6342 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
6343 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6344 .accessfn
= access_aa64_tid3
,
6346 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6347 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
6348 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6349 .accessfn
= access_aa64_tid3
,
6351 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6352 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
6353 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6354 .accessfn
= access_aa64_tid3
,
6355 .resetvalue
= cpu
->id_aa64afr0
},
6356 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6357 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
6358 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6359 .accessfn
= access_aa64_tid3
,
6360 .resetvalue
= cpu
->id_aa64afr1
},
6361 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6362 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
6363 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6364 .accessfn
= access_aa64_tid3
,
6366 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6367 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
6368 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6369 .accessfn
= access_aa64_tid3
,
6371 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
6372 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
6373 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6374 .accessfn
= access_aa64_tid3
,
6375 .resetvalue
= cpu
->isar
.id_aa64isar0
},
6376 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
6377 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
6378 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6379 .accessfn
= access_aa64_tid3
,
6380 .resetvalue
= cpu
->isar
.id_aa64isar1
},
6381 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6382 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
6383 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6384 .accessfn
= access_aa64_tid3
,
6386 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6387 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
6388 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6389 .accessfn
= access_aa64_tid3
,
6391 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6392 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
6393 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6394 .accessfn
= access_aa64_tid3
,
6396 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6397 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
6398 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6399 .accessfn
= access_aa64_tid3
,
6401 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6402 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
6403 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6404 .accessfn
= access_aa64_tid3
,
6406 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6407 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
6408 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6409 .accessfn
= access_aa64_tid3
,
6411 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6412 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6413 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6414 .accessfn
= access_aa64_tid3
,
6415 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
6416 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6417 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
6418 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6419 .accessfn
= access_aa64_tid3
,
6420 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
6421 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6422 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
6423 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6424 .accessfn
= access_aa64_tid3
,
6426 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6427 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
6428 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6429 .accessfn
= access_aa64_tid3
,
6431 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6432 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
6433 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6434 .accessfn
= access_aa64_tid3
,
6436 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6437 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
6438 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6439 .accessfn
= access_aa64_tid3
,
6441 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6442 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
6443 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6444 .accessfn
= access_aa64_tid3
,
6446 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6447 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
6448 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6449 .accessfn
= access_aa64_tid3
,
6451 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
6452 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
6453 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6454 .accessfn
= access_aa64_tid3
,
6455 .resetvalue
= cpu
->isar
.mvfr0
},
6456 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
6457 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
6458 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6459 .accessfn
= access_aa64_tid3
,
6460 .resetvalue
= cpu
->isar
.mvfr1
},
6461 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
6462 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
6463 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6464 .accessfn
= access_aa64_tid3
,
6465 .resetvalue
= cpu
->isar
.mvfr2
},
6466 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6467 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
6468 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6469 .accessfn
= access_aa64_tid3
,
6471 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6472 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
6473 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6474 .accessfn
= access_aa64_tid3
,
6476 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6477 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
6478 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6479 .accessfn
= access_aa64_tid3
,
6481 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6482 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
6483 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6484 .accessfn
= access_aa64_tid3
,
6486 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
6487 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
6488 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6489 .accessfn
= access_aa64_tid3
,
6491 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
6492 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
6493 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6494 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
6495 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
6496 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
6497 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6498 .resetvalue
= cpu
->pmceid0
},
6499 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
6500 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
6501 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6502 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
6503 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
6504 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
6505 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6506 .resetvalue
= cpu
->pmceid1
},
6509 #ifdef CONFIG_USER_ONLY
6510 ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
6511 { .name
= "ID_AA64PFR0_EL1",
6512 .exported_bits
= 0x000f000f00ff0000,
6513 .fixed_bits
= 0x0000000000000011 },
6514 { .name
= "ID_AA64PFR1_EL1",
6515 .exported_bits
= 0x00000000000000f0 },
6516 { .name
= "ID_AA64PFR*_EL1_RESERVED",
6518 { .name
= "ID_AA64ZFR0_EL1" },
6519 { .name
= "ID_AA64MMFR0_EL1",
6520 .fixed_bits
= 0x00000000ff000000 },
6521 { .name
= "ID_AA64MMFR1_EL1" },
6522 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
6524 { .name
= "ID_AA64DFR0_EL1",
6525 .fixed_bits
= 0x0000000000000006 },
6526 { .name
= "ID_AA64DFR1_EL1" },
6527 { .name
= "ID_AA64DFR*_EL1_RESERVED",
6529 { .name
= "ID_AA64AFR*",
6531 { .name
= "ID_AA64ISAR0_EL1",
6532 .exported_bits
= 0x00fffffff0fffff0 },
6533 { .name
= "ID_AA64ISAR1_EL1",
6534 .exported_bits
= 0x000000f0ffffffff },
6535 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
6537 REGUSERINFO_SENTINEL
6539 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
6541 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
6542 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
6543 !arm_feature(env
, ARM_FEATURE_EL2
)) {
6544 ARMCPRegInfo rvbar
= {
6545 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
6546 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6547 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
6549 define_one_arm_cp_reg(cpu
, &rvbar
);
6551 define_arm_cp_regs(cpu
, v8_idregs
);
6552 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
6554 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
6555 uint64_t vmpidr_def
= mpidr_read_val(env
);
6556 ARMCPRegInfo vpidr_regs
[] = {
6557 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
6558 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6559 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6560 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
6561 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
6562 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6563 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6564 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
6565 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
6566 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
6567 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6568 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6569 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
6570 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
6571 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
6572 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6574 .resetvalue
= vmpidr_def
,
6575 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
6578 define_arm_cp_regs(cpu
, vpidr_regs
);
6579 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
6580 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6581 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
6583 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
6584 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
6585 ARMCPRegInfo rvbar
= {
6586 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
6587 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
6588 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
6590 define_one_arm_cp_reg(cpu
, &rvbar
);
6593 /* If EL2 is missing but higher ELs are enabled, we need to
6594 * register the no_el2 reginfos.
6596 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6597 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
6598 * of MIDR_EL1 and MPIDR_EL1.
6600 ARMCPRegInfo vpidr_regs
[] = {
6601 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6602 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
6603 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
6604 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
6605 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
6606 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6607 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
6608 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
6609 .type
= ARM_CP_NO_RAW
,
6610 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
6613 define_arm_cp_regs(cpu
, vpidr_regs
);
6614 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
6615 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6616 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
6620 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6621 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
6622 ARMCPRegInfo el3_regs
[] = {
6623 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6624 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
6625 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
6626 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
6627 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
6629 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6630 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
6631 .resetvalue
= cpu
->reset_sctlr
},
6635 define_arm_cp_regs(cpu
, el3_regs
);
6637 /* The behaviour of NSACR is sufficiently various that we don't
6638 * try to describe it in a single reginfo:
6639 * if EL3 is 64 bit, then trap to EL3 from S EL1,
6640 * reads as constant 0xc00 from NS EL1 and NS EL2
6641 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
6642 * if v7 without EL3, register doesn't exist
6643 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
6645 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6646 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6647 ARMCPRegInfo nsacr
= {
6648 .name
= "NSACR", .type
= ARM_CP_CONST
,
6649 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6650 .access
= PL1_RW
, .accessfn
= nsacr_access
,
6653 define_one_arm_cp_reg(cpu
, &nsacr
);
6655 ARMCPRegInfo nsacr
= {
6657 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6658 .access
= PL3_RW
| PL1_R
,
6660 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
6662 define_one_arm_cp_reg(cpu
, &nsacr
);
6665 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6666 ARMCPRegInfo nsacr
= {
6667 .name
= "NSACR", .type
= ARM_CP_CONST
,
6668 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
6672 define_one_arm_cp_reg(cpu
, &nsacr
);
6676 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
6677 if (arm_feature(env
, ARM_FEATURE_V6
)) {
6678 /* PMSAv6 not implemented */
6679 assert(arm_feature(env
, ARM_FEATURE_V7
));
6680 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
6681 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
6683 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
6686 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
6687 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
6688 /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
6689 if (FIELD_EX32(cpu
->id_mmfr4
, ID_MMFR4
, HPDS
) != 0) {
6690 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
6693 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
6694 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
6696 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
6697 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
6699 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
6700 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
6702 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
6703 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
6705 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
6706 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
6708 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
6709 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
6711 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
6712 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
6714 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
6715 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
6717 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6718 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
6720 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
6721 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
6723 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
6724 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
6726 if (cpu_isar_feature(jazelle
, cpu
)) {
6727 define_arm_cp_regs(cpu
, jazelle_regs
);
6729 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
6730 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
6731 * be read-only (ie write causes UNDEF exception).
6734 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
6735 /* Pre-v8 MIDR space.
6736 * Note that the MIDR isn't a simple constant register because
6737 * of the TI925 behaviour where writes to another register can
6738 * cause the MIDR value to change.
6740 * Unimplemented registers in the c15 0 0 0 space default to
6741 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
6742 * and friends override accordingly.
6745 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
6746 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
6747 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
6748 .readfn
= midr_read
,
6749 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
6750 .type
= ARM_CP_OVERRIDE
},
6751 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
6753 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
6754 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6756 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
6757 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6759 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
6760 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6762 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
6763 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6765 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
6766 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6769 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
6770 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6771 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
6772 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
6773 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
6774 .readfn
= midr_read
},
6775 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
6776 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
6777 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
6778 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
6779 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
6780 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
6781 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
6782 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6783 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
6785 .accessfn
= access_aa64_tid1
,
6786 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
6789 ARMCPRegInfo id_cp_reginfo
[] = {
6790 /* These are common to v8 and pre-v8 */
6792 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
6793 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
6794 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
6795 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
6796 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
6797 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
6798 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
6799 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
6801 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
6803 .accessfn
= access_aa32_tid1
,
6804 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6807 /* TLBTR is specific to VMSA */
6808 ARMCPRegInfo id_tlbtr_reginfo
= {
6810 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
6812 .accessfn
= access_aa32_tid1
,
6813 .type
= ARM_CP_CONST
, .resetvalue
= 0,
6815 /* MPUIR is specific to PMSA V6+ */
6816 ARMCPRegInfo id_mpuir_reginfo
= {
6818 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
6819 .access
= PL1_R
, .type
= ARM_CP_CONST
,
6820 .resetvalue
= cpu
->pmsav7_dregion
<< 8
6822 ARMCPRegInfo crn0_wi_reginfo
= {
6823 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
6824 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
6825 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
6827 #ifdef CONFIG_USER_ONLY
6828 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
6829 { .name
= "MIDR_EL1",
6830 .exported_bits
= 0x00000000ffffffff },
6831 { .name
= "REVIDR_EL1" },
6832 REGUSERINFO_SENTINEL
6834 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
6836 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
6837 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
6839 /* Register the blanket "writes ignored" value first to cover the
6840 * whole space. Then update the specific ID registers to allow write
6841 * access, so that they ignore writes rather than causing them to
6844 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
6845 for (r
= id_pre_v8_midr_cp_reginfo
;
6846 r
->type
!= ARM_CP_SENTINEL
; r
++) {
6849 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
6852 id_mpuir_reginfo
.access
= PL1_RW
;
6853 id_tlbtr_reginfo
.access
= PL1_RW
;
6855 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6856 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
6858 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
6860 define_arm_cp_regs(cpu
, id_cp_reginfo
);
6861 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
6862 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
6863 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
6864 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
6868 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
6869 ARMCPRegInfo mpidr_cp_reginfo
[] = {
6870 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6871 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
6872 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
6875 #ifdef CONFIG_USER_ONLY
6876 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
6877 { .name
= "MPIDR_EL1",
6878 .fixed_bits
= 0x0000000080000000 },
6879 REGUSERINFO_SENTINEL
6881 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
6883 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
6886 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
6887 ARMCPRegInfo auxcr_reginfo
[] = {
6888 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6889 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
6890 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
6891 .resetvalue
= cpu
->reset_auxcr
},
6892 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6893 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
6894 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6896 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
6897 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
6898 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6902 define_arm_cp_regs(cpu
, auxcr_reginfo
);
6903 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6904 /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
6905 ARMCPRegInfo hactlr2_reginfo
= {
6906 .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
6907 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
6908 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6911 define_one_arm_cp_reg(cpu
, &hactlr2_reginfo
);
6915 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
6917 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
6918 * There are two flavours:
6919 * (1) older 32-bit only cores have a simple 32-bit CBAR
6920 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
6921 * 32-bit register visible to AArch32 at a different encoding
6922 * to the "flavour 1" register and with the bits rearranged to
6923 * be able to squash a 64-bit address into the 32-bit view.
6924 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
6925 * in future if we support AArch32-only configs of some of the
6926 * AArch64 cores we might need to add a specific feature flag
6927 * to indicate cores with "flavour 2" CBAR.
6929 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
6930 /* 32 bit view is [31:18] 0...0 [43:32]. */
6931 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
6932 | extract64(cpu
->reset_cbar
, 32, 12);
6933 ARMCPRegInfo cbar_reginfo
[] = {
6935 .type
= ARM_CP_CONST
,
6936 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
6937 .access
= PL1_R
, .resetvalue
= cbar32
},
6938 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
6939 .type
= ARM_CP_CONST
,
6940 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
6941 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
6944 /* We don't implement a r/w 64 bit CBAR currently */
6945 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
6946 define_arm_cp_regs(cpu
, cbar_reginfo
);
6948 ARMCPRegInfo cbar
= {
6950 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
6951 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
6952 .fieldoffset
= offsetof(CPUARMState
,
6953 cp15
.c15_config_base_address
)
6955 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
6956 cbar
.access
= PL1_R
;
6957 cbar
.fieldoffset
= 0;
6958 cbar
.type
= ARM_CP_CONST
;
6960 define_one_arm_cp_reg(cpu
, &cbar
);
6964 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
6965 ARMCPRegInfo vbar_cp_reginfo
[] = {
6966 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
6967 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
6968 .access
= PL1_RW
, .writefn
= vbar_write
,
6969 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
6970 offsetof(CPUARMState
, cp15
.vbar_ns
) },
6974 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
6977 /* Generic registers whose values depend on the implementation */
6979 ARMCPRegInfo sctlr
= {
6980 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
6981 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6983 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
6984 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
6985 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
6986 .raw_writefn
= raw_write
,
6988 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6989 /* Normally we would always end the TB on an SCTLR write, but Linux
6990 * arch/arm/mach-pxa/sleep.S expects two instructions following
6991 * an MMU enable to execute from cache. Imitate this behaviour.
6993 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
6995 define_one_arm_cp_reg(cpu
, &sctlr
);
6998 if (cpu_isar_feature(aa64_lor
, cpu
)) {
7000 * A trivial implementation of ARMv8.1-LOR leaves all of these
7001 * registers fixed at 0, which indicates that there are zero
7002 * supported Limited Ordering regions.
7004 static const ARMCPRegInfo lor_reginfo
[] = {
7005 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7006 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7007 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7008 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7009 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7010 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7011 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7012 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7013 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7014 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7015 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7016 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7017 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7018 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7019 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7020 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7021 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7022 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7023 .access
= PL1_R
, .accessfn
= access_lorid
,
7024 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7027 define_arm_cp_regs(cpu
, lor_reginfo
);
7030 if (cpu_isar_feature(aa64_sve
, cpu
)) {
7031 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
7032 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
7033 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
7035 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
7037 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7038 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
7042 #ifdef TARGET_AARCH64
7043 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
7044 define_arm_cp_regs(cpu
, pauth_reginfo
);
7046 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
7047 define_arm_cp_regs(cpu
, rndr_reginfo
);
7052 * While all v8.0 cpus support aarch64, QEMU does have configurations
7053 * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max,
7054 * which will set ID_ISAR6.
7056 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
7057 ? cpu_isar_feature(aa64_predinv
, cpu
)
7058 : cpu_isar_feature(aa32_predinv
, cpu
)) {
7059 define_arm_cp_regs(cpu
, predinv_reginfo
);
7063 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
7065 CPUState
*cs
= CPU(cpu
);
7066 CPUARMState
*env
= &cpu
->env
;
7068 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7069 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
7070 aarch64_fpu_gdb_set_reg
,
7071 34, "aarch64-fpu.xml", 0);
7072 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
7073 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7074 51, "arm-neon.xml", 0);
7075 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
7076 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7077 35, "arm-vfp3.xml", 0);
7078 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
7079 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
7080 19, "arm-vfp.xml", 0);
7082 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
7083 arm_gen_dynamic_xml(cs
),
7084 "system-registers.xml", 0);
7087 /* Sort alphabetically by type name, except for "any". */
7088 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
7090 ObjectClass
*class_a
= (ObjectClass
*)a
;
7091 ObjectClass
*class_b
= (ObjectClass
*)b
;
7092 const char *name_a
, *name_b
;
7094 name_a
= object_class_get_name(class_a
);
7095 name_b
= object_class_get_name(class_b
);
7096 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
7098 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
7101 return strcmp(name_a
, name_b
);
7105 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
7107 ObjectClass
*oc
= data
;
7108 const char *typename
;
7111 typename
= object_class_get_name(oc
);
7112 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
7113 qemu_printf(" %s\n", name
);
7117 void arm_cpu_list(void)
7121 list
= object_class_get_list(TYPE_ARM_CPU
, false);
7122 list
= g_slist_sort(list
, arm_cpu_list_compare
);
7123 qemu_printf("Available CPUs:\n");
7124 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
7128 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
7130 ObjectClass
*oc
= data
;
7131 CpuDefinitionInfoList
**cpu_list
= user_data
;
7132 CpuDefinitionInfoList
*entry
;
7133 CpuDefinitionInfo
*info
;
7134 const char *typename
;
7136 typename
= object_class_get_name(oc
);
7137 info
= g_malloc0(sizeof(*info
));
7138 info
->name
= g_strndup(typename
,
7139 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
7140 info
->q_typename
= g_strdup(typename
);
7142 entry
= g_malloc0(sizeof(*entry
));
7143 entry
->value
= info
;
7144 entry
->next
= *cpu_list
;
7148 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
7150 CpuDefinitionInfoList
*cpu_list
= NULL
;
7153 list
= object_class_get_list(TYPE_ARM_CPU
, false);
7154 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
7160 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
7161 void *opaque
, int state
, int secstate
,
7162 int crm
, int opc1
, int opc2
,
7165 /* Private utility function for define_one_arm_cp_reg_with_opaque():
7166 * add a single reginfo struct to the hash table.
7168 uint32_t *key
= g_new(uint32_t, 1);
7169 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
7170 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
7171 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
7173 r2
->name
= g_strdup(name
);
7174 /* Reset the secure state to the specific incoming state. This is
7175 * necessary as the register may have been defined with both states.
7177 r2
->secure
= secstate
;
7179 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
7180 /* Register is banked (using both entries in array).
7181 * Overwriting fieldoffset as the array is only used to define
7182 * banked registers but later only fieldoffset is used.
7184 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
7187 if (state
== ARM_CP_STATE_AA32
) {
7188 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
7189 /* If the register is banked then we don't need to migrate or
7190 * reset the 32-bit instance in certain cases:
7192 * 1) If the register has both 32-bit and 64-bit instances then we
7193 * can count on the 64-bit instance taking care of the
7195 * 2) If ARMv8 is enabled then we can count on a 64-bit version
7196 * taking care of the secure bank. This requires that separate
7197 * 32 and 64-bit definitions are provided.
7199 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
7200 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
7201 r2
->type
|= ARM_CP_ALIAS
;
7203 } else if ((secstate
!= r
->secure
) && !ns
) {
7204 /* The register is not banked so we only want to allow migration of
7205 * the non-secure instance.
7207 r2
->type
|= ARM_CP_ALIAS
;
7210 if (r
->state
== ARM_CP_STATE_BOTH
) {
7211 /* We assume it is a cp15 register if the .cp field is left unset.
7217 #ifdef HOST_WORDS_BIGENDIAN
7218 if (r2
->fieldoffset
) {
7219 r2
->fieldoffset
+= sizeof(uint32_t);
7224 if (state
== ARM_CP_STATE_AA64
) {
7225 /* To allow abbreviation of ARMCPRegInfo
7226 * definitions, we treat cp == 0 as equivalent to
7227 * the value for "standard guest-visible sysreg".
7228 * STATE_BOTH definitions are also always "standard
7229 * sysreg" in their AArch64 view (the .cp value may
7230 * be non-zero for the benefit of the AArch32 view).
7232 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
7233 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
7235 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
7236 r2
->opc0
, opc1
, opc2
);
7238 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
7241 r2
->opaque
= opaque
;
7243 /* reginfo passed to helpers is correct for the actual access,
7244 * and is never ARM_CP_STATE_BOTH:
7247 /* Make sure reginfo passed to helpers for wildcarded regs
7248 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
7253 /* By convention, for wildcarded registers only the first
7254 * entry is used for migration; the others are marked as
7255 * ALIAS so we don't try to transfer the register
7256 * multiple times. Special registers (ie NOP/WFI) are
7257 * never migratable and not even raw-accessible.
7259 if ((r
->type
& ARM_CP_SPECIAL
)) {
7260 r2
->type
|= ARM_CP_NO_RAW
;
7262 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
7263 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
7264 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
7265 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
7268 /* Check that raw accesses are either forbidden or handled. Note that
7269 * we can't assert this earlier because the setup of fieldoffset for
7270 * banked registers has to be done first.
7272 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
7273 assert(!raw_accessors_invalid(r2
));
7276 /* Overriding of an existing definition must be explicitly
7279 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
7280 ARMCPRegInfo
*oldreg
;
7281 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
7282 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
7283 fprintf(stderr
, "Register redefined: cp=%d %d bit "
7284 "crn=%d crm=%d opc1=%d opc2=%d, "
7285 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
7286 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
7287 oldreg
->name
, r2
->name
);
7288 g_assert_not_reached();
7291 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
7295 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
7296 const ARMCPRegInfo
*r
, void *opaque
)
7298 /* Define implementations of coprocessor registers.
7299 * We store these in a hashtable because typically
7300 * there are less than 150 registers in a space which
7301 * is 16*16*16*8*8 = 262144 in size.
7302 * Wildcarding is supported for the crm, opc1 and opc2 fields.
7303 * If a register is defined twice then the second definition is
7304 * used, so this can be used to define some generic registers and
7305 * then override them with implementation specific variations.
7306 * At least one of the original and the second definition should
7307 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
7308 * against accidental use.
7310 * The state field defines whether the register is to be
7311 * visible in the AArch32 or AArch64 execution state. If the
7312 * state is set to ARM_CP_STATE_BOTH then we synthesise a
7313 * reginfo structure for the AArch32 view, which sees the lower
7314 * 32 bits of the 64 bit register.
7316 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
7317 * be wildcarded. AArch64 registers are always considered to be 64
7318 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
7319 * the register, if any.
7321 int crm
, opc1
, opc2
, state
;
7322 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
7323 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
7324 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
7325 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
7326 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
7327 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
7328 /* 64 bit registers have only CRm and Opc1 fields */
7329 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
7330 /* op0 only exists in the AArch64 encodings */
7331 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
7332 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
7333 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
7334 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
7335 * encodes a minimum access level for the register. We roll this
7336 * runtime check into our general permission check code, so check
7337 * here that the reginfo's specified permissions are strict enough
7338 * to encompass the generic architectural permission check.
7340 if (r
->state
!= ARM_CP_STATE_AA32
) {
7344 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
7345 mask
= PL0U_R
| PL1_RW
;
7360 /* unallocated encoding, so not possible */
7368 /* min_EL EL1, secure mode only (we don't check the latter) */
7372 /* broken reginfo with out-of-range opc1 */
7376 /* assert our permissions are not too lax (stricter is fine) */
7377 assert((r
->access
& ~mask
) == 0);
7380 /* Check that the register definition has enough info to handle
7381 * reads and writes if they are permitted.
7383 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
7384 if (r
->access
& PL3_R
) {
7385 assert((r
->fieldoffset
||
7386 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
7389 if (r
->access
& PL3_W
) {
7390 assert((r
->fieldoffset
||
7391 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
7395 /* Bad type field probably means missing sentinel at end of reg list */
7396 assert(cptype_valid(r
->type
));
7397 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
7398 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
7399 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
7400 for (state
= ARM_CP_STATE_AA32
;
7401 state
<= ARM_CP_STATE_AA64
; state
++) {
7402 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
7405 if (state
== ARM_CP_STATE_AA32
) {
7406 /* Under AArch32 CP registers can be common
7407 * (same for secure and non-secure world) or banked.
7411 switch (r
->secure
) {
7412 case ARM_CP_SECSTATE_S
:
7413 case ARM_CP_SECSTATE_NS
:
7414 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7415 r
->secure
, crm
, opc1
, opc2
,
7419 name
= g_strdup_printf("%s_S", r
->name
);
7420 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7422 crm
, opc1
, opc2
, name
);
7424 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7426 crm
, opc1
, opc2
, r
->name
);
7430 /* AArch64 registers get mapped to non-secure instance
7432 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
7434 crm
, opc1
, opc2
, r
->name
);
7442 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
7443 const ARMCPRegInfo
*regs
, void *opaque
)
7445 /* Define a whole list of registers */
7446 const ARMCPRegInfo
*r
;
7447 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7448 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
7453 * Modify ARMCPRegInfo for access from userspace.
7455 * This is a data driven modification directed by
7456 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
7457 * user-space cannot alter any values and dynamic values pertaining to
7458 * execution state are hidden from user space view anyway.
7460 void modify_arm_cp_regs(ARMCPRegInfo
*regs
, const ARMCPRegUserSpaceInfo
*mods
)
7462 const ARMCPRegUserSpaceInfo
*m
;
7465 for (m
= mods
; m
->name
; m
++) {
7466 GPatternSpec
*pat
= NULL
;
7468 pat
= g_pattern_spec_new(m
->name
);
7470 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
7471 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
7472 r
->type
= ARM_CP_CONST
;
7476 } else if (strcmp(r
->name
, m
->name
) == 0) {
7477 r
->type
= ARM_CP_CONST
;
7479 r
->resetvalue
&= m
->exported_bits
;
7480 r
->resetvalue
|= m
->fixed_bits
;
7485 g_pattern_spec_free(pat
);
7490 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
7492 return g_hash_table_lookup(cpregs
, &encoded_cp
);
7495 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7498 /* Helper coprocessor write function for write-ignore registers */
7501 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7503 /* Helper coprocessor write function for read-as-zero registers */
7507 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
7509 /* Helper coprocessor reset function for do-nothing-on-reset registers */
7512 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
7514 /* Return true if it is not valid for us to switch to
7515 * this CPU mode (ie all the UNPREDICTABLE cases in
7516 * the ARM ARM CPSRWriteByInstr pseudocode).
7519 /* Changes to or from Hyp via MSR and CPS are illegal. */
7520 if (write_type
== CPSRWriteByInstr
&&
7521 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
7522 mode
== ARM_CPU_MODE_HYP
)) {
7527 case ARM_CPU_MODE_USR
:
7529 case ARM_CPU_MODE_SYS
:
7530 case ARM_CPU_MODE_SVC
:
7531 case ARM_CPU_MODE_ABT
:
7532 case ARM_CPU_MODE_UND
:
7533 case ARM_CPU_MODE_IRQ
:
7534 case ARM_CPU_MODE_FIQ
:
7535 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
7536 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
7538 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
7539 * and CPS are treated as illegal mode changes.
7541 if (write_type
== CPSRWriteByInstr
&&
7542 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
7543 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
7547 case ARM_CPU_MODE_HYP
:
7548 return !arm_feature(env
, ARM_FEATURE_EL2
)
7549 || arm_current_el(env
) < 2 || arm_is_secure_below_el3(env
);
7550 case ARM_CPU_MODE_MON
:
7551 return arm_current_el(env
) < 3;
7557 uint32_t cpsr_read(CPUARMState
*env
)
7560 ZF
= (env
->ZF
== 0);
7561 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
7562 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
7563 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
7564 | ((env
->condexec_bits
& 0xfc) << 8)
7565 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
7568 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
7569 CPSRWriteType write_type
)
7571 uint32_t changed_daif
;
7573 if (mask
& CPSR_NZCV
) {
7574 env
->ZF
= (~val
) & CPSR_Z
;
7576 env
->CF
= (val
>> 29) & 1;
7577 env
->VF
= (val
<< 3) & 0x80000000;
7580 env
->QF
= ((val
& CPSR_Q
) != 0);
7582 env
->thumb
= ((val
& CPSR_T
) != 0);
7583 if (mask
& CPSR_IT_0_1
) {
7584 env
->condexec_bits
&= ~3;
7585 env
->condexec_bits
|= (val
>> 25) & 3;
7587 if (mask
& CPSR_IT_2_7
) {
7588 env
->condexec_bits
&= 3;
7589 env
->condexec_bits
|= (val
>> 8) & 0xfc;
7591 if (mask
& CPSR_GE
) {
7592 env
->GE
= (val
>> 16) & 0xf;
7595 /* In a V7 implementation that includes the security extensions but does
7596 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
7597 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
7598 * bits respectively.
7600 * In a V8 implementation, it is permitted for privileged software to
7601 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
7603 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
7604 arm_feature(env
, ARM_FEATURE_EL3
) &&
7605 !arm_feature(env
, ARM_FEATURE_EL2
) &&
7606 !arm_is_secure(env
)) {
7608 changed_daif
= (env
->daif
^ val
) & mask
;
7610 if (changed_daif
& CPSR_A
) {
7611 /* Check to see if we are allowed to change the masking of async
7612 * abort exceptions from a non-secure state.
7614 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
7615 qemu_log_mask(LOG_GUEST_ERROR
,
7616 "Ignoring attempt to switch CPSR_A flag from "
7617 "non-secure world with SCR.AW bit clear\n");
7622 if (changed_daif
& CPSR_F
) {
7623 /* Check to see if we are allowed to change the masking of FIQ
7624 * exceptions from a non-secure state.
7626 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
7627 qemu_log_mask(LOG_GUEST_ERROR
,
7628 "Ignoring attempt to switch CPSR_F flag from "
7629 "non-secure world with SCR.FW bit clear\n");
7633 /* Check whether non-maskable FIQ (NMFI) support is enabled.
7634 * If this bit is set software is not allowed to mask
7635 * FIQs, but is allowed to set CPSR_F to 0.
7637 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
7639 qemu_log_mask(LOG_GUEST_ERROR
,
7640 "Ignoring attempt to enable CPSR_F flag "
7641 "(non-maskable FIQ [NMFI] support enabled)\n");
7647 env
->daif
&= ~(CPSR_AIF
& mask
);
7648 env
->daif
|= val
& CPSR_AIF
& mask
;
7650 if (write_type
!= CPSRWriteRaw
&&
7651 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
7652 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
7653 /* Note that we can only get here in USR mode if this is a
7654 * gdb stub write; for this case we follow the architectural
7655 * behaviour for guest writes in USR mode of ignoring an attempt
7656 * to switch mode. (Those are caught by translate.c for writes
7657 * triggered by guest instructions.)
7660 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
7661 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
7662 * v7, and has defined behaviour in v8:
7663 * + leave CPSR.M untouched
7664 * + allow changes to the other CPSR fields
7666 * For user changes via the GDB stub, we don't set PSTATE.IL,
7667 * as this would be unnecessarily harsh for a user error.
7670 if (write_type
!= CPSRWriteByGDBStub
&&
7671 arm_feature(env
, ARM_FEATURE_V8
)) {
7675 qemu_log_mask(LOG_GUEST_ERROR
,
7676 "Illegal AArch32 mode switch attempt from %s to %s\n",
7677 aarch32_mode_name(env
->uncached_cpsr
),
7678 aarch32_mode_name(val
));
7680 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
7681 write_type
== CPSRWriteExceptionReturn
?
7682 "Exception return from AArch32" :
7683 "AArch32 mode switch from",
7684 aarch32_mode_name(env
->uncached_cpsr
),
7685 aarch32_mode_name(val
), env
->regs
[15]);
7686 switch_mode(env
, val
& CPSR_M
);
7689 mask
&= ~CACHED_CPSR_BITS
;
7690 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
7693 /* Sign/zero extend */
7694 uint32_t HELPER(sxtb16
)(uint32_t x
)
7697 res
= (uint16_t)(int8_t)x
;
7698 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
7702 uint32_t HELPER(uxtb16
)(uint32_t x
)
7705 res
= (uint16_t)(uint8_t)x
;
7706 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
7710 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
7714 if (num
== INT_MIN
&& den
== -1)
7719 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
7726 uint32_t HELPER(rbit
)(uint32_t x
)
7731 #ifdef CONFIG_USER_ONLY
7733 static void switch_mode(CPUARMState
*env
, int mode
)
7735 ARMCPU
*cpu
= env_archcpu(env
);
7737 if (mode
!= ARM_CPU_MODE_USR
) {
7738 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
7742 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
7743 uint32_t cur_el
, bool secure
)
7748 void aarch64_sync_64_to_32(CPUARMState
*env
)
7750 g_assert_not_reached();
7755 static void switch_mode(CPUARMState
*env
, int mode
)
7760 old_mode
= env
->uncached_cpsr
& CPSR_M
;
7761 if (mode
== old_mode
)
7764 if (old_mode
== ARM_CPU_MODE_FIQ
) {
7765 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
7766 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
7767 } else if (mode
== ARM_CPU_MODE_FIQ
) {
7768 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
7769 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
7772 i
= bank_number(old_mode
);
7773 env
->banked_r13
[i
] = env
->regs
[13];
7774 env
->banked_spsr
[i
] = env
->spsr
;
7776 i
= bank_number(mode
);
7777 env
->regs
[13] = env
->banked_r13
[i
];
7778 env
->spsr
= env
->banked_spsr
[i
];
7780 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
7781 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
7784 /* Physical Interrupt Target EL Lookup Table
7786 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
7788 * The below multi-dimensional table is used for looking up the target
7789 * exception level given numerous condition criteria. Specifically, the
7790 * target EL is based on SCR and HCR routing controls as well as the
7791 * currently executing EL and secure state.
7794 * target_el_table[2][2][2][2][2][4]
7795 * | | | | | +--- Current EL
7796 * | | | | +------ Non-secure(0)/Secure(1)
7797 * | | | +--------- HCR mask override
7798 * | | +------------ SCR exec state control
7799 * | +--------------- SCR mask override
7800 * +------------------ 32-bit(0)/64-bit(1) EL3
7802 * The table values are as such:
7806 * The ARM ARM target EL table includes entries indicating that an "exception
7807 * is not taken". The two cases where this is applicable are:
7808 * 1) An exception is taken from EL3 but the SCR does not have the exception
7810 * 2) An exception is taken from EL2 but the HCR does not have the exception
7812 * In these two cases, the below table contain a target of EL1. This value is
7813 * returned as it is expected that the consumer of the table data will check
7814 * for "target EL >= current EL" to ensure the exception is not taken.
7818 * BIT IRQ IMO Non-secure Secure
7819 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
7821 static const int8_t target_el_table
[2][2][2][2][2][4] = {
7822 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
7823 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
7824 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
7825 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
7826 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
7827 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
7828 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
7829 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
7830 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
7831 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
7832 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
7833 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
7834 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
7835 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
7836 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
7837 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
7841 * Determine the target EL for physical exceptions
7843 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
7844 uint32_t cur_el
, bool secure
)
7846 CPUARMState
*env
= cs
->env_ptr
;
7851 /* Is the highest EL AArch64? */
7852 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
7855 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7856 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
7858 /* Either EL2 is the highest EL (and so the EL2 register width
7859 * is given by is64); or there is no EL2 or EL3, in which case
7860 * the value of 'rw' does not affect the table lookup anyway.
7865 hcr_el2
= arm_hcr_el2_eff(env
);
7868 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
7869 hcr
= hcr_el2
& HCR_IMO
;
7872 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
7873 hcr
= hcr_el2
& HCR_FMO
;
7876 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
7877 hcr
= hcr_el2
& HCR_AMO
;
7881 /* Perform a table-lookup for the target EL given the current state */
7882 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
7884 assert(target_el
> 0);
7889 void arm_log_exception(int idx
)
7891 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
7892 const char *exc
= NULL
;
7893 static const char * const excnames
[] = {
7894 [EXCP_UDEF
] = "Undefined Instruction",
7896 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
7897 [EXCP_DATA_ABORT
] = "Data Abort",
7900 [EXCP_BKPT
] = "Breakpoint",
7901 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
7902 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
7903 [EXCP_HVC
] = "Hypervisor Call",
7904 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
7905 [EXCP_SMC
] = "Secure Monitor Call",
7906 [EXCP_VIRQ
] = "Virtual IRQ",
7907 [EXCP_VFIQ
] = "Virtual FIQ",
7908 [EXCP_SEMIHOST
] = "Semihosting call",
7909 [EXCP_NOCP
] = "v7M NOCP UsageFault",
7910 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
7911 [EXCP_STKOF
] = "v8M STKOF UsageFault",
7912 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
7913 [EXCP_LSERR
] = "v8M LSERR UsageFault",
7914 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
7917 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
7918 exc
= excnames
[idx
];
7923 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
7928 * Function used to synchronize QEMU's AArch64 register set with AArch32
7929 * register set. This is necessary when switching between AArch32 and AArch64
7932 void aarch64_sync_32_to_64(CPUARMState
*env
)
7935 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7937 /* We can blanket copy R[0:7] to X[0:7] */
7938 for (i
= 0; i
< 8; i
++) {
7939 env
->xregs
[i
] = env
->regs
[i
];
7943 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
7944 * Otherwise, they come from the banked user regs.
7946 if (mode
== ARM_CPU_MODE_FIQ
) {
7947 for (i
= 8; i
< 13; i
++) {
7948 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
7951 for (i
= 8; i
< 13; i
++) {
7952 env
->xregs
[i
] = env
->regs
[i
];
7957 * Registers x13-x23 are the various mode SP and FP registers. Registers
7958 * r13 and r14 are only copied if we are in that mode, otherwise we copy
7959 * from the mode banked register.
7961 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7962 env
->xregs
[13] = env
->regs
[13];
7963 env
->xregs
[14] = env
->regs
[14];
7965 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
7966 /* HYP is an exception in that it is copied from r14 */
7967 if (mode
== ARM_CPU_MODE_HYP
) {
7968 env
->xregs
[14] = env
->regs
[14];
7970 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
7974 if (mode
== ARM_CPU_MODE_HYP
) {
7975 env
->xregs
[15] = env
->regs
[13];
7977 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
7980 if (mode
== ARM_CPU_MODE_IRQ
) {
7981 env
->xregs
[16] = env
->regs
[14];
7982 env
->xregs
[17] = env
->regs
[13];
7984 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
7985 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
7988 if (mode
== ARM_CPU_MODE_SVC
) {
7989 env
->xregs
[18] = env
->regs
[14];
7990 env
->xregs
[19] = env
->regs
[13];
7992 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
7993 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
7996 if (mode
== ARM_CPU_MODE_ABT
) {
7997 env
->xregs
[20] = env
->regs
[14];
7998 env
->xregs
[21] = env
->regs
[13];
8000 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
8001 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
8004 if (mode
== ARM_CPU_MODE_UND
) {
8005 env
->xregs
[22] = env
->regs
[14];
8006 env
->xregs
[23] = env
->regs
[13];
8008 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
8009 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
8013 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8014 * mode, then we can copy from r8-r14. Otherwise, we copy from the
8015 * FIQ bank for r8-r14.
8017 if (mode
== ARM_CPU_MODE_FIQ
) {
8018 for (i
= 24; i
< 31; i
++) {
8019 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
8022 for (i
= 24; i
< 29; i
++) {
8023 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
8025 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
8026 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
8029 env
->pc
= env
->regs
[15];
8033 * Function used to synchronize QEMU's AArch32 register set with AArch64
8034 * register set. This is necessary when switching between AArch32 and AArch64
8037 void aarch64_sync_64_to_32(CPUARMState
*env
)
8040 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
8042 /* We can blanket copy X[0:7] to R[0:7] */
8043 for (i
= 0; i
< 8; i
++) {
8044 env
->regs
[i
] = env
->xregs
[i
];
8048 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
8049 * Otherwise, we copy x8-x12 into the banked user regs.
8051 if (mode
== ARM_CPU_MODE_FIQ
) {
8052 for (i
= 8; i
< 13; i
++) {
8053 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
8056 for (i
= 8; i
< 13; i
++) {
8057 env
->regs
[i
] = env
->xregs
[i
];
8062 * Registers r13 & r14 depend on the current mode.
8063 * If we are in a given mode, we copy the corresponding x registers to r13
8064 * and r14. Otherwise, we copy the x register to the banked r13 and r14
8067 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
8068 env
->regs
[13] = env
->xregs
[13];
8069 env
->regs
[14] = env
->xregs
[14];
8071 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
8074 * HYP is an exception in that it does not have its own banked r14 but
8075 * shares the USR r14
8077 if (mode
== ARM_CPU_MODE_HYP
) {
8078 env
->regs
[14] = env
->xregs
[14];
8080 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
8084 if (mode
== ARM_CPU_MODE_HYP
) {
8085 env
->regs
[13] = env
->xregs
[15];
8087 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
8090 if (mode
== ARM_CPU_MODE_IRQ
) {
8091 env
->regs
[14] = env
->xregs
[16];
8092 env
->regs
[13] = env
->xregs
[17];
8094 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
8095 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
8098 if (mode
== ARM_CPU_MODE_SVC
) {
8099 env
->regs
[14] = env
->xregs
[18];
8100 env
->regs
[13] = env
->xregs
[19];
8102 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
8103 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
8106 if (mode
== ARM_CPU_MODE_ABT
) {
8107 env
->regs
[14] = env
->xregs
[20];
8108 env
->regs
[13] = env
->xregs
[21];
8110 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
8111 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
8114 if (mode
== ARM_CPU_MODE_UND
) {
8115 env
->regs
[14] = env
->xregs
[22];
8116 env
->regs
[13] = env
->xregs
[23];
8118 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
8119 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
8122 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
8123 * mode, then we can copy to r8-r14. Otherwise, we copy to the
8124 * FIQ bank for r8-r14.
8126 if (mode
== ARM_CPU_MODE_FIQ
) {
8127 for (i
= 24; i
< 31; i
++) {
8128 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
8131 for (i
= 24; i
< 29; i
++) {
8132 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
8134 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
8135 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
8138 env
->regs
[15] = env
->pc
;
8141 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
8142 uint32_t mask
, uint32_t offset
,
8145 /* Change the CPU state so as to actually take the exception. */
8146 switch_mode(env
, new_mode
);
8148 * For exceptions taken to AArch32 we must clear the SS bit in both
8149 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
8151 env
->uncached_cpsr
&= ~PSTATE_SS
;
8152 env
->spsr
= cpsr_read(env
);
8153 /* Clear IT bits. */
8154 env
->condexec_bits
= 0;
8155 /* Switch to the new mode, and to the correct instruction set. */
8156 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
8157 /* Set new mode endianness */
8158 env
->uncached_cpsr
&= ~CPSR_E
;
8159 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
8160 env
->uncached_cpsr
|= CPSR_E
;
8162 /* J and IL must always be cleared for exception entry */
8163 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
8166 if (new_mode
== ARM_CPU_MODE_HYP
) {
8167 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
8168 env
->elr_el
[2] = env
->regs
[15];
8171 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
8172 * and we should just guard the thumb mode on V4
8174 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
8176 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
8178 env
->regs
[14] = env
->regs
[15] + offset
;
8180 env
->regs
[15] = newpc
;
8181 arm_rebuild_hflags(env
);
8184 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
8187 * Handle exception entry to Hyp mode; this is sufficiently
8188 * different to entry to other AArch32 modes that we handle it
8191 * The vector table entry used is always the 0x14 Hyp mode entry point,
8192 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
8193 * The offset applied to the preferred return address is always zero
8194 * (see DDI0487C.a section G1.12.3).
8195 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
8197 uint32_t addr
, mask
;
8198 ARMCPU
*cpu
= ARM_CPU(cs
);
8199 CPUARMState
*env
= &cpu
->env
;
8201 switch (cs
->exception_index
) {
8209 /* Fall through to prefetch abort. */
8210 case EXCP_PREFETCH_ABORT
:
8211 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
8212 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
8213 (uint32_t)env
->exception
.vaddress
);
8216 case EXCP_DATA_ABORT
:
8217 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
8218 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
8219 (uint32_t)env
->exception
.vaddress
);
8235 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8238 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
8239 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8241 * QEMU syndrome values are v8-style. v7 has the IL bit
8242 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
8243 * If this is a v7 CPU, squash the IL bit in those cases.
8245 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
8246 (cs
->exception_index
== EXCP_DATA_ABORT
&&
8247 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
8248 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
8249 env
->exception
.syndrome
&= ~ARM_EL_IL
;
8252 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
8255 if (arm_current_el(env
) != 2 && addr
< 0x14) {
8260 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
8263 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
8266 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
8270 addr
+= env
->cp15
.hvbar
;
8272 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
8275 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
8277 ARMCPU
*cpu
= ARM_CPU(cs
);
8278 CPUARMState
*env
= &cpu
->env
;
8285 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
8286 switch (syn_get_ec(env
->exception
.syndrome
)) {
8288 case EC_BREAKPOINT_SAME_EL
:
8292 case EC_WATCHPOINT_SAME_EL
:
8298 case EC_VECTORCATCH
:
8307 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
8310 if (env
->exception
.target_el
== 2) {
8311 arm_cpu_do_interrupt_aarch32_hyp(cs
);
8315 switch (cs
->exception_index
) {
8317 new_mode
= ARM_CPU_MODE_UND
;
8326 new_mode
= ARM_CPU_MODE_SVC
;
8329 /* The PC already points to the next instruction. */
8333 /* Fall through to prefetch abort. */
8334 case EXCP_PREFETCH_ABORT
:
8335 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
8336 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
8337 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
8338 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
8339 new_mode
= ARM_CPU_MODE_ABT
;
8341 mask
= CPSR_A
| CPSR_I
;
8344 case EXCP_DATA_ABORT
:
8345 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
8346 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
8347 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
8349 (uint32_t)env
->exception
.vaddress
);
8350 new_mode
= ARM_CPU_MODE_ABT
;
8352 mask
= CPSR_A
| CPSR_I
;
8356 new_mode
= ARM_CPU_MODE_IRQ
;
8358 /* Disable IRQ and imprecise data aborts. */
8359 mask
= CPSR_A
| CPSR_I
;
8361 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
8362 /* IRQ routed to monitor mode */
8363 new_mode
= ARM_CPU_MODE_MON
;
8368 new_mode
= ARM_CPU_MODE_FIQ
;
8370 /* Disable FIQ, IRQ and imprecise data aborts. */
8371 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8372 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
8373 /* FIQ routed to monitor mode */
8374 new_mode
= ARM_CPU_MODE_MON
;
8379 new_mode
= ARM_CPU_MODE_IRQ
;
8381 /* Disable IRQ and imprecise data aborts. */
8382 mask
= CPSR_A
| CPSR_I
;
8386 new_mode
= ARM_CPU_MODE_FIQ
;
8388 /* Disable FIQ, IRQ and imprecise data aborts. */
8389 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8393 new_mode
= ARM_CPU_MODE_MON
;
8395 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
8399 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8400 return; /* Never happens. Keep compiler happy. */
8403 if (new_mode
== ARM_CPU_MODE_MON
) {
8404 addr
+= env
->cp15
.mvbar
;
8405 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
8406 /* High vectors. When enabled, base address cannot be remapped. */
8409 /* ARM v7 architectures provide a vector base address register to remap
8410 * the interrupt vector table.
8411 * This register is only followed in non-monitor mode, and is banked.
8412 * Note: only bits 31:5 are valid.
8414 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
8417 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
8418 env
->cp15
.scr_el3
&= ~SCR_NS
;
8421 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
8424 /* Handle exception entry to a target EL which is using AArch64 */
8425 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
8427 ARMCPU
*cpu
= ARM_CPU(cs
);
8428 CPUARMState
*env
= &cpu
->env
;
8429 unsigned int new_el
= env
->exception
.target_el
;
8430 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
8431 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
8432 unsigned int cur_el
= arm_current_el(env
);
8435 * Note that new_el can never be 0. If cur_el is 0, then
8436 * el0_a64 is is_a64(), else el0_a64 is ignored.
8438 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
8440 if (cur_el
< new_el
) {
8441 /* Entry vector offset depends on whether the implemented EL
8442 * immediately lower than the target level is using AArch32 or AArch64
8448 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
8451 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
8454 is_aa64
= is_a64(env
);
8457 g_assert_not_reached();
8465 } else if (pstate_read(env
) & PSTATE_SP
) {
8469 switch (cs
->exception_index
) {
8470 case EXCP_PREFETCH_ABORT
:
8471 case EXCP_DATA_ABORT
:
8472 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
8473 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
8474 env
->cp15
.far_el
[new_el
]);
8482 if (syn_get_ec(env
->exception
.syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
8484 * QEMU internal FP/SIMD syndromes from AArch32 include the
8485 * TA and coproc fields which are only exposed if the exception
8486 * is taken to AArch32 Hyp mode. Mask them out to get a valid
8487 * AArch64 format syndrome.
8489 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
8491 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
8502 qemu_log_mask(CPU_LOG_INT
,
8503 "...handling as semihosting call 0x%" PRIx64
"\n",
8505 env
->xregs
[0] = do_arm_semihosting(env
);
8508 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
8512 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
8513 aarch64_save_sp(env
, arm_current_el(env
));
8514 env
->elr_el
[new_el
] = env
->pc
;
8516 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
8517 env
->elr_el
[new_el
] = env
->regs
[15];
8519 aarch64_sync_32_to_64(env
);
8521 env
->condexec_bits
= 0;
8523 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
8524 env
->elr_el
[new_el
]);
8526 pstate_write(env
, PSTATE_DAIF
| new_mode
);
8528 aarch64_restore_sp(env
, new_el
);
8529 helper_rebuild_hflags_a64(env
, new_el
);
8533 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
8534 new_el
, env
->pc
, pstate_read(env
));
8538 * Do semihosting call and set the appropriate return value. All the
8539 * permission and validity checks have been done at translate time.
8541 * We only see semihosting exceptions in TCG only as they are not
8542 * trapped to the hypervisor in KVM.
8545 static void handle_semihosting(CPUState
*cs
)
8547 ARMCPU
*cpu
= ARM_CPU(cs
);
8548 CPUARMState
*env
= &cpu
->env
;
8551 qemu_log_mask(CPU_LOG_INT
,
8552 "...handling as semihosting call 0x%" PRIx64
"\n",
8554 env
->xregs
[0] = do_arm_semihosting(env
);
8556 qemu_log_mask(CPU_LOG_INT
,
8557 "...handling as semihosting call 0x%x\n",
8559 env
->regs
[0] = do_arm_semihosting(env
);
8564 /* Handle a CPU exception for A and R profile CPUs.
8565 * Do any appropriate logging, handle PSCI calls, and then hand off
8566 * to the AArch64-entry or AArch32-entry function depending on the
8567 * target exception level's register width.
8569 void arm_cpu_do_interrupt(CPUState
*cs
)
8571 ARMCPU
*cpu
= ARM_CPU(cs
);
8572 CPUARMState
*env
= &cpu
->env
;
8573 unsigned int new_el
= env
->exception
.target_el
;
8575 assert(!arm_feature(env
, ARM_FEATURE_M
));
8577 arm_log_exception(cs
->exception_index
);
8578 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
8580 if (qemu_loglevel_mask(CPU_LOG_INT
)
8581 && !excp_is_internal(cs
->exception_index
)) {
8582 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
8583 syn_get_ec(env
->exception
.syndrome
),
8584 env
->exception
.syndrome
);
8587 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
8588 arm_handle_psci_call(cpu
);
8589 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
8594 * Semihosting semantics depend on the register width of the code
8595 * that caused the exception, not the target exception level, so
8596 * must be handled here.
8599 if (cs
->exception_index
== EXCP_SEMIHOST
) {
8600 handle_semihosting(cs
);
8605 /* Hooks may change global state so BQL should be held, also the
8606 * BQL needs to be held for any modification of
8607 * cs->interrupt_request.
8609 g_assert(qemu_mutex_iothread_locked());
8611 arm_call_pre_el_change_hook(cpu
);
8613 assert(!excp_is_internal(cs
->exception_index
));
8614 if (arm_el_is_aa64(env
, new_el
)) {
8615 arm_cpu_do_interrupt_aarch64(cs
);
8617 arm_cpu_do_interrupt_aarch32(cs
);
8620 arm_call_el_change_hook(cpu
);
8622 if (!kvm_enabled()) {
8623 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
8626 #endif /* !CONFIG_USER_ONLY */
8628 /* Return the exception level which controls this address translation regime */
8629 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8632 case ARMMMUIdx_S2NS
:
8633 case ARMMMUIdx_S1E2
:
8635 case ARMMMUIdx_S1E3
:
8637 case ARMMMUIdx_S1SE0
:
8638 return arm_el_is_aa64(env
, 3) ? 1 : 3;
8639 case ARMMMUIdx_S1SE1
:
8640 case ARMMMUIdx_S1NSE0
:
8641 case ARMMMUIdx_S1NSE1
:
8642 case ARMMMUIdx_MPrivNegPri
:
8643 case ARMMMUIdx_MUserNegPri
:
8644 case ARMMMUIdx_MPriv
:
8645 case ARMMMUIdx_MUser
:
8646 case ARMMMUIdx_MSPrivNegPri
:
8647 case ARMMMUIdx_MSUserNegPri
:
8648 case ARMMMUIdx_MSPriv
:
8649 case ARMMMUIdx_MSUser
:
8652 g_assert_not_reached();
8656 #ifndef CONFIG_USER_ONLY
8658 /* Return the SCTLR value which controls this address translation regime */
8659 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8661 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
8664 /* Return true if the specified stage of address translation is disabled */
8665 static inline bool regime_translation_disabled(CPUARMState
*env
,
8668 if (arm_feature(env
, ARM_FEATURE_M
)) {
8669 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
8670 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
8671 case R_V7M_MPU_CTRL_ENABLE_MASK
:
8672 /* Enabled, but not for HardFault and NMI */
8673 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
8674 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
8675 /* Enabled for all cases */
8679 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
8680 * we warned about that in armv7m_nvic.c when the guest set it.
8686 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8687 /* HCR.DC means HCR.VM behaves as 1 */
8688 return (env
->cp15
.hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
8691 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
8692 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
8693 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
8698 if ((env
->cp15
.hcr_el2
& HCR_DC
) &&
8699 (mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
)) {
8700 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
8704 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
8707 static inline bool regime_translation_big_endian(CPUARMState
*env
,
8710 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
8713 /* Return the TTBR associated with this translation regime */
8714 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8717 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8718 return env
->cp15
.vttbr_el2
;
8721 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
8723 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
8727 #endif /* !CONFIG_USER_ONLY */
8729 /* Return the TCR controlling this translation regime */
8730 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8732 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8733 return &env
->cp15
.vtcr_el2
;
8735 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
8738 /* Convert a possible stage1+2 MMU index into the appropriate
8741 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
8743 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
8744 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
8749 /* Return true if the translation regime is using LPAE format page tables */
8750 static inline bool regime_using_lpae_format(CPUARMState
*env
,
8753 int el
= regime_el(env
, mmu_idx
);
8754 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
8757 if (arm_feature(env
, ARM_FEATURE_LPAE
)
8758 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
8764 /* Returns true if the stage 1 translation regime is using LPAE format page
8765 * tables. Used when raising alignment exceptions, whose FSR changes depending
8766 * on whether the long or short descriptor format is in use. */
8767 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8769 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8771 return regime_using_lpae_format(env
, mmu_idx
);
8774 #ifndef CONFIG_USER_ONLY
8775 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8778 case ARMMMUIdx_S1SE0
:
8779 case ARMMMUIdx_S1NSE0
:
8780 case ARMMMUIdx_MUser
:
8781 case ARMMMUIdx_MSUser
:
8782 case ARMMMUIdx_MUserNegPri
:
8783 case ARMMMUIdx_MSUserNegPri
:
8787 case ARMMMUIdx_S12NSE0
:
8788 case ARMMMUIdx_S12NSE1
:
8789 g_assert_not_reached();
8793 /* Translate section/page access permissions to page
8794 * R/W protection flags
8797 * @mmu_idx: MMU index indicating required translation regime
8798 * @ap: The 3-bit access permissions (AP[2:0])
8799 * @domain_prot: The 2-bit domain access permissions
8801 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8802 int ap
, int domain_prot
)
8804 bool is_user
= regime_is_user(env
, mmu_idx
);
8806 if (domain_prot
== 3) {
8807 return PAGE_READ
| PAGE_WRITE
;
8812 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8815 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
8817 return is_user
? 0 : PAGE_READ
;
8824 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8829 return PAGE_READ
| PAGE_WRITE
;
8832 return PAGE_READ
| PAGE_WRITE
;
8833 case 4: /* Reserved. */
8836 return is_user
? 0 : PAGE_READ
;
8840 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
8845 g_assert_not_reached();
8849 /* Translate section/page access permissions to page
8850 * R/W protection flags.
8852 * @ap: The 2-bit simple AP (AP[2:1])
8853 * @is_user: TRUE if accessing from PL0
8855 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
8859 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8861 return PAGE_READ
| PAGE_WRITE
;
8863 return is_user
? 0 : PAGE_READ
;
8867 g_assert_not_reached();
8872 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
8874 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
8877 /* Translate S2 section/page access permissions to protection flags
8880 * @s2ap: The 2-bit stage2 access permissions (S2AP)
8881 * @xn: XN (execute-never) bit
8883 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
8894 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
8901 /* Translate section/page access permissions to protection flags
8904 * @mmu_idx: MMU index indicating required translation regime
8905 * @is_aa64: TRUE if AArch64
8906 * @ap: The 2-bit simple AP (AP[2:1])
8907 * @ns: NS (non-secure) bit
8908 * @xn: XN (execute-never) bit
8909 * @pxn: PXN (privileged execute-never) bit
8911 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
8912 int ap
, int ns
, int xn
, int pxn
)
8914 bool is_user
= regime_is_user(env
, mmu_idx
);
8915 int prot_rw
, user_rw
;
8919 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
8921 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
8925 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
8928 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
8932 /* TODO have_wxn should be replaced with
8933 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
8934 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
8935 * compatible processors have EL2, which is required for [U]WXN.
8937 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
8940 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
8944 switch (regime_el(env
, mmu_idx
)) {
8947 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
8954 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8955 switch (regime_el(env
, mmu_idx
)) {
8959 xn
= xn
|| !(user_rw
& PAGE_READ
);
8963 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
8965 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
8966 (uwxn
&& (user_rw
& PAGE_WRITE
));
8976 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
8979 return prot_rw
| PAGE_EXEC
;
8982 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8983 uint32_t *table
, uint32_t address
)
8985 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
8986 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8988 if (address
& tcr
->mask
) {
8989 if (tcr
->raw_tcr
& TTBCR_PD1
) {
8990 /* Translation table walk disabled for TTBR1 */
8993 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
8995 if (tcr
->raw_tcr
& TTBCR_PD0
) {
8996 /* Translation table walk disabled for TTBR0 */
8999 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
9001 *table
|= (address
>> 18) & 0x3ffc;
9005 /* Translate a S1 pagetable walk through S2 if needed. */
9006 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
9007 hwaddr addr
, MemTxAttrs txattrs
,
9008 ARMMMUFaultInfo
*fi
)
9010 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
9011 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
9012 target_ulong s2size
;
9016 ARMCacheAttrs cacheattrs
= {};
9017 ARMCacheAttrs
*pcacheattrs
= NULL
;
9019 if (env
->cp15
.hcr_el2
& HCR_PTW
) {
9021 * PTW means we must fault if this S1 walk touches S2 Device
9022 * memory; otherwise we don't care about the attributes and can
9023 * save the S2 translation the effort of computing them.
9025 pcacheattrs
= &cacheattrs
;
9028 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
9029 &txattrs
, &s2prot
, &s2size
, fi
, pcacheattrs
);
9031 assert(fi
->type
!= ARMFault_None
);
9037 if (pcacheattrs
&& (pcacheattrs
->attrs
& 0xf0) == 0) {
9038 /* Access was to Device memory: generate Permission fault */
9039 fi
->type
= ARMFault_Permission
;
9050 /* All loads done in the course of a page table walk go through here. */
9051 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9052 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9054 ARMCPU
*cpu
= ARM_CPU(cs
);
9055 CPUARMState
*env
= &cpu
->env
;
9056 MemTxAttrs attrs
= {};
9057 MemTxResult result
= MEMTX_OK
;
9061 attrs
.secure
= is_secure
;
9062 as
= arm_addressspace(cs
, attrs
);
9063 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
9067 if (regime_translation_big_endian(env
, mmu_idx
)) {
9068 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
9070 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
9072 if (result
== MEMTX_OK
) {
9075 fi
->type
= ARMFault_SyncExternalOnWalk
;
9076 fi
->ea
= arm_extabort_type(result
);
9080 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
9081 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
9083 ARMCPU
*cpu
= ARM_CPU(cs
);
9084 CPUARMState
*env
= &cpu
->env
;
9085 MemTxAttrs attrs
= {};
9086 MemTxResult result
= MEMTX_OK
;
9090 attrs
.secure
= is_secure
;
9091 as
= arm_addressspace(cs
, attrs
);
9092 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
9096 if (regime_translation_big_endian(env
, mmu_idx
)) {
9097 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
9099 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
9101 if (result
== MEMTX_OK
) {
9104 fi
->type
= ARMFault_SyncExternalOnWalk
;
9105 fi
->ea
= arm_extabort_type(result
);
9109 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
9110 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9111 hwaddr
*phys_ptr
, int *prot
,
9112 target_ulong
*page_size
,
9113 ARMMMUFaultInfo
*fi
)
9115 CPUState
*cs
= env_cpu(env
);
9126 /* Pagetable walk. */
9127 /* Lookup l1 descriptor. */
9128 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
9129 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9130 fi
->type
= ARMFault_Translation
;
9133 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9135 if (fi
->type
!= ARMFault_None
) {
9139 domain
= (desc
>> 5) & 0x0f;
9140 if (regime_el(env
, mmu_idx
) == 1) {
9141 dacr
= env
->cp15
.dacr_ns
;
9143 dacr
= env
->cp15
.dacr_s
;
9145 domain_prot
= (dacr
>> (domain
* 2)) & 3;
9147 /* Section translation fault. */
9148 fi
->type
= ARMFault_Translation
;
9154 if (domain_prot
== 0 || domain_prot
== 2) {
9155 fi
->type
= ARMFault_Domain
;
9160 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9161 ap
= (desc
>> 10) & 3;
9162 *page_size
= 1024 * 1024;
9164 /* Lookup l2 entry. */
9166 /* Coarse pagetable. */
9167 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9169 /* Fine pagetable. */
9170 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
9172 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9174 if (fi
->type
!= ARMFault_None
) {
9178 case 0: /* Page translation fault. */
9179 fi
->type
= ARMFault_Translation
;
9181 case 1: /* 64k page. */
9182 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9183 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
9184 *page_size
= 0x10000;
9186 case 2: /* 4k page. */
9187 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9188 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
9189 *page_size
= 0x1000;
9191 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
9193 /* ARMv6/XScale extended small page format */
9194 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
9195 || arm_feature(env
, ARM_FEATURE_V6
)) {
9196 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9197 *page_size
= 0x1000;
9199 /* UNPREDICTABLE in ARMv5; we choose to take a
9200 * page translation fault.
9202 fi
->type
= ARMFault_Translation
;
9206 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
9209 ap
= (desc
>> 4) & 3;
9212 /* Never happens, but compiler isn't smart enough to tell. */
9216 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9217 *prot
|= *prot
? PAGE_EXEC
: 0;
9218 if (!(*prot
& (1 << access_type
))) {
9219 /* Access permission fault. */
9220 fi
->type
= ARMFault_Permission
;
9223 *phys_ptr
= phys_addr
;
9226 fi
->domain
= domain
;
9231 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
9232 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9233 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
9234 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
9236 CPUState
*cs
= env_cpu(env
);
9250 /* Pagetable walk. */
9251 /* Lookup l1 descriptor. */
9252 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
9253 /* Section translation fault if page walk is disabled by PD0 or PD1 */
9254 fi
->type
= ARMFault_Translation
;
9257 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9259 if (fi
->type
!= ARMFault_None
) {
9263 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
9264 /* Section translation fault, or attempt to use the encoding
9265 * which is Reserved on implementations without PXN.
9267 fi
->type
= ARMFault_Translation
;
9270 if ((type
== 1) || !(desc
& (1 << 18))) {
9271 /* Page or Section. */
9272 domain
= (desc
>> 5) & 0x0f;
9274 if (regime_el(env
, mmu_idx
) == 1) {
9275 dacr
= env
->cp15
.dacr_ns
;
9277 dacr
= env
->cp15
.dacr_s
;
9282 domain_prot
= (dacr
>> (domain
* 2)) & 3;
9283 if (domain_prot
== 0 || domain_prot
== 2) {
9284 /* Section or Page domain fault */
9285 fi
->type
= ARMFault_Domain
;
9289 if (desc
& (1 << 18)) {
9291 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
9292 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
9293 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
9294 *page_size
= 0x1000000;
9297 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
9298 *page_size
= 0x100000;
9300 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
9301 xn
= desc
& (1 << 4);
9303 ns
= extract32(desc
, 19, 1);
9305 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
9306 pxn
= (desc
>> 2) & 1;
9308 ns
= extract32(desc
, 3, 1);
9309 /* Lookup l2 entry. */
9310 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
9311 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
9313 if (fi
->type
!= ARMFault_None
) {
9316 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
9318 case 0: /* Page translation fault. */
9319 fi
->type
= ARMFault_Translation
;
9321 case 1: /* 64k page. */
9322 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
9323 xn
= desc
& (1 << 15);
9324 *page_size
= 0x10000;
9326 case 2: case 3: /* 4k page. */
9327 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
9329 *page_size
= 0x1000;
9332 /* Never happens, but compiler isn't smart enough to tell. */
9336 if (domain_prot
== 3) {
9337 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9339 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
9342 if (xn
&& access_type
== MMU_INST_FETCH
) {
9343 fi
->type
= ARMFault_Permission
;
9347 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
9348 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
9349 /* The simplified model uses AP[0] as an access control bit. */
9350 if ((ap
& 1) == 0) {
9351 /* Access flag fault. */
9352 fi
->type
= ARMFault_AccessFlag
;
9355 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
9357 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
9362 if (!(*prot
& (1 << access_type
))) {
9363 /* Access permission fault. */
9364 fi
->type
= ARMFault_Permission
;
9369 /* The NS bit will (as required by the architecture) have no effect if
9370 * the CPU doesn't support TZ or this is a non-secure translation
9371 * regime, because the attribute will already be non-secure.
9373 attrs
->secure
= false;
9375 *phys_ptr
= phys_addr
;
9378 fi
->domain
= domain
;
9384 * check_s2_mmu_setup
9386 * @is_aa64: True if the translation regime is in AArch64 state
9387 * @startlevel: Suggested starting level
9388 * @inputsize: Bitsize of IPAs
9389 * @stride: Page-table stride (See the ARM ARM)
9391 * Returns true if the suggested S2 translation parameters are OK and
9394 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
9395 int inputsize
, int stride
)
9397 const int grainsize
= stride
+ 3;
9400 /* Negative levels are never allowed. */
9405 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
9406 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
9411 CPUARMState
*env
= &cpu
->env
;
9412 unsigned int pamax
= arm_pamax(cpu
);
9415 case 13: /* 64KB Pages. */
9416 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
9420 case 11: /* 16KB Pages. */
9421 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
9425 case 9: /* 4KB Pages. */
9426 if (level
== 0 && pamax
<= 42) {
9431 g_assert_not_reached();
9434 /* Inputsize checks. */
9435 if (inputsize
> pamax
&&
9436 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
9437 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
9441 /* AArch32 only supports 4KB pages. Assert on that. */
9442 assert(stride
== 9);
9451 /* Translate from the 4-bit stage 2 representation of
9452 * memory attributes (without cache-allocation hints) to
9453 * the 8-bit representation of the stage 1 MAIR registers
9454 * (which includes allocation hints).
9456 * ref: shared/translation/attrs/S2AttrDecode()
9457 * .../S2ConvertAttrsHints()
9459 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
9461 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
9462 uint8_t loattr
= extract32(s2attrs
, 0, 2);
9463 uint8_t hihint
= 0, lohint
= 0;
9465 if (hiattr
!= 0) { /* normal memory */
9466 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
9467 hiattr
= loattr
= 1; /* non-cacheable */
9469 if (hiattr
!= 1) { /* Write-through or write-back */
9470 hihint
= 3; /* RW allocate */
9472 if (loattr
!= 1) { /* Write-through or write-back */
9473 lohint
= 3; /* RW allocate */
9478 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
9480 #endif /* !CONFIG_USER_ONLY */
9482 ARMVAParameters
aa64_va_parameters_both(CPUARMState
*env
, uint64_t va
,
9485 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
9486 uint32_t el
= regime_el(env
, mmu_idx
);
9487 bool tbi
, tbid
, epd
, hpd
, using16k
, using64k
;
9491 * Bit 55 is always between the two regions, and is canonical for
9492 * determining if address tagging is enabled.
9494 select
= extract64(va
, 55, 1);
9497 tsz
= extract32(tcr
, 0, 6);
9498 using64k
= extract32(tcr
, 14, 1);
9499 using16k
= extract32(tcr
, 15, 1);
9500 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9502 tbi
= tbid
= hpd
= false;
9504 tbi
= extract32(tcr
, 20, 1);
9505 hpd
= extract32(tcr
, 24, 1);
9506 tbid
= extract32(tcr
, 29, 1);
9509 } else if (!select
) {
9510 tsz
= extract32(tcr
, 0, 6);
9511 epd
= extract32(tcr
, 7, 1);
9512 using64k
= extract32(tcr
, 14, 1);
9513 using16k
= extract32(tcr
, 15, 1);
9514 tbi
= extract64(tcr
, 37, 1);
9515 hpd
= extract64(tcr
, 41, 1);
9516 tbid
= extract64(tcr
, 51, 1);
9518 int tg
= extract32(tcr
, 30, 2);
9521 tsz
= extract32(tcr
, 16, 6);
9522 epd
= extract32(tcr
, 23, 1);
9523 tbi
= extract64(tcr
, 38, 1);
9524 hpd
= extract64(tcr
, 42, 1);
9525 tbid
= extract64(tcr
, 52, 1);
9527 tsz
= MIN(tsz
, 39); /* TODO: ARMv8.4-TTST */
9528 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
9530 return (ARMVAParameters
) {
9537 .using16k
= using16k
,
9538 .using64k
= using64k
,
9542 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
9543 ARMMMUIdx mmu_idx
, bool data
)
9545 ARMVAParameters ret
= aa64_va_parameters_both(env
, va
, mmu_idx
);
9547 /* Present TBI as a composite with TBID. */
9548 ret
.tbi
&= (data
|| !ret
.tbid
);
9552 #ifndef CONFIG_USER_ONLY
9553 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
9556 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
9557 uint32_t el
= regime_el(env
, mmu_idx
);
9561 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9563 bool sext
= extract32(tcr
, 4, 1);
9564 bool sign
= extract32(tcr
, 3, 1);
9567 * If the sign-extend bit is not the same as t0sz[3], the result
9568 * is unpredictable. Flag this as a guest error.
9571 qemu_log_mask(LOG_GUEST_ERROR
,
9572 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
9574 tsz
= sextract32(tcr
, 0, 4) + 8;
9578 } else if (el
== 2) {
9580 tsz
= extract32(tcr
, 0, 3);
9582 hpd
= extract64(tcr
, 24, 1);
9585 int t0sz
= extract32(tcr
, 0, 3);
9586 int t1sz
= extract32(tcr
, 16, 3);
9589 select
= va
> (0xffffffffu
>> t0sz
);
9591 /* Note that we will detect errors later. */
9592 select
= va
>= ~(0xffffffffu
>> t1sz
);
9596 epd
= extract32(tcr
, 7, 1);
9597 hpd
= extract64(tcr
, 41, 1);
9600 epd
= extract32(tcr
, 23, 1);
9601 hpd
= extract64(tcr
, 42, 1);
9603 /* For aarch32, hpd0 is not enabled without t2e as well. */
9604 hpd
&= extract32(tcr
, 6, 1);
9607 return (ARMVAParameters
) {
9615 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
9616 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9617 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
9618 target_ulong
*page_size_ptr
,
9619 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
9621 ARMCPU
*cpu
= env_archcpu(env
);
9622 CPUState
*cs
= CPU(cpu
);
9623 /* Read an LPAE long-descriptor translation table. */
9624 ARMFaultType fault_type
= ARMFault_Translation
;
9626 ARMVAParameters param
;
9628 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
9629 uint32_t tableattrs
;
9630 target_ulong page_size
;
9633 int addrsize
, inputsize
;
9634 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
9635 int ap
, ns
, xn
, pxn
;
9636 uint32_t el
= regime_el(env
, mmu_idx
);
9638 uint64_t descaddrmask
;
9639 bool aarch64
= arm_el_is_aa64(env
, el
);
9640 bool guarded
= false;
9643 * This code does not handle the different format TCR for VTCR_EL2.
9644 * This code also does not support shareability levels.
9645 * Attribute and permission bit handling should also be checked when adding
9646 * support for those page table walks.
9649 param
= aa64_va_parameters(env
, address
, mmu_idx
,
9650 access_type
!= MMU_INST_FETCH
);
9652 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
9655 ttbr1_valid
= (el
< 2);
9656 addrsize
= 64 - 8 * param
.tbi
;
9657 inputsize
= 64 - param
.tsz
;
9659 param
= aa32_va_parameters(env
, address
, mmu_idx
);
9661 /* There is no TTBR1 for EL2 */
9662 ttbr1_valid
= (el
!= 2);
9663 addrsize
= (mmu_idx
== ARMMMUIdx_S2NS
? 40 : 32);
9664 inputsize
= addrsize
- param
.tsz
;
9668 * We determined the region when collecting the parameters, but we
9669 * have not yet validated that the address is valid for the region.
9670 * Extract the top bits and verify that they all match select.
9672 * For aa32, if inputsize == addrsize, then we have selected the
9673 * region by exclusion in aa32_va_parameters and there is no more
9674 * validation to do here.
9676 if (inputsize
< addrsize
) {
9677 target_ulong top_bits
= sextract64(address
, inputsize
,
9678 addrsize
- inputsize
);
9679 if (-top_bits
!= param
.select
|| (param
.select
&& !ttbr1_valid
)) {
9680 /* The gap between the two regions is a Translation fault */
9681 fault_type
= ARMFault_Translation
;
9686 if (param
.using64k
) {
9688 } else if (param
.using16k
) {
9694 /* Note that QEMU ignores shareability and cacheability attributes,
9695 * so we don't need to do anything with the SH, ORGN, IRGN fields
9696 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
9697 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
9698 * implement any ASID-like capability so we can ignore it (instead
9699 * we will always flush the TLB any time the ASID is changed).
9701 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
9703 /* Here we should have set up all the parameters for the translation:
9704 * inputsize, ttbr, epd, stride, tbi
9708 /* Translation table walk disabled => Translation fault on TLB miss
9709 * Note: This is always 0 on 64-bit EL2 and EL3.
9714 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
9715 /* The starting level depends on the virtual address size (which can
9716 * be up to 48 bits) and the translation granule size. It indicates
9717 * the number of strides (stride bits at a time) needed to
9718 * consume the bits of the input address. In the pseudocode this is:
9719 * level = 4 - RoundUp((inputsize - grainsize) / stride)
9720 * where their 'inputsize' is our 'inputsize', 'grainsize' is
9721 * our 'stride + 3' and 'stride' is our 'stride'.
9722 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
9723 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
9724 * = 4 - (inputsize - 4) / stride;
9726 level
= 4 - (inputsize
- 4) / stride
;
9728 /* For stage 2 translations the starting level is specified by the
9729 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
9731 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
9732 uint32_t startlevel
;
9735 if (!aarch64
|| stride
== 9) {
9736 /* AArch32 or 4KB pages */
9737 startlevel
= 2 - sl0
;
9739 /* 16KB or 64KB pages */
9740 startlevel
= 3 - sl0
;
9743 /* Check that the starting level is valid. */
9744 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
9747 fault_type
= ARMFault_Translation
;
9753 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
9754 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
9756 /* Now we can extract the actual base address from the TTBR */
9757 descaddr
= extract64(ttbr
, 0, 48);
9758 descaddr
&= ~indexmask
;
9760 /* The address field in the descriptor goes up to bit 39 for ARMv7
9761 * but up to bit 47 for ARMv8, but we use the descaddrmask
9762 * up to bit 39 for AArch32, because we don't need other bits in that case
9763 * to construct next descriptor address (anyway they should be all zeroes).
9765 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
9766 ~indexmask_grainsize
;
9768 /* Secure accesses start with the page table in secure memory and
9769 * can be downgraded to non-secure at any step. Non-secure accesses
9770 * remain non-secure. We implement this by just ORing in the NSTable/NS
9771 * bits at each step.
9773 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
9775 uint64_t descriptor
;
9778 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
9780 nstable
= extract32(tableattrs
, 4, 1);
9781 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
9782 if (fi
->type
!= ARMFault_None
) {
9786 if (!(descriptor
& 1) ||
9787 (!(descriptor
& 2) && (level
== 3))) {
9788 /* Invalid, or the Reserved level 3 encoding */
9791 descaddr
= descriptor
& descaddrmask
;
9793 if ((descriptor
& 2) && (level
< 3)) {
9794 /* Table entry. The top five bits are attributes which may
9795 * propagate down through lower levels of the table (and
9796 * which are all arranged so that 0 means "no effect", so
9797 * we can gather them up by ORing in the bits at each level).
9799 tableattrs
|= extract64(descriptor
, 59, 5);
9801 indexmask
= indexmask_grainsize
;
9804 /* Block entry at level 1 or 2, or page entry at level 3.
9805 * These are basically the same thing, although the number
9806 * of bits we pull in from the vaddr varies.
9808 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
9809 descaddr
|= (address
& (page_size
- 1));
9810 /* Extract attributes from the descriptor */
9811 attrs
= extract64(descriptor
, 2, 10)
9812 | (extract64(descriptor
, 52, 12) << 10);
9814 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9815 /* Stage 2 table descriptors do not include any attribute fields */
9818 /* Merge in attributes from table descriptors */
9819 attrs
|= nstable
<< 3; /* NS */
9820 guarded
= extract64(descriptor
, 50, 1); /* GP */
9822 /* HPD disables all the table attributes except NSTable. */
9825 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
9826 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
9827 * means "force PL1 access only", which means forcing AP[1] to 0.
9829 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
9830 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
9833 /* Here descaddr is the final physical address, and attributes
9836 fault_type
= ARMFault_AccessFlag
;
9837 if ((attrs
& (1 << 8)) == 0) {
9842 ap
= extract32(attrs
, 4, 2);
9843 xn
= extract32(attrs
, 12, 1);
9845 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9847 *prot
= get_S2prot(env
, ap
, xn
);
9849 ns
= extract32(attrs
, 3, 1);
9850 pxn
= extract32(attrs
, 11, 1);
9851 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
9854 fault_type
= ARMFault_Permission
;
9855 if (!(*prot
& (1 << access_type
))) {
9860 /* The NS bit will (as required by the architecture) have no effect if
9861 * the CPU doesn't support TZ or this is a non-secure translation
9862 * regime, because the attribute will already be non-secure.
9864 txattrs
->secure
= false;
9866 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
9867 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
9868 txattrs
->target_tlb_bit0
= true;
9871 if (cacheattrs
!= NULL
) {
9872 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9873 cacheattrs
->attrs
= convert_stage2_attrs(env
,
9874 extract32(attrs
, 0, 4));
9876 /* Index into MAIR registers for cache attributes */
9877 uint8_t attrindx
= extract32(attrs
, 0, 3);
9878 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
9879 assert(attrindx
<= 7);
9880 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
9882 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
9885 *phys_ptr
= descaddr
;
9886 *page_size_ptr
= page_size
;
9890 fi
->type
= fault_type
;
9892 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
9893 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
9897 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
9899 int32_t address
, int *prot
)
9901 if (!arm_feature(env
, ARM_FEATURE_M
)) {
9902 *prot
= PAGE_READ
| PAGE_WRITE
;
9904 case 0xF0000000 ... 0xFFFFFFFF:
9905 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
9906 /* hivecs execing is ok */
9910 case 0x00000000 ... 0x7FFFFFFF:
9915 /* Default system address map for M profile cores.
9916 * The architecture specifies which regions are execute-never;
9917 * at the MPU level no other checks are defined.
9920 case 0x00000000 ... 0x1fffffff: /* ROM */
9921 case 0x20000000 ... 0x3fffffff: /* SRAM */
9922 case 0x60000000 ... 0x7fffffff: /* RAM */
9923 case 0x80000000 ... 0x9fffffff: /* RAM */
9924 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9926 case 0x40000000 ... 0x5fffffff: /* Peripheral */
9927 case 0xa0000000 ... 0xbfffffff: /* Device */
9928 case 0xc0000000 ... 0xdfffffff: /* Device */
9929 case 0xe0000000 ... 0xffffffff: /* System */
9930 *prot
= PAGE_READ
| PAGE_WRITE
;
9933 g_assert_not_reached();
9938 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
9939 ARMMMUIdx mmu_idx
, bool is_user
)
9941 /* Return true if we should use the default memory map as a
9942 * "background" region if there are no hits against any MPU regions.
9944 CPUARMState
*env
= &cpu
->env
;
9950 if (arm_feature(env
, ARM_FEATURE_M
)) {
9951 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
9952 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
9954 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
9958 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
9960 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
9961 return arm_feature(env
, ARM_FEATURE_M
) &&
9962 extract32(address
, 20, 12) == 0xe00;
9965 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
9967 /* True if address is in the M profile system region
9968 * 0xe0000000 - 0xffffffff
9970 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
9973 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
9974 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9975 hwaddr
*phys_ptr
, int *prot
,
9976 target_ulong
*page_size
,
9977 ARMMMUFaultInfo
*fi
)
9979 ARMCPU
*cpu
= env_archcpu(env
);
9981 bool is_user
= regime_is_user(env
, mmu_idx
);
9983 *phys_ptr
= address
;
9984 *page_size
= TARGET_PAGE_SIZE
;
9987 if (regime_translation_disabled(env
, mmu_idx
) ||
9988 m_is_ppb_region(env
, address
)) {
9989 /* MPU disabled or M profile PPB access: use default memory map.
9990 * The other case which uses the default memory map in the
9991 * v7M ARM ARM pseudocode is exception vector reads from the vector
9992 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
9993 * which always does a direct read using address_space_ldl(), rather
9994 * than going via this function, so we don't need to check that here.
9996 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9997 } else { /* MPU enabled */
9998 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
10000 uint32_t base
= env
->pmsav7
.drbar
[n
];
10001 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
10003 bool srdis
= false;
10005 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
10010 qemu_log_mask(LOG_GUEST_ERROR
,
10011 "DRSR[%d]: Rsize field cannot be 0\n", n
);
10015 rmask
= (1ull << rsize
) - 1;
10017 if (base
& rmask
) {
10018 qemu_log_mask(LOG_GUEST_ERROR
,
10019 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
10020 "to DRSR region size, mask = 0x%" PRIx32
"\n",
10025 if (address
< base
|| address
> base
+ rmask
) {
10027 * Address not in this region. We must check whether the
10028 * region covers addresses in the same page as our address.
10029 * In that case we must not report a size that covers the
10030 * whole page for a subsequent hit against a different MPU
10031 * region or the background region, because it would result in
10032 * incorrect TLB hits for subsequent accesses to addresses that
10033 * are in this MPU region.
10035 if (ranges_overlap(base
, rmask
,
10036 address
& TARGET_PAGE_MASK
,
10037 TARGET_PAGE_SIZE
)) {
10043 /* Region matched */
10045 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
10047 uint32_t srdis_mask
;
10049 rsize
-= 3; /* sub region size (power of 2) */
10050 snd
= ((address
- base
) >> rsize
) & 0x7;
10051 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
10053 srdis_mask
= srdis
? 0x3 : 0x0;
10054 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
10055 /* This will check in groups of 2, 4 and then 8, whether
10056 * the subregion bits are consistent. rsize is incremented
10057 * back up to give the region size, considering consistent
10058 * adjacent subregions as one region. Stop testing if rsize
10059 * is already big enough for an entire QEMU page.
10061 int snd_rounded
= snd
& ~(i
- 1);
10062 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
10063 snd_rounded
+ 8, i
);
10064 if (srdis_mask
^ srdis_multi
) {
10067 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
10074 if (rsize
< TARGET_PAGE_BITS
) {
10075 *page_size
= 1 << rsize
;
10080 if (n
== -1) { /* no hits */
10081 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
10082 /* background fault */
10083 fi
->type
= ARMFault_Background
;
10086 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10087 } else { /* a MPU hit! */
10088 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
10089 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
10091 if (m_is_system_region(env
, address
)) {
10092 /* System space is always execute never */
10096 if (is_user
) { /* User mode AP bit decoding */
10101 break; /* no access */
10103 *prot
|= PAGE_WRITE
;
10107 *prot
|= PAGE_READ
| PAGE_EXEC
;
10110 /* for v7M, same as 6; for R profile a reserved value */
10111 if (arm_feature(env
, ARM_FEATURE_M
)) {
10112 *prot
|= PAGE_READ
| PAGE_EXEC
;
10117 qemu_log_mask(LOG_GUEST_ERROR
,
10118 "DRACR[%d]: Bad value for AP bits: 0x%"
10119 PRIx32
"\n", n
, ap
);
10121 } else { /* Priv. mode AP bits decoding */
10124 break; /* no access */
10128 *prot
|= PAGE_WRITE
;
10132 *prot
|= PAGE_READ
| PAGE_EXEC
;
10135 /* for v7M, same as 6; for R profile a reserved value */
10136 if (arm_feature(env
, ARM_FEATURE_M
)) {
10137 *prot
|= PAGE_READ
| PAGE_EXEC
;
10142 qemu_log_mask(LOG_GUEST_ERROR
,
10143 "DRACR[%d]: Bad value for AP bits: 0x%"
10144 PRIx32
"\n", n
, ap
);
10148 /* execute never */
10150 *prot
&= ~PAGE_EXEC
;
10155 fi
->type
= ARMFault_Permission
;
10157 return !(*prot
& (1 << access_type
));
10160 static bool v8m_is_sau_exempt(CPUARMState
*env
,
10161 uint32_t address
, MMUAccessType access_type
)
10163 /* The architecture specifies that certain address ranges are
10164 * exempt from v8M SAU/IDAU checks.
10167 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
10168 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
10169 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
10170 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
10171 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
10172 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
10175 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
10176 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10177 V8M_SAttributes
*sattrs
)
10179 /* Look up the security attributes for this address. Compare the
10180 * pseudocode SecurityCheck() function.
10181 * We assume the caller has zero-initialized *sattrs.
10183 ARMCPU
*cpu
= env_archcpu(env
);
10185 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
10186 int idau_region
= IREGION_NOTVALID
;
10187 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
10188 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
10191 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
10192 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
10194 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
10198 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
10199 /* 0xf0000000..0xffffffff is always S for insn fetches */
10203 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
10204 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
10208 if (idau_region
!= IREGION_NOTVALID
) {
10209 sattrs
->irvalid
= true;
10210 sattrs
->iregion
= idau_region
;
10213 switch (env
->sau
.ctrl
& 3) {
10214 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
10216 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
10219 default: /* SAU.ENABLE == 1 */
10220 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
10221 if (env
->sau
.rlar
[r
] & 1) {
10222 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
10223 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
10225 if (base
<= address
&& limit
>= address
) {
10226 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
10227 sattrs
->subpage
= true;
10229 if (sattrs
->srvalid
) {
10230 /* If we hit in more than one region then we must report
10231 * as Secure, not NS-Callable, with no valid region
10234 sattrs
->ns
= false;
10235 sattrs
->nsc
= false;
10236 sattrs
->sregion
= 0;
10237 sattrs
->srvalid
= false;
10240 if (env
->sau
.rlar
[r
] & 2) {
10241 sattrs
->nsc
= true;
10245 sattrs
->srvalid
= true;
10246 sattrs
->sregion
= r
;
10250 * Address not in this region. We must check whether the
10251 * region covers addresses in the same page as our address.
10252 * In that case we must not report a size that covers the
10253 * whole page for a subsequent hit against a different MPU
10254 * region or the background region, because it would result
10255 * in incorrect TLB hits for subsequent accesses to
10256 * addresses that are in this MPU region.
10258 if (limit
>= base
&&
10259 ranges_overlap(base
, limit
- base
+ 1,
10261 TARGET_PAGE_SIZE
)) {
10262 sattrs
->subpage
= true;
10271 * The IDAU will override the SAU lookup results if it specifies
10272 * higher security than the SAU does.
10275 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
10276 sattrs
->ns
= false;
10277 sattrs
->nsc
= idau_nsc
;
10282 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
10283 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10284 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
10285 int *prot
, bool *is_subpage
,
10286 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
10288 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
10289 * that a full phys-to-virt translation does).
10290 * mregion is (if not NULL) set to the region number which matched,
10291 * or -1 if no region number is returned (MPU off, address did not
10292 * hit a region, address hit in multiple regions).
10293 * We set is_subpage to true if the region hit doesn't cover the
10294 * entire TARGET_PAGE the address is within.
10296 ARMCPU
*cpu
= env_archcpu(env
);
10297 bool is_user
= regime_is_user(env
, mmu_idx
);
10298 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
10300 int matchregion
= -1;
10302 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
10303 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
10305 *is_subpage
= false;
10306 *phys_ptr
= address
;
10312 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
10313 * was an exception vector read from the vector table (which is always
10314 * done using the default system address map), because those accesses
10315 * are done in arm_v7m_load_vector(), which always does a direct
10316 * read using address_space_ldl(), rather than going via this function.
10318 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
10320 } else if (m_is_ppb_region(env
, address
)) {
10323 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
10327 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
10328 /* region search */
10329 /* Note that the base address is bits [31:5] from the register
10330 * with bits [4:0] all zeroes, but the limit address is bits
10331 * [31:5] from the register with bits [4:0] all ones.
10333 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
10334 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
10336 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
10337 /* Region disabled */
10341 if (address
< base
|| address
> limit
) {
10343 * Address not in this region. We must check whether the
10344 * region covers addresses in the same page as our address.
10345 * In that case we must not report a size that covers the
10346 * whole page for a subsequent hit against a different MPU
10347 * region or the background region, because it would result in
10348 * incorrect TLB hits for subsequent accesses to addresses that
10349 * are in this MPU region.
10351 if (limit
>= base
&&
10352 ranges_overlap(base
, limit
- base
+ 1,
10354 TARGET_PAGE_SIZE
)) {
10355 *is_subpage
= true;
10360 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
10361 *is_subpage
= true;
10364 if (matchregion
!= -1) {
10365 /* Multiple regions match -- always a failure (unlike
10366 * PMSAv7 where highest-numbered-region wins)
10368 fi
->type
= ARMFault_Permission
;
10379 /* background fault */
10380 fi
->type
= ARMFault_Background
;
10384 if (matchregion
== -1) {
10385 /* hit using the background region */
10386 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
10388 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
10389 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
10391 if (m_is_system_region(env
, address
)) {
10392 /* System space is always execute never */
10396 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
10397 if (*prot
&& !xn
) {
10398 *prot
|= PAGE_EXEC
;
10400 /* We don't need to look the attribute up in the MAIR0/MAIR1
10401 * registers because that only tells us about cacheability.
10404 *mregion
= matchregion
;
10408 fi
->type
= ARMFault_Permission
;
10410 return !(*prot
& (1 << access_type
));
10414 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
10415 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10416 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
10417 int *prot
, target_ulong
*page_size
,
10418 ARMMMUFaultInfo
*fi
)
10420 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
10421 V8M_SAttributes sattrs
= {};
10423 bool mpu_is_subpage
;
10425 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10426 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
10427 if (access_type
== MMU_INST_FETCH
) {
10428 /* Instruction fetches always use the MMU bank and the
10429 * transaction attribute determined by the fetch address,
10430 * regardless of CPU state. This is painful for QEMU
10431 * to handle, because it would mean we need to encode
10432 * into the mmu_idx not just the (user, negpri) information
10433 * for the current security state but also that for the
10434 * other security state, which would balloon the number
10435 * of mmu_idx values needed alarmingly.
10436 * Fortunately we can avoid this because it's not actually
10437 * possible to arbitrarily execute code from memory with
10438 * the wrong security attribute: it will always generate
10439 * an exception of some kind or another, apart from the
10440 * special case of an NS CPU executing an SG instruction
10441 * in S&NSC memory. So we always just fail the translation
10442 * here and sort things out in the exception handler
10443 * (including possibly emulating an SG instruction).
10445 if (sattrs
.ns
!= !secure
) {
10447 fi
->type
= ARMFault_QEMU_NSCExec
;
10449 fi
->type
= ARMFault_QEMU_SFault
;
10451 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
10452 *phys_ptr
= address
;
10457 /* For data accesses we always use the MMU bank indicated
10458 * by the current CPU state, but the security attributes
10459 * might downgrade a secure access to nonsecure.
10462 txattrs
->secure
= false;
10463 } else if (!secure
) {
10464 /* NS access to S memory must fault.
10465 * Architecturally we should first check whether the
10466 * MPU information for this address indicates that we
10467 * are doing an unaligned access to Device memory, which
10468 * should generate a UsageFault instead. QEMU does not
10469 * currently check for that kind of unaligned access though.
10470 * If we added it we would need to do so as a special case
10471 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
10473 fi
->type
= ARMFault_QEMU_SFault
;
10474 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
10475 *phys_ptr
= address
;
10482 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
10483 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
10484 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
10488 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
10489 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10490 hwaddr
*phys_ptr
, int *prot
,
10491 ARMMMUFaultInfo
*fi
)
10496 bool is_user
= regime_is_user(env
, mmu_idx
);
10498 if (regime_translation_disabled(env
, mmu_idx
)) {
10499 /* MPU disabled. */
10500 *phys_ptr
= address
;
10501 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10505 *phys_ptr
= address
;
10506 for (n
= 7; n
>= 0; n
--) {
10507 base
= env
->cp15
.c6_region
[n
];
10508 if ((base
& 1) == 0) {
10511 mask
= 1 << ((base
>> 1) & 0x1f);
10512 /* Keep this shift separate from the above to avoid an
10513 (undefined) << 32. */
10514 mask
= (mask
<< 1) - 1;
10515 if (((base
^ address
) & ~mask
) == 0) {
10520 fi
->type
= ARMFault_Background
;
10524 if (access_type
== MMU_INST_FETCH
) {
10525 mask
= env
->cp15
.pmsav5_insn_ap
;
10527 mask
= env
->cp15
.pmsav5_data_ap
;
10529 mask
= (mask
>> (n
* 4)) & 0xf;
10532 fi
->type
= ARMFault_Permission
;
10537 fi
->type
= ARMFault_Permission
;
10541 *prot
= PAGE_READ
| PAGE_WRITE
;
10546 *prot
|= PAGE_WRITE
;
10550 *prot
= PAGE_READ
| PAGE_WRITE
;
10554 fi
->type
= ARMFault_Permission
;
10564 /* Bad permission. */
10565 fi
->type
= ARMFault_Permission
;
10569 *prot
|= PAGE_EXEC
;
10573 /* Combine either inner or outer cacheability attributes for normal
10574 * memory, according to table D4-42 and pseudocode procedure
10575 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
10577 * NB: only stage 1 includes allocation hints (RW bits), leading to
10580 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
10582 if (s1
== 4 || s2
== 4) {
10583 /* non-cacheable has precedence */
10585 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
10586 /* stage 1 write-through takes precedence */
10588 } else if (extract32(s2
, 2, 2) == 2) {
10589 /* stage 2 write-through takes precedence, but the allocation hint
10590 * is still taken from stage 1
10592 return (2 << 2) | extract32(s1
, 0, 2);
10593 } else { /* write-back */
10598 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
10599 * and CombineS1S2Desc()
10601 * @s1: Attributes from stage 1 walk
10602 * @s2: Attributes from stage 2 walk
10604 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
10606 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
10607 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
10610 /* Combine shareability attributes (table D4-43) */
10611 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
10612 /* if either are outer-shareable, the result is outer-shareable */
10613 ret
.shareability
= 2;
10614 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
10615 /* if either are inner-shareable, the result is inner-shareable */
10616 ret
.shareability
= 3;
10618 /* both non-shareable */
10619 ret
.shareability
= 0;
10622 /* Combine memory type and cacheability attributes */
10623 if (s1hi
== 0 || s2hi
== 0) {
10624 /* Device has precedence over normal */
10625 if (s1lo
== 0 || s2lo
== 0) {
10626 /* nGnRnE has precedence over anything */
10628 } else if (s1lo
== 4 || s2lo
== 4) {
10629 /* non-Reordering has precedence over Reordering */
10630 ret
.attrs
= 4; /* nGnRE */
10631 } else if (s1lo
== 8 || s2lo
== 8) {
10632 /* non-Gathering has precedence over Gathering */
10633 ret
.attrs
= 8; /* nGRE */
10635 ret
.attrs
= 0xc; /* GRE */
10638 /* Any location for which the resultant memory type is any
10639 * type of Device memory is always treated as Outer Shareable.
10641 ret
.shareability
= 2;
10642 } else { /* Normal memory */
10643 /* Outer/inner cacheability combine independently */
10644 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
10645 | combine_cacheattr_nibble(s1lo
, s2lo
);
10647 if (ret
.attrs
== 0x44) {
10648 /* Any location for which the resultant memory type is Normal
10649 * Inner Non-cacheable, Outer Non-cacheable is always treated
10650 * as Outer Shareable.
10652 ret
.shareability
= 2;
10660 /* get_phys_addr - get the physical address for this virtual address
10662 * Find the physical address corresponding to the given virtual address,
10663 * by doing a translation table walk on MMU based systems or using the
10664 * MPU state on MPU based systems.
10666 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10667 * prot and page_size may not be filled in, and the populated fsr value provides
10668 * information on why the translation aborted, in the format of a
10669 * DFSR/IFSR fault register, with the following caveats:
10670 * * we honour the short vs long DFSR format differences.
10671 * * the WnR bit is never set (the caller must do this).
10672 * * for PSMAv5 based systems we don't bother to return a full FSR format
10675 * @env: CPUARMState
10676 * @address: virtual address to get physical address for
10677 * @access_type: 0 for read, 1 for write, 2 for execute
10678 * @mmu_idx: MMU index indicating required translation regime
10679 * @phys_ptr: set to the physical address corresponding to the virtual address
10680 * @attrs: set to the memory transaction attributes to use
10681 * @prot: set to the permissions for the page containing phys_ptr
10682 * @page_size: set to the size of the page containing phys_ptr
10683 * @fi: set to fault info if the translation fails
10684 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10686 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
10687 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10688 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10689 target_ulong
*page_size
,
10690 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
10692 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
10693 /* Call ourselves recursively to do the stage 1 and then stage 2
10696 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
10700 ARMCacheAttrs cacheattrs2
= {};
10702 ret
= get_phys_addr(env
, address
, access_type
,
10703 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
10704 prot
, page_size
, fi
, cacheattrs
);
10706 /* If S1 fails or S2 is disabled, return early. */
10707 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
10712 /* S1 is done. Now do S2 translation. */
10713 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
10714 phys_ptr
, attrs
, &s2_prot
,
10716 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
10718 /* Combine the S1 and S2 perms. */
10721 /* Combine the S1 and S2 cache attributes, if needed */
10722 if (!ret
&& cacheattrs
!= NULL
) {
10723 if (env
->cp15
.hcr_el2
& HCR_DC
) {
10725 * HCR.DC forces the first stage attributes to
10726 * Normal Non-Shareable,
10727 * Inner Write-Back Read-Allocate Write-Allocate,
10728 * Outer Write-Back Read-Allocate Write-Allocate.
10730 cacheattrs
->attrs
= 0xff;
10731 cacheattrs
->shareability
= 0;
10733 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
10739 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
10741 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10745 /* The page table entries may downgrade secure to non-secure, but
10746 * cannot upgrade an non-secure translation regime's attributes
10749 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
10750 attrs
->user
= regime_is_user(env
, mmu_idx
);
10752 /* Fast Context Switch Extension. This doesn't exist at all in v8.
10753 * In v7 and earlier it affects all stage 1 translations.
10755 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
10756 && !arm_feature(env
, ARM_FEATURE_V8
)) {
10757 if (regime_el(env
, mmu_idx
) == 3) {
10758 address
+= env
->cp15
.fcseidr_s
;
10760 address
+= env
->cp15
.fcseidr_ns
;
10764 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
10766 *page_size
= TARGET_PAGE_SIZE
;
10768 if (arm_feature(env
, ARM_FEATURE_V8
)) {
10770 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
10771 phys_ptr
, attrs
, prot
, page_size
, fi
);
10772 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10774 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
10775 phys_ptr
, prot
, page_size
, fi
);
10778 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
10779 phys_ptr
, prot
, fi
);
10781 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
10782 " mmu_idx %u -> %s (prot %c%c%c)\n",
10783 access_type
== MMU_DATA_LOAD
? "reading" :
10784 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
10785 (uint32_t)address
, mmu_idx
,
10786 ret
? "Miss" : "Hit",
10787 *prot
& PAGE_READ
? 'r' : '-',
10788 *prot
& PAGE_WRITE
? 'w' : '-',
10789 *prot
& PAGE_EXEC
? 'x' : '-');
10794 /* Definitely a real MMU, not an MPU */
10796 if (regime_translation_disabled(env
, mmu_idx
)) {
10797 /* MMU disabled. */
10798 *phys_ptr
= address
;
10799 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10800 *page_size
= TARGET_PAGE_SIZE
;
10804 if (regime_using_lpae_format(env
, mmu_idx
)) {
10805 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
10806 phys_ptr
, attrs
, prot
, page_size
,
10808 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
10809 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
10810 phys_ptr
, attrs
, prot
, page_size
, fi
);
10812 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
10813 phys_ptr
, prot
, page_size
, fi
);
10817 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
10820 ARMCPU
*cpu
= ARM_CPU(cs
);
10821 CPUARMState
*env
= &cpu
->env
;
10823 target_ulong page_size
;
10826 ARMMMUFaultInfo fi
= {};
10827 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
10829 *attrs
= (MemTxAttrs
) {};
10831 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
10832 attrs
, &prot
, &page_size
, &fi
, NULL
);
10842 /* Note that signed overflow is undefined in C. The following routines are
10843 careful to use unsigned types where modulo arithmetic is required.
10844 Failure to do so _will_ break on newer gcc. */
10846 /* Signed saturating arithmetic. */
10848 /* Perform 16-bit signed saturating addition. */
10849 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10854 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10863 /* Perform 8-bit signed saturating addition. */
10864 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10869 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10878 /* Perform 16-bit signed saturating subtraction. */
10879 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10884 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10893 /* Perform 8-bit signed saturating subtraction. */
10894 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10899 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10908 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10909 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10910 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10911 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10914 #include "op_addsub.h"
10916 /* Unsigned saturating arithmetic. */
10917 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10926 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10934 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10943 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10951 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10952 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10953 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10954 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10957 #include "op_addsub.h"
10959 /* Signed modulo arithmetic. */
10960 #define SARITH16(a, b, n, op) do { \
10962 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10963 RESULT(sum, n, 16); \
10965 ge |= 3 << (n * 2); \
10968 #define SARITH8(a, b, n, op) do { \
10970 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10971 RESULT(sum, n, 8); \
10977 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10978 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10979 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10980 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10984 #include "op_addsub.h"
10986 /* Unsigned modulo arithmetic. */
10987 #define ADD16(a, b, n) do { \
10989 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10990 RESULT(sum, n, 16); \
10991 if ((sum >> 16) == 1) \
10992 ge |= 3 << (n * 2); \
10995 #define ADD8(a, b, n) do { \
10997 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10998 RESULT(sum, n, 8); \
10999 if ((sum >> 8) == 1) \
11003 #define SUB16(a, b, n) do { \
11005 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11006 RESULT(sum, n, 16); \
11007 if ((sum >> 16) == 0) \
11008 ge |= 3 << (n * 2); \
11011 #define SUB8(a, b, n) do { \
11013 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11014 RESULT(sum, n, 8); \
11015 if ((sum >> 8) == 0) \
11022 #include "op_addsub.h"
11024 /* Halved signed arithmetic. */
11025 #define ADD16(a, b, n) \
11026 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11027 #define SUB16(a, b, n) \
11028 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11029 #define ADD8(a, b, n) \
11030 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11031 #define SUB8(a, b, n) \
11032 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11035 #include "op_addsub.h"
11037 /* Halved unsigned arithmetic. */
11038 #define ADD16(a, b, n) \
11039 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11040 #define SUB16(a, b, n) \
11041 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11042 #define ADD8(a, b, n) \
11043 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11044 #define SUB8(a, b, n) \
11045 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11048 #include "op_addsub.h"
11050 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11058 /* Unsigned sum of absolute byte differences. */
11059 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11062 sum
= do_usad(a
, b
);
11063 sum
+= do_usad(a
>> 8, b
>> 8);
11064 sum
+= do_usad(a
>> 16, b
>>16);
11065 sum
+= do_usad(a
>> 24, b
>> 24);
11069 /* For ARMv6 SEL instruction. */
11070 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11082 mask
|= 0xff000000;
11083 return (a
& mask
) | (b
& ~mask
);
11087 * The upper bytes of val (above the number specified by 'bytes') must have
11088 * been zeroed out by the caller.
11090 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11094 stl_le_p(buf
, val
);
11096 /* zlib crc32 converts the accumulator and output to one's complement. */
11097 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11100 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11104 stl_le_p(buf
, val
);
11106 /* Linux crc32c converts the output to one's complement. */
11107 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11110 /* Return the exception level to which FP-disabled exceptions should
11111 * be taken, or 0 if FP is enabled.
11113 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11115 #ifndef CONFIG_USER_ONLY
11118 /* CPACR and the CPTR registers don't exist before v6, so FP is
11119 * always accessible
11121 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11125 if (arm_feature(env
, ARM_FEATURE_M
)) {
11126 /* CPACR can cause a NOCP UsageFault taken to current security state */
11127 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11131 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11132 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11133 /* FP insns cause a NOCP UsageFault taken to Secure */
11141 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11142 * 0, 2 : trap EL0 and EL1/PL1 accesses
11143 * 1 : trap only EL0 accesses
11144 * 3 : trap no accesses
11146 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
11150 if (cur_el
== 0 || cur_el
== 1) {
11151 /* Trap to PL1, which might be EL1 or EL3 */
11152 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
11157 if (cur_el
== 3 && !is_a64(env
)) {
11158 /* Secure PL1 running at EL3 */
11172 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11173 * to control non-secure access to the FPU. It doesn't have any
11174 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11176 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11177 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11178 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11179 /* FP insns act as UNDEF */
11180 return cur_el
== 2 ? 2 : 1;
11184 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
11185 * check because zero bits in the registers mean "don't trap".
11188 /* CPTR_EL2 : present in v7VE or v8 */
11189 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
11190 && !arm_is_secure_below_el3(env
)) {
11191 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
11195 /* CPTR_EL3 : present in v8 */
11196 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
11197 /* Trap all FP ops to EL3 */
11205 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
11207 g_assert_not_reached();
11211 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
11213 if (arm_feature(env
, ARM_FEATURE_M
)) {
11214 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
11217 if (el
< 2 && arm_is_secure_below_el3(env
)) {
11218 return ARMMMUIdx_S1SE0
+ el
;
11220 return ARMMMUIdx_S12NSE0
+ el
;
11224 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
11226 return arm_mmu_idx_el(env
, arm_current_el(env
));
11229 int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
11231 return arm_to_core_mmu_idx(arm_mmu_idx(env
));
11234 #ifndef CONFIG_USER_ONLY
11235 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
11237 return stage_1_mmu_idx(arm_mmu_idx(env
));
11241 static uint32_t rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
11242 ARMMMUIdx mmu_idx
, uint32_t flags
)
11244 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, FPEXC_EL
, fp_el
);
11245 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, MMUIDX
,
11246 arm_to_core_mmu_idx(mmu_idx
));
11248 if (arm_singlestep_active(env
)) {
11249 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, SS_ACTIVE
, 1);
11254 static uint32_t rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
11255 ARMMMUIdx mmu_idx
, uint32_t flags
)
11257 bool sctlr_b
= arm_sctlr_b(env
);
11260 flags
= FIELD_DP32(flags
, TBFLAG_A32
, SCTLR_B
, 1);
11262 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
11263 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
11265 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NS
, !access_secure_reg(env
));
11267 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11270 static uint32_t rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
11273 uint32_t flags
= 0;
11275 /* v8M always enables the fpu. */
11276 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
11278 if (arm_v7m_is_handler_mode(env
)) {
11279 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HANDLER
, 1);
11283 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
11284 * is suppressing them because the requested execution priority
11287 if (arm_feature(env
, ARM_FEATURE_V8
) &&
11288 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
11289 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
11290 flags
= FIELD_DP32(flags
, TBFLAG_A32
, STACKCHECK
, 1);
11293 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11296 static uint32_t rebuild_hflags_aprofile(CPUARMState
*env
)
11300 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
,
11301 arm_debug_target_el(env
));
11305 static uint32_t rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
11308 uint32_t flags
= rebuild_hflags_aprofile(env
);
11310 if (arm_el_is_aa64(env
, 1)) {
11311 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
11314 if (arm_current_el(env
) < 2 && env
->cp15
.hstr_el2
&&
11315 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11316 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HSTR_ACTIVE
, 1);
11319 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11322 static uint32_t rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
11325 uint32_t flags
= rebuild_hflags_aprofile(env
);
11326 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
11327 ARMVAParameters p0
= aa64_va_parameters_both(env
, 0, stage1
);
11331 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, AARCH64_STATE
, 1);
11333 /* FIXME: ARMv8.1-VHE S2 translation regime. */
11334 if (regime_el(env
, stage1
) < 2) {
11335 ARMVAParameters p1
= aa64_va_parameters_both(env
, -1, stage1
);
11336 tbid
= (p1
.tbi
<< 1) | p0
.tbi
;
11337 tbii
= tbid
& ~((p1
.tbid
<< 1) | p0
.tbid
);
11340 tbii
= tbid
& !p0
.tbid
;
11343 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBII
, tbii
);
11344 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBID
, tbid
);
11346 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
11347 int sve_el
= sve_exception_el(env
, el
);
11351 * If SVE is disabled, but FP is enabled,
11352 * then the effective len is 0.
11354 if (sve_el
!= 0 && fp_el
== 0) {
11357 zcr_len
= sve_zcr_len_for_el(env
, el
);
11359 flags
= FIELD_DP32(flags
, TBFLAG_A64
, SVEEXC_EL
, sve_el
);
11360 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ZCR_LEN
, zcr_len
);
11363 sctlr
= arm_sctlr(env
, el
);
11365 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
11366 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
11369 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
11371 * In order to save space in flags, we record only whether
11372 * pauth is "inactive", meaning all insns are implemented as
11373 * a nop, or "active" when some action must be performed.
11374 * The decision of which action to take is left to a helper.
11376 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
11377 flags
= FIELD_DP32(flags
, TBFLAG_A64
, PAUTH_ACTIVE
, 1);
11381 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11382 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
11383 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
11384 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BT
, 1);
11388 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11391 static uint32_t rebuild_hflags_internal(CPUARMState
*env
)
11393 int el
= arm_current_el(env
);
11394 int fp_el
= fp_exception_el(env
, el
);
11395 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11398 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11399 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
11400 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11402 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11406 void arm_rebuild_hflags(CPUARMState
*env
)
11408 env
->hflags
= rebuild_hflags_internal(env
);
11411 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
11413 int fp_el
= fp_exception_el(env
, el
);
11414 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11416 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11419 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
11421 int fp_el
= fp_exception_el(env
, el
);
11422 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11424 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11427 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
11429 int fp_el
= fp_exception_el(env
, el
);
11430 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11432 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11435 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
11436 target_ulong
*cs_base
, uint32_t *pflags
)
11438 uint32_t flags
= env
->hflags
;
11439 uint32_t pstate_for_ss
;
11442 #ifdef CONFIG_DEBUG_TCG
11443 assert(flags
== rebuild_hflags_internal(env
));
11446 if (FIELD_EX32(flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
11448 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11449 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BTYPE
, env
->btype
);
11451 pstate_for_ss
= env
->pstate
;
11453 *pc
= env
->regs
[15];
11455 if (arm_feature(env
, ARM_FEATURE_M
)) {
11456 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
11457 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
11458 != env
->v7m
.secure
) {
11459 flags
= FIELD_DP32(flags
, TBFLAG_A32
, FPCCR_S_WRONG
, 1);
11462 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
11463 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
11464 (env
->v7m
.secure
&&
11465 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
11467 * ASPEN is set, but FPCA/SFPA indicate that there is no
11468 * active FP context; we must create a new FP context before
11469 * executing any FP insn.
11471 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NEW_FP_CTXT_NEEDED
, 1);
11474 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
11475 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
11476 flags
= FIELD_DP32(flags
, TBFLAG_A32
, LSPACT
, 1);
11480 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
11481 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
11483 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
11484 flags
= FIELD_DP32(flags
, TBFLAG_A32
,
11485 XSCALE_CPAR
, env
->cp15
.c15_cpar
);
11487 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECLEN
,
11489 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECSTRIDE
,
11490 env
->vfp
.vec_stride
);
11492 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
11493 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
11497 flags
= FIELD_DP32(flags
, TBFLAG_A32
, THUMB
, env
->thumb
);
11498 flags
= FIELD_DP32(flags
, TBFLAG_A32
, CONDEXEC
, env
->condexec_bits
);
11499 pstate_for_ss
= env
->uncached_cpsr
;
11503 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
11504 * states defined in the ARM ARM for software singlestep:
11505 * SS_ACTIVE PSTATE.SS State
11506 * 0 x Inactive (the TB flag for SS is always 0)
11507 * 1 0 Active-pending
11508 * 1 1 Active-not-pending
11509 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
11511 if (FIELD_EX32(flags
, TBFLAG_ANY
, SS_ACTIVE
) &&
11512 (pstate_for_ss
& PSTATE_SS
)) {
11513 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
11519 #ifdef TARGET_AARCH64
11521 * The manual says that when SVE is enabled and VQ is widened the
11522 * implementation is allowed to zero the previously inaccessible
11523 * portion of the registers. The corollary to that is that when
11524 * SVE is enabled and VQ is narrowed we are also allowed to zero
11525 * the now inaccessible portion of the registers.
11527 * The intent of this is that no predicate bit beyond VQ is ever set.
11528 * Which means that some operations on predicate registers themselves
11529 * may operate on full uint64_t or even unrolled across the maximum
11530 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
11531 * may well be cheaper than conditionals to restrict the operation
11532 * to the relevant portion of a uint16_t[16].
11534 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
11539 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
11540 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
11542 /* Zap the high bits of the zregs. */
11543 for (i
= 0; i
< 32; i
++) {
11544 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
11547 /* Zap the high bits of the pregs and ffr. */
11550 pmask
= ~(-1ULL << (16 * (vq
& 3)));
11552 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
11553 for (i
= 0; i
< 17; ++i
) {
11554 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
11561 * Notice a change in SVE vector size when changing EL.
11563 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
11564 int new_el
, bool el0_a64
)
11566 ARMCPU
*cpu
= env_archcpu(env
);
11567 int old_len
, new_len
;
11568 bool old_a64
, new_a64
;
11570 /* Nothing to do if no SVE. */
11571 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
11575 /* Nothing to do if FP is disabled in either EL. */
11576 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
11581 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
11582 * at ELx, or not available because the EL is in AArch32 state, then
11583 * for all purposes other than a direct read, the ZCR_ELx.LEN field
11584 * has an effective value of 0".
11586 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
11587 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
11588 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
11589 * we already have the correct register contents when encountering the
11590 * vq0->vq0 transition between EL0->EL1.
11592 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
11593 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
11594 ? sve_zcr_len_for_el(env
, old_el
) : 0);
11595 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
11596 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
11597 ? sve_zcr_len_for_el(env
, new_el
) : 0);
11599 /* When changing vector length, clear inaccessible state. */
11600 if (new_len
< old_len
) {
11601 aarch64_sve_narrow_vq(env
, new_len
+ 1);