include/hw/arm/smmu-common.h

   1 /*
   2  * ARM SMMU Support
   3  *
   4  * Copyright (C) 2015-2016 Broadcom Corporation
   5  * Copyright (c) 2017 Red Hat, Inc.
   6  * Written by Prem Mallappa, Eric Auger
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #ifndef HW_ARM_SMMU_COMMON_H
  20 #define HW_ARM_SMMU_COMMON_H
  21
  22 #include "hw/sysbus.h"
  23 #include "hw/pci/pci.h"
  24 #include "qom/object.h"
  25
  26 #define SMMU_PCI_BUS_MAX                    256
  27 #define SMMU_PCI_DEVFN_MAX                  256
  28 #define SMMU_PCI_DEVFN(sid)                 (sid & 0xFF)
  29
  30 /* VMSAv8-64 Translation constants and functions */
  31 #define VMSA_LEVELS                         4
  32
  33 #define VMSA_STRIDE(gran)                   ((gran) - VMSA_LEVELS + 1)
  34 #define VMSA_BIT_LVL(isz, strd, lvl)        ((isz) - (strd) * \
  35                                              (VMSA_LEVELS - (lvl)))
  36 #define VMSA_IDXMSK(isz, strd, lvl)         ((1ULL << \
  37                                              VMSA_BIT_LVL(isz, strd, lvl)) - 1)
  38
  39 /*
  40  * Page table walk error types
  41  */
  42 typedef enum {
  43     SMMU_PTW_ERR_NONE,
  44     SMMU_PTW_ERR_WALK_EABT,   /* Translation walk external abort */
  45     SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
  46     SMMU_PTW_ERR_ADDR_SIZE,   /* Address Size fault */
  47     SMMU_PTW_ERR_ACCESS,      /* Access fault */
  48     SMMU_PTW_ERR_PERMISSION,  /* Permission fault */
  49 } SMMUPTWEventType;
  50
  51 typedef struct SMMUPTWEventInfo {
  52     int stage;
  53     SMMUPTWEventType type;
  54     dma_addr_t addr; /* fetched address that induced an abort, if any */
  55 } SMMUPTWEventInfo;
  56
  57 typedef struct SMMUTransTableInfo {
  58     bool disabled;             /* is the translation table disabled? */
  59     uint64_t ttb;              /* TT base address */
  60     uint8_t tsz;               /* input range, ie. 2^(64 -tsz)*/
  61     uint8_t granule_sz;        /* granule page shift */
  62     bool had;                  /* hierarchical attribute disable */
  63 } SMMUTransTableInfo;
  64
  65 typedef struct SMMUTLBEntry {
  66     IOMMUTLBEntry entry;
  67     uint8_t level;
  68     uint8_t granule;
  69 } SMMUTLBEntry;
  70
  71 /* Stage-2 configuration. */
  72 typedef struct SMMUS2Cfg {
  73     uint8_t tsz;            /* Size of IPA input region (S2T0SZ) */
  74     uint8_t sl0;            /* Start level of translation (S2SL0) */
  75     bool affd;              /* AF Fault Disable (S2AFFD) */
  76     bool record_faults;     /* Record fault events (S2R) */
  77     uint8_t granule_sz;     /* Granule page shift (based on S2TG) */
  78     uint8_t eff_ps;         /* Effective PA output range (based on S2PS) */
  79     uint16_t vmid;          /* Virtual Machine ID (S2VMID) */
  80     uint64_t vttb;          /* Address of translation table base (S2TTB) */
  81 } SMMUS2Cfg;
  82
  83 /*
  84  * Generic structure populated by derived SMMU devices
  85  * after decoding the configuration information and used as
  86  * input to the page table walk
  87  */
  88 typedef struct SMMUTransCfg {
  89     /* Shared fields between stage-1 and stage-2. */
  90     int stage;                 /* translation stage */
  91     bool disabled;             /* smmu is disabled */
  92     bool bypassed;             /* translation is bypassed */
  93     bool aborted;              /* translation is aborted */
  94     uint32_t iotlb_hits;       /* counts IOTLB hits */
  95     uint32_t iotlb_misses;     /* counts IOTLB misses*/
  96     /* Used by stage-1 only. */
  97     bool aa64;                 /* arch64 or aarch32 translation table */
  98     bool record_faults;        /* record fault events */
  99     uint64_t ttb;              /* TT base address */
 100     uint8_t oas;               /* output address width */
 101     uint8_t tbi;               /* Top Byte Ignore */
 102     uint16_t asid;
 103     SMMUTransTableInfo tt[2];
 104     /* Used by stage-2 only. */
 105     struct SMMUS2Cfg s2cfg;
 106 } SMMUTransCfg;
 107
 108 typedef struct SMMUDevice {
 109     void               *smmu;
 110     PCIBus             *bus;
 111     int                devfn;
 112     IOMMUMemoryRegion  iommu;
 113     AddressSpace       as;
 114     uint32_t           cfg_cache_hits;
 115     uint32_t           cfg_cache_misses;
 116     QLIST_ENTRY(SMMUDevice) next;
 117 } SMMUDevice;
 118
 119 typedef struct SMMUPciBus {
 120     PCIBus       *bus;
 121     SMMUDevice   *pbdev[]; /* Parent array is sparse, so dynamically alloc */
 122 } SMMUPciBus;
 123
 124 typedef struct SMMUIOTLBKey {
 125     uint64_t iova;
 126     uint16_t asid;
 127     uint8_t tg;
 128     uint8_t level;
 129 } SMMUIOTLBKey;
 130
 131 struct SMMUState {
 132     /* <private> */
 133     SysBusDevice  dev;
 134     const char *mrtypename;
 135     MemoryRegion iomem;
 136
 137     GHashTable *smmu_pcibus_by_busptr;
 138     GHashTable *configs; /* cache for configuration data */
 139     GHashTable *iotlb;
 140     SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX];
 141     PCIBus *pci_bus;
 142     QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
 143     uint8_t bus_num;
 144     PCIBus *primary_bus;
 145 };
 146
 147 struct SMMUBaseClass {
 148     /* <private> */
 149     SysBusDeviceClass parent_class;
 150
 151     /*< public >*/
 152
 153     DeviceRealize parent_realize;
 154
 155 };
 156
 157 #define TYPE_ARM_SMMU "arm-smmu"
 158 OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU)
 159
 160 /* Return the SMMUPciBus handle associated to a PCI bus number */
 161 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
 162
 163 /* Return the stream ID of an SMMU device */
 164 static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
 165 {
 166     return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);
 167 }
 168
 169 /**
 170  * smmu_ptw - Perform the page table walk for a given iova / access flags
 171  * pair, according to @cfg translation config
 172  */
 173 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
 174              SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);
 175
 176 /**
 177  * select_tt - compute which translation table shall be used according to
 178  * the input iova and translation config and return the TT specific info
 179  */
 180 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
 181
 182 /* Return the iommu mr associated to @sid, or NULL if none */
 183 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
 184
 185 #define SMMU_IOTLB_MAX_SIZE 256
 186
 187 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
 188                                 SMMUTransTableInfo *tt, hwaddr iova);
 189 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
 190 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
 191                                 uint8_t tg, uint8_t level);
 192 void smmu_iotlb_inv_all(SMMUState *s);
 193 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
 194 void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
 195                          uint8_t tg, uint64_t num_pages, uint8_t ttl);
 196
 197 /* Unmap the range of all the notifiers registered to any IOMMU mr */
 198 void smmu_inv_notifiers_all(SMMUState *s);
 199
 200 #endif /* HW_ARM_SMMU_COMMON_H */