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virtio_blk: Factor virtio_blk_handle_request out
[qemu/ar7.git] / target-mips / op_helper.c
blobcccfd8e07ed32ebeeed6a3ddb64e90bba61c1bb1
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include "exec.h"
21
22 #include "host-utils.h"
23
24 #include "helper.h"
25 /*****************************************************************************/
26 /* Exceptions processing helpers */
27
28 void helper_raise_exception_err (uint32_t exception, int error_code)
29 {
30 #if 1
31 if (exception < 0x100)
32 qemu_log("%s: %d %d\n", __func__, exception, error_code);
33 #endif
34 env->exception_index = exception;
35 env->error_code = error_code;
36 cpu_loop_exit();
37 }
38
39 void helper_raise_exception (uint32_t exception)
40 {
41 helper_raise_exception_err(exception, 0);
42 }
43
44 void helper_interrupt_restart (void)
45 {
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
47 !(env->CP0_Status & (1 << CP0St_ERL)) &&
48 !(env->hflags & MIPS_HFLAG_DM) &&
49 (env->CP0_Status & (1 << CP0St_IE)) &&
50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
51 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
52 helper_raise_exception(EXCP_EXT_INTERRUPT);
53 }
54 }
55
56 #if !defined(CONFIG_USER_ONLY)
57 static void do_restore_state (void *pc_ptr)
58 {
59 TranslationBlock *tb;
60 unsigned long pc = (unsigned long) pc_ptr;
61
62 tb = tb_find_pc (pc);
63 if (tb) {
64 cpu_restore_state (tb, env, pc, NULL);
65 }
66 }
67 #endif
68
69 #if defined(CONFIG_USER_ONLY)
70 #define HELPER_LD(name, insn, type) \
71 static inline type do_##name(target_ulong addr, int mem_idx) \
72 { \
73 return (type) insn##_raw(addr); \
74 }
75 #else
76 #define HELPER_LD(name, insn, type) \
77 static inline type do_##name(target_ulong addr, int mem_idx) \
78 { \
79 switch (mem_idx) \
80 { \
81 case 0: return (type) insn##_kernel(addr); break; \
82 case 1: return (type) insn##_super(addr); break; \
83 default: \
84 case 2: return (type) insn##_user(addr); break; \
85 } \
86 }
87 #endif
88 HELPER_LD(lbu, ldub, uint8_t)
89 HELPER_LD(lw, ldl, int32_t)
90 #ifdef TARGET_MIPS64
91 HELPER_LD(ld, ldq, int64_t)
92 #endif
93 #undef HELPER_LD
94
95 #if defined(CONFIG_USER_ONLY)
96 #define HELPER_ST(name, insn, type) \
97 static inline void do_##name(target_ulong addr, type val, int mem_idx) \
98 { \
99 insn##_raw(addr, val); \
100 }
101 #else
102 #define HELPER_ST(name, insn, type) \
103 static inline void do_##name(target_ulong addr, type val, int mem_idx) \
104 { \
105 switch (mem_idx) \
106 { \
107 case 0: insn##_kernel(addr, val); break; \
108 case 1: insn##_super(addr, val); break; \
109 default: \
110 case 2: insn##_user(addr, val); break; \
111 } \
112 }
113 #endif
114 HELPER_ST(sb, stb, uint8_t)
115 HELPER_ST(sw, stl, uint32_t)
116 #ifdef TARGET_MIPS64
117 HELPER_ST(sd, stq, uint64_t)
118 #endif
119 #undef HELPER_ST
120
121 target_ulong helper_clo (target_ulong arg1)
122 {
123 return clo32(arg1);
124 }
125
126 target_ulong helper_clz (target_ulong arg1)
127 {
128 return clz32(arg1);
129 }
130
131 #if defined(TARGET_MIPS64)
132 target_ulong helper_dclo (target_ulong arg1)
133 {
134 return clo64(arg1);
135 }
136
137 target_ulong helper_dclz (target_ulong arg1)
138 {
139 return clz64(arg1);
140 }
141 #endif /* TARGET_MIPS64 */
142
143 /* 64 bits arithmetic for 32 bits hosts */
144 static inline uint64_t get_HILO (void)
145 {
146 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
147 }
148
149 static inline void set_HILO (uint64_t HILO)
150 {
151 env->active_tc.LO[0] = (int32_t)HILO;
152 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
153 }
154
155 static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
156 {
157 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
158 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
159 }
160
161 static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
162 {
163 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
164 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
165 }
166
167 /* Multiplication variants of the vr54xx. */
168 target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
169 {
170 set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
171
172 return arg1;
173 }
174
175 target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
176 {
177 set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
178
179 return arg1;
180 }
181
182 target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
183 {
184 set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
185
186 return arg1;
187 }
188
189 target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
190 {
191 set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
192
193 return arg1;
194 }
195
196 target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
197 {
198 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
199
200 return arg1;
201 }
202
203 target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
204 {
205 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
206
207 return arg1;
208 }
209
210 target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
211 {
212 set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
213
214 return arg1;
215 }
216
217 target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
218 {
219 set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
220
221 return arg1;
222 }
223
224 target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
225 {
226 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
227
228 return arg1;
229 }
230
231 target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
232 {
233 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
234
235 return arg1;
236 }
237
238 target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
239 {
240 set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
241
242 return arg1;
243 }
244
245 target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
246 {
247 set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
248
249 return arg1;
250 }
251
252 target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
253 {
254 set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
255
256 return arg1;
257 }
258
259 target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
260 {
261 set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
262
263 return arg1;
264 }
265
266 #ifdef TARGET_MIPS64
267 void helper_dmult (target_ulong arg1, target_ulong arg2)
268 {
269 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
270 }
271
272 void helper_dmultu (target_ulong arg1, target_ulong arg2)
273 {
274 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
275 }
276 #endif
277
278 #ifndef CONFIG_USER_ONLY
279 #define HELPER_LD_ATOMIC(name, insn) \
280 target_ulong helper_##name(target_ulong arg, int mem_idx) \
281 { \
282 env->lladdr = do_translate_address(env, arg, 0); \
283 env->llval = do_##insn(arg, mem_idx); \
284 return env->llval; \
285 }
286 HELPER_LD_ATOMIC(ll, lw)
287 #ifdef TARGET_MIPS64
288 HELPER_LD_ATOMIC(lld, ld)
289 #endif
290 #undef HELPER_LD_ATOMIC
291
292 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
293 target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
294 { \
295 target_long tmp; \
296 \
297 if (arg2 & almask) { \
298 env->CP0_BadVAddr = arg2; \
299 helper_raise_exception(EXCP_AdES); \
300 } \
301 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
302 tmp = do_##ld_insn(arg2, mem_idx); \
303 if (tmp == env->llval) { \
304 do_##st_insn(arg2, arg1, mem_idx); \
305 return 1; \
306 } \
307 } \
308 return 0; \
309 }
310 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
311 #ifdef TARGET_MIPS64
312 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
313 #endif
314 #undef HELPER_ST_ATOMIC
315 #endif
316
317 #ifdef TARGET_WORDS_BIGENDIAN
318 #define GET_LMASK(v) ((v) & 3)
319 #define GET_OFFSET(addr, offset) (addr + (offset))
320 #else
321 #define GET_LMASK(v) (((v) & 3) ^ 3)
322 #define GET_OFFSET(addr, offset) (addr - (offset))
323 #endif
324
325 target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
326 {
327 target_ulong tmp;
328
329 tmp = do_lbu(arg2, mem_idx);
330 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
331
332 if (GET_LMASK(arg2) <= 2) {
333 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
334 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
335 }
336
337 if (GET_LMASK(arg2) <= 1) {
338 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
339 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
340 }
341
342 if (GET_LMASK(arg2) == 0) {
343 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
344 arg1 = (arg1 & 0xFFFFFF00) | tmp;
345 }
346 return (int32_t)arg1;
347 }
348
349 target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
350 {
351 target_ulong tmp;
352
353 tmp = do_lbu(arg2, mem_idx);
354 arg1 = (arg1 & 0xFFFFFF00) | tmp;
355
356 if (GET_LMASK(arg2) >= 1) {
357 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
358 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
359 }
360
361 if (GET_LMASK(arg2) >= 2) {
362 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
363 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
364 }
365
366 if (GET_LMASK(arg2) == 3) {
367 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
368 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
369 }
370 return (int32_t)arg1;
371 }
372
373 void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
374 {
375 do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
376
377 if (GET_LMASK(arg2) <= 2)
378 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
379
380 if (GET_LMASK(arg2) <= 1)
381 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
382
383 if (GET_LMASK(arg2) == 0)
384 do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
385 }
386
387 void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
388 {
389 do_sb(arg2, (uint8_t)arg1, mem_idx);
390
391 if (GET_LMASK(arg2) >= 1)
392 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
393
394 if (GET_LMASK(arg2) >= 2)
395 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
396
397 if (GET_LMASK(arg2) == 3)
398 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
399 }
400
401 #if defined(TARGET_MIPS64)
402 /* "half" load and stores. We must do the memory access inline,
403 or fault handling won't work. */
404
405 #ifdef TARGET_WORDS_BIGENDIAN
406 #define GET_LMASK64(v) ((v) & 7)
407 #else
408 #define GET_LMASK64(v) (((v) & 7) ^ 7)
409 #endif
410
411 target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
412 {
413 uint64_t tmp;
414
415 tmp = do_lbu(arg2, mem_idx);
416 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
417
418 if (GET_LMASK64(arg2) <= 6) {
419 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
420 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
421 }
422
423 if (GET_LMASK64(arg2) <= 5) {
424 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
425 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
426 }
427
428 if (GET_LMASK64(arg2) <= 4) {
429 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
430 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
431 }
432
433 if (GET_LMASK64(arg2) <= 3) {
434 tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
435 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
436 }
437
438 if (GET_LMASK64(arg2) <= 2) {
439 tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
440 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
441 }
442
443 if (GET_LMASK64(arg2) <= 1) {
444 tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
445 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
446 }
447
448 if (GET_LMASK64(arg2) == 0) {
449 tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
450 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
451 }
452
453 return arg1;
454 }
455
456 target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
457 {
458 uint64_t tmp;
459
460 tmp = do_lbu(arg2, mem_idx);
461 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
462
463 if (GET_LMASK64(arg2) >= 1) {
464 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
465 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
466 }
467
468 if (GET_LMASK64(arg2) >= 2) {
469 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
470 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
471 }
472
473 if (GET_LMASK64(arg2) >= 3) {
474 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
475 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
476 }
477
478 if (GET_LMASK64(arg2) >= 4) {
479 tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
480 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
481 }
482
483 if (GET_LMASK64(arg2) >= 5) {
484 tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
485 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
486 }
487
488 if (GET_LMASK64(arg2) >= 6) {
489 tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
490 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
491 }
492
493 if (GET_LMASK64(arg2) == 7) {
494 tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
495 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
496 }
497
498 return arg1;
499 }
500
501 void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
502 {
503 do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
504
505 if (GET_LMASK64(arg2) <= 6)
506 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
507
508 if (GET_LMASK64(arg2) <= 5)
509 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
510
511 if (GET_LMASK64(arg2) <= 4)
512 do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
513
514 if (GET_LMASK64(arg2) <= 3)
515 do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
516
517 if (GET_LMASK64(arg2) <= 2)
518 do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
519
520 if (GET_LMASK64(arg2) <= 1)
521 do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
522
523 if (GET_LMASK64(arg2) <= 0)
524 do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
525 }
526
527 void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
528 {
529 do_sb(arg2, (uint8_t)arg1, mem_idx);
530
531 if (GET_LMASK64(arg2) >= 1)
532 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
533
534 if (GET_LMASK64(arg2) >= 2)
535 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
536
537 if (GET_LMASK64(arg2) >= 3)
538 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
539
540 if (GET_LMASK64(arg2) >= 4)
541 do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
542
543 if (GET_LMASK64(arg2) >= 5)
544 do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
545
546 if (GET_LMASK64(arg2) >= 6)
547 do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
548
549 if (GET_LMASK64(arg2) == 7)
550 do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
551 }
552 #endif /* TARGET_MIPS64 */
553
554 #ifndef CONFIG_USER_ONLY
555 /* CP0 helpers */
556 target_ulong helper_mfc0_mvpcontrol (void)
557 {
558 return env->mvp->CP0_MVPControl;
559 }
560
561 target_ulong helper_mfc0_mvpconf0 (void)
562 {
563 return env->mvp->CP0_MVPConf0;
564 }
565
566 target_ulong helper_mfc0_mvpconf1 (void)
567 {
568 return env->mvp->CP0_MVPConf1;
569 }
570
571 target_ulong helper_mfc0_random (void)
572 {
573 return (int32_t)cpu_mips_get_random(env);
574 }
575
576 target_ulong helper_mfc0_tcstatus (void)
577 {
578 return env->active_tc.CP0_TCStatus;
579 }
580
581 target_ulong helper_mftc0_tcstatus(void)
582 {
583 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
584
585 if (other_tc == env->current_tc)
586 return env->active_tc.CP0_TCStatus;
587 else
588 return env->tcs[other_tc].CP0_TCStatus;
589 }
590
591 target_ulong helper_mfc0_tcbind (void)
592 {
593 return env->active_tc.CP0_TCBind;
594 }
595
596 target_ulong helper_mftc0_tcbind(void)
597 {
598 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
599
600 if (other_tc == env->current_tc)
601 return env->active_tc.CP0_TCBind;
602 else
603 return env->tcs[other_tc].CP0_TCBind;
604 }
605
606 target_ulong helper_mfc0_tcrestart (void)
607 {
608 return env->active_tc.PC;
609 }
610
611 target_ulong helper_mftc0_tcrestart(void)
612 {
613 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
614
615 if (other_tc == env->current_tc)
616 return env->active_tc.PC;
617 else
618 return env->tcs[other_tc].PC;
619 }
620
621 target_ulong helper_mfc0_tchalt (void)
622 {
623 return env->active_tc.CP0_TCHalt;
624 }
625
626 target_ulong helper_mftc0_tchalt(void)
627 {
628 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
629
630 if (other_tc == env->current_tc)
631 return env->active_tc.CP0_TCHalt;
632 else
633 return env->tcs[other_tc].CP0_TCHalt;
634 }
635
636 target_ulong helper_mfc0_tccontext (void)
637 {
638 return env->active_tc.CP0_TCContext;
639 }
640
641 target_ulong helper_mftc0_tccontext(void)
642 {
643 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
644
645 if (other_tc == env->current_tc)
646 return env->active_tc.CP0_TCContext;
647 else
648 return env->tcs[other_tc].CP0_TCContext;
649 }
650
651 target_ulong helper_mfc0_tcschedule (void)
652 {
653 return env->active_tc.CP0_TCSchedule;
654 }
655
656 target_ulong helper_mftc0_tcschedule(void)
657 {
658 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
659
660 if (other_tc == env->current_tc)
661 return env->active_tc.CP0_TCSchedule;
662 else
663 return env->tcs[other_tc].CP0_TCSchedule;
664 }
665
666 target_ulong helper_mfc0_tcschefback (void)
667 {
668 return env->active_tc.CP0_TCScheFBack;
669 }
670
671 target_ulong helper_mftc0_tcschefback(void)
672 {
673 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
674
675 if (other_tc == env->current_tc)
676 return env->active_tc.CP0_TCScheFBack;
677 else
678 return env->tcs[other_tc].CP0_TCScheFBack;
679 }
680
681 target_ulong helper_mfc0_count (void)
682 {
683 return (int32_t)cpu_mips_get_count(env);
684 }
685
686 target_ulong helper_mftc0_entryhi(void)
687 {
688 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
689 int32_t tcstatus;
690
691 if (other_tc == env->current_tc)
692 tcstatus = env->active_tc.CP0_TCStatus;
693 else
694 tcstatus = env->tcs[other_tc].CP0_TCStatus;
695
696 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
697 }
698
699 target_ulong helper_mftc0_status(void)
700 {
701 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
702 target_ulong t0;
703 int32_t tcstatus;
704
705 if (other_tc == env->current_tc)
706 tcstatus = env->active_tc.CP0_TCStatus;
707 else
708 tcstatus = env->tcs[other_tc].CP0_TCStatus;
709
710 t0 = env->CP0_Status & ~0xf1000018;
711 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
712 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
713 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
714
715 return t0;
716 }
717
718 target_ulong helper_mfc0_lladdr (void)
719 {
720 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
721 }
722
723 target_ulong helper_mfc0_watchlo (uint32_t sel)
724 {
725 return (int32_t)env->CP0_WatchLo[sel];
726 }
727
728 target_ulong helper_mfc0_watchhi (uint32_t sel)
729 {
730 return env->CP0_WatchHi[sel];
731 }
732
733 target_ulong helper_mfc0_debug (void)
734 {
735 target_ulong t0 = env->CP0_Debug;
736 if (env->hflags & MIPS_HFLAG_DM)
737 t0 |= 1 << CP0DB_DM;
738
739 return t0;
740 }
741
742 target_ulong helper_mftc0_debug(void)
743 {
744 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
745 int32_t tcstatus;
746
747 if (other_tc == env->current_tc)
748 tcstatus = env->active_tc.CP0_Debug_tcstatus;
749 else
750 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
751
752 /* XXX: Might be wrong, check with EJTAG spec. */
753 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
754 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
755 }
756
757 #if defined(TARGET_MIPS64)
758 target_ulong helper_dmfc0_tcrestart (void)
759 {
760 return env->active_tc.PC;
761 }
762
763 target_ulong helper_dmfc0_tchalt (void)
764 {
765 return env->active_tc.CP0_TCHalt;
766 }
767
768 target_ulong helper_dmfc0_tccontext (void)
769 {
770 return env->active_tc.CP0_TCContext;
771 }
772
773 target_ulong helper_dmfc0_tcschedule (void)
774 {
775 return env->active_tc.CP0_TCSchedule;
776 }
777
778 target_ulong helper_dmfc0_tcschefback (void)
779 {
780 return env->active_tc.CP0_TCScheFBack;
781 }
782
783 target_ulong helper_dmfc0_lladdr (void)
784 {
785 return env->lladdr >> env->CP0_LLAddr_shift;
786 }
787
788 target_ulong helper_dmfc0_watchlo (uint32_t sel)
789 {
790 return env->CP0_WatchLo[sel];
791 }
792 #endif /* TARGET_MIPS64 */
793
794 void helper_mtc0_index (target_ulong arg1)
795 {
796 int num = 1;
797 unsigned int tmp = env->tlb->nb_tlb;
798
799 do {
800 tmp >>= 1;
801 num <<= 1;
802 } while (tmp);
803 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
804 }
805
806 void helper_mtc0_mvpcontrol (target_ulong arg1)
807 {
808 uint32_t mask = 0;
809 uint32_t newval;
810
811 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
812 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
813 (1 << CP0MVPCo_EVP);
814 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
815 mask |= (1 << CP0MVPCo_STLB);
816 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
817
818 // TODO: Enable/disable shared TLB, enable/disable VPEs.
819
820 env->mvp->CP0_MVPControl = newval;
821 }
822
823 void helper_mtc0_vpecontrol (target_ulong arg1)
824 {
825 uint32_t mask;
826 uint32_t newval;
827
828 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
829 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
830 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
831
832 /* Yield scheduler intercept not implemented. */
833 /* Gating storage scheduler intercept not implemented. */
834
835 // TODO: Enable/disable TCs.
836
837 env->CP0_VPEControl = newval;
838 }
839
840 void helper_mtc0_vpeconf0 (target_ulong arg1)
841 {
842 uint32_t mask = 0;
843 uint32_t newval;
844
845 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
846 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
847 mask |= (0xff << CP0VPEC0_XTC);
848 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
849 }
850 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
851
852 // TODO: TC exclusive handling due to ERL/EXL.
853
854 env->CP0_VPEConf0 = newval;
855 }
856
857 void helper_mtc0_vpeconf1 (target_ulong arg1)
858 {
859 uint32_t mask = 0;
860 uint32_t newval;
861
862 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
863 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
864 (0xff << CP0VPEC1_NCP1);
865 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
866
867 /* UDI not implemented. */
868 /* CP2 not implemented. */
869
870 // TODO: Handle FPU (CP1) binding.
871
872 env->CP0_VPEConf1 = newval;
873 }
874
875 void helper_mtc0_yqmask (target_ulong arg1)
876 {
877 /* Yield qualifier inputs not implemented. */
878 env->CP0_YQMask = 0x00000000;
879 }
880
881 void helper_mtc0_vpeopt (target_ulong arg1)
882 {
883 env->CP0_VPEOpt = arg1 & 0x0000ffff;
884 }
885
886 void helper_mtc0_entrylo0 (target_ulong arg1)
887 {
888 /* Large physaddr (PABITS) not implemented */
889 /* 1k pages not implemented */
890 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
891 }
892
893 void helper_mtc0_tcstatus (target_ulong arg1)
894 {
895 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
896 uint32_t newval;
897
898 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
899
900 // TODO: Sync with CP0_Status.
901
902 env->active_tc.CP0_TCStatus = newval;
903 }
904
905 void helper_mttc0_tcstatus (target_ulong arg1)
906 {
907 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
908
909 // TODO: Sync with CP0_Status.
910
911 if (other_tc == env->current_tc)
912 env->active_tc.CP0_TCStatus = arg1;
913 else
914 env->tcs[other_tc].CP0_TCStatus = arg1;
915 }
916
917 void helper_mtc0_tcbind (target_ulong arg1)
918 {
919 uint32_t mask = (1 << CP0TCBd_TBE);
920 uint32_t newval;
921
922 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
923 mask |= (1 << CP0TCBd_CurVPE);
924 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
925 env->active_tc.CP0_TCBind = newval;
926 }
927
928 void helper_mttc0_tcbind (target_ulong arg1)
929 {
930 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
931 uint32_t mask = (1 << CP0TCBd_TBE);
932 uint32_t newval;
933
934 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
935 mask |= (1 << CP0TCBd_CurVPE);
936 if (other_tc == env->current_tc) {
937 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
938 env->active_tc.CP0_TCBind = newval;
939 } else {
940 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
941 env->tcs[other_tc].CP0_TCBind = newval;
942 }
943 }
944
945 void helper_mtc0_tcrestart (target_ulong arg1)
946 {
947 env->active_tc.PC = arg1;
948 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
949 env->lladdr = 0ULL;
950 /* MIPS16 not implemented. */
951 }
952
953 void helper_mttc0_tcrestart (target_ulong arg1)
954 {
955 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
956
957 if (other_tc == env->current_tc) {
958 env->active_tc.PC = arg1;
959 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
960 env->lladdr = 0ULL;
961 /* MIPS16 not implemented. */
962 } else {
963 env->tcs[other_tc].PC = arg1;
964 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
965 env->lladdr = 0ULL;
966 /* MIPS16 not implemented. */
967 }
968 }
969
970 void helper_mtc0_tchalt (target_ulong arg1)
971 {
972 env->active_tc.CP0_TCHalt = arg1 & 0x1;
973
974 // TODO: Halt TC / Restart (if allocated+active) TC.
975 }
976
977 void helper_mttc0_tchalt (target_ulong arg1)
978 {
979 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
980
981 // TODO: Halt TC / Restart (if allocated+active) TC.
982
983 if (other_tc == env->current_tc)
984 env->active_tc.CP0_TCHalt = arg1;
985 else
986 env->tcs[other_tc].CP0_TCHalt = arg1;
987 }
988
989 void helper_mtc0_tccontext (target_ulong arg1)
990 {
991 env->active_tc.CP0_TCContext = arg1;
992 }
993
994 void helper_mttc0_tccontext (target_ulong arg1)
995 {
996 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
997
998 if (other_tc == env->current_tc)
999 env->active_tc.CP0_TCContext = arg1;
1000 else
1001 env->tcs[other_tc].CP0_TCContext = arg1;
1002 }
1003
1004 void helper_mtc0_tcschedule (target_ulong arg1)
1005 {
1006 env->active_tc.CP0_TCSchedule = arg1;
1007 }
1008
1009 void helper_mttc0_tcschedule (target_ulong arg1)
1010 {
1011 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1012
1013 if (other_tc == env->current_tc)
1014 env->active_tc.CP0_TCSchedule = arg1;
1015 else
1016 env->tcs[other_tc].CP0_TCSchedule = arg1;
1017 }
1018
1019 void helper_mtc0_tcschefback (target_ulong arg1)
1020 {
1021 env->active_tc.CP0_TCScheFBack = arg1;
1022 }
1023
1024 void helper_mttc0_tcschefback (target_ulong arg1)
1025 {
1026 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1027
1028 if (other_tc == env->current_tc)
1029 env->active_tc.CP0_TCScheFBack = arg1;
1030 else
1031 env->tcs[other_tc].CP0_TCScheFBack = arg1;
1032 }
1033
1034 void helper_mtc0_entrylo1 (target_ulong arg1)
1035 {
1036 /* Large physaddr (PABITS) not implemented */
1037 /* 1k pages not implemented */
1038 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1039 }
1040
1041 void helper_mtc0_context (target_ulong arg1)
1042 {
1043 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1044 }
1045
1046 void helper_mtc0_pagemask (target_ulong arg1)
1047 {
1048 /* 1k pages not implemented */
1049 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1050 }
1051
1052 void helper_mtc0_pagegrain (target_ulong arg1)
1053 {
1054 /* SmartMIPS not implemented */
1055 /* Large physaddr (PABITS) not implemented */
1056 /* 1k pages not implemented */
1057 env->CP0_PageGrain = 0;
1058 }
1059
1060 void helper_mtc0_wired (target_ulong arg1)
1061 {
1062 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1063 }
1064
1065 void helper_mtc0_srsconf0 (target_ulong arg1)
1066 {
1067 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1068 }
1069
1070 void helper_mtc0_srsconf1 (target_ulong arg1)
1071 {
1072 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1073 }
1074
1075 void helper_mtc0_srsconf2 (target_ulong arg1)
1076 {
1077 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1078 }
1079
1080 void helper_mtc0_srsconf3 (target_ulong arg1)
1081 {
1082 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1083 }
1084
1085 void helper_mtc0_srsconf4 (target_ulong arg1)
1086 {
1087 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1088 }
1089
1090 void helper_mtc0_hwrena (target_ulong arg1)
1091 {
1092 env->CP0_HWREna = arg1 & 0x0000000F;
1093 }
1094
1095 void helper_mtc0_count (target_ulong arg1)
1096 {
1097 cpu_mips_store_count(env, arg1);
1098 }
1099
1100 void helper_mtc0_entryhi (target_ulong arg1)
1101 {
1102 target_ulong old, val;
1103
1104 /* 1k pages not implemented */
1105 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1106 #if defined(TARGET_MIPS64)
1107 val &= env->SEGMask;
1108 #endif
1109 old = env->CP0_EntryHi;
1110 env->CP0_EntryHi = val;
1111 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1112 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1113 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
1114 }
1115 /* If the ASID changes, flush qemu's TLB. */
1116 if ((old & 0xFF) != (val & 0xFF))
1117 cpu_mips_tlb_flush(env, 1);
1118 }
1119
1120 void helper_mttc0_entryhi(target_ulong arg1)
1121 {
1122 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1123 int32_t tcstatus;
1124
1125 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
1126 if (other_tc == env->current_tc) {
1127 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1128 env->active_tc.CP0_TCStatus = tcstatus;
1129 } else {
1130 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1131 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1132 }
1133 }
1134
1135 void helper_mtc0_compare (target_ulong arg1)
1136 {
1137 cpu_mips_store_compare(env, arg1);
1138 }
1139
1140 void helper_mtc0_status (target_ulong arg1)
1141 {
1142 uint32_t val, old;
1143 uint32_t mask = env->CP0_Status_rw_bitmask;
1144
1145 val = arg1 & mask;
1146 old = env->CP0_Status;
1147 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1148 compute_hflags(env);
1149 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1150 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1151 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1152 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1153 env->CP0_Cause);
1154 switch (env->hflags & MIPS_HFLAG_KSU) {
1155 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1156 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1157 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1158 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1159 }
1160 }
1161 cpu_mips_update_irq(env);
1162 }
1163
1164 void helper_mttc0_status(target_ulong arg1)
1165 {
1166 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1167 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
1168
1169 env->CP0_Status = arg1 & ~0xf1000018;
1170 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
1171 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1172 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1173 if (other_tc == env->current_tc)
1174 env->active_tc.CP0_TCStatus = tcstatus;
1175 else
1176 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1177 }
1178
1179 void helper_mtc0_intctl (target_ulong arg1)
1180 {
1181 /* vectored interrupts not implemented, no performance counters. */
1182 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
1183 }
1184
1185 void helper_mtc0_srsctl (target_ulong arg1)
1186 {
1187 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1188 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1189 }
1190
1191 void helper_mtc0_cause (target_ulong arg1)
1192 {
1193 uint32_t mask = 0x00C00300;
1194 uint32_t old = env->CP0_Cause;
1195
1196 if (env->insn_flags & ISA_MIPS32R2)
1197 mask |= 1 << CP0Ca_DC;
1198
1199 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
1200
1201 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1202 if (env->CP0_Cause & (1 << CP0Ca_DC))
1203 cpu_mips_stop_count(env);
1204 else
1205 cpu_mips_start_count(env);
1206 }
1207
1208 /* Handle the software interrupt as an hardware one, as they
1209 are very similar */
1210 if (arg1 & CP0Ca_IP_mask) {
1211 cpu_mips_update_irq(env);
1212 }
1213 }
1214
1215 void helper_mtc0_ebase (target_ulong arg1)
1216 {
1217 /* vectored interrupts not implemented */
1218 /* Multi-CPU not implemented */
1219 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
1220 }
1221
1222 void helper_mtc0_config0 (target_ulong arg1)
1223 {
1224 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1225 }
1226
1227 void helper_mtc0_config2 (target_ulong arg1)
1228 {
1229 /* tertiary/secondary caches not implemented */
1230 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1231 }
1232
1233 void helper_mtc0_lladdr (target_ulong arg1)
1234 {
1235 target_long mask = env->CP0_LLAddr_rw_bitmask;
1236 arg1 = arg1 << env->CP0_LLAddr_shift;
1237 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1238 }
1239
1240 void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
1241 {
1242 /* Watch exceptions for instructions, data loads, data stores
1243 not implemented. */
1244 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1245 }
1246
1247 void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
1248 {
1249 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1250 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1251 }
1252
1253 void helper_mtc0_xcontext (target_ulong arg1)
1254 {
1255 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1256 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1257 }
1258
1259 void helper_mtc0_framemask (target_ulong arg1)
1260 {
1261 env->CP0_Framemask = arg1; /* XXX */
1262 }
1263
1264 void helper_mtc0_debug (target_ulong arg1)
1265 {
1266 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1267 if (arg1 & (1 << CP0DB_DM))
1268 env->hflags |= MIPS_HFLAG_DM;
1269 else
1270 env->hflags &= ~MIPS_HFLAG_DM;
1271 }
1272
1273 void helper_mttc0_debug(target_ulong arg1)
1274 {
1275 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1276 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1277
1278 /* XXX: Might be wrong, check with EJTAG spec. */
1279 if (other_tc == env->current_tc)
1280 env->active_tc.CP0_Debug_tcstatus = val;
1281 else
1282 env->tcs[other_tc].CP0_Debug_tcstatus = val;
1283 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1284 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1285 }
1286
1287 void helper_mtc0_performance0 (target_ulong arg1)
1288 {
1289 env->CP0_Performance0 = arg1 & 0x000007ff;
1290 }
1291
1292 void helper_mtc0_taglo (target_ulong arg1)
1293 {
1294 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1295 }
1296
1297 void helper_mtc0_datalo (target_ulong arg1)
1298 {
1299 env->CP0_DataLo = arg1; /* XXX */
1300 }
1301
1302 void helper_mtc0_taghi (target_ulong arg1)
1303 {
1304 env->CP0_TagHi = arg1; /* XXX */
1305 }
1306
1307 void helper_mtc0_datahi (target_ulong arg1)
1308 {
1309 env->CP0_DataHi = arg1; /* XXX */
1310 }
1311
1312 /* MIPS MT functions */
1313 target_ulong helper_mftgpr(uint32_t sel)
1314 {
1315 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1316
1317 if (other_tc == env->current_tc)
1318 return env->active_tc.gpr[sel];
1319 else
1320 return env->tcs[other_tc].gpr[sel];
1321 }
1322
1323 target_ulong helper_mftlo(uint32_t sel)
1324 {
1325 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1326
1327 if (other_tc == env->current_tc)
1328 return env->active_tc.LO[sel];
1329 else
1330 return env->tcs[other_tc].LO[sel];
1331 }
1332
1333 target_ulong helper_mfthi(uint32_t sel)
1334 {
1335 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1336
1337 if (other_tc == env->current_tc)
1338 return env->active_tc.HI[sel];
1339 else
1340 return env->tcs[other_tc].HI[sel];
1341 }
1342
1343 target_ulong helper_mftacx(uint32_t sel)
1344 {
1345 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1346
1347 if (other_tc == env->current_tc)
1348 return env->active_tc.ACX[sel];
1349 else
1350 return env->tcs[other_tc].ACX[sel];
1351 }
1352
1353 target_ulong helper_mftdsp(void)
1354 {
1355 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1356
1357 if (other_tc == env->current_tc)
1358 return env->active_tc.DSPControl;
1359 else
1360 return env->tcs[other_tc].DSPControl;
1361 }
1362
1363 void helper_mttgpr(target_ulong arg1, uint32_t sel)
1364 {
1365 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1366
1367 if (other_tc == env->current_tc)
1368 env->active_tc.gpr[sel] = arg1;
1369 else
1370 env->tcs[other_tc].gpr[sel] = arg1;
1371 }
1372
1373 void helper_mttlo(target_ulong arg1, uint32_t sel)
1374 {
1375 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1376
1377 if (other_tc == env->current_tc)
1378 env->active_tc.LO[sel] = arg1;
1379 else
1380 env->tcs[other_tc].LO[sel] = arg1;
1381 }
1382
1383 void helper_mtthi(target_ulong arg1, uint32_t sel)
1384 {
1385 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1386
1387 if (other_tc == env->current_tc)
1388 env->active_tc.HI[sel] = arg1;
1389 else
1390 env->tcs[other_tc].HI[sel] = arg1;
1391 }
1392
1393 void helper_mttacx(target_ulong arg1, uint32_t sel)
1394 {
1395 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1396
1397 if (other_tc == env->current_tc)
1398 env->active_tc.ACX[sel] = arg1;
1399 else
1400 env->tcs[other_tc].ACX[sel] = arg1;
1401 }
1402
1403 void helper_mttdsp(target_ulong arg1)
1404 {
1405 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1406
1407 if (other_tc == env->current_tc)
1408 env->active_tc.DSPControl = arg1;
1409 else
1410 env->tcs[other_tc].DSPControl = arg1;
1411 }
1412
1413 /* MIPS MT functions */
1414 target_ulong helper_dmt(target_ulong arg1)
1415 {
1416 // TODO
1417 arg1 = 0;
1418 // rt = arg1
1419
1420 return arg1;
1421 }
1422
1423 target_ulong helper_emt(target_ulong arg1)
1424 {
1425 // TODO
1426 arg1 = 0;
1427 // rt = arg1
1428
1429 return arg1;
1430 }
1431
1432 target_ulong helper_dvpe(target_ulong arg1)
1433 {
1434 // TODO
1435 arg1 = 0;
1436 // rt = arg1
1437
1438 return arg1;
1439 }
1440
1441 target_ulong helper_evpe(target_ulong arg1)
1442 {
1443 // TODO
1444 arg1 = 0;
1445 // rt = arg1
1446
1447 return arg1;
1448 }
1449 #endif /* !CONFIG_USER_ONLY */
1450
1451 void helper_fork(target_ulong arg1, target_ulong arg2)
1452 {
1453 // arg1 = rt, arg2 = rs
1454 arg1 = 0;
1455 // TODO: store to TC register
1456 }
1457
1458 target_ulong helper_yield(target_ulong arg1)
1459 {
1460 if (arg1 < 0) {
1461 /* No scheduling policy implemented. */
1462 if (arg1 != -2) {
1463 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1464 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1465 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1466 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1467 helper_raise_exception(EXCP_THREAD);
1468 }
1469 }
1470 } else if (arg1 == 0) {
1471 if (0 /* TODO: TC underflow */) {
1472 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1473 helper_raise_exception(EXCP_THREAD);
1474 } else {
1475 // TODO: Deallocate TC
1476 }
1477 } else if (arg1 > 0) {
1478 /* Yield qualifier inputs not implemented. */
1479 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1480 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1481 helper_raise_exception(EXCP_THREAD);
1482 }
1483 return env->CP0_YQMask;
1484 }
1485
1486 #ifndef CONFIG_USER_ONLY
1487 /* TLB management */
1488 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1489 {
1490 /* Flush qemu's TLB and discard all shadowed entries. */
1491 tlb_flush (env, flush_global);
1492 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1493 }
1494
1495 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
1496 {
1497 /* Discard entries from env->tlb[first] onwards. */
1498 while (env->tlb->tlb_in_use > first) {
1499 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1500 }
1501 }
1502
1503 static void r4k_fill_tlb (int idx)
1504 {
1505 r4k_tlb_t *tlb;
1506
1507 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1508 tlb = &env->tlb->mmu.r4k.tlb[idx];
1509 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1510 #if defined(TARGET_MIPS64)
1511 tlb->VPN &= env->SEGMask;
1512 #endif
1513 tlb->ASID = env->CP0_EntryHi & 0xFF;
1514 tlb->PageMask = env->CP0_PageMask;
1515 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1516 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1517 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1518 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1519 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1520 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1521 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1522 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1523 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1524 }
1525
1526 void r4k_helper_tlbwi (void)
1527 {
1528 int idx;
1529
1530 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1531
1532 /* Discard cached TLB entries. We could avoid doing this if the
1533 tlbwi is just upgrading access permissions on the current entry;
1534 that might be a further win. */
1535 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
1536
1537 r4k_invalidate_tlb(env, idx, 0);
1538 r4k_fill_tlb(idx);
1539 }
1540
1541 void r4k_helper_tlbwr (void)
1542 {
1543 int r = cpu_mips_get_random(env);
1544
1545 r4k_invalidate_tlb(env, r, 1);
1546 r4k_fill_tlb(r);
1547 }
1548
1549 void r4k_helper_tlbp (void)
1550 {
1551 r4k_tlb_t *tlb;
1552 target_ulong mask;
1553 target_ulong tag;
1554 target_ulong VPN;
1555 uint8_t ASID;
1556 int i;
1557
1558 ASID = env->CP0_EntryHi & 0xFF;
1559 for (i = 0; i < env->tlb->nb_tlb; i++) {
1560 tlb = &env->tlb->mmu.r4k.tlb[i];
1561 /* 1k pages are not supported. */
1562 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1563 tag = env->CP0_EntryHi & ~mask;
1564 VPN = tlb->VPN & ~mask;
1565 /* Check ASID, virtual page number & size */
1566 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1567 /* TLB match */
1568 env->CP0_Index = i;
1569 break;
1570 }
1571 }
1572 if (i == env->tlb->nb_tlb) {
1573 /* No match. Discard any shadow entries, if any of them match. */
1574 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1575 tlb = &env->tlb->mmu.r4k.tlb[i];
1576 /* 1k pages are not supported. */
1577 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1578 tag = env->CP0_EntryHi & ~mask;
1579 VPN = tlb->VPN & ~mask;
1580 /* Check ASID, virtual page number & size */
1581 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1582 r4k_mips_tlb_flush_extra (env, i);
1583 break;
1584 }
1585 }
1586
1587 env->CP0_Index |= 0x80000000;
1588 }
1589 }
1590
1591 void r4k_helper_tlbr (void)
1592 {
1593 r4k_tlb_t *tlb;
1594 uint8_t ASID;
1595 int idx;
1596
1597 ASID = env->CP0_EntryHi & 0xFF;
1598 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1599 tlb = &env->tlb->mmu.r4k.tlb[idx];
1600
1601 /* If this will change the current ASID, flush qemu's TLB. */
1602 if (ASID != tlb->ASID)
1603 cpu_mips_tlb_flush (env, 1);
1604
1605 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1606
1607 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1608 env->CP0_PageMask = tlb->PageMask;
1609 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1610 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1611 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1612 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1613 }
1614
1615 void helper_tlbwi(void)
1616 {
1617 env->tlb->helper_tlbwi();
1618 }
1619
1620 void helper_tlbwr(void)
1621 {
1622 env->tlb->helper_tlbwr();
1623 }
1624
1625 void helper_tlbp(void)
1626 {
1627 env->tlb->helper_tlbp();
1628 }
1629
1630 void helper_tlbr(void)
1631 {
1632 env->tlb->helper_tlbr();
1633 }
1634
1635 /* Specials */
1636 target_ulong helper_di (void)
1637 {
1638 target_ulong t0 = env->CP0_Status;
1639
1640 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1641 cpu_mips_update_irq(env);
1642
1643 return t0;
1644 }
1645
1646 target_ulong helper_ei (void)
1647 {
1648 target_ulong t0 = env->CP0_Status;
1649
1650 env->CP0_Status = t0 | (1 << CP0St_IE);
1651 cpu_mips_update_irq(env);
1652
1653 return t0;
1654 }
1655
1656 static void debug_pre_eret (void)
1657 {
1658 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1659 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1660 env->active_tc.PC, env->CP0_EPC);
1661 if (env->CP0_Status & (1 << CP0St_ERL))
1662 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1663 if (env->hflags & MIPS_HFLAG_DM)
1664 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1665 qemu_log("\n");
1666 }
1667 }
1668
1669 static void debug_post_eret (void)
1670 {
1671 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1672 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1673 env->active_tc.PC, env->CP0_EPC);
1674 if (env->CP0_Status & (1 << CP0St_ERL))
1675 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1676 if (env->hflags & MIPS_HFLAG_DM)
1677 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1678 switch (env->hflags & MIPS_HFLAG_KSU) {
1679 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1680 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1681 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1682 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1683 }
1684 }
1685 }
1686
1687 static void set_pc (target_ulong error_pc)
1688 {
1689 env->active_tc.PC = error_pc & ~(target_ulong)1;
1690 if (error_pc & 1) {
1691 env->hflags |= MIPS_HFLAG_M16;
1692 } else {
1693 env->hflags &= ~(MIPS_HFLAG_M16);
1694 }
1695 }
1696
1697 void helper_eret (void)
1698 {
1699 debug_pre_eret();
1700 if (env->CP0_Status & (1 << CP0St_ERL)) {
1701 set_pc(env->CP0_ErrorEPC);
1702 env->CP0_Status &= ~(1 << CP0St_ERL);
1703 } else {
1704 set_pc(env->CP0_EPC);
1705 env->CP0_Status &= ~(1 << CP0St_EXL);
1706 }
1707 compute_hflags(env);
1708 debug_post_eret();
1709 env->lladdr = 1;
1710 }
1711
1712 void helper_deret (void)
1713 {
1714 debug_pre_eret();
1715 set_pc(env->CP0_DEPC);
1716
1717 env->hflags &= MIPS_HFLAG_DM;
1718 compute_hflags(env);
1719 debug_post_eret();
1720 env->lladdr = 1;
1721 }
1722 #endif /* !CONFIG_USER_ONLY */
1723
1724 target_ulong helper_rdhwr_cpunum(void)
1725 {
1726 if ((env->hflags & MIPS_HFLAG_CP0) ||
1727 (env->CP0_HWREna & (1 << 0)))
1728 return env->CP0_EBase & 0x3ff;
1729 else
1730 helper_raise_exception(EXCP_RI);
1731
1732 return 0;
1733 }
1734
1735 target_ulong helper_rdhwr_synci_step(void)
1736 {
1737 if ((env->hflags & MIPS_HFLAG_CP0) ||
1738 (env->CP0_HWREna & (1 << 1)))
1739 return env->SYNCI_Step;
1740 else
1741 helper_raise_exception(EXCP_RI);
1742
1743 return 0;
1744 }
1745
1746 target_ulong helper_rdhwr_cc(void)
1747 {
1748 if ((env->hflags & MIPS_HFLAG_CP0) ||
1749 (env->CP0_HWREna & (1 << 2)))
1750 return env->CP0_Count;
1751 else
1752 helper_raise_exception(EXCP_RI);
1753
1754 return 0;
1755 }
1756
1757 target_ulong helper_rdhwr_ccres(void)
1758 {
1759 if ((env->hflags & MIPS_HFLAG_CP0) ||
1760 (env->CP0_HWREna & (1 << 3)))
1761 return env->CCRes;
1762 else
1763 helper_raise_exception(EXCP_RI);
1764
1765 return 0;
1766 }
1767
1768 void helper_pmon (int function)
1769 {
1770 function /= 2;
1771 switch (function) {
1772 case 2: /* TODO: char inbyte(int waitflag); */
1773 if (env->active_tc.gpr[4] == 0)
1774 env->active_tc.gpr[2] = -1;
1775 /* Fall through */
1776 case 11: /* TODO: char inbyte (void); */
1777 env->active_tc.gpr[2] = -1;
1778 break;
1779 case 3:
1780 case 12:
1781 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
1782 break;
1783 case 17:
1784 break;
1785 case 158:
1786 {
1787 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
1788 printf("%s", fmt);
1789 }
1790 break;
1791 }
1792 }
1793
1794 void helper_wait (void)
1795 {
1796 env->halted = 1;
1797 helper_raise_exception(EXCP_HLT);
1798 }
1799
1800 #if !defined(CONFIG_USER_ONLY)
1801
1802 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1803
1804 #define MMUSUFFIX _mmu
1805 #define ALIGNED_ONLY
1806
1807 #define SHIFT 0
1808 #include "softmmu_template.h"
1809
1810 #define SHIFT 1
1811 #include "softmmu_template.h"
1812
1813 #define SHIFT 2
1814 #include "softmmu_template.h"
1815
1816 #define SHIFT 3
1817 #include "softmmu_template.h"
1818
1819 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1820 {
1821 env->CP0_BadVAddr = addr;
1822 do_restore_state (retaddr);
1823 helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1824 }
1825
1826 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1827 {
1828 TranslationBlock *tb;
1829 CPUState *saved_env;
1830 unsigned long pc;
1831 int ret;
1832
1833 /* XXX: hack to restore env in all cases, even if not called from
1834 generated code */
1835 saved_env = env;
1836 env = cpu_single_env;
1837 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1838 if (ret) {
1839 if (retaddr) {
1840 /* now we have a real cpu fault */
1841 pc = (unsigned long)retaddr;
1842 tb = tb_find_pc(pc);
1843 if (tb) {
1844 /* the PC is inside the translated code. It means that we have
1845 a virtual CPU fault */
1846 cpu_restore_state(tb, env, pc, NULL);
1847 }
1848 }
1849 helper_raise_exception_err(env->exception_index, env->error_code);
1850 }
1851 env = saved_env;
1852 }
1853
1854 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1855 int unused, int size)
1856 {
1857 if (is_exec)
1858 helper_raise_exception(EXCP_IBE);
1859 else
1860 helper_raise_exception(EXCP_DBE);
1861 }
1862 #endif /* !CONFIG_USER_ONLY */
1863
1864 /* Complex FPU operations which may need stack space. */
1865
1866 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1867 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1868 #define FLOAT_TWO32 make_float32(1 << 30)
1869 #define FLOAT_TWO64 make_float64(1ULL << 62)
1870 #define FLOAT_QNAN32 0x7fbfffff
1871 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1872 #define FLOAT_SNAN32 0x7fffffff
1873 #define FLOAT_SNAN64 0x7fffffffffffffffULL
1874
1875 /* convert MIPS rounding mode in FCR31 to IEEE library */
1876 static unsigned int ieee_rm[] = {
1877 float_round_nearest_even,
1878 float_round_to_zero,
1879 float_round_up,
1880 float_round_down
1881 };
1882
1883 #define RESTORE_ROUNDING_MODE \
1884 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1885
1886 #define RESTORE_FLUSH_MODE \
1887 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
1888
1889 target_ulong helper_cfc1 (uint32_t reg)
1890 {
1891 target_ulong arg1;
1892
1893 switch (reg) {
1894 case 0:
1895 arg1 = (int32_t)env->active_fpu.fcr0;
1896 break;
1897 case 25:
1898 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
1899 break;
1900 case 26:
1901 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
1902 break;
1903 case 28:
1904 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
1905 break;
1906 default:
1907 arg1 = (int32_t)env->active_fpu.fcr31;
1908 break;
1909 }
1910
1911 return arg1;
1912 }
1913
1914 void helper_ctc1 (target_ulong arg1, uint32_t reg)
1915 {
1916 switch(reg) {
1917 case 25:
1918 if (arg1 & 0xffffff00)
1919 return;
1920 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
1921 ((arg1 & 0x1) << 23);
1922 break;
1923 case 26:
1924 if (arg1 & 0x007c0000)
1925 return;
1926 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
1927 break;
1928 case 28:
1929 if (arg1 & 0x007c0000)
1930 return;
1931 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
1932 ((arg1 & 0x4) << 22);
1933 break;
1934 case 31:
1935 if (arg1 & 0x007c0000)
1936 return;
1937 env->active_fpu.fcr31 = arg1;
1938 break;
1939 default:
1940 return;
1941 }
1942 /* set rounding mode */
1943 RESTORE_ROUNDING_MODE;
1944 /* set flush-to-zero mode */
1945 RESTORE_FLUSH_MODE;
1946 set_float_exception_flags(0, &env->active_fpu.fp_status);
1947 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
1948 helper_raise_exception(EXCP_FPE);
1949 }
1950
1951 static inline char ieee_ex_to_mips(char xcpt)
1952 {
1953 return (xcpt & float_flag_inexact) >> 5 |
1954 (xcpt & float_flag_underflow) >> 3 |
1955 (xcpt & float_flag_overflow) >> 1 |
1956 (xcpt & float_flag_divbyzero) << 1 |
1957 (xcpt & float_flag_invalid) << 4;
1958 }
1959
1960 static inline char mips_ex_to_ieee(char xcpt)
1961 {
1962 return (xcpt & FP_INEXACT) << 5 |
1963 (xcpt & FP_UNDERFLOW) << 3 |
1964 (xcpt & FP_OVERFLOW) << 1 |
1965 (xcpt & FP_DIV0) >> 1 |
1966 (xcpt & FP_INVALID) >> 4;
1967 }
1968
1969 static inline void update_fcr31(void)
1970 {
1971 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
1972
1973 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
1974 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
1975 helper_raise_exception(EXCP_FPE);
1976 else
1977 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
1978 }
1979
1980 /* Float support.
1981 Single precition routines have a "s" suffix, double precision a
1982 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
1983 paired single lower "pl", paired single upper "pu". */
1984
1985 /* unary operations, modifying fp status */
1986 uint64_t helper_float_sqrt_d(uint64_t fdt0)
1987 {
1988 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
1989 }
1990
1991 uint32_t helper_float_sqrt_s(uint32_t fst0)
1992 {
1993 return float32_sqrt(fst0, &env->active_fpu.fp_status);
1994 }
1995
1996 uint64_t helper_float_cvtd_s(uint32_t fst0)
1997 {
1998 uint64_t fdt2;
1999
2000 set_float_exception_flags(0, &env->active_fpu.fp_status);
2001 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2002 update_fcr31();
2003 return fdt2;
2004 }
2005
2006 uint64_t helper_float_cvtd_w(uint32_t wt0)
2007 {
2008 uint64_t fdt2;
2009
2010 set_float_exception_flags(0, &env->active_fpu.fp_status);
2011 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2012 update_fcr31();
2013 return fdt2;
2014 }
2015
2016 uint64_t helper_float_cvtd_l(uint64_t dt0)
2017 {
2018 uint64_t fdt2;
2019
2020 set_float_exception_flags(0, &env->active_fpu.fp_status);
2021 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2022 update_fcr31();
2023 return fdt2;
2024 }
2025
2026 uint64_t helper_float_cvtl_d(uint64_t fdt0)
2027 {
2028 uint64_t dt2;
2029
2030 set_float_exception_flags(0, &env->active_fpu.fp_status);
2031 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2032 update_fcr31();
2033 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2034 dt2 = FLOAT_SNAN64;
2035 return dt2;
2036 }
2037
2038 uint64_t helper_float_cvtl_s(uint32_t fst0)
2039 {
2040 uint64_t dt2;
2041
2042 set_float_exception_flags(0, &env->active_fpu.fp_status);
2043 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2044 update_fcr31();
2045 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2046 dt2 = FLOAT_SNAN64;
2047 return dt2;
2048 }
2049
2050 uint64_t helper_float_cvtps_pw(uint64_t dt0)
2051 {
2052 uint32_t fst2;
2053 uint32_t fsth2;
2054
2055 set_float_exception_flags(0, &env->active_fpu.fp_status);
2056 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2057 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2058 update_fcr31();
2059 return ((uint64_t)fsth2 << 32) | fst2;
2060 }
2061
2062 uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
2063 {
2064 uint32_t wt2;
2065 uint32_t wth2;
2066
2067 set_float_exception_flags(0, &env->active_fpu.fp_status);
2068 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2069 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2070 update_fcr31();
2071 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2072 wt2 = FLOAT_SNAN32;
2073 wth2 = FLOAT_SNAN32;
2074 }
2075 return ((uint64_t)wth2 << 32) | wt2;
2076 }
2077
2078 uint32_t helper_float_cvts_d(uint64_t fdt0)
2079 {
2080 uint32_t fst2;
2081
2082 set_float_exception_flags(0, &env->active_fpu.fp_status);
2083 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2084 update_fcr31();
2085 return fst2;
2086 }
2087
2088 uint32_t helper_float_cvts_w(uint32_t wt0)
2089 {
2090 uint32_t fst2;
2091
2092 set_float_exception_flags(0, &env->active_fpu.fp_status);
2093 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2094 update_fcr31();
2095 return fst2;
2096 }
2097
2098 uint32_t helper_float_cvts_l(uint64_t dt0)
2099 {
2100 uint32_t fst2;
2101
2102 set_float_exception_flags(0, &env->active_fpu.fp_status);
2103 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2104 update_fcr31();
2105 return fst2;
2106 }
2107
2108 uint32_t helper_float_cvts_pl(uint32_t wt0)
2109 {
2110 uint32_t wt2;
2111
2112 set_float_exception_flags(0, &env->active_fpu.fp_status);
2113 wt2 = wt0;
2114 update_fcr31();
2115 return wt2;
2116 }
2117
2118 uint32_t helper_float_cvts_pu(uint32_t wth0)
2119 {
2120 uint32_t wt2;
2121
2122 set_float_exception_flags(0, &env->active_fpu.fp_status);
2123 wt2 = wth0;
2124 update_fcr31();
2125 return wt2;
2126 }
2127
2128 uint32_t helper_float_cvtw_s(uint32_t fst0)
2129 {
2130 uint32_t wt2;
2131
2132 set_float_exception_flags(0, &env->active_fpu.fp_status);
2133 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2134 update_fcr31();
2135 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2136 wt2 = FLOAT_SNAN32;
2137 return wt2;
2138 }
2139
2140 uint32_t helper_float_cvtw_d(uint64_t fdt0)
2141 {
2142 uint32_t wt2;
2143
2144 set_float_exception_flags(0, &env->active_fpu.fp_status);
2145 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2146 update_fcr31();
2147 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2148 wt2 = FLOAT_SNAN32;
2149 return wt2;
2150 }
2151
2152 uint64_t helper_float_roundl_d(uint64_t fdt0)
2153 {
2154 uint64_t dt2;
2155
2156 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2157 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2158 RESTORE_ROUNDING_MODE;
2159 update_fcr31();
2160 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2161 dt2 = FLOAT_SNAN64;
2162 return dt2;
2163 }
2164
2165 uint64_t helper_float_roundl_s(uint32_t fst0)
2166 {
2167 uint64_t dt2;
2168
2169 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2170 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2171 RESTORE_ROUNDING_MODE;
2172 update_fcr31();
2173 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2174 dt2 = FLOAT_SNAN64;
2175 return dt2;
2176 }
2177
2178 uint32_t helper_float_roundw_d(uint64_t fdt0)
2179 {
2180 uint32_t wt2;
2181
2182 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2183 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2184 RESTORE_ROUNDING_MODE;
2185 update_fcr31();
2186 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2187 wt2 = FLOAT_SNAN32;
2188 return wt2;
2189 }
2190
2191 uint32_t helper_float_roundw_s(uint32_t fst0)
2192 {
2193 uint32_t wt2;
2194
2195 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2196 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2197 RESTORE_ROUNDING_MODE;
2198 update_fcr31();
2199 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2200 wt2 = FLOAT_SNAN32;
2201 return wt2;
2202 }
2203
2204 uint64_t helper_float_truncl_d(uint64_t fdt0)
2205 {
2206 uint64_t dt2;
2207
2208 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2209 update_fcr31();
2210 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2211 dt2 = FLOAT_SNAN64;
2212 return dt2;
2213 }
2214
2215 uint64_t helper_float_truncl_s(uint32_t fst0)
2216 {
2217 uint64_t dt2;
2218
2219 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2220 update_fcr31();
2221 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2222 dt2 = FLOAT_SNAN64;
2223 return dt2;
2224 }
2225
2226 uint32_t helper_float_truncw_d(uint64_t fdt0)
2227 {
2228 uint32_t wt2;
2229
2230 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2231 update_fcr31();
2232 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2233 wt2 = FLOAT_SNAN32;
2234 return wt2;
2235 }
2236
2237 uint32_t helper_float_truncw_s(uint32_t fst0)
2238 {
2239 uint32_t wt2;
2240
2241 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2242 update_fcr31();
2243 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2244 wt2 = FLOAT_SNAN32;
2245 return wt2;
2246 }
2247
2248 uint64_t helper_float_ceill_d(uint64_t fdt0)
2249 {
2250 uint64_t dt2;
2251
2252 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2253 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2254 RESTORE_ROUNDING_MODE;
2255 update_fcr31();
2256 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2257 dt2 = FLOAT_SNAN64;
2258 return dt2;
2259 }
2260
2261 uint64_t helper_float_ceill_s(uint32_t fst0)
2262 {
2263 uint64_t dt2;
2264
2265 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2266 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2267 RESTORE_ROUNDING_MODE;
2268 update_fcr31();
2269 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2270 dt2 = FLOAT_SNAN64;
2271 return dt2;
2272 }
2273
2274 uint32_t helper_float_ceilw_d(uint64_t fdt0)
2275 {
2276 uint32_t wt2;
2277
2278 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2279 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2280 RESTORE_ROUNDING_MODE;
2281 update_fcr31();
2282 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2283 wt2 = FLOAT_SNAN32;
2284 return wt2;
2285 }
2286
2287 uint32_t helper_float_ceilw_s(uint32_t fst0)
2288 {
2289 uint32_t wt2;
2290
2291 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2292 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2293 RESTORE_ROUNDING_MODE;
2294 update_fcr31();
2295 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2296 wt2 = FLOAT_SNAN32;
2297 return wt2;
2298 }
2299
2300 uint64_t helper_float_floorl_d(uint64_t fdt0)
2301 {
2302 uint64_t dt2;
2303
2304 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2305 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2306 RESTORE_ROUNDING_MODE;
2307 update_fcr31();
2308 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2309 dt2 = FLOAT_SNAN64;
2310 return dt2;
2311 }
2312
2313 uint64_t helper_float_floorl_s(uint32_t fst0)
2314 {
2315 uint64_t dt2;
2316
2317 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2318 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2319 RESTORE_ROUNDING_MODE;
2320 update_fcr31();
2321 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2322 dt2 = FLOAT_SNAN64;
2323 return dt2;
2324 }
2325
2326 uint32_t helper_float_floorw_d(uint64_t fdt0)
2327 {
2328 uint32_t wt2;
2329
2330 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2331 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2332 RESTORE_ROUNDING_MODE;
2333 update_fcr31();
2334 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2335 wt2 = FLOAT_SNAN32;
2336 return wt2;
2337 }
2338
2339 uint32_t helper_float_floorw_s(uint32_t fst0)
2340 {
2341 uint32_t wt2;
2342
2343 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2344 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2345 RESTORE_ROUNDING_MODE;
2346 update_fcr31();
2347 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2348 wt2 = FLOAT_SNAN32;
2349 return wt2;
2350 }
2351
2352 /* unary operations, not modifying fp status */
2353 #define FLOAT_UNOP(name) \
2354 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2355 { \
2356 return float64_ ## name(fdt0); \
2357 } \
2358 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2359 { \
2360 return float32_ ## name(fst0); \
2361 } \
2362 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2363 { \
2364 uint32_t wt0; \
2365 uint32_t wth0; \
2366 \
2367 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2368 wth0 = float32_ ## name(fdt0 >> 32); \
2369 return ((uint64_t)wth0 << 32) | wt0; \
2370 }
2371 FLOAT_UNOP(abs)
2372 FLOAT_UNOP(chs)
2373 #undef FLOAT_UNOP
2374
2375 /* MIPS specific unary operations */
2376 uint64_t helper_float_recip_d(uint64_t fdt0)
2377 {
2378 uint64_t fdt2;
2379
2380 set_float_exception_flags(0, &env->active_fpu.fp_status);
2381 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2382 update_fcr31();
2383 return fdt2;
2384 }
2385
2386 uint32_t helper_float_recip_s(uint32_t fst0)
2387 {
2388 uint32_t fst2;
2389
2390 set_float_exception_flags(0, &env->active_fpu.fp_status);
2391 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2392 update_fcr31();
2393 return fst2;
2394 }
2395
2396 uint64_t helper_float_rsqrt_d(uint64_t fdt0)
2397 {
2398 uint64_t fdt2;
2399
2400 set_float_exception_flags(0, &env->active_fpu.fp_status);
2401 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2402 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2403 update_fcr31();
2404 return fdt2;
2405 }
2406
2407 uint32_t helper_float_rsqrt_s(uint32_t fst0)
2408 {
2409 uint32_t fst2;
2410
2411 set_float_exception_flags(0, &env->active_fpu.fp_status);
2412 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2413 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2414 update_fcr31();
2415 return fst2;
2416 }
2417
2418 uint64_t helper_float_recip1_d(uint64_t fdt0)
2419 {
2420 uint64_t fdt2;
2421
2422 set_float_exception_flags(0, &env->active_fpu.fp_status);
2423 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2424 update_fcr31();
2425 return fdt2;
2426 }
2427
2428 uint32_t helper_float_recip1_s(uint32_t fst0)
2429 {
2430 uint32_t fst2;
2431
2432 set_float_exception_flags(0, &env->active_fpu.fp_status);
2433 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2434 update_fcr31();
2435 return fst2;
2436 }
2437
2438 uint64_t helper_float_recip1_ps(uint64_t fdt0)
2439 {
2440 uint32_t fst2;
2441 uint32_t fsth2;
2442
2443 set_float_exception_flags(0, &env->active_fpu.fp_status);
2444 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2445 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2446 update_fcr31();
2447 return ((uint64_t)fsth2 << 32) | fst2;
2448 }
2449
2450 uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
2451 {
2452 uint64_t fdt2;
2453
2454 set_float_exception_flags(0, &env->active_fpu.fp_status);
2455 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2456 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2457 update_fcr31();
2458 return fdt2;
2459 }
2460
2461 uint32_t helper_float_rsqrt1_s(uint32_t fst0)
2462 {
2463 uint32_t fst2;
2464
2465 set_float_exception_flags(0, &env->active_fpu.fp_status);
2466 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2467 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2468 update_fcr31();
2469 return fst2;
2470 }
2471
2472 uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
2473 {
2474 uint32_t fst2;
2475 uint32_t fsth2;
2476
2477 set_float_exception_flags(0, &env->active_fpu.fp_status);
2478 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2479 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2480 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2481 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2482 update_fcr31();
2483 return ((uint64_t)fsth2 << 32) | fst2;
2484 }
2485
2486 #define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
2487
2488 /* binary operations */
2489 #define FLOAT_BINOP(name) \
2490 uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2491 { \
2492 uint64_t dt2; \
2493 \
2494 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2495 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2496 update_fcr31(); \
2497 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2498 dt2 = FLOAT_QNAN64; \
2499 return dt2; \
2500 } \
2501 \
2502 uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2503 { \
2504 uint32_t wt2; \
2505 \
2506 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2507 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2508 update_fcr31(); \
2509 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2510 wt2 = FLOAT_QNAN32; \
2511 return wt2; \
2512 } \
2513 \
2514 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
2515 { \
2516 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2517 uint32_t fsth0 = fdt0 >> 32; \
2518 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2519 uint32_t fsth1 = fdt1 >> 32; \
2520 uint32_t wt2; \
2521 uint32_t wth2; \
2522 \
2523 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2524 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2525 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2526 update_fcr31(); \
2527 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
2528 wt2 = FLOAT_QNAN32; \
2529 wth2 = FLOAT_QNAN32; \
2530 } \
2531 return ((uint64_t)wth2 << 32) | wt2; \
2532 }
2533
2534 FLOAT_BINOP(add)
2535 FLOAT_BINOP(sub)
2536 FLOAT_BINOP(mul)
2537 FLOAT_BINOP(div)
2538 #undef FLOAT_BINOP
2539
2540 /* ternary operations */
2541 #define FLOAT_TERNOP(name1, name2) \
2542 uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2543 uint64_t fdt2) \
2544 { \
2545 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2546 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2547 } \
2548 \
2549 uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2550 uint32_t fst2) \
2551 { \
2552 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2553 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2554 } \
2555 \
2556 uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2557 uint64_t fdt2) \
2558 { \
2559 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2560 uint32_t fsth0 = fdt0 >> 32; \
2561 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2562 uint32_t fsth1 = fdt1 >> 32; \
2563 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2564 uint32_t fsth2 = fdt2 >> 32; \
2565 \
2566 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2567 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2568 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2569 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2570 return ((uint64_t)fsth2 << 32) | fst2; \
2571 }
2572
2573 FLOAT_TERNOP(mul, add)
2574 FLOAT_TERNOP(mul, sub)
2575 #undef FLOAT_TERNOP
2576
2577 /* negated ternary operations */
2578 #define FLOAT_NTERNOP(name1, name2) \
2579 uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2580 uint64_t fdt2) \
2581 { \
2582 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2583 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2584 return float64_chs(fdt2); \
2585 } \
2586 \
2587 uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2588 uint32_t fst2) \
2589 { \
2590 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2591 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2592 return float32_chs(fst2); \
2593 } \
2594 \
2595 uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2596 uint64_t fdt2) \
2597 { \
2598 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2599 uint32_t fsth0 = fdt0 >> 32; \
2600 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2601 uint32_t fsth1 = fdt1 >> 32; \
2602 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2603 uint32_t fsth2 = fdt2 >> 32; \
2604 \
2605 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2606 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2607 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2608 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2609 fst2 = float32_chs(fst2); \
2610 fsth2 = float32_chs(fsth2); \
2611 return ((uint64_t)fsth2 << 32) | fst2; \
2612 }
2613
2614 FLOAT_NTERNOP(mul, add)
2615 FLOAT_NTERNOP(mul, sub)
2616 #undef FLOAT_NTERNOP
2617
2618 /* MIPS specific binary operations */
2619 uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2620 {
2621 set_float_exception_flags(0, &env->active_fpu.fp_status);
2622 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2623 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
2624 update_fcr31();
2625 return fdt2;
2626 }
2627
2628 uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
2629 {
2630 set_float_exception_flags(0, &env->active_fpu.fp_status);
2631 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2632 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2633 update_fcr31();
2634 return fst2;
2635 }
2636
2637 uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2638 {
2639 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2640 uint32_t fsth0 = fdt0 >> 32;
2641 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2642 uint32_t fsth2 = fdt2 >> 32;
2643
2644 set_float_exception_flags(0, &env->active_fpu.fp_status);
2645 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2646 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2647 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2648 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
2649 update_fcr31();
2650 return ((uint64_t)fsth2 << 32) | fst2;
2651 }
2652
2653 uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2654 {
2655 set_float_exception_flags(0, &env->active_fpu.fp_status);
2656 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2657 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2658 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2659 update_fcr31();
2660 return fdt2;
2661 }
2662
2663 uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2664 {
2665 set_float_exception_flags(0, &env->active_fpu.fp_status);
2666 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2667 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2668 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2669 update_fcr31();
2670 return fst2;
2671 }
2672
2673 uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2674 {
2675 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2676 uint32_t fsth0 = fdt0 >> 32;
2677 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2678 uint32_t fsth2 = fdt2 >> 32;
2679
2680 set_float_exception_flags(0, &env->active_fpu.fp_status);
2681 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2682 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2683 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2684 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2685 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2686 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2687 update_fcr31();
2688 return ((uint64_t)fsth2 << 32) | fst2;
2689 }
2690
2691 uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2692 {
2693 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2694 uint32_t fsth0 = fdt0 >> 32;
2695 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2696 uint32_t fsth1 = fdt1 >> 32;
2697 uint32_t fst2;
2698 uint32_t fsth2;
2699
2700 set_float_exception_flags(0, &env->active_fpu.fp_status);
2701 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2702 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2703 update_fcr31();
2704 return ((uint64_t)fsth2 << 32) | fst2;
2705 }
2706
2707 uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2708 {
2709 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2710 uint32_t fsth0 = fdt0 >> 32;
2711 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2712 uint32_t fsth1 = fdt1 >> 32;
2713 uint32_t fst2;
2714 uint32_t fsth2;
2715
2716 set_float_exception_flags(0, &env->active_fpu.fp_status);
2717 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2718 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
2719 update_fcr31();
2720 return ((uint64_t)fsth2 << 32) | fst2;
2721 }
2722
2723 /* compare operations */
2724 #define FOP_COND_D(op, cond) \
2725 void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2726 { \
2727 int c = cond; \
2728 update_fcr31(); \
2729 if (c) \
2730 SET_FP_COND(cc, env->active_fpu); \
2731 else \
2732 CLEAR_FP_COND(cc, env->active_fpu); \
2733 } \
2734 void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2735 { \
2736 int c; \
2737 fdt0 = float64_abs(fdt0); \
2738 fdt1 = float64_abs(fdt1); \
2739 c = cond; \
2740 update_fcr31(); \
2741 if (c) \
2742 SET_FP_COND(cc, env->active_fpu); \
2743 else \
2744 CLEAR_FP_COND(cc, env->active_fpu); \
2745 }
2746
2747 static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2748 {
2749 if (float64_is_signaling_nan(a) ||
2750 float64_is_signaling_nan(b) ||
2751 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2752 float_raise(float_flag_invalid, status);
2753 return 1;
2754 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2755 return 1;
2756 } else {
2757 return 0;
2758 }
2759 }
2760
2761 /* NOTE: the comma operator will make "cond" to eval to false,
2762 * but float*_is_unordered() is still called. */
2763 FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2764 FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2765 FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2766 FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2767 FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2768 FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2769 FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2770 FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2771 /* NOTE: the comma operator will make "cond" to eval to false,
2772 * but float*_is_unordered() is still called. */
2773 FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2774 FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2775 FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2776 FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2777 FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2778 FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2779 FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2780 FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2781
2782 #define FOP_COND_S(op, cond) \
2783 void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2784 { \
2785 int c = cond; \
2786 update_fcr31(); \
2787 if (c) \
2788 SET_FP_COND(cc, env->active_fpu); \
2789 else \
2790 CLEAR_FP_COND(cc, env->active_fpu); \
2791 } \
2792 void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2793 { \
2794 int c; \
2795 fst0 = float32_abs(fst0); \
2796 fst1 = float32_abs(fst1); \
2797 c = cond; \
2798 update_fcr31(); \
2799 if (c) \
2800 SET_FP_COND(cc, env->active_fpu); \
2801 else \
2802 CLEAR_FP_COND(cc, env->active_fpu); \
2803 }
2804
2805 static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2806 {
2807 if (float32_is_signaling_nan(a) ||
2808 float32_is_signaling_nan(b) ||
2809 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2810 float_raise(float_flag_invalid, status);
2811 return 1;
2812 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2813 return 1;
2814 } else {
2815 return 0;
2816 }
2817 }
2818
2819 /* NOTE: the comma operator will make "cond" to eval to false,
2820 * but float*_is_unordered() is still called. */
2821 FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2822 FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2823 FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2824 FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2825 FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2826 FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2827 FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2828 FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2829 /* NOTE: the comma operator will make "cond" to eval to false,
2830 * but float*_is_unordered() is still called. */
2831 FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2832 FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2833 FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2834 FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2835 FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2836 FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2837 FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2838 FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2839
2840 #define FOP_COND_PS(op, condl, condh) \
2841 void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2842 { \
2843 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2844 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2845 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2846 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2847 int cl = condl; \
2848 int ch = condh; \
2849 \
2850 update_fcr31(); \
2851 if (cl) \
2852 SET_FP_COND(cc, env->active_fpu); \
2853 else \
2854 CLEAR_FP_COND(cc, env->active_fpu); \
2855 if (ch) \
2856 SET_FP_COND(cc + 1, env->active_fpu); \
2857 else \
2858 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2859 } \
2860 void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2861 { \
2862 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2863 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2864 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2865 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2866 int cl = condl; \
2867 int ch = condh; \
2868 \
2869 update_fcr31(); \
2870 if (cl) \
2871 SET_FP_COND(cc, env->active_fpu); \
2872 else \
2873 CLEAR_FP_COND(cc, env->active_fpu); \
2874 if (ch) \
2875 SET_FP_COND(cc + 1, env->active_fpu); \
2876 else \
2877 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2878 }
2879
2880 /* NOTE: the comma operator will make "cond" to eval to false,
2881 * but float*_is_unordered() is still called. */
2882 FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
2883 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2884 FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
2885 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
2886 FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2887 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2888 FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2889 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2890 FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2891 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2892 FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2893 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2894 FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2895 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2896 FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2897 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2898 /* NOTE: the comma operator will make "cond" to eval to false,
2899 * but float*_is_unordered() is still called. */
2900 FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
2901 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2902 FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
2903 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
2904 FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2905 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2906 FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2907 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2908 FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2909 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2910 FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2911 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2912 FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2913 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2914 FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2915 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
AR7 emulation for QEMU