hw/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  * Contributions after 2012-01-13 are licensed under the terms of the
  14  * GNU GPL, version 2 or (at your option) any later version.
  15  */
  16
  17 #include "hw.h"
  18 #include "msi.h"
  19 #include "msix.h"
  20 #include "pci.h"
  21 #include "range.h"
  22
  23 #define MSIX_CAP_LENGTH 12
  24
  25 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
  26 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
  27 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  28 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
  29
  30 /* How much space does an MSIX table need. */
  31 /* The spec requires giving the table structure
  32  * a 4K aligned region all by itself. */
  33 #define MSIX_PAGE_SIZE 0x1000
  34 /* Reserve second half of the page for pending bits */
  35 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
  36 #define MSIX_MAX_ENTRIES 32
  37
  38 static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
  39 {
  40     uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
  41     MSIMessage msg;
  42
  43     msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
  44     msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
  45     return msg;
  46 }
  47
  48 /* Add MSI-X capability to the config space for the device. */
  49 /* Given a bar and its size, add MSI-X table on top of it
  50  * and fill MSI-X capability in the config space.
  51  * Original bar size must be a power of 2 or 0.
  52  * New bar size is returned. */
  53 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
  54                            unsigned bar_nr, unsigned bar_size)
  55 {
  56     int config_offset;
  57     uint8_t *config;
  58     uint32_t new_size;
  59
  60     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
  61         return -EINVAL;
  62     if (bar_size > 0x80000000)
  63         return -ENOSPC;
  64
  65     /* Add space for MSI-X structures */
  66     if (!bar_size) {
  67         new_size = MSIX_PAGE_SIZE;
  68     } else if (bar_size < MSIX_PAGE_SIZE) {
  69         bar_size = MSIX_PAGE_SIZE;
  70         new_size = MSIX_PAGE_SIZE * 2;
  71     } else {
  72         new_size = bar_size * 2;
  73     }
  74
  75     pdev->msix_bar_size = new_size;
  76     config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
  77                                        0, MSIX_CAP_LENGTH);
  78     if (config_offset < 0)
  79         return config_offset;
  80     config = pdev->config + config_offset;
  81
  82     pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
  83     /* Table on top of BAR */
  84     pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
  85     /* Pending bits on top of that */
  86     pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
  87                  bar_nr);
  88     pdev->msix_cap = config_offset;
  89     /* Make flags bit writable. */
  90     pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
  91             MSIX_MASKALL_MASK;
  92     pdev->msix_function_masked = true;
  93     return 0;
  94 }
  95
  96 static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
  97                                unsigned size)
  98 {
  99     PCIDevice *dev = opaque;
 100     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 101     void *page = dev->msix_table_page;
 102
 103     return pci_get_long(page + offset);
 104 }
 105
 106 static uint8_t msix_pending_mask(int vector)
 107 {
 108     return 1 << (vector % 8);
 109 }
 110
 111 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
 112 {
 113     return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
 114 }
 115
 116 static int msix_is_pending(PCIDevice *dev, int vector)
 117 {
 118     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
 119 }
 120
 121 static void msix_set_pending(PCIDevice *dev, int vector)
 122 {
 123     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 124 }
 125
 126 static void msix_clr_pending(PCIDevice *dev, int vector)
 127 {
 128     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 129 }
 130
 131 static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
 132 {
 133     unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 134     return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
 135 }
 136
 137 static bool msix_is_masked(PCIDevice *dev, int vector)
 138 {
 139     return msix_vector_masked(dev, vector, dev->msix_function_masked);
 140 }
 141
 142 static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
 143 {
 144     bool is_masked = msix_is_masked(dev, vector);
 145     if (is_masked == was_masked) {
 146         return;
 147     }
 148
 149     if (!is_masked && msix_is_pending(dev, vector)) {
 150         msix_clr_pending(dev, vector);
 151         msix_notify(dev, vector);
 152     }
 153 }
 154
 155 static void msix_update_function_masked(PCIDevice *dev)
 156 {
 157     dev->msix_function_masked = !msix_enabled(dev) ||
 158         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
 159 }
 160
 161 /* Handle MSI-X capability config write. */
 162 void msix_write_config(PCIDevice *dev, uint32_t addr,
 163                        uint32_t val, int len)
 164 {
 165     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
 166     int vector;
 167     bool was_masked;
 168
 169     if (!range_covers_byte(addr, len, enable_pos)) {
 170         return;
 171     }
 172
 173     was_masked = dev->msix_function_masked;
 174     msix_update_function_masked(dev);
 175
 176     if (!msix_enabled(dev)) {
 177         return;
 178     }
 179
 180     pci_device_deassert_intx(dev);
 181
 182     if (dev->msix_function_masked == was_masked) {
 183         return;
 184     }
 185
 186     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 187         msix_handle_mask_update(dev, vector,
 188                                 msix_vector_masked(dev, vector, was_masked));
 189     }
 190 }
 191
 192 static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
 193                             uint64_t val, unsigned size)
 194 {
 195     PCIDevice *dev = opaque;
 196     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 197     int vector = offset / PCI_MSIX_ENTRY_SIZE;
 198     bool was_masked;
 199
 200     /* MSI-X page includes a read-only PBA and a writeable Vector Control. */
 201     if (vector >= dev->msix_entries_nr) {
 202         return;
 203     }
 204
 205     was_masked = msix_is_masked(dev, vector);
 206     pci_set_long(dev->msix_table_page + offset, val);
 207     msix_handle_mask_update(dev, vector, was_masked);
 208 }
 209
 210 static const MemoryRegionOps msix_mmio_ops = {
 211     .read = msix_mmio_read,
 212     .write = msix_mmio_write,
 213     .endianness = DEVICE_NATIVE_ENDIAN,
 214     .valid = {
 215         .min_access_size = 4,
 216         .max_access_size = 4,
 217     },
 218 };
 219
 220 static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
 221 {
 222     uint8_t *config = d->config + d->msix_cap;
 223     uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
 224     uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
 225     /* TODO: for assigned devices, we'll want to make it possible to map
 226      * pending bits separately in case they are in a separate bar. */
 227
 228     memory_region_add_subregion(bar, offset, &d->msix_mmio);
 229 }
 230
 231 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
 232 {
 233     int vector;
 234     for (vector = 0; vector < nentries; ++vector) {
 235         unsigned offset =
 236             vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 237         dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 238     }
 239 }
 240
 241 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 242  * modified, it should be retrieved with msix_bar_size. */
 243 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 244               MemoryRegion *bar,
 245               unsigned bar_nr, unsigned bar_size)
 246 {
 247     int ret;
 248
 249     /* Nothing to do if MSI is not supported by interrupt controller */
 250     if (!msi_supported) {
 251         return -ENOTSUP;
 252     }
 253     if (nentries > MSIX_MAX_ENTRIES)
 254         return -EINVAL;
 255
 256     dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
 257                                         sizeof *dev->msix_entry_used);
 258
 259     dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
 260     msix_mask_all(dev, nentries);
 261
 262     memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
 263                           "msix", MSIX_PAGE_SIZE);
 264
 265     dev->msix_entries_nr = nentries;
 266     ret = msix_add_config(dev, nentries, bar_nr, bar_size);
 267     if (ret)
 268         goto err_config;
 269
 270     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 271     msix_mmio_setup(dev, bar);
 272     return 0;
 273
 274 err_config:
 275     dev->msix_entries_nr = 0;
 276     memory_region_destroy(&dev->msix_mmio);
 277     g_free(dev->msix_table_page);
 278     dev->msix_table_page = NULL;
 279     g_free(dev->msix_entry_used);
 280     dev->msix_entry_used = NULL;
 281     return ret;
 282 }
 283
 284 static void msix_free_irq_entries(PCIDevice *dev)
 285 {
 286     int vector;
 287
 288     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 289         dev->msix_entry_used[vector] = 0;
 290         msix_clr_pending(dev, vector);
 291     }
 292 }
 293
 294 /* Clean up resources for the device. */
 295 int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
 296 {
 297     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 298         return 0;
 299     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 300     dev->msix_cap = 0;
 301     msix_free_irq_entries(dev);
 302     dev->msix_entries_nr = 0;
 303     memory_region_del_subregion(bar, &dev->msix_mmio);
 304     memory_region_destroy(&dev->msix_mmio);
 305     g_free(dev->msix_table_page);
 306     dev->msix_table_page = NULL;
 307     g_free(dev->msix_entry_used);
 308     dev->msix_entry_used = NULL;
 309     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 310     return 0;
 311 }
 312
 313 void msix_save(PCIDevice *dev, QEMUFile *f)
 314 {
 315     unsigned n = dev->msix_entries_nr;
 316
 317     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 318         return;
 319     }
 320
 321     qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
 322     qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 323 }
 324
 325 /* Should be called after restoring the config space. */
 326 void msix_load(PCIDevice *dev, QEMUFile *f)
 327 {
 328     unsigned n = dev->msix_entries_nr;
 329
 330     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 331         return;
 332     }
 333
 334     msix_free_irq_entries(dev);
 335     qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
 336     qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 337     msix_update_function_masked(dev);
 338 }
 339
 340 /* Does device support MSI-X? */
 341 int msix_present(PCIDevice *dev)
 342 {
 343     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 344 }
 345
 346 /* Is MSI-X enabled? */
 347 int msix_enabled(PCIDevice *dev)
 348 {
 349     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 350         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 351          MSIX_ENABLE_MASK);
 352 }
 353
 354 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
 355 uint32_t msix_bar_size(PCIDevice *dev)
 356 {
 357     return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
 358         dev->msix_bar_size : 0;
 359 }
 360
 361 /* Send an MSI-X message */
 362 void msix_notify(PCIDevice *dev, unsigned vector)
 363 {
 364     MSIMessage msg;
 365
 366     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 367         return;
 368     if (msix_is_masked(dev, vector)) {
 369         msix_set_pending(dev, vector);
 370         return;
 371     }
 372
 373     msg = msix_get_message(dev, vector);
 374
 375     stl_le_phys(msg.address, msg.data);
 376 }
 377
 378 void msix_reset(PCIDevice *dev)
 379 {
 380     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 381         return;
 382     msix_free_irq_entries(dev);
 383     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
 384             ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
 385     memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
 386     msix_mask_all(dev, dev->msix_entries_nr);
 387 }
 388
 389 /* PCI spec suggests that devices make it possible for software to configure
 390  * less vectors than supported by the device, but does not specify a standard
 391  * mechanism for devices to do so.
 392  *
 393  * We support this by asking devices to declare vectors software is going to
 394  * actually use, and checking this on the notification path. Devices that
 395  * don't want to follow the spec suggestion can declare all vectors as used. */
 396
 397 /* Mark vector as used. */
 398 int msix_vector_use(PCIDevice *dev, unsigned vector)
 399 {
 400     if (vector >= dev->msix_entries_nr)
 401         return -EINVAL;
 402     dev->msix_entry_used[vector]++;
 403     return 0;
 404 }
 405
 406 /* Mark vector as unused. */
 407 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 408 {
 409     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
 410         return;
 411     }
 412     if (--dev->msix_entry_used[vector]) {
 413         return;
 414     }
 415     msix_clr_pending(dev, vector);
 416 }
 417
 418 void msix_unuse_all_vectors(PCIDevice *dev)
 419 {
 420     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 421         return;
 422     msix_free_irq_entries(dev);
 423 }