4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
40 static TCGv_i64 cpu_X
[32];
41 static TCGv_i64 cpu_pc
;
43 /* Load/store exclusive handling */
44 static TCGv_i64 cpu_exclusive_high
;
45 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
47 static const char *regnames
[] = {
48 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
49 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
50 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
51 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 A64_SHIFT_TYPE_LSL
= 0,
56 A64_SHIFT_TYPE_LSR
= 1,
57 A64_SHIFT_TYPE_ASR
= 2,
58 A64_SHIFT_TYPE_ROR
= 3
61 /* Table based decoder typedefs - used when the relevant bits for decode
62 * are too awkwardly scattered across the instruction (eg SIMD).
64 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
66 typedef struct AArch64DecodeTable
{
69 AArch64DecodeFn
*disas_fn
;
72 /* Function prototype for gen_ functions for calling Neon helpers */
73 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
74 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
79 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
80 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
81 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
82 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
83 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
84 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
85 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
86 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 /* Note that the gvec expanders operate on offsets + sizes. */
89 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
90 uint32_t, uint32_t, uint32_t);
92 /* initialize TCG globals. */
93 void a64_translate_init(void)
97 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
98 offsetof(CPUARMState
, pc
),
100 for (i
= 0; i
< 32; i
++) {
101 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
102 offsetof(CPUARMState
, xregs
[i
]),
106 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
107 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
110 static inline int get_a64_user_mem_index(DisasContext
*s
)
112 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
113 * if EL1, access as if EL0; otherwise access at current EL
117 switch (s
->mmu_idx
) {
118 case ARMMMUIdx_S12NSE1
:
119 useridx
= ARMMMUIdx_S12NSE0
;
121 case ARMMMUIdx_S1SE1
:
122 useridx
= ARMMMUIdx_S1SE0
;
125 g_assert_not_reached();
127 useridx
= s
->mmu_idx
;
130 return arm_to_core_mmu_idx(useridx
);
133 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
134 fprintf_function cpu_fprintf
, int flags
)
136 ARMCPU
*cpu
= ARM_CPU(cs
);
137 CPUARMState
*env
= &cpu
->env
;
138 uint32_t psr
= pstate_read(env
);
140 int el
= arm_current_el(env
);
141 const char *ns_status
;
143 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
144 env
->pc
, env
->xregs
[31]);
145 for (i
= 0; i
< 31; i
++) {
146 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
148 cpu_fprintf(f
, "\n");
154 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
155 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
160 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
162 psr
& PSTATE_N
? 'N' : '-',
163 psr
& PSTATE_Z
? 'Z' : '-',
164 psr
& PSTATE_C
? 'C' : '-',
165 psr
& PSTATE_V
? 'V' : '-',
168 psr
& PSTATE_SP
? 'h' : 't');
170 if (flags
& CPU_DUMP_FPU
) {
172 for (i
= 0; i
< numvfpregs
; i
++) {
173 uint64_t *q
= aa64_vfp_qreg(env
, i
);
176 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"%c",
177 i
, vhi
, vlo
, (i
& 1 ? '\n' : ' '));
179 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
180 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
184 void gen_a64_set_pc_im(uint64_t val
)
186 tcg_gen_movi_i64(cpu_pc
, val
);
189 /* Load the PC from a generic TCG variable.
191 * If address tagging is enabled via the TCR TBI bits, then loading
192 * an address into the PC will clear out any tag in the it:
193 * + for EL2 and EL3 there is only one TBI bit, and if it is set
194 * then the address is zero-extended, clearing bits [63:56]
195 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
196 * and TBI1 controls addressses with bit 55 == 1.
197 * If the appropriate TBI bit is set for the address then
198 * the address is sign-extended from bit 55 into bits [63:56]
200 * We can avoid doing this for relative-branches, because the
201 * PC + offset can never overflow into the tag bits (assuming
202 * that virtual addresses are less than 56 bits wide, as they
203 * are currently), but we must handle it for branch-to-register.
205 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
208 if (s
->current_el
<= 1) {
209 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
210 * examine bit 55 of address, can just generate code.
211 * If mixed, then test via generated code
213 if (s
->tbi0
&& s
->tbi1
) {
214 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
215 /* Both bits set, sign extension from bit 55 into [63:56] will
218 tcg_gen_shli_i64(tmp_reg
, src
, 8);
219 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
220 tcg_temp_free_i64(tmp_reg
);
221 } else if (!s
->tbi0
&& !s
->tbi1
) {
222 /* Neither bit set, just load it as-is */
223 tcg_gen_mov_i64(cpu_pc
, src
);
225 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
226 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
227 TCGv_i64 tcg_zero
= tcg_const_i64(0);
229 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
232 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
233 tcg_gen_andi_i64(tcg_tmpval
, src
,
234 0x00FFFFFFFFFFFFFFull
);
235 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
238 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
239 tcg_gen_ori_i64(tcg_tmpval
, src
,
240 0xFF00000000000000ull
);
241 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
244 tcg_temp_free_i64(tcg_zero
);
245 tcg_temp_free_i64(tcg_bit55
);
246 tcg_temp_free_i64(tcg_tmpval
);
248 } else { /* EL > 1 */
250 /* Force tag byte to all zero */
251 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
253 /* Load unmodified address */
254 tcg_gen_mov_i64(cpu_pc
, src
);
259 typedef struct DisasCompare64
{
264 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
268 arm_test_cc(&c32
, cc
);
270 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
271 * properly. The NE/EQ comparisons are also fine with this choice. */
272 c64
->cond
= c32
.cond
;
273 c64
->value
= tcg_temp_new_i64();
274 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
279 static void a64_free_cc(DisasCompare64
*c64
)
281 tcg_temp_free_i64(c64
->value
);
284 static void gen_exception_internal(int excp
)
286 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
288 assert(excp_is_internal(excp
));
289 gen_helper_exception_internal(cpu_env
, tcg_excp
);
290 tcg_temp_free_i32(tcg_excp
);
293 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
295 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
296 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
297 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
299 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
301 tcg_temp_free_i32(tcg_el
);
302 tcg_temp_free_i32(tcg_syn
);
303 tcg_temp_free_i32(tcg_excp
);
306 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
308 gen_a64_set_pc_im(s
->pc
- offset
);
309 gen_exception_internal(excp
);
310 s
->base
.is_jmp
= DISAS_NORETURN
;
313 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
314 uint32_t syndrome
, uint32_t target_el
)
316 gen_a64_set_pc_im(s
->pc
- offset
);
317 gen_exception(excp
, syndrome
, target_el
);
318 s
->base
.is_jmp
= DISAS_NORETURN
;
321 static void gen_ss_advance(DisasContext
*s
)
323 /* If the singlestep state is Active-not-pending, advance to
328 gen_helper_clear_pstate_ss(cpu_env
);
332 static void gen_step_complete_exception(DisasContext
*s
)
334 /* We just completed step of an insn. Move from Active-not-pending
335 * to Active-pending, and then also take the swstep exception.
336 * This corresponds to making the (IMPDEF) choice to prioritize
337 * swstep exceptions over asynchronous exceptions taken to an exception
338 * level where debug is disabled. This choice has the advantage that
339 * we do not need to maintain internal state corresponding to the
340 * ISV/EX syndrome bits between completion of the step and generation
341 * of the exception, and our syndrome information is always correct.
344 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
345 default_exception_el(s
));
346 s
->base
.is_jmp
= DISAS_NORETURN
;
349 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
351 /* No direct tb linking with singlestep (either QEMU's or the ARM
352 * debug architecture kind) or deterministic io
354 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
355 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
359 #ifndef CONFIG_USER_ONLY
360 /* Only link tbs from inside the same guest page */
361 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
369 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
371 TranslationBlock
*tb
;
374 if (use_goto_tb(s
, n
, dest
)) {
376 gen_a64_set_pc_im(dest
);
377 tcg_gen_exit_tb((intptr_t)tb
+ n
);
378 s
->base
.is_jmp
= DISAS_NORETURN
;
380 gen_a64_set_pc_im(dest
);
382 gen_step_complete_exception(s
);
383 } else if (s
->base
.singlestep_enabled
) {
384 gen_exception_internal(EXCP_DEBUG
);
386 tcg_gen_lookup_and_goto_ptr();
387 s
->base
.is_jmp
= DISAS_NORETURN
;
392 static void unallocated_encoding(DisasContext
*s
)
394 /* Unallocated and reserved encodings are uncategorized */
395 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
396 default_exception_el(s
));
399 #define unsupported_encoding(s, insn) \
401 qemu_log_mask(LOG_UNIMP, \
402 "%s:%d: unsupported instruction encoding 0x%08x " \
403 "at pc=%016" PRIx64 "\n", \
404 __FILE__, __LINE__, insn, s->pc - 4); \
405 unallocated_encoding(s); \
408 static void init_tmp_a64_array(DisasContext
*s
)
410 #ifdef CONFIG_DEBUG_TCG
411 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
413 s
->tmp_a64_count
= 0;
416 static void free_tmp_a64(DisasContext
*s
)
419 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
420 tcg_temp_free_i64(s
->tmp_a64
[i
]);
422 init_tmp_a64_array(s
);
425 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
427 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
428 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
431 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
433 TCGv_i64 t
= new_tmp_a64(s
);
434 tcg_gen_movi_i64(t
, 0);
439 * Register access functions
441 * These functions are used for directly accessing a register in where
442 * changes to the final register value are likely to be made. If you
443 * need to use a register for temporary calculation (e.g. index type
444 * operations) use the read_* form.
446 * B1.2.1 Register mappings
448 * In instruction register encoding 31 can refer to ZR (zero register) or
449 * the SP (stack pointer) depending on context. In QEMU's case we map SP
450 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
451 * This is the point of the _sp forms.
453 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
456 return new_tmp_a64_zero(s
);
462 /* register access for when 31 == SP */
463 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
468 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
469 * representing the register contents. This TCGv is an auto-freed
470 * temporary so it need not be explicitly freed, and may be modified.
472 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
474 TCGv_i64 v
= new_tmp_a64(s
);
477 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
479 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
482 tcg_gen_movi_i64(v
, 0);
487 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
489 TCGv_i64 v
= new_tmp_a64(s
);
491 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
493 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
498 /* We should have at some point before trying to access an FP register
499 * done the necessary access check, so assert that
500 * (a) we did the check and
501 * (b) we didn't then just plough ahead anyway if it failed.
502 * Print the instruction pattern in the abort message so we can figure
503 * out what we need to fix if a user encounters this problem in the wild.
505 static inline void assert_fp_access_checked(DisasContext
*s
)
507 #ifdef CONFIG_DEBUG_TCG
508 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
509 fprintf(stderr
, "target-arm: FP access check missing for "
510 "instruction 0x%08x\n", s
->insn
);
516 /* Return the offset into CPUARMState of an element of specified
517 * size, 'element' places in from the least significant end of
518 * the FP/vector register Qn.
520 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
521 int element
, TCGMemOp size
)
524 #ifdef HOST_WORDS_BIGENDIAN
525 /* This is complicated slightly because vfp.regs[2n] is
526 * still the low half and vfp.regs[2n+1] the high half
527 * of the 128 bit vector, even on big endian systems.
528 * Calculate the offset assuming a fully bigendian 128 bits,
529 * then XOR to account for the order of the two 64 bit halves.
531 offs
+= (16 - ((element
+ 1) * (1 << size
)));
534 offs
+= element
* (1 << size
);
536 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
537 assert_fp_access_checked(s
);
541 /* Return the offset info CPUARMState of the "whole" vector register Qn. */
542 static inline int vec_full_reg_offset(DisasContext
*s
, int regno
)
544 assert_fp_access_checked(s
);
545 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
548 /* Return a newly allocated pointer to the vector register. */
549 static TCGv_ptr
vec_full_reg_ptr(DisasContext
*s
, int regno
)
551 TCGv_ptr ret
= tcg_temp_new_ptr();
552 tcg_gen_addi_ptr(ret
, cpu_env
, vec_full_reg_offset(s
, regno
));
556 /* Return the byte size of the "whole" vector register, VL / 8. */
557 static inline int vec_full_reg_size(DisasContext
*s
)
559 /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
560 In the meantime this is just the AdvSIMD length of 128. */
564 /* Return the offset into CPUARMState of a slice (from
565 * the least significant end) of FP register Qn (ie
567 * (Note that this is not the same mapping as for A32; see cpu.h)
569 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
571 return vec_reg_offset(s
, regno
, 0, size
);
574 /* Offset of the high half of the 128 bit vector Qn */
575 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
577 return vec_reg_offset(s
, regno
, 1, MO_64
);
580 /* Convenience accessors for reading and writing single and double
581 * FP registers. Writing clears the upper parts of the associated
582 * 128 bit vector register, as required by the architecture.
583 * Note that unlike the GP register accessors, the values returned
584 * by the read functions must be manually freed.
586 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
588 TCGv_i64 v
= tcg_temp_new_i64();
590 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
594 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
596 TCGv_i32 v
= tcg_temp_new_i32();
598 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
602 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
604 TCGv_i64 tcg_zero
= tcg_const_i64(0);
606 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
607 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
608 tcg_temp_free_i64(tcg_zero
);
611 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
613 TCGv_i64 tmp
= tcg_temp_new_i64();
615 tcg_gen_extu_i32_i64(tmp
, v
);
616 write_fp_dreg(s
, reg
, tmp
);
617 tcg_temp_free_i64(tmp
);
620 static TCGv_ptr
get_fpstatus_ptr(void)
622 TCGv_ptr statusptr
= tcg_temp_new_ptr();
625 /* In A64 all instructions (both FP and Neon) use the FPCR;
626 * there is no equivalent of the A32 Neon "standard FPSCR value"
627 * and all operations use vfp.fp_status.
629 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
630 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
634 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
635 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
636 GVecGen3Fn
*gvec_fn
, int vece
)
638 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
639 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
642 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
643 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
644 int rn
, int rm
, const GVecGen3
*gvec_op
)
646 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
647 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
648 vec_full_reg_size(s
), gvec_op
);
651 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
652 * than the 32 bit equivalent.
654 static inline void gen_set_NZ64(TCGv_i64 result
)
656 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
657 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
660 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
661 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
664 gen_set_NZ64(result
);
666 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
667 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
669 tcg_gen_movi_i32(cpu_CF
, 0);
670 tcg_gen_movi_i32(cpu_VF
, 0);
673 /* dest = T0 + T1; compute C, N, V and Z flags */
674 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
677 TCGv_i64 result
, flag
, tmp
;
678 result
= tcg_temp_new_i64();
679 flag
= tcg_temp_new_i64();
680 tmp
= tcg_temp_new_i64();
682 tcg_gen_movi_i64(tmp
, 0);
683 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
685 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
687 gen_set_NZ64(result
);
689 tcg_gen_xor_i64(flag
, result
, t0
);
690 tcg_gen_xor_i64(tmp
, t0
, t1
);
691 tcg_gen_andc_i64(flag
, flag
, tmp
);
692 tcg_temp_free_i64(tmp
);
693 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
695 tcg_gen_mov_i64(dest
, result
);
696 tcg_temp_free_i64(result
);
697 tcg_temp_free_i64(flag
);
699 /* 32 bit arithmetic */
700 TCGv_i32 t0_32
= tcg_temp_new_i32();
701 TCGv_i32 t1_32
= tcg_temp_new_i32();
702 TCGv_i32 tmp
= tcg_temp_new_i32();
704 tcg_gen_movi_i32(tmp
, 0);
705 tcg_gen_extrl_i64_i32(t0_32
, t0
);
706 tcg_gen_extrl_i64_i32(t1_32
, t1
);
707 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
708 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
709 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
710 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
711 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
712 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
714 tcg_temp_free_i32(tmp
);
715 tcg_temp_free_i32(t0_32
);
716 tcg_temp_free_i32(t1_32
);
720 /* dest = T0 - T1; compute C, N, V and Z flags */
721 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
724 /* 64 bit arithmetic */
725 TCGv_i64 result
, flag
, tmp
;
727 result
= tcg_temp_new_i64();
728 flag
= tcg_temp_new_i64();
729 tcg_gen_sub_i64(result
, t0
, t1
);
731 gen_set_NZ64(result
);
733 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
734 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
736 tcg_gen_xor_i64(flag
, result
, t0
);
737 tmp
= tcg_temp_new_i64();
738 tcg_gen_xor_i64(tmp
, t0
, t1
);
739 tcg_gen_and_i64(flag
, flag
, tmp
);
740 tcg_temp_free_i64(tmp
);
741 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
742 tcg_gen_mov_i64(dest
, result
);
743 tcg_temp_free_i64(flag
);
744 tcg_temp_free_i64(result
);
746 /* 32 bit arithmetic */
747 TCGv_i32 t0_32
= tcg_temp_new_i32();
748 TCGv_i32 t1_32
= tcg_temp_new_i32();
751 tcg_gen_extrl_i64_i32(t0_32
, t0
);
752 tcg_gen_extrl_i64_i32(t1_32
, t1
);
753 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
754 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
755 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
756 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
757 tmp
= tcg_temp_new_i32();
758 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
759 tcg_temp_free_i32(t0_32
);
760 tcg_temp_free_i32(t1_32
);
761 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
762 tcg_temp_free_i32(tmp
);
763 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
767 /* dest = T0 + T1 + CF; do not compute flags. */
768 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
770 TCGv_i64 flag
= tcg_temp_new_i64();
771 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
772 tcg_gen_add_i64(dest
, t0
, t1
);
773 tcg_gen_add_i64(dest
, dest
, flag
);
774 tcg_temp_free_i64(flag
);
777 tcg_gen_ext32u_i64(dest
, dest
);
781 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
782 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
785 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
786 result
= tcg_temp_new_i64();
787 cf_64
= tcg_temp_new_i64();
788 vf_64
= tcg_temp_new_i64();
789 tmp
= tcg_const_i64(0);
791 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
792 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
793 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
794 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
795 gen_set_NZ64(result
);
797 tcg_gen_xor_i64(vf_64
, result
, t0
);
798 tcg_gen_xor_i64(tmp
, t0
, t1
);
799 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
800 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
802 tcg_gen_mov_i64(dest
, result
);
804 tcg_temp_free_i64(tmp
);
805 tcg_temp_free_i64(vf_64
);
806 tcg_temp_free_i64(cf_64
);
807 tcg_temp_free_i64(result
);
809 TCGv_i32 t0_32
, t1_32
, tmp
;
810 t0_32
= tcg_temp_new_i32();
811 t1_32
= tcg_temp_new_i32();
812 tmp
= tcg_const_i32(0);
814 tcg_gen_extrl_i64_i32(t0_32
, t0
);
815 tcg_gen_extrl_i64_i32(t1_32
, t1
);
816 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
817 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
819 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
820 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
821 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
822 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
823 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
825 tcg_temp_free_i32(tmp
);
826 tcg_temp_free_i32(t1_32
);
827 tcg_temp_free_i32(t0_32
);
832 * Load/Store generators
836 * Store from GPR register to memory.
838 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
839 TCGv_i64 tcg_addr
, int size
, int memidx
,
841 unsigned int iss_srt
,
842 bool iss_sf
, bool iss_ar
)
845 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
850 syn
= syn_data_abort_with_iss(0,
856 0, 0, 0, 0, 0, false);
857 disas_set_insn_syndrome(s
, syn
);
861 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
862 TCGv_i64 tcg_addr
, int size
,
864 unsigned int iss_srt
,
865 bool iss_sf
, bool iss_ar
)
867 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
868 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
872 * Load from memory to GPR register
874 static void do_gpr_ld_memidx(DisasContext
*s
,
875 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
876 int size
, bool is_signed
,
877 bool extend
, int memidx
,
878 bool iss_valid
, unsigned int iss_srt
,
879 bool iss_sf
, bool iss_ar
)
881 TCGMemOp memop
= s
->be_data
+ size
;
889 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
891 if (extend
&& is_signed
) {
893 tcg_gen_ext32u_i64(dest
, dest
);
899 syn
= syn_data_abort_with_iss(0,
905 0, 0, 0, 0, 0, false);
906 disas_set_insn_syndrome(s
, syn
);
910 static void do_gpr_ld(DisasContext
*s
,
911 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
912 int size
, bool is_signed
, bool extend
,
913 bool iss_valid
, unsigned int iss_srt
,
914 bool iss_sf
, bool iss_ar
)
916 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
918 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
922 * Store from FP register to memory
924 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
926 /* This writes the bottom N bits of a 128 bit wide vector to memory */
927 TCGv_i64 tmp
= tcg_temp_new_i64();
928 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
930 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
933 bool be
= s
->be_data
== MO_BE
;
934 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
936 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
937 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
939 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
940 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
942 tcg_temp_free_i64(tcg_hiaddr
);
945 tcg_temp_free_i64(tmp
);
949 * Load from memory to FP register
951 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
953 /* This always zero-extends and writes to a full 128 bit wide vector */
954 TCGv_i64 tmplo
= tcg_temp_new_i64();
958 TCGMemOp memop
= s
->be_data
+ size
;
959 tmphi
= tcg_const_i64(0);
960 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
962 bool be
= s
->be_data
== MO_BE
;
965 tmphi
= tcg_temp_new_i64();
966 tcg_hiaddr
= tcg_temp_new_i64();
968 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
969 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
971 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
973 tcg_temp_free_i64(tcg_hiaddr
);
976 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
977 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
979 tcg_temp_free_i64(tmplo
);
980 tcg_temp_free_i64(tmphi
);
984 * Vector load/store helpers.
986 * The principal difference between this and a FP load is that we don't
987 * zero extend as we are filling a partial chunk of the vector register.
988 * These functions don't support 128 bit loads/stores, which would be
989 * normal load/store operations.
991 * The _i32 versions are useful when operating on 32 bit quantities
992 * (eg for floating point single or using Neon helper functions).
995 /* Get value of an element within a vector register */
996 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
997 int element
, TCGMemOp memop
)
999 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1002 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1005 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1008 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1011 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1014 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1017 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1021 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1024 g_assert_not_reached();
1028 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1029 int element
, TCGMemOp memop
)
1031 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1034 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1037 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1040 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1043 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1047 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1050 g_assert_not_reached();
1054 /* Set value of an element within a vector register */
1055 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1056 int element
, TCGMemOp memop
)
1058 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1061 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1064 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1067 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1070 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1073 g_assert_not_reached();
1077 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1078 int destidx
, int element
, TCGMemOp memop
)
1080 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1083 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1086 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1089 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1092 g_assert_not_reached();
1096 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1097 * vector ops all need to do this).
1099 static void clear_vec_high(DisasContext
*s
, int rd
)
1101 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1103 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1104 tcg_temp_free_i64(tcg_zero
);
1107 /* Store from vector register to memory */
1108 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1109 TCGv_i64 tcg_addr
, int size
)
1111 TCGMemOp memop
= s
->be_data
+ size
;
1112 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1114 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1115 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1117 tcg_temp_free_i64(tcg_tmp
);
1120 /* Load from memory to vector register */
1121 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1122 TCGv_i64 tcg_addr
, int size
)
1124 TCGMemOp memop
= s
->be_data
+ size
;
1125 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1127 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1128 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1130 tcg_temp_free_i64(tcg_tmp
);
1133 /* Check that FP/Neon access is enabled. If it is, return
1134 * true. If not, emit code to generate an appropriate exception,
1135 * and return false; the caller should not emit any code for
1136 * the instruction. Note that this check must happen after all
1137 * unallocated-encoding checks (otherwise the syndrome information
1138 * for the resulting exception will be incorrect).
1140 static inline bool fp_access_check(DisasContext
*s
)
1142 assert(!s
->fp_access_checked
);
1143 s
->fp_access_checked
= true;
1145 if (!s
->fp_excp_el
) {
1149 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1155 * This utility function is for doing register extension with an
1156 * optional shift. You will likely want to pass a temporary for the
1157 * destination register. See DecodeRegExtend() in the ARM ARM.
1159 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1160 int option
, unsigned int shift
)
1162 int extsize
= extract32(option
, 0, 2);
1163 bool is_signed
= extract32(option
, 2, 1);
1168 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1171 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1174 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1177 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1183 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1186 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1189 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1192 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1198 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1202 static inline void gen_check_sp_alignment(DisasContext
*s
)
1204 /* The AArch64 architecture mandates that (if enabled via PSTATE
1205 * or SCTLR bits) there is a check that SP is 16-aligned on every
1206 * SP-relative load or store (with an exception generated if it is not).
1207 * In line with general QEMU practice regarding misaligned accesses,
1208 * we omit these checks for the sake of guest program performance.
1209 * This function is provided as a hook so we can more easily add these
1210 * checks in future (possibly as a "favour catching guest program bugs
1211 * over speed" user selectable option).
1216 * This provides a simple table based table lookup decoder. It is
1217 * intended to be used when the relevant bits for decode are too
1218 * awkwardly placed and switch/if based logic would be confusing and
1219 * deeply nested. Since it's a linear search through the table, tables
1220 * should be kept small.
1222 * It returns the first handler where insn & mask == pattern, or
1223 * NULL if there is no match.
1224 * The table is terminated by an empty mask (i.e. 0)
1226 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1229 const AArch64DecodeTable
*tptr
= table
;
1231 while (tptr
->mask
) {
1232 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1233 return tptr
->disas_fn
;
1241 * The instruction disassembly implemented here matches
1242 * the instruction encoding classifications in chapter C4
1243 * of the ARM Architecture Reference Manual (DDI0487B_a);
1244 * classification names and decode diagrams here should generally
1245 * match up with those in the manual.
1248 /* Unconditional branch (immediate)
1250 * +----+-----------+-------------------------------------+
1251 * | op | 0 0 1 0 1 | imm26 |
1252 * +----+-----------+-------------------------------------+
1254 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1256 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1258 if (insn
& (1U << 31)) {
1259 /* BL Branch with link */
1260 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1263 /* B Branch / BL Branch with link */
1264 gen_goto_tb(s
, 0, addr
);
1267 /* Compare and branch (immediate)
1268 * 31 30 25 24 23 5 4 0
1269 * +----+-------------+----+---------------------+--------+
1270 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1271 * +----+-------------+----+---------------------+--------+
1273 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1275 unsigned int sf
, op
, rt
;
1277 TCGLabel
*label_match
;
1280 sf
= extract32(insn
, 31, 1);
1281 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1282 rt
= extract32(insn
, 0, 5);
1283 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1285 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1286 label_match
= gen_new_label();
1288 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1289 tcg_cmp
, 0, label_match
);
1291 gen_goto_tb(s
, 0, s
->pc
);
1292 gen_set_label(label_match
);
1293 gen_goto_tb(s
, 1, addr
);
1296 /* Test and branch (immediate)
1297 * 31 30 25 24 23 19 18 5 4 0
1298 * +----+-------------+----+-------+-------------+------+
1299 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1300 * +----+-------------+----+-------+-------------+------+
1302 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1304 unsigned int bit_pos
, op
, rt
;
1306 TCGLabel
*label_match
;
1309 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1310 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1311 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1312 rt
= extract32(insn
, 0, 5);
1314 tcg_cmp
= tcg_temp_new_i64();
1315 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1316 label_match
= gen_new_label();
1317 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1318 tcg_cmp
, 0, label_match
);
1319 tcg_temp_free_i64(tcg_cmp
);
1320 gen_goto_tb(s
, 0, s
->pc
);
1321 gen_set_label(label_match
);
1322 gen_goto_tb(s
, 1, addr
);
1325 /* Conditional branch (immediate)
1326 * 31 25 24 23 5 4 3 0
1327 * +---------------+----+---------------------+----+------+
1328 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1329 * +---------------+----+---------------------+----+------+
1331 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1336 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1337 unallocated_encoding(s
);
1340 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1341 cond
= extract32(insn
, 0, 4);
1344 /* genuinely conditional branches */
1345 TCGLabel
*label_match
= gen_new_label();
1346 arm_gen_test_cc(cond
, label_match
);
1347 gen_goto_tb(s
, 0, s
->pc
);
1348 gen_set_label(label_match
);
1349 gen_goto_tb(s
, 1, addr
);
1351 /* 0xe and 0xf are both "always" conditions */
1352 gen_goto_tb(s
, 0, addr
);
1356 /* HINT instruction group, including various allocated HINTs */
1357 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1358 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1360 unsigned int selector
= crm
<< 3 | op2
;
1363 unallocated_encoding(s
);
1371 s
->base
.is_jmp
= DISAS_WFI
;
1373 /* When running in MTTCG we don't generate jumps to the yield and
1374 * WFE helpers as it won't affect the scheduling of other vCPUs.
1375 * If we wanted to more completely model WFE/SEV so we don't busy
1376 * spin unnecessarily we would need to do something more involved.
1379 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1380 s
->base
.is_jmp
= DISAS_YIELD
;
1384 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1385 s
->base
.is_jmp
= DISAS_WFE
;
1390 /* we treat all as NOP at least for now */
1393 /* default specified as NOP equivalent */
1398 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1400 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1403 /* CLREX, DSB, DMB, ISB */
1404 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1405 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1410 unallocated_encoding(s
);
1421 case 1: /* MBReqTypes_Reads */
1422 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1424 case 2: /* MBReqTypes_Writes */
1425 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1427 default: /* MBReqTypes_All */
1428 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1434 /* We need to break the TB after this insn to execute
1435 * a self-modified code correctly and also to take
1436 * any pending interrupts immediately.
1438 gen_goto_tb(s
, 0, s
->pc
);
1441 unallocated_encoding(s
);
1446 /* MSR (immediate) - move immediate to processor state field */
1447 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1448 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1450 int op
= op1
<< 3 | op2
;
1452 case 0x05: /* SPSel */
1453 if (s
->current_el
== 0) {
1454 unallocated_encoding(s
);
1458 case 0x1e: /* DAIFSet */
1459 case 0x1f: /* DAIFClear */
1461 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1462 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1463 gen_a64_set_pc_im(s
->pc
- 4);
1464 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1465 tcg_temp_free_i32(tcg_imm
);
1466 tcg_temp_free_i32(tcg_op
);
1467 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1468 gen_a64_set_pc_im(s
->pc
);
1469 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1473 unallocated_encoding(s
);
1478 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1480 TCGv_i32 tmp
= tcg_temp_new_i32();
1481 TCGv_i32 nzcv
= tcg_temp_new_i32();
1483 /* build bit 31, N */
1484 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1485 /* build bit 30, Z */
1486 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1487 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1488 /* build bit 29, C */
1489 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1490 /* build bit 28, V */
1491 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1492 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1493 /* generate result */
1494 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1496 tcg_temp_free_i32(nzcv
);
1497 tcg_temp_free_i32(tmp
);
1500 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1503 TCGv_i32 nzcv
= tcg_temp_new_i32();
1505 /* take NZCV from R[t] */
1506 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1509 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1511 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1512 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1514 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1515 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1517 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1518 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1519 tcg_temp_free_i32(nzcv
);
1522 /* MRS - move from system register
1523 * MSR (register) - move to system register
1526 * These are all essentially the same insn in 'read' and 'write'
1527 * versions, with varying op0 fields.
1529 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1530 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1531 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1533 const ARMCPRegInfo
*ri
;
1536 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1537 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1538 crn
, crm
, op0
, op1
, op2
));
1541 /* Unknown register; this might be a guest error or a QEMU
1542 * unimplemented feature.
1544 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1545 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1546 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1547 unallocated_encoding(s
);
1551 /* Check access permissions */
1552 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1553 unallocated_encoding(s
);
1558 /* Emit code to perform further access permissions checks at
1559 * runtime; this may result in an exception.
1562 TCGv_i32 tcg_syn
, tcg_isread
;
1565 gen_a64_set_pc_im(s
->pc
- 4);
1566 tmpptr
= tcg_const_ptr(ri
);
1567 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1568 tcg_syn
= tcg_const_i32(syndrome
);
1569 tcg_isread
= tcg_const_i32(isread
);
1570 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1571 tcg_temp_free_ptr(tmpptr
);
1572 tcg_temp_free_i32(tcg_syn
);
1573 tcg_temp_free_i32(tcg_isread
);
1576 /* Handle special cases first */
1577 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1581 tcg_rt
= cpu_reg(s
, rt
);
1583 gen_get_nzcv(tcg_rt
);
1585 gen_set_nzcv(tcg_rt
);
1588 case ARM_CP_CURRENTEL
:
1589 /* Reads as current EL value from pstate, which is
1590 * guaranteed to be constant by the tb flags.
1592 tcg_rt
= cpu_reg(s
, rt
);
1593 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1596 /* Writes clear the aligned block of memory which rt points into. */
1597 tcg_rt
= cpu_reg(s
, rt
);
1598 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1604 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1608 tcg_rt
= cpu_reg(s
, rt
);
1611 if (ri
->type
& ARM_CP_CONST
) {
1612 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1613 } else if (ri
->readfn
) {
1615 tmpptr
= tcg_const_ptr(ri
);
1616 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1617 tcg_temp_free_ptr(tmpptr
);
1619 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1622 if (ri
->type
& ARM_CP_CONST
) {
1623 /* If not forbidden by access permissions, treat as WI */
1625 } else if (ri
->writefn
) {
1627 tmpptr
= tcg_const_ptr(ri
);
1628 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1629 tcg_temp_free_ptr(tmpptr
);
1631 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1635 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1636 /* I/O operations must end the TB here (whether read or write) */
1638 s
->base
.is_jmp
= DISAS_UPDATE
;
1639 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1640 /* We default to ending the TB on a coprocessor register write,
1641 * but allow this to be suppressed by the register definition
1642 * (usually only necessary to work around guest bugs).
1644 s
->base
.is_jmp
= DISAS_UPDATE
;
1649 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1650 * +---------------------+---+-----+-----+-------+-------+-----+------+
1651 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1652 * +---------------------+---+-----+-----+-------+-------+-----+------+
1654 static void disas_system(DisasContext
*s
, uint32_t insn
)
1656 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1657 l
= extract32(insn
, 21, 1);
1658 op0
= extract32(insn
, 19, 2);
1659 op1
= extract32(insn
, 16, 3);
1660 crn
= extract32(insn
, 12, 4);
1661 crm
= extract32(insn
, 8, 4);
1662 op2
= extract32(insn
, 5, 3);
1663 rt
= extract32(insn
, 0, 5);
1666 if (l
|| rt
!= 31) {
1667 unallocated_encoding(s
);
1671 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1672 handle_hint(s
, insn
, op1
, op2
, crm
);
1674 case 3: /* CLREX, DSB, DMB, ISB */
1675 handle_sync(s
, insn
, op1
, op2
, crm
);
1677 case 4: /* MSR (immediate) */
1678 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1681 unallocated_encoding(s
);
1686 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1689 /* Exception generation
1691 * 31 24 23 21 20 5 4 2 1 0
1692 * +-----------------+-----+------------------------+-----+----+
1693 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1694 * +-----------------------+------------------------+----------+
1696 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1698 int opc
= extract32(insn
, 21, 3);
1699 int op2_ll
= extract32(insn
, 0, 5);
1700 int imm16
= extract32(insn
, 5, 16);
1705 /* For SVC, HVC and SMC we advance the single-step state
1706 * machine before taking the exception. This is architecturally
1707 * mandated, to ensure that single-stepping a system call
1708 * instruction works properly.
1713 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1714 default_exception_el(s
));
1717 if (s
->current_el
== 0) {
1718 unallocated_encoding(s
);
1721 /* The pre HVC helper handles cases when HVC gets trapped
1722 * as an undefined insn by runtime configuration.
1724 gen_a64_set_pc_im(s
->pc
- 4);
1725 gen_helper_pre_hvc(cpu_env
);
1727 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1730 if (s
->current_el
== 0) {
1731 unallocated_encoding(s
);
1734 gen_a64_set_pc_im(s
->pc
- 4);
1735 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1736 gen_helper_pre_smc(cpu_env
, tmp
);
1737 tcg_temp_free_i32(tmp
);
1739 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1742 unallocated_encoding(s
);
1748 unallocated_encoding(s
);
1752 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1753 default_exception_el(s
));
1757 unallocated_encoding(s
);
1760 /* HLT. This has two purposes.
1761 * Architecturally, it is an external halting debug instruction.
1762 * Since QEMU doesn't implement external debug, we treat this as
1763 * it is required for halting debug disabled: it will UNDEF.
1764 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1766 if (semihosting_enabled() && imm16
== 0xf000) {
1767 #ifndef CONFIG_USER_ONLY
1768 /* In system mode, don't allow userspace access to semihosting,
1769 * to provide some semblance of security (and for consistency
1770 * with our 32-bit semihosting).
1772 if (s
->current_el
== 0) {
1773 unsupported_encoding(s
, insn
);
1777 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1779 unsupported_encoding(s
, insn
);
1783 if (op2_ll
< 1 || op2_ll
> 3) {
1784 unallocated_encoding(s
);
1787 /* DCPS1, DCPS2, DCPS3 */
1788 unsupported_encoding(s
, insn
);
1791 unallocated_encoding(s
);
1796 /* Unconditional branch (register)
1797 * 31 25 24 21 20 16 15 10 9 5 4 0
1798 * +---------------+-------+-------+-------+------+-------+
1799 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1800 * +---------------+-------+-------+-------+------+-------+
1802 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1804 unsigned int opc
, op2
, op3
, rn
, op4
;
1806 opc
= extract32(insn
, 21, 4);
1807 op2
= extract32(insn
, 16, 5);
1808 op3
= extract32(insn
, 10, 6);
1809 rn
= extract32(insn
, 5, 5);
1810 op4
= extract32(insn
, 0, 5);
1812 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1813 unallocated_encoding(s
);
1821 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1822 /* BLR also needs to load return address */
1824 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1828 if (s
->current_el
== 0) {
1829 unallocated_encoding(s
);
1832 gen_helper_exception_return(cpu_env
);
1833 /* Must exit loop to check un-masked IRQs */
1834 s
->base
.is_jmp
= DISAS_EXIT
;
1838 unallocated_encoding(s
);
1840 unsupported_encoding(s
, insn
);
1844 unallocated_encoding(s
);
1848 s
->base
.is_jmp
= DISAS_JUMP
;
1851 /* Branches, exception generating and system instructions */
1852 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1854 switch (extract32(insn
, 25, 7)) {
1855 case 0x0a: case 0x0b:
1856 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1857 disas_uncond_b_imm(s
, insn
);
1859 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1860 disas_comp_b_imm(s
, insn
);
1862 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1863 disas_test_b_imm(s
, insn
);
1865 case 0x2a: /* Conditional branch (immediate) */
1866 disas_cond_b_imm(s
, insn
);
1868 case 0x6a: /* Exception generation / System */
1869 if (insn
& (1 << 24)) {
1870 disas_system(s
, insn
);
1875 case 0x6b: /* Unconditional branch (register) */
1876 disas_uncond_b_reg(s
, insn
);
1879 unallocated_encoding(s
);
1885 * Load/Store exclusive instructions are implemented by remembering
1886 * the value/address loaded, and seeing if these are the same
1887 * when the store is performed. This is not actually the architecturally
1888 * mandated semantics, but it works for typical guest code sequences
1889 * and avoids having to monitor regular stores.
1891 * The store exclusive uses the atomic cmpxchg primitives to avoid
1892 * races in multi-threaded linux-user and when MTTCG softmmu is
1895 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1896 TCGv_i64 addr
, int size
, bool is_pair
)
1898 int idx
= get_mem_index(s
);
1899 TCGMemOp memop
= s
->be_data
;
1901 g_assert(size
<= 3);
1903 g_assert(size
>= 2);
1905 /* The pair must be single-copy atomic for the doubleword. */
1906 memop
|= MO_64
| MO_ALIGN
;
1907 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
1908 if (s
->be_data
== MO_LE
) {
1909 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
1910 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
1912 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
1913 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
1916 /* The pair must be single-copy atomic for *each* doubleword, not
1917 the entire quadword, however it must be quadword aligned. */
1919 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
1920 memop
| MO_ALIGN_16
);
1922 TCGv_i64 addr2
= tcg_temp_new_i64();
1923 tcg_gen_addi_i64(addr2
, addr
, 8);
1924 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
1925 tcg_temp_free_i64(addr2
);
1927 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
1928 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
1931 memop
|= size
| MO_ALIGN
;
1932 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
1933 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
1935 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1938 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1939 TCGv_i64 addr
, int size
, int is_pair
)
1941 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1942 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1945 * [addr + datasize] = {Rt2};
1951 * env->exclusive_addr = -1;
1953 TCGLabel
*fail_label
= gen_new_label();
1954 TCGLabel
*done_label
= gen_new_label();
1957 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1959 tmp
= tcg_temp_new_i64();
1962 if (s
->be_data
== MO_LE
) {
1963 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1965 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
1967 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
1968 cpu_exclusive_val
, tmp
,
1970 MO_64
| MO_ALIGN
| s
->be_data
);
1971 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1972 } else if (s
->be_data
== MO_LE
) {
1973 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
1974 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
1979 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
1980 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1983 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
1984 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
1989 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
1990 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1994 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
1995 cpu_reg(s
, rt
), get_mem_index(s
),
1996 size
| MO_ALIGN
| s
->be_data
);
1997 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1999 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2000 tcg_temp_free_i64(tmp
);
2001 tcg_gen_br(done_label
);
2003 gen_set_label(fail_label
);
2004 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2005 gen_set_label(done_label
);
2006 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2009 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2010 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2012 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2014 int opc0
= extract32(opc
, 0, 1);
2018 regsize
= opc0
? 32 : 64;
2020 regsize
= size
== 3 ? 64 : 32;
2022 return regsize
== 64;
2025 /* Load/store exclusive
2027 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2028 * +-----+-------------+----+---+----+------+----+-------+------+------+
2029 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2030 * +-----+-------------+----+---+----+------+----+-------+------+------+
2032 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2033 * L: 0 -> store, 1 -> load
2034 * o2: 0 -> exclusive, 1 -> not
2035 * o1: 0 -> single register, 1 -> register pair
2036 * o0: 1 -> load-acquire/store-release, 0 -> not
2038 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2040 int rt
= extract32(insn
, 0, 5);
2041 int rn
= extract32(insn
, 5, 5);
2042 int rt2
= extract32(insn
, 10, 5);
2043 int is_lasr
= extract32(insn
, 15, 1);
2044 int rs
= extract32(insn
, 16, 5);
2045 int is_pair
= extract32(insn
, 21, 1);
2046 int is_store
= !extract32(insn
, 22, 1);
2047 int is_excl
= !extract32(insn
, 23, 1);
2048 int size
= extract32(insn
, 30, 2);
2051 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
2052 (!is_excl
&& is_pair
) ||
2053 (is_pair
&& size
< 2)) {
2054 unallocated_encoding(s
);
2059 gen_check_sp_alignment(s
);
2061 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2063 /* Note that since TCG is single threaded load-acquire/store-release
2064 * semantics require no extra if (is_lasr) { ... } handling.
2070 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2072 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2076 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2078 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2081 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2082 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2084 /* Generate ISS for non-exclusive accesses including LASR. */
2087 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2089 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2090 true, rt
, iss_sf
, is_lasr
);
2092 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2093 true, rt
, iss_sf
, is_lasr
);
2095 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2102 * Load register (literal)
2104 * 31 30 29 27 26 25 24 23 5 4 0
2105 * +-----+-------+---+-----+-------------------+-------+
2106 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2107 * +-----+-------+---+-----+-------------------+-------+
2109 * V: 1 -> vector (simd/fp)
2110 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2111 * 10-> 32 bit signed, 11 -> prefetch
2112 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2114 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2116 int rt
= extract32(insn
, 0, 5);
2117 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2118 bool is_vector
= extract32(insn
, 26, 1);
2119 int opc
= extract32(insn
, 30, 2);
2120 bool is_signed
= false;
2122 TCGv_i64 tcg_rt
, tcg_addr
;
2126 unallocated_encoding(s
);
2130 if (!fp_access_check(s
)) {
2135 /* PRFM (literal) : prefetch */
2138 size
= 2 + extract32(opc
, 0, 1);
2139 is_signed
= extract32(opc
, 1, 1);
2142 tcg_rt
= cpu_reg(s
, rt
);
2144 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2146 do_fp_ld(s
, rt
, tcg_addr
, size
);
2148 /* Only unsigned 32bit loads target 32bit registers. */
2149 bool iss_sf
= opc
!= 0;
2151 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2152 true, rt
, iss_sf
, false);
2154 tcg_temp_free_i64(tcg_addr
);
2158 * LDNP (Load Pair - non-temporal hint)
2159 * LDP (Load Pair - non vector)
2160 * LDPSW (Load Pair Signed Word - non vector)
2161 * STNP (Store Pair - non-temporal hint)
2162 * STP (Store Pair - non vector)
2163 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2164 * LDP (Load Pair of SIMD&FP)
2165 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2166 * STP (Store Pair of SIMD&FP)
2168 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2169 * +-----+-------+---+---+-------+---+-----------------------------+
2170 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2171 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2173 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2175 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2176 * V: 0 -> GPR, 1 -> Vector
2177 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2178 * 10 -> signed offset, 11 -> pre-index
2179 * L: 0 -> Store 1 -> Load
2181 * Rt, Rt2 = GPR or SIMD registers to be stored
2182 * Rn = general purpose register containing address
2183 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2185 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2187 int rt
= extract32(insn
, 0, 5);
2188 int rn
= extract32(insn
, 5, 5);
2189 int rt2
= extract32(insn
, 10, 5);
2190 uint64_t offset
= sextract64(insn
, 15, 7);
2191 int index
= extract32(insn
, 23, 2);
2192 bool is_vector
= extract32(insn
, 26, 1);
2193 bool is_load
= extract32(insn
, 22, 1);
2194 int opc
= extract32(insn
, 30, 2);
2196 bool is_signed
= false;
2197 bool postindex
= false;
2200 TCGv_i64 tcg_addr
; /* calculated address */
2204 unallocated_encoding(s
);
2211 size
= 2 + extract32(opc
, 1, 1);
2212 is_signed
= extract32(opc
, 0, 1);
2213 if (!is_load
&& is_signed
) {
2214 unallocated_encoding(s
);
2220 case 1: /* post-index */
2225 /* signed offset with "non-temporal" hint. Since we don't emulate
2226 * caches we don't care about hints to the cache system about
2227 * data access patterns, and handle this identically to plain
2231 /* There is no non-temporal-hint version of LDPSW */
2232 unallocated_encoding(s
);
2237 case 2: /* signed offset, rn not updated */
2240 case 3: /* pre-index */
2246 if (is_vector
&& !fp_access_check(s
)) {
2253 gen_check_sp_alignment(s
);
2256 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2259 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2264 do_fp_ld(s
, rt
, tcg_addr
, size
);
2266 do_fp_st(s
, rt
, tcg_addr
, size
);
2268 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2270 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2272 do_fp_st(s
, rt2
, tcg_addr
, size
);
2275 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2276 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2279 TCGv_i64 tmp
= tcg_temp_new_i64();
2281 /* Do not modify tcg_rt before recognizing any exception
2282 * from the second load.
2284 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2285 false, 0, false, false);
2286 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2287 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2288 false, 0, false, false);
2290 tcg_gen_mov_i64(tcg_rt
, tmp
);
2291 tcg_temp_free_i64(tmp
);
2293 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2294 false, 0, false, false);
2295 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2296 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2297 false, 0, false, false);
2303 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2305 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2307 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2312 * Load/store (immediate post-indexed)
2313 * Load/store (immediate pre-indexed)
2314 * Load/store (unscaled immediate)
2316 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2317 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2318 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2319 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2321 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2323 * V = 0 -> non-vector
2324 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2325 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2327 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2333 int rn
= extract32(insn
, 5, 5);
2334 int imm9
= sextract32(insn
, 12, 9);
2335 int idx
= extract32(insn
, 10, 2);
2336 bool is_signed
= false;
2337 bool is_store
= false;
2338 bool is_extended
= false;
2339 bool is_unpriv
= (idx
== 2);
2340 bool iss_valid
= !is_vector
;
2347 size
|= (opc
& 2) << 1;
2348 if (size
> 4 || is_unpriv
) {
2349 unallocated_encoding(s
);
2352 is_store
= ((opc
& 1) == 0);
2353 if (!fp_access_check(s
)) {
2357 if (size
== 3 && opc
== 2) {
2358 /* PRFM - prefetch */
2360 unallocated_encoding(s
);
2365 if (opc
== 3 && size
> 1) {
2366 unallocated_encoding(s
);
2369 is_store
= (opc
== 0);
2370 is_signed
= extract32(opc
, 1, 1);
2371 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2389 g_assert_not_reached();
2393 gen_check_sp_alignment(s
);
2395 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2398 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2403 do_fp_st(s
, rt
, tcg_addr
, size
);
2405 do_fp_ld(s
, rt
, tcg_addr
, size
);
2408 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2409 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2410 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2413 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2414 iss_valid
, rt
, iss_sf
, false);
2416 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2417 is_signed
, is_extended
, memidx
,
2418 iss_valid
, rt
, iss_sf
, false);
2423 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2425 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2427 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2432 * Load/store (register offset)
2434 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2435 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2436 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2437 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2440 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2441 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2443 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2444 * opc<0>: 0 -> store, 1 -> load
2445 * V: 1 -> vector/simd
2446 * opt: extend encoding (see DecodeRegExtend)
2447 * S: if S=1 then scale (essentially index by sizeof(size))
2448 * Rt: register to transfer into/out of
2449 * Rn: address register or SP for base
2450 * Rm: offset register or ZR for offset
2452 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2458 int rn
= extract32(insn
, 5, 5);
2459 int shift
= extract32(insn
, 12, 1);
2460 int rm
= extract32(insn
, 16, 5);
2461 int opt
= extract32(insn
, 13, 3);
2462 bool is_signed
= false;
2463 bool is_store
= false;
2464 bool is_extended
= false;
2469 if (extract32(opt
, 1, 1) == 0) {
2470 unallocated_encoding(s
);
2475 size
|= (opc
& 2) << 1;
2477 unallocated_encoding(s
);
2480 is_store
= !extract32(opc
, 0, 1);
2481 if (!fp_access_check(s
)) {
2485 if (size
== 3 && opc
== 2) {
2486 /* PRFM - prefetch */
2489 if (opc
== 3 && size
> 1) {
2490 unallocated_encoding(s
);
2493 is_store
= (opc
== 0);
2494 is_signed
= extract32(opc
, 1, 1);
2495 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2499 gen_check_sp_alignment(s
);
2501 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2503 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2504 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2506 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2510 do_fp_st(s
, rt
, tcg_addr
, size
);
2512 do_fp_ld(s
, rt
, tcg_addr
, size
);
2515 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2516 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2518 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2519 true, rt
, iss_sf
, false);
2521 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2522 is_signed
, is_extended
,
2523 true, rt
, iss_sf
, false);
2529 * Load/store (unsigned immediate)
2531 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2532 * +----+-------+---+-----+-----+------------+-------+------+
2533 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2534 * +----+-------+---+-----+-----+------------+-------+------+
2537 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2538 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2540 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2541 * opc<0>: 0 -> store, 1 -> load
2542 * Rn: base address register (inc SP)
2543 * Rt: target register
2545 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2551 int rn
= extract32(insn
, 5, 5);
2552 unsigned int imm12
= extract32(insn
, 10, 12);
2553 unsigned int offset
;
2558 bool is_signed
= false;
2559 bool is_extended
= false;
2562 size
|= (opc
& 2) << 1;
2564 unallocated_encoding(s
);
2567 is_store
= !extract32(opc
, 0, 1);
2568 if (!fp_access_check(s
)) {
2572 if (size
== 3 && opc
== 2) {
2573 /* PRFM - prefetch */
2576 if (opc
== 3 && size
> 1) {
2577 unallocated_encoding(s
);
2580 is_store
= (opc
== 0);
2581 is_signed
= extract32(opc
, 1, 1);
2582 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2586 gen_check_sp_alignment(s
);
2588 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2589 offset
= imm12
<< size
;
2590 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2594 do_fp_st(s
, rt
, tcg_addr
, size
);
2596 do_fp_ld(s
, rt
, tcg_addr
, size
);
2599 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2600 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2602 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2603 true, rt
, iss_sf
, false);
2605 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2606 true, rt
, iss_sf
, false);
2611 /* Load/store register (all forms) */
2612 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2614 int rt
= extract32(insn
, 0, 5);
2615 int opc
= extract32(insn
, 22, 2);
2616 bool is_vector
= extract32(insn
, 26, 1);
2617 int size
= extract32(insn
, 30, 2);
2619 switch (extract32(insn
, 24, 2)) {
2621 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2622 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2624 /* Load/store register (unscaled immediate)
2625 * Load/store immediate pre/post-indexed
2626 * Load/store register unprivileged
2628 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2632 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2635 unallocated_encoding(s
);
2640 /* AdvSIMD load/store multiple structures
2642 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2643 * +---+---+---------------+---+-------------+--------+------+------+------+
2644 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2645 * +---+---+---------------+---+-------------+--------+------+------+------+
2647 * AdvSIMD load/store multiple structures (post-indexed)
2649 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2650 * +---+---+---------------+---+---+---------+--------+------+------+------+
2651 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2652 * +---+---+---------------+---+---+---------+--------+------+------+------+
2654 * Rt: first (or only) SIMD&FP register to be transferred
2655 * Rn: base address or SP
2656 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2658 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2660 int rt
= extract32(insn
, 0, 5);
2661 int rn
= extract32(insn
, 5, 5);
2662 int size
= extract32(insn
, 10, 2);
2663 int opcode
= extract32(insn
, 12, 4);
2664 bool is_store
= !extract32(insn
, 22, 1);
2665 bool is_postidx
= extract32(insn
, 23, 1);
2666 bool is_q
= extract32(insn
, 30, 1);
2667 TCGv_i64 tcg_addr
, tcg_rn
;
2669 int ebytes
= 1 << size
;
2670 int elements
= (is_q
? 128 : 64) / (8 << size
);
2671 int rpt
; /* num iterations */
2672 int selem
; /* structure elements */
2675 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2676 unallocated_encoding(s
);
2680 /* From the shared decode logic */
2711 unallocated_encoding(s
);
2715 if (size
== 3 && !is_q
&& selem
!= 1) {
2717 unallocated_encoding(s
);
2721 if (!fp_access_check(s
)) {
2726 gen_check_sp_alignment(s
);
2729 tcg_rn
= cpu_reg_sp(s
, rn
);
2730 tcg_addr
= tcg_temp_new_i64();
2731 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2733 for (r
= 0; r
< rpt
; r
++) {
2735 for (e
= 0; e
< elements
; e
++) {
2736 int tt
= (rt
+ r
) % 32;
2738 for (xs
= 0; xs
< selem
; xs
++) {
2740 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2742 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2744 /* For non-quad operations, setting a slice of the low
2745 * 64 bits of the register clears the high 64 bits (in
2746 * the ARM ARM pseudocode this is implicit in the fact
2747 * that 'rval' is a 64 bit wide variable). We optimize
2748 * by noticing that we only need to do this the first
2749 * time we touch a register.
2751 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2752 clear_vec_high(s
, tt
);
2755 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2762 int rm
= extract32(insn
, 16, 5);
2764 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2766 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2769 tcg_temp_free_i64(tcg_addr
);
2772 /* AdvSIMD load/store single structure
2774 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2775 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2776 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2777 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2779 * AdvSIMD load/store single structure (post-indexed)
2781 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2782 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2783 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2784 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2786 * Rt: first (or only) SIMD&FP register to be transferred
2787 * Rn: base address or SP
2788 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2789 * index = encoded in Q:S:size dependent on size
2791 * lane_size = encoded in R, opc
2792 * transfer width = encoded in opc, S, size
2794 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2796 int rt
= extract32(insn
, 0, 5);
2797 int rn
= extract32(insn
, 5, 5);
2798 int size
= extract32(insn
, 10, 2);
2799 int S
= extract32(insn
, 12, 1);
2800 int opc
= extract32(insn
, 13, 3);
2801 int R
= extract32(insn
, 21, 1);
2802 int is_load
= extract32(insn
, 22, 1);
2803 int is_postidx
= extract32(insn
, 23, 1);
2804 int is_q
= extract32(insn
, 30, 1);
2806 int scale
= extract32(opc
, 1, 2);
2807 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2808 bool replicate
= false;
2809 int index
= is_q
<< 3 | S
<< 2 | size
;
2811 TCGv_i64 tcg_addr
, tcg_rn
;
2815 if (!is_load
|| S
) {
2816 unallocated_encoding(s
);
2825 if (extract32(size
, 0, 1)) {
2826 unallocated_encoding(s
);
2832 if (extract32(size
, 1, 1)) {
2833 unallocated_encoding(s
);
2836 if (!extract32(size
, 0, 1)) {
2840 unallocated_encoding(s
);
2848 g_assert_not_reached();
2851 if (!fp_access_check(s
)) {
2855 ebytes
= 1 << scale
;
2858 gen_check_sp_alignment(s
);
2861 tcg_rn
= cpu_reg_sp(s
, rn
);
2862 tcg_addr
= tcg_temp_new_i64();
2863 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2865 for (xs
= 0; xs
< selem
; xs
++) {
2867 /* Load and replicate to all elements */
2869 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2871 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2872 get_mem_index(s
), s
->be_data
+ scale
);
2875 mulconst
= 0x0101010101010101ULL
;
2878 mulconst
= 0x0001000100010001ULL
;
2881 mulconst
= 0x0000000100000001ULL
;
2887 g_assert_not_reached();
2890 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2892 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2894 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2896 clear_vec_high(s
, rt
);
2898 tcg_temp_free_i64(tcg_tmp
);
2900 /* Load/store one element per register */
2902 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2904 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2907 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2912 int rm
= extract32(insn
, 16, 5);
2914 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2916 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2919 tcg_temp_free_i64(tcg_addr
);
2922 /* Loads and stores */
2923 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2925 switch (extract32(insn
, 24, 6)) {
2926 case 0x08: /* Load/store exclusive */
2927 disas_ldst_excl(s
, insn
);
2929 case 0x18: case 0x1c: /* Load register (literal) */
2930 disas_ld_lit(s
, insn
);
2932 case 0x28: case 0x29:
2933 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2934 disas_ldst_pair(s
, insn
);
2936 case 0x38: case 0x39:
2937 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2938 disas_ldst_reg(s
, insn
);
2940 case 0x0c: /* AdvSIMD load/store multiple structures */
2941 disas_ldst_multiple_struct(s
, insn
);
2943 case 0x0d: /* AdvSIMD load/store single structure */
2944 disas_ldst_single_struct(s
, insn
);
2947 unallocated_encoding(s
);
2952 /* PC-rel. addressing
2953 * 31 30 29 28 24 23 5 4 0
2954 * +----+-------+-----------+-------------------+------+
2955 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2956 * +----+-------+-----------+-------------------+------+
2958 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2960 unsigned int page
, rd
;
2964 page
= extract32(insn
, 31, 1);
2965 /* SignExtend(immhi:immlo) -> offset */
2966 offset
= sextract64(insn
, 5, 19);
2967 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2968 rd
= extract32(insn
, 0, 5);
2972 /* ADRP (page based) */
2977 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2981 * Add/subtract (immediate)
2983 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2984 * +--+--+--+-----------+-----+-------------+-----+-----+
2985 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2986 * +--+--+--+-----------+-----+-------------+-----+-----+
2988 * sf: 0 -> 32bit, 1 -> 64bit
2989 * op: 0 -> add , 1 -> sub
2991 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2993 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2995 int rd
= extract32(insn
, 0, 5);
2996 int rn
= extract32(insn
, 5, 5);
2997 uint64_t imm
= extract32(insn
, 10, 12);
2998 int shift
= extract32(insn
, 22, 2);
2999 bool setflags
= extract32(insn
, 29, 1);
3000 bool sub_op
= extract32(insn
, 30, 1);
3001 bool is_64bit
= extract32(insn
, 31, 1);
3003 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3004 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3005 TCGv_i64 tcg_result
;
3014 unallocated_encoding(s
);
3018 tcg_result
= tcg_temp_new_i64();
3021 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3023 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3026 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3028 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3030 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3032 tcg_temp_free_i64(tcg_imm
);
3036 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3038 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3041 tcg_temp_free_i64(tcg_result
);
3044 /* The input should be a value in the bottom e bits (with higher
3045 * bits zero); returns that value replicated into every element
3046 * of size e in a 64 bit integer.
3048 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3058 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3059 static inline uint64_t bitmask64(unsigned int length
)
3061 assert(length
> 0 && length
<= 64);
3062 return ~0ULL >> (64 - length
);
3065 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3066 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3067 * value (ie should cause a guest UNDEF exception), and true if they are
3068 * valid, in which case the decoded bit pattern is written to result.
3070 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3071 unsigned int imms
, unsigned int immr
)
3074 unsigned e
, levels
, s
, r
;
3077 assert(immn
< 2 && imms
< 64 && immr
< 64);
3079 /* The bit patterns we create here are 64 bit patterns which
3080 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3081 * 64 bits each. Each element contains the same value: a run
3082 * of between 1 and e-1 non-zero bits, rotated within the
3083 * element by between 0 and e-1 bits.
3085 * The element size and run length are encoded into immn (1 bit)
3086 * and imms (6 bits) as follows:
3087 * 64 bit elements: immn = 1, imms = <length of run - 1>
3088 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3089 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3090 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3091 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3092 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3093 * Notice that immn = 0, imms = 11111x is the only combination
3094 * not covered by one of the above options; this is reserved.
3095 * Further, <length of run - 1> all-ones is a reserved pattern.
3097 * In all cases the rotation is by immr % e (and immr is 6 bits).
3100 /* First determine the element size */
3101 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3103 /* This is the immn == 0, imms == 0x11111x case */
3113 /* <length of run - 1> mustn't be all-ones. */
3117 /* Create the value of one element: s+1 set bits rotated
3118 * by r within the element (which is e bits wide)...
3120 mask
= bitmask64(s
+ 1);
3122 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3123 mask
&= bitmask64(e
);
3125 /* ...then replicate the element over the whole 64 bit value */
3126 mask
= bitfield_replicate(mask
, e
);
3131 /* Logical (immediate)
3132 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3133 * +----+-----+-------------+---+------+------+------+------+
3134 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3135 * +----+-----+-------------+---+------+------+------+------+
3137 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3139 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3140 TCGv_i64 tcg_rd
, tcg_rn
;
3142 bool is_and
= false;
3144 sf
= extract32(insn
, 31, 1);
3145 opc
= extract32(insn
, 29, 2);
3146 is_n
= extract32(insn
, 22, 1);
3147 immr
= extract32(insn
, 16, 6);
3148 imms
= extract32(insn
, 10, 6);
3149 rn
= extract32(insn
, 5, 5);
3150 rd
= extract32(insn
, 0, 5);
3153 unallocated_encoding(s
);
3157 if (opc
== 0x3) { /* ANDS */
3158 tcg_rd
= cpu_reg(s
, rd
);
3160 tcg_rd
= cpu_reg_sp(s
, rd
);
3162 tcg_rn
= cpu_reg(s
, rn
);
3164 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3165 /* some immediate field values are reserved */
3166 unallocated_encoding(s
);
3171 wmask
&= 0xffffffff;
3175 case 0x3: /* ANDS */
3177 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3181 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3184 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3187 assert(FALSE
); /* must handle all above */
3191 if (!sf
&& !is_and
) {
3192 /* zero extend final result; we know we can skip this for AND
3193 * since the immediate had the high 32 bits clear.
3195 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3198 if (opc
== 3) { /* ANDS */
3199 gen_logic_CC(sf
, tcg_rd
);
3204 * Move wide (immediate)
3206 * 31 30 29 28 23 22 21 20 5 4 0
3207 * +--+-----+-------------+-----+----------------+------+
3208 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3209 * +--+-----+-------------+-----+----------------+------+
3211 * sf: 0 -> 32 bit, 1 -> 64 bit
3212 * opc: 00 -> N, 10 -> Z, 11 -> K
3213 * hw: shift/16 (0,16, and sf only 32, 48)
3215 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3217 int rd
= extract32(insn
, 0, 5);
3218 uint64_t imm
= extract32(insn
, 5, 16);
3219 int sf
= extract32(insn
, 31, 1);
3220 int opc
= extract32(insn
, 29, 2);
3221 int pos
= extract32(insn
, 21, 2) << 4;
3222 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3225 if (!sf
&& (pos
>= 32)) {
3226 unallocated_encoding(s
);
3240 tcg_gen_movi_i64(tcg_rd
, imm
);
3243 tcg_imm
= tcg_const_i64(imm
);
3244 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3245 tcg_temp_free_i64(tcg_imm
);
3247 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3251 unallocated_encoding(s
);
3257 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3258 * +----+-----+-------------+---+------+------+------+------+
3259 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3260 * +----+-----+-------------+---+------+------+------+------+
3262 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3264 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3265 TCGv_i64 tcg_rd
, tcg_tmp
;
3267 sf
= extract32(insn
, 31, 1);
3268 opc
= extract32(insn
, 29, 2);
3269 n
= extract32(insn
, 22, 1);
3270 ri
= extract32(insn
, 16, 6);
3271 si
= extract32(insn
, 10, 6);
3272 rn
= extract32(insn
, 5, 5);
3273 rd
= extract32(insn
, 0, 5);
3274 bitsize
= sf
? 64 : 32;
3276 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3277 unallocated_encoding(s
);
3281 tcg_rd
= cpu_reg(s
, rd
);
3283 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3284 to be smaller than bitsize, we'll never reference data outside the
3285 low 32-bits anyway. */
3286 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3288 /* Recognize simple(r) extractions. */
3290 /* Wd<s-r:0> = Wn<s:r> */
3291 len
= (si
- ri
) + 1;
3292 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3293 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3295 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3296 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3299 /* opc == 1, BXFIL fall through to deposit */
3300 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3303 /* Handle the ri > si case with a deposit
3304 * Wd<32+s-r,32-r> = Wn<s:0>
3307 pos
= (bitsize
- ri
) & (bitsize
- 1);
3310 if (opc
== 0 && len
< ri
) {
3311 /* SBFM: sign extend the destination field from len to fill
3312 the balance of the word. Let the deposit below insert all
3313 of those sign bits. */
3314 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3318 if (opc
== 1) { /* BFM, BXFIL */
3319 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3321 /* SBFM or UBFM: We start with zero, and we haven't modified
3322 any bits outside bitsize, therefore the zero-extension
3323 below is unneeded. */
3324 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3329 if (!sf
) { /* zero extend final result */
3330 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3335 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3336 * +----+------+-------------+---+----+------+--------+------+------+
3337 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3338 * +----+------+-------------+---+----+------+--------+------+------+
3340 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3342 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3344 sf
= extract32(insn
, 31, 1);
3345 n
= extract32(insn
, 22, 1);
3346 rm
= extract32(insn
, 16, 5);
3347 imm
= extract32(insn
, 10, 6);
3348 rn
= extract32(insn
, 5, 5);
3349 rd
= extract32(insn
, 0, 5);
3350 op21
= extract32(insn
, 29, 2);
3351 op0
= extract32(insn
, 21, 1);
3352 bitsize
= sf
? 64 : 32;
3354 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3355 unallocated_encoding(s
);
3357 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3359 tcg_rd
= cpu_reg(s
, rd
);
3361 if (unlikely(imm
== 0)) {
3362 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3363 * so an extract from bit 0 is a special case.
3366 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3368 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3370 } else if (rm
== rn
) { /* ROR */
3371 tcg_rm
= cpu_reg(s
, rm
);
3373 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3375 TCGv_i32 tmp
= tcg_temp_new_i32();
3376 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3377 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3378 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3379 tcg_temp_free_i32(tmp
);
3382 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3383 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3384 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3385 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3386 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3388 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3394 /* Data processing - immediate */
3395 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3397 switch (extract32(insn
, 23, 6)) {
3398 case 0x20: case 0x21: /* PC-rel. addressing */
3399 disas_pc_rel_adr(s
, insn
);
3401 case 0x22: case 0x23: /* Add/subtract (immediate) */
3402 disas_add_sub_imm(s
, insn
);
3404 case 0x24: /* Logical (immediate) */
3405 disas_logic_imm(s
, insn
);
3407 case 0x25: /* Move wide (immediate) */
3408 disas_movw_imm(s
, insn
);
3410 case 0x26: /* Bitfield */
3411 disas_bitfield(s
, insn
);
3413 case 0x27: /* Extract */
3414 disas_extract(s
, insn
);
3417 unallocated_encoding(s
);
3422 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3423 * Note that it is the caller's responsibility to ensure that the
3424 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3425 * mandated semantics for out of range shifts.
3427 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3428 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3430 switch (shift_type
) {
3431 case A64_SHIFT_TYPE_LSL
:
3432 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3434 case A64_SHIFT_TYPE_LSR
:
3435 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3437 case A64_SHIFT_TYPE_ASR
:
3439 tcg_gen_ext32s_i64(dst
, src
);
3441 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3443 case A64_SHIFT_TYPE_ROR
:
3445 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3448 t0
= tcg_temp_new_i32();
3449 t1
= tcg_temp_new_i32();
3450 tcg_gen_extrl_i64_i32(t0
, src
);
3451 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3452 tcg_gen_rotr_i32(t0
, t0
, t1
);
3453 tcg_gen_extu_i32_i64(dst
, t0
);
3454 tcg_temp_free_i32(t0
);
3455 tcg_temp_free_i32(t1
);
3459 assert(FALSE
); /* all shift types should be handled */
3463 if (!sf
) { /* zero extend final result */
3464 tcg_gen_ext32u_i64(dst
, dst
);
3468 /* Shift a TCGv src by immediate, put result in dst.
3469 * The shift amount must be in range (this should always be true as the
3470 * relevant instructions will UNDEF on bad shift immediates).
3472 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3473 enum a64_shift_type shift_type
, unsigned int shift_i
)
3475 assert(shift_i
< (sf
? 64 : 32));
3478 tcg_gen_mov_i64(dst
, src
);
3480 TCGv_i64 shift_const
;
3482 shift_const
= tcg_const_i64(shift_i
);
3483 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3484 tcg_temp_free_i64(shift_const
);
3488 /* Logical (shifted register)
3489 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3490 * +----+-----+-----------+-------+---+------+--------+------+------+
3491 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3492 * +----+-----+-----------+-------+---+------+--------+------+------+
3494 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3496 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3497 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3499 sf
= extract32(insn
, 31, 1);
3500 opc
= extract32(insn
, 29, 2);
3501 shift_type
= extract32(insn
, 22, 2);
3502 invert
= extract32(insn
, 21, 1);
3503 rm
= extract32(insn
, 16, 5);
3504 shift_amount
= extract32(insn
, 10, 6);
3505 rn
= extract32(insn
, 5, 5);
3506 rd
= extract32(insn
, 0, 5);
3508 if (!sf
&& (shift_amount
& (1 << 5))) {
3509 unallocated_encoding(s
);
3513 tcg_rd
= cpu_reg(s
, rd
);
3515 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3516 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3517 * register-register MOV and MVN, so it is worth special casing.
3519 tcg_rm
= cpu_reg(s
, rm
);
3521 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3523 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3527 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3529 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3535 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3538 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3541 tcg_rn
= cpu_reg(s
, rn
);
3543 switch (opc
| (invert
<< 2)) {
3546 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3549 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3552 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3556 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3559 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3562 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3570 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3574 gen_logic_CC(sf
, tcg_rd
);
3579 * Add/subtract (extended register)
3581 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3582 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3583 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3584 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3586 * sf: 0 -> 32bit, 1 -> 64bit
3587 * op: 0 -> add , 1 -> sub
3590 * option: extension type (see DecodeRegExtend)
3591 * imm3: optional shift to Rm
3593 * Rd = Rn + LSL(extend(Rm), amount)
3595 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3597 int rd
= extract32(insn
, 0, 5);
3598 int rn
= extract32(insn
, 5, 5);
3599 int imm3
= extract32(insn
, 10, 3);
3600 int option
= extract32(insn
, 13, 3);
3601 int rm
= extract32(insn
, 16, 5);
3602 bool setflags
= extract32(insn
, 29, 1);
3603 bool sub_op
= extract32(insn
, 30, 1);
3604 bool sf
= extract32(insn
, 31, 1);
3606 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3608 TCGv_i64 tcg_result
;
3611 unallocated_encoding(s
);
3615 /* non-flag setting ops may use SP */
3617 tcg_rd
= cpu_reg_sp(s
, rd
);
3619 tcg_rd
= cpu_reg(s
, rd
);
3621 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3623 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3624 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3626 tcg_result
= tcg_temp_new_i64();
3630 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3632 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3636 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3638 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3643 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3645 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3648 tcg_temp_free_i64(tcg_result
);
3652 * Add/subtract (shifted register)
3654 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3655 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3656 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3657 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3659 * sf: 0 -> 32bit, 1 -> 64bit
3660 * op: 0 -> add , 1 -> sub
3662 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3663 * imm6: Shift amount to apply to Rm before the add/sub
3665 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3667 int rd
= extract32(insn
, 0, 5);
3668 int rn
= extract32(insn
, 5, 5);
3669 int imm6
= extract32(insn
, 10, 6);
3670 int rm
= extract32(insn
, 16, 5);
3671 int shift_type
= extract32(insn
, 22, 2);
3672 bool setflags
= extract32(insn
, 29, 1);
3673 bool sub_op
= extract32(insn
, 30, 1);
3674 bool sf
= extract32(insn
, 31, 1);
3676 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3677 TCGv_i64 tcg_rn
, tcg_rm
;
3678 TCGv_i64 tcg_result
;
3680 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3681 unallocated_encoding(s
);
3685 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3686 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3688 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3690 tcg_result
= tcg_temp_new_i64();
3694 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3696 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3700 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3702 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3707 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3709 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3712 tcg_temp_free_i64(tcg_result
);
3715 /* Data-processing (3 source)
3717 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3718 * +--+------+-----------+------+------+----+------+------+------+
3719 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3720 * +--+------+-----------+------+------+----+------+------+------+
3722 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3724 int rd
= extract32(insn
, 0, 5);
3725 int rn
= extract32(insn
, 5, 5);
3726 int ra
= extract32(insn
, 10, 5);
3727 int rm
= extract32(insn
, 16, 5);
3728 int op_id
= (extract32(insn
, 29, 3) << 4) |
3729 (extract32(insn
, 21, 3) << 1) |
3730 extract32(insn
, 15, 1);
3731 bool sf
= extract32(insn
, 31, 1);
3732 bool is_sub
= extract32(op_id
, 0, 1);
3733 bool is_high
= extract32(op_id
, 2, 1);
3734 bool is_signed
= false;
3739 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3741 case 0x42: /* SMADDL */
3742 case 0x43: /* SMSUBL */
3743 case 0x44: /* SMULH */
3746 case 0x0: /* MADD (32bit) */
3747 case 0x1: /* MSUB (32bit) */
3748 case 0x40: /* MADD (64bit) */
3749 case 0x41: /* MSUB (64bit) */
3750 case 0x4a: /* UMADDL */
3751 case 0x4b: /* UMSUBL */
3752 case 0x4c: /* UMULH */
3755 unallocated_encoding(s
);
3760 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3761 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3762 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3763 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3766 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3768 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3771 tcg_temp_free_i64(low_bits
);
3775 tcg_op1
= tcg_temp_new_i64();
3776 tcg_op2
= tcg_temp_new_i64();
3777 tcg_tmp
= tcg_temp_new_i64();
3780 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3781 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3784 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3785 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3787 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3788 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3792 if (ra
== 31 && !is_sub
) {
3793 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3794 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3796 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3798 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3800 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3805 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3808 tcg_temp_free_i64(tcg_op1
);
3809 tcg_temp_free_i64(tcg_op2
);
3810 tcg_temp_free_i64(tcg_tmp
);
3813 /* Add/subtract (with carry)
3814 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3815 * +--+--+--+------------------------+------+---------+------+-----+
3816 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3817 * +--+--+--+------------------------+------+---------+------+-----+
3821 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3823 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3824 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3826 if (extract32(insn
, 10, 6) != 0) {
3827 unallocated_encoding(s
);
3831 sf
= extract32(insn
, 31, 1);
3832 op
= extract32(insn
, 30, 1);
3833 setflags
= extract32(insn
, 29, 1);
3834 rm
= extract32(insn
, 16, 5);
3835 rn
= extract32(insn
, 5, 5);
3836 rd
= extract32(insn
, 0, 5);
3838 tcg_rd
= cpu_reg(s
, rd
);
3839 tcg_rn
= cpu_reg(s
, rn
);
3842 tcg_y
= new_tmp_a64(s
);
3843 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3845 tcg_y
= cpu_reg(s
, rm
);
3849 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3851 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3855 /* Conditional compare (immediate / register)
3856 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3857 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3858 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3859 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3862 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3864 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3865 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3866 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3869 if (!extract32(insn
, 29, 1)) {
3870 unallocated_encoding(s
);
3873 if (insn
& (1 << 10 | 1 << 4)) {
3874 unallocated_encoding(s
);
3877 sf
= extract32(insn
, 31, 1);
3878 op
= extract32(insn
, 30, 1);
3879 is_imm
= extract32(insn
, 11, 1);
3880 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3881 cond
= extract32(insn
, 12, 4);
3882 rn
= extract32(insn
, 5, 5);
3883 nzcv
= extract32(insn
, 0, 4);
3885 /* Set T0 = !COND. */
3886 tcg_t0
= tcg_temp_new_i32();
3887 arm_test_cc(&c
, cond
);
3888 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3891 /* Load the arguments for the new comparison. */
3893 tcg_y
= new_tmp_a64(s
);
3894 tcg_gen_movi_i64(tcg_y
, y
);
3896 tcg_y
= cpu_reg(s
, y
);
3898 tcg_rn
= cpu_reg(s
, rn
);
3900 /* Set the flags for the new comparison. */
3901 tcg_tmp
= tcg_temp_new_i64();
3903 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3905 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3907 tcg_temp_free_i64(tcg_tmp
);
3909 /* If COND was false, force the flags to #nzcv. Compute two masks
3910 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3911 * For tcg hosts that support ANDC, we can make do with just T1.
3912 * In either case, allow the tcg optimizer to delete any unused mask.
3914 tcg_t1
= tcg_temp_new_i32();
3915 tcg_t2
= tcg_temp_new_i32();
3916 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3917 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3919 if (nzcv
& 8) { /* N */
3920 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3922 if (TCG_TARGET_HAS_andc_i32
) {
3923 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3925 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3928 if (nzcv
& 4) { /* Z */
3929 if (TCG_TARGET_HAS_andc_i32
) {
3930 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3932 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3935 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3937 if (nzcv
& 2) { /* C */
3938 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3940 if (TCG_TARGET_HAS_andc_i32
) {
3941 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3943 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3946 if (nzcv
& 1) { /* V */
3947 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3949 if (TCG_TARGET_HAS_andc_i32
) {
3950 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3952 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3955 tcg_temp_free_i32(tcg_t0
);
3956 tcg_temp_free_i32(tcg_t1
);
3957 tcg_temp_free_i32(tcg_t2
);
3960 /* Conditional select
3961 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3962 * +----+----+---+-----------------+------+------+-----+------+------+
3963 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3964 * +----+----+---+-----------------+------+------+-----+------+------+
3966 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3968 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3969 TCGv_i64 tcg_rd
, zero
;
3972 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3973 /* S == 1 or op2<1> == 1 */
3974 unallocated_encoding(s
);
3977 sf
= extract32(insn
, 31, 1);
3978 else_inv
= extract32(insn
, 30, 1);
3979 rm
= extract32(insn
, 16, 5);
3980 cond
= extract32(insn
, 12, 4);
3981 else_inc
= extract32(insn
, 10, 1);
3982 rn
= extract32(insn
, 5, 5);
3983 rd
= extract32(insn
, 0, 5);
3985 tcg_rd
= cpu_reg(s
, rd
);
3987 a64_test_cc(&c
, cond
);
3988 zero
= tcg_const_i64(0);
3990 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3992 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3994 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3997 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3998 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3999 if (else_inv
&& else_inc
) {
4000 tcg_gen_neg_i64(t_false
, t_false
);
4001 } else if (else_inv
) {
4002 tcg_gen_not_i64(t_false
, t_false
);
4003 } else if (else_inc
) {
4004 tcg_gen_addi_i64(t_false
, t_false
, 1);
4006 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4009 tcg_temp_free_i64(zero
);
4013 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4017 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4018 unsigned int rn
, unsigned int rd
)
4020 TCGv_i64 tcg_rd
, tcg_rn
;
4021 tcg_rd
= cpu_reg(s
, rd
);
4022 tcg_rn
= cpu_reg(s
, rn
);
4025 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4027 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4028 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4029 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4030 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4031 tcg_temp_free_i32(tcg_tmp32
);
4035 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4036 unsigned int rn
, unsigned int rd
)
4038 TCGv_i64 tcg_rd
, tcg_rn
;
4039 tcg_rd
= cpu_reg(s
, rd
);
4040 tcg_rn
= cpu_reg(s
, rn
);
4043 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4045 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4046 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4047 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4048 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4049 tcg_temp_free_i32(tcg_tmp32
);
4053 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4054 unsigned int rn
, unsigned int rd
)
4056 TCGv_i64 tcg_rd
, tcg_rn
;
4057 tcg_rd
= cpu_reg(s
, rd
);
4058 tcg_rn
= cpu_reg(s
, rn
);
4061 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4063 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4064 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4065 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4066 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4067 tcg_temp_free_i32(tcg_tmp32
);
4071 /* REV with sf==1, opcode==3 ("REV64") */
4072 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4073 unsigned int rn
, unsigned int rd
)
4076 unallocated_encoding(s
);
4079 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4082 /* REV with sf==0, opcode==2
4083 * REV32 (sf==1, opcode==2)
4085 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4086 unsigned int rn
, unsigned int rd
)
4088 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4091 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4092 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4094 /* bswap32_i64 requires zero high word */
4095 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4096 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4097 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4098 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4099 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4101 tcg_temp_free_i64(tcg_tmp
);
4103 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4104 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4108 /* REV16 (opcode==1) */
4109 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4110 unsigned int rn
, unsigned int rd
)
4112 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4113 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4114 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4115 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4117 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4118 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4119 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4120 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4121 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4123 tcg_temp_free_i64(mask
);
4124 tcg_temp_free_i64(tcg_tmp
);
4127 /* Data-processing (1 source)
4128 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4129 * +----+---+---+-----------------+---------+--------+------+------+
4130 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4131 * +----+---+---+-----------------+---------+--------+------+------+
4133 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4135 unsigned int sf
, opcode
, rn
, rd
;
4137 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4138 unallocated_encoding(s
);
4142 sf
= extract32(insn
, 31, 1);
4143 opcode
= extract32(insn
, 10, 6);
4144 rn
= extract32(insn
, 5, 5);
4145 rd
= extract32(insn
, 0, 5);
4149 handle_rbit(s
, sf
, rn
, rd
);
4152 handle_rev16(s
, sf
, rn
, rd
);
4155 handle_rev32(s
, sf
, rn
, rd
);
4158 handle_rev64(s
, sf
, rn
, rd
);
4161 handle_clz(s
, sf
, rn
, rd
);
4164 handle_cls(s
, sf
, rn
, rd
);
4169 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4170 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4172 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4173 tcg_rd
= cpu_reg(s
, rd
);
4175 if (!sf
&& is_signed
) {
4176 tcg_n
= new_tmp_a64(s
);
4177 tcg_m
= new_tmp_a64(s
);
4178 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4179 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4181 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4182 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4186 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4188 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4191 if (!sf
) { /* zero extend final result */
4192 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4196 /* LSLV, LSRV, ASRV, RORV */
4197 static void handle_shift_reg(DisasContext
*s
,
4198 enum a64_shift_type shift_type
, unsigned int sf
,
4199 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4201 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4202 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4203 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4205 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4206 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4207 tcg_temp_free_i64(tcg_shift
);
4210 /* CRC32[BHWX], CRC32C[BHWX] */
4211 static void handle_crc32(DisasContext
*s
,
4212 unsigned int sf
, unsigned int sz
, bool crc32c
,
4213 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4215 TCGv_i64 tcg_acc
, tcg_val
;
4218 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4219 || (sf
== 1 && sz
!= 3)
4220 || (sf
== 0 && sz
== 3)) {
4221 unallocated_encoding(s
);
4226 tcg_val
= cpu_reg(s
, rm
);
4240 g_assert_not_reached();
4242 tcg_val
= new_tmp_a64(s
);
4243 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4246 tcg_acc
= cpu_reg(s
, rn
);
4247 tcg_bytes
= tcg_const_i32(1 << sz
);
4250 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4252 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4255 tcg_temp_free_i32(tcg_bytes
);
4258 /* Data-processing (2 source)
4259 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4260 * +----+---+---+-----------------+------+--------+------+------+
4261 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4262 * +----+---+---+-----------------+------+--------+------+------+
4264 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4266 unsigned int sf
, rm
, opcode
, rn
, rd
;
4267 sf
= extract32(insn
, 31, 1);
4268 rm
= extract32(insn
, 16, 5);
4269 opcode
= extract32(insn
, 10, 6);
4270 rn
= extract32(insn
, 5, 5);
4271 rd
= extract32(insn
, 0, 5);
4273 if (extract32(insn
, 29, 1)) {
4274 unallocated_encoding(s
);
4280 handle_div(s
, false, sf
, rm
, rn
, rd
);
4283 handle_div(s
, true, sf
, rm
, rn
, rd
);
4286 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4289 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4292 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4295 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4304 case 23: /* CRC32 */
4306 int sz
= extract32(opcode
, 0, 2);
4307 bool crc32c
= extract32(opcode
, 2, 1);
4308 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4312 unallocated_encoding(s
);
4317 /* Data processing - register */
4318 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4320 switch (extract32(insn
, 24, 5)) {
4321 case 0x0a: /* Logical (shifted register) */
4322 disas_logic_reg(s
, insn
);
4324 case 0x0b: /* Add/subtract */
4325 if (insn
& (1 << 21)) { /* (extended register) */
4326 disas_add_sub_ext_reg(s
, insn
);
4328 disas_add_sub_reg(s
, insn
);
4331 case 0x1b: /* Data-processing (3 source) */
4332 disas_data_proc_3src(s
, insn
);
4335 switch (extract32(insn
, 21, 3)) {
4336 case 0x0: /* Add/subtract (with carry) */
4337 disas_adc_sbc(s
, insn
);
4339 case 0x2: /* Conditional compare */
4340 disas_cc(s
, insn
); /* both imm and reg forms */
4342 case 0x4: /* Conditional select */
4343 disas_cond_select(s
, insn
);
4345 case 0x6: /* Data-processing */
4346 if (insn
& (1 << 30)) { /* (1 source) */
4347 disas_data_proc_1src(s
, insn
);
4348 } else { /* (2 source) */
4349 disas_data_proc_2src(s
, insn
);
4353 unallocated_encoding(s
);
4358 unallocated_encoding(s
);
4363 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4364 unsigned int rn
, unsigned int rm
,
4365 bool cmp_with_zero
, bool signal_all_nans
)
4367 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4368 TCGv_ptr fpst
= get_fpstatus_ptr();
4371 TCGv_i64 tcg_vn
, tcg_vm
;
4373 tcg_vn
= read_fp_dreg(s
, rn
);
4374 if (cmp_with_zero
) {
4375 tcg_vm
= tcg_const_i64(0);
4377 tcg_vm
= read_fp_dreg(s
, rm
);
4379 if (signal_all_nans
) {
4380 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4382 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4384 tcg_temp_free_i64(tcg_vn
);
4385 tcg_temp_free_i64(tcg_vm
);
4387 TCGv_i32 tcg_vn
, tcg_vm
;
4389 tcg_vn
= read_fp_sreg(s
, rn
);
4390 if (cmp_with_zero
) {
4391 tcg_vm
= tcg_const_i32(0);
4393 tcg_vm
= read_fp_sreg(s
, rm
);
4395 if (signal_all_nans
) {
4396 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4398 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4400 tcg_temp_free_i32(tcg_vn
);
4401 tcg_temp_free_i32(tcg_vm
);
4404 tcg_temp_free_ptr(fpst
);
4406 gen_set_nzcv(tcg_flags
);
4408 tcg_temp_free_i64(tcg_flags
);
4411 /* Floating point compare
4412 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4413 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4414 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4415 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4417 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4419 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4421 mos
= extract32(insn
, 29, 3);
4422 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4423 rm
= extract32(insn
, 16, 5);
4424 op
= extract32(insn
, 14, 2);
4425 rn
= extract32(insn
, 5, 5);
4426 opc
= extract32(insn
, 3, 2);
4427 op2r
= extract32(insn
, 0, 3);
4429 if (mos
|| op
|| op2r
|| type
> 1) {
4430 unallocated_encoding(s
);
4434 if (!fp_access_check(s
)) {
4438 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4441 /* Floating point conditional compare
4442 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4443 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4444 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4445 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4447 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4449 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4451 TCGLabel
*label_continue
= NULL
;
4453 mos
= extract32(insn
, 29, 3);
4454 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4455 rm
= extract32(insn
, 16, 5);
4456 cond
= extract32(insn
, 12, 4);
4457 rn
= extract32(insn
, 5, 5);
4458 op
= extract32(insn
, 4, 1);
4459 nzcv
= extract32(insn
, 0, 4);
4461 if (mos
|| type
> 1) {
4462 unallocated_encoding(s
);
4466 if (!fp_access_check(s
)) {
4470 if (cond
< 0x0e) { /* not always */
4471 TCGLabel
*label_match
= gen_new_label();
4472 label_continue
= gen_new_label();
4473 arm_gen_test_cc(cond
, label_match
);
4475 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4476 gen_set_nzcv(tcg_flags
);
4477 tcg_temp_free_i64(tcg_flags
);
4478 tcg_gen_br(label_continue
);
4479 gen_set_label(label_match
);
4482 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4485 gen_set_label(label_continue
);
4489 /* Floating point conditional select
4490 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4491 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4492 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4493 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4495 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4497 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4498 TCGv_i64 t_true
, t_false
, t_zero
;
4501 mos
= extract32(insn
, 29, 3);
4502 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4503 rm
= extract32(insn
, 16, 5);
4504 cond
= extract32(insn
, 12, 4);
4505 rn
= extract32(insn
, 5, 5);
4506 rd
= extract32(insn
, 0, 5);
4508 if (mos
|| type
> 1) {
4509 unallocated_encoding(s
);
4513 if (!fp_access_check(s
)) {
4517 /* Zero extend sreg inputs to 64 bits now. */
4518 t_true
= tcg_temp_new_i64();
4519 t_false
= tcg_temp_new_i64();
4520 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4521 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4523 a64_test_cc(&c
, cond
);
4524 t_zero
= tcg_const_i64(0);
4525 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4526 tcg_temp_free_i64(t_zero
);
4527 tcg_temp_free_i64(t_false
);
4530 /* Note that sregs write back zeros to the high bits,
4531 and we've already done the zero-extension. */
4532 write_fp_dreg(s
, rd
, t_true
);
4533 tcg_temp_free_i64(t_true
);
4536 /* Floating-point data-processing (1 source) - single precision */
4537 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4543 fpst
= get_fpstatus_ptr();
4544 tcg_op
= read_fp_sreg(s
, rn
);
4545 tcg_res
= tcg_temp_new_i32();
4548 case 0x0: /* FMOV */
4549 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4551 case 0x1: /* FABS */
4552 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4554 case 0x2: /* FNEG */
4555 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4557 case 0x3: /* FSQRT */
4558 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4560 case 0x8: /* FRINTN */
4561 case 0x9: /* FRINTP */
4562 case 0xa: /* FRINTM */
4563 case 0xb: /* FRINTZ */
4564 case 0xc: /* FRINTA */
4566 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4568 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4569 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4571 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4572 tcg_temp_free_i32(tcg_rmode
);
4575 case 0xe: /* FRINTX */
4576 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4578 case 0xf: /* FRINTI */
4579 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4585 write_fp_sreg(s
, rd
, tcg_res
);
4587 tcg_temp_free_ptr(fpst
);
4588 tcg_temp_free_i32(tcg_op
);
4589 tcg_temp_free_i32(tcg_res
);
4592 /* Floating-point data-processing (1 source) - double precision */
4593 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4599 fpst
= get_fpstatus_ptr();
4600 tcg_op
= read_fp_dreg(s
, rn
);
4601 tcg_res
= tcg_temp_new_i64();
4604 case 0x0: /* FMOV */
4605 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4607 case 0x1: /* FABS */
4608 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4610 case 0x2: /* FNEG */
4611 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4613 case 0x3: /* FSQRT */
4614 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4616 case 0x8: /* FRINTN */
4617 case 0x9: /* FRINTP */
4618 case 0xa: /* FRINTM */
4619 case 0xb: /* FRINTZ */
4620 case 0xc: /* FRINTA */
4622 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4624 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4625 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4627 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4628 tcg_temp_free_i32(tcg_rmode
);
4631 case 0xe: /* FRINTX */
4632 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4634 case 0xf: /* FRINTI */
4635 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4641 write_fp_dreg(s
, rd
, tcg_res
);
4643 tcg_temp_free_ptr(fpst
);
4644 tcg_temp_free_i64(tcg_op
);
4645 tcg_temp_free_i64(tcg_res
);
4648 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4649 int rd
, int rn
, int dtype
, int ntype
)
4654 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4656 /* Single to double */
4657 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4658 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4659 write_fp_dreg(s
, rd
, tcg_rd
);
4660 tcg_temp_free_i64(tcg_rd
);
4662 /* Single to half */
4663 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4664 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4665 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4666 write_fp_sreg(s
, rd
, tcg_rd
);
4667 tcg_temp_free_i32(tcg_rd
);
4669 tcg_temp_free_i32(tcg_rn
);
4674 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4675 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4677 /* Double to single */
4678 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4680 /* Double to half */
4681 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4682 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4684 write_fp_sreg(s
, rd
, tcg_rd
);
4685 tcg_temp_free_i32(tcg_rd
);
4686 tcg_temp_free_i64(tcg_rn
);
4691 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4692 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4694 /* Half to single */
4695 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4696 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4697 write_fp_sreg(s
, rd
, tcg_rd
);
4698 tcg_temp_free_i32(tcg_rd
);
4700 /* Half to double */
4701 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4702 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4703 write_fp_dreg(s
, rd
, tcg_rd
);
4704 tcg_temp_free_i64(tcg_rd
);
4706 tcg_temp_free_i32(tcg_rn
);
4714 /* Floating point data-processing (1 source)
4715 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4716 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4717 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4718 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4720 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4722 int type
= extract32(insn
, 22, 2);
4723 int opcode
= extract32(insn
, 15, 6);
4724 int rn
= extract32(insn
, 5, 5);
4725 int rd
= extract32(insn
, 0, 5);
4728 case 0x4: case 0x5: case 0x7:
4730 /* FCVT between half, single and double precision */
4731 int dtype
= extract32(opcode
, 0, 2);
4732 if (type
== 2 || dtype
== type
) {
4733 unallocated_encoding(s
);
4736 if (!fp_access_check(s
)) {
4740 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4746 /* 32-to-32 and 64-to-64 ops */
4749 if (!fp_access_check(s
)) {
4753 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4756 if (!fp_access_check(s
)) {
4760 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4763 unallocated_encoding(s
);
4767 unallocated_encoding(s
);
4772 /* Floating-point data-processing (2 source) - single precision */
4773 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4774 int rd
, int rn
, int rm
)
4781 tcg_res
= tcg_temp_new_i32();
4782 fpst
= get_fpstatus_ptr();
4783 tcg_op1
= read_fp_sreg(s
, rn
);
4784 tcg_op2
= read_fp_sreg(s
, rm
);
4787 case 0x0: /* FMUL */
4788 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4790 case 0x1: /* FDIV */
4791 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4793 case 0x2: /* FADD */
4794 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4796 case 0x3: /* FSUB */
4797 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4799 case 0x4: /* FMAX */
4800 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4802 case 0x5: /* FMIN */
4803 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4805 case 0x6: /* FMAXNM */
4806 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4808 case 0x7: /* FMINNM */
4809 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4811 case 0x8: /* FNMUL */
4812 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4813 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4817 write_fp_sreg(s
, rd
, tcg_res
);
4819 tcg_temp_free_ptr(fpst
);
4820 tcg_temp_free_i32(tcg_op1
);
4821 tcg_temp_free_i32(tcg_op2
);
4822 tcg_temp_free_i32(tcg_res
);
4825 /* Floating-point data-processing (2 source) - double precision */
4826 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4827 int rd
, int rn
, int rm
)
4834 tcg_res
= tcg_temp_new_i64();
4835 fpst
= get_fpstatus_ptr();
4836 tcg_op1
= read_fp_dreg(s
, rn
);
4837 tcg_op2
= read_fp_dreg(s
, rm
);
4840 case 0x0: /* FMUL */
4841 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4843 case 0x1: /* FDIV */
4844 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4846 case 0x2: /* FADD */
4847 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4849 case 0x3: /* FSUB */
4850 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4852 case 0x4: /* FMAX */
4853 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4855 case 0x5: /* FMIN */
4856 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4858 case 0x6: /* FMAXNM */
4859 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4861 case 0x7: /* FMINNM */
4862 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4864 case 0x8: /* FNMUL */
4865 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4866 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4870 write_fp_dreg(s
, rd
, tcg_res
);
4872 tcg_temp_free_ptr(fpst
);
4873 tcg_temp_free_i64(tcg_op1
);
4874 tcg_temp_free_i64(tcg_op2
);
4875 tcg_temp_free_i64(tcg_res
);
4878 /* Floating point data-processing (2 source)
4879 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4880 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4881 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4882 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4884 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4886 int type
= extract32(insn
, 22, 2);
4887 int rd
= extract32(insn
, 0, 5);
4888 int rn
= extract32(insn
, 5, 5);
4889 int rm
= extract32(insn
, 16, 5);
4890 int opcode
= extract32(insn
, 12, 4);
4893 unallocated_encoding(s
);
4899 if (!fp_access_check(s
)) {
4902 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4905 if (!fp_access_check(s
)) {
4908 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4911 unallocated_encoding(s
);
4915 /* Floating-point data-processing (3 source) - single precision */
4916 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4917 int rd
, int rn
, int rm
, int ra
)
4919 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4920 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4921 TCGv_ptr fpst
= get_fpstatus_ptr();
4923 tcg_op1
= read_fp_sreg(s
, rn
);
4924 tcg_op2
= read_fp_sreg(s
, rm
);
4925 tcg_op3
= read_fp_sreg(s
, ra
);
4927 /* These are fused multiply-add, and must be done as one
4928 * floating point operation with no rounding between the
4929 * multiplication and addition steps.
4930 * NB that doing the negations here as separate steps is
4931 * correct : an input NaN should come out with its sign bit
4932 * flipped if it is a negated-input.
4935 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4939 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4942 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4944 write_fp_sreg(s
, rd
, tcg_res
);
4946 tcg_temp_free_ptr(fpst
);
4947 tcg_temp_free_i32(tcg_op1
);
4948 tcg_temp_free_i32(tcg_op2
);
4949 tcg_temp_free_i32(tcg_op3
);
4950 tcg_temp_free_i32(tcg_res
);
4953 /* Floating-point data-processing (3 source) - double precision */
4954 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4955 int rd
, int rn
, int rm
, int ra
)
4957 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4958 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4959 TCGv_ptr fpst
= get_fpstatus_ptr();
4961 tcg_op1
= read_fp_dreg(s
, rn
);
4962 tcg_op2
= read_fp_dreg(s
, rm
);
4963 tcg_op3
= read_fp_dreg(s
, ra
);
4965 /* These are fused multiply-add, and must be done as one
4966 * floating point operation with no rounding between the
4967 * multiplication and addition steps.
4968 * NB that doing the negations here as separate steps is
4969 * correct : an input NaN should come out with its sign bit
4970 * flipped if it is a negated-input.
4973 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4977 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4980 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4982 write_fp_dreg(s
, rd
, tcg_res
);
4984 tcg_temp_free_ptr(fpst
);
4985 tcg_temp_free_i64(tcg_op1
);
4986 tcg_temp_free_i64(tcg_op2
);
4987 tcg_temp_free_i64(tcg_op3
);
4988 tcg_temp_free_i64(tcg_res
);
4991 /* Floating point data-processing (3 source)
4992 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4993 * +---+---+---+-----------+------+----+------+----+------+------+------+
4994 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4995 * +---+---+---+-----------+------+----+------+----+------+------+------+
4997 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4999 int type
= extract32(insn
, 22, 2);
5000 int rd
= extract32(insn
, 0, 5);
5001 int rn
= extract32(insn
, 5, 5);
5002 int ra
= extract32(insn
, 10, 5);
5003 int rm
= extract32(insn
, 16, 5);
5004 bool o0
= extract32(insn
, 15, 1);
5005 bool o1
= extract32(insn
, 21, 1);
5009 if (!fp_access_check(s
)) {
5012 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5015 if (!fp_access_check(s
)) {
5018 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5021 unallocated_encoding(s
);
5025 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
5026 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
5027 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
5029 static uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
5035 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5036 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5037 extract32(imm8
, 0, 6);
5041 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5042 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5043 (extract32(imm8
, 0, 6) << 3);
5047 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5048 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
5049 (extract32(imm8
, 0, 6) << 6);
5052 g_assert_not_reached();
5057 /* Floating point immediate
5058 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5059 * +---+---+---+-----------+------+---+------------+-------+------+------+
5060 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5061 * +---+---+---+-----------+------+---+------------+-------+------+------+
5063 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
5065 int rd
= extract32(insn
, 0, 5);
5066 int imm8
= extract32(insn
, 13, 8);
5067 int is_double
= extract32(insn
, 22, 2);
5071 if (is_double
> 1) {
5072 unallocated_encoding(s
);
5076 if (!fp_access_check(s
)) {
5080 imm
= vfp_expand_imm(MO_32
+ is_double
, imm8
);
5082 tcg_res
= tcg_const_i64(imm
);
5083 write_fp_dreg(s
, rd
, tcg_res
);
5084 tcg_temp_free_i64(tcg_res
);
5087 /* Handle floating point <=> fixed point conversions. Note that we can
5088 * also deal with fp <=> integer conversions as a special case (scale == 64)
5089 * OPTME: consider handling that special case specially or at least skipping
5090 * the call to scalbn in the helpers for zero shifts.
5092 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5093 bool itof
, int rmode
, int scale
, int sf
, int type
)
5095 bool is_signed
= !(opcode
& 1);
5096 bool is_double
= type
;
5097 TCGv_ptr tcg_fpstatus
;
5100 tcg_fpstatus
= get_fpstatus_ptr();
5102 tcg_shift
= tcg_const_i32(64 - scale
);
5105 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5107 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5110 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5112 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5115 tcg_int
= tcg_extend
;
5119 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5121 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5122 tcg_shift
, tcg_fpstatus
);
5124 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5125 tcg_shift
, tcg_fpstatus
);
5127 write_fp_dreg(s
, rd
, tcg_double
);
5128 tcg_temp_free_i64(tcg_double
);
5130 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5132 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5133 tcg_shift
, tcg_fpstatus
);
5135 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5136 tcg_shift
, tcg_fpstatus
);
5138 write_fp_sreg(s
, rd
, tcg_single
);
5139 tcg_temp_free_i32(tcg_single
);
5142 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5145 if (extract32(opcode
, 2, 1)) {
5146 /* There are too many rounding modes to all fit into rmode,
5147 * so FCVTA[US] is a special case.
5149 rmode
= FPROUNDING_TIEAWAY
;
5152 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5154 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5157 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5160 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5161 tcg_shift
, tcg_fpstatus
);
5163 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5164 tcg_shift
, tcg_fpstatus
);
5168 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5169 tcg_shift
, tcg_fpstatus
);
5171 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5172 tcg_shift
, tcg_fpstatus
);
5175 tcg_temp_free_i64(tcg_double
);
5177 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5180 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5181 tcg_shift
, tcg_fpstatus
);
5183 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5184 tcg_shift
, tcg_fpstatus
);
5187 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5189 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5190 tcg_shift
, tcg_fpstatus
);
5192 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5193 tcg_shift
, tcg_fpstatus
);
5195 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5196 tcg_temp_free_i32(tcg_dest
);
5198 tcg_temp_free_i32(tcg_single
);
5201 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5202 tcg_temp_free_i32(tcg_rmode
);
5205 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5209 tcg_temp_free_ptr(tcg_fpstatus
);
5210 tcg_temp_free_i32(tcg_shift
);
5213 /* Floating point <-> fixed point conversions
5214 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5215 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5216 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5217 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5219 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5221 int rd
= extract32(insn
, 0, 5);
5222 int rn
= extract32(insn
, 5, 5);
5223 int scale
= extract32(insn
, 10, 6);
5224 int opcode
= extract32(insn
, 16, 3);
5225 int rmode
= extract32(insn
, 19, 2);
5226 int type
= extract32(insn
, 22, 2);
5227 bool sbit
= extract32(insn
, 29, 1);
5228 bool sf
= extract32(insn
, 31, 1);
5231 if (sbit
|| (type
> 1)
5232 || (!sf
&& scale
< 32)) {
5233 unallocated_encoding(s
);
5237 switch ((rmode
<< 3) | opcode
) {
5238 case 0x2: /* SCVTF */
5239 case 0x3: /* UCVTF */
5242 case 0x18: /* FCVTZS */
5243 case 0x19: /* FCVTZU */
5247 unallocated_encoding(s
);
5251 if (!fp_access_check(s
)) {
5255 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5258 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5260 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5261 * without conversion.
5265 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5271 TCGv_i64 tmp
= tcg_temp_new_i64();
5272 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5273 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5274 tcg_gen_movi_i64(tmp
, 0);
5275 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5276 tcg_temp_free_i64(tmp
);
5282 TCGv_i64 tmp
= tcg_const_i64(0);
5283 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5284 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5285 tcg_temp_free_i64(tmp
);
5289 /* 64 bit to top half. */
5290 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5294 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5299 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5303 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5306 /* 64 bits from top half */
5307 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5313 /* Floating point <-> integer conversions
5314 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5315 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5316 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5317 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5319 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5321 int rd
= extract32(insn
, 0, 5);
5322 int rn
= extract32(insn
, 5, 5);
5323 int opcode
= extract32(insn
, 16, 3);
5324 int rmode
= extract32(insn
, 19, 2);
5325 int type
= extract32(insn
, 22, 2);
5326 bool sbit
= extract32(insn
, 29, 1);
5327 bool sf
= extract32(insn
, 31, 1);
5330 unallocated_encoding(s
);
5336 bool itof
= opcode
& 1;
5339 unallocated_encoding(s
);
5343 switch (sf
<< 3 | type
<< 1 | rmode
) {
5344 case 0x0: /* 32 bit */
5345 case 0xa: /* 64 bit */
5346 case 0xd: /* 64 bit to top half of quad */
5349 /* all other sf/type/rmode combinations are invalid */
5350 unallocated_encoding(s
);
5354 if (!fp_access_check(s
)) {
5357 handle_fmov(s
, rd
, rn
, type
, itof
);
5359 /* actual FP conversions */
5360 bool itof
= extract32(opcode
, 1, 1);
5362 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5363 unallocated_encoding(s
);
5367 if (!fp_access_check(s
)) {
5370 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5374 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5375 * 31 30 29 28 25 24 0
5376 * +---+---+---+---------+-----------------------------+
5377 * | | 0 | | 1 1 1 1 | |
5378 * +---+---+---+---------+-----------------------------+
5380 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5382 if (extract32(insn
, 24, 1)) {
5383 /* Floating point data-processing (3 source) */
5384 disas_fp_3src(s
, insn
);
5385 } else if (extract32(insn
, 21, 1) == 0) {
5386 /* Floating point to fixed point conversions */
5387 disas_fp_fixed_conv(s
, insn
);
5389 switch (extract32(insn
, 10, 2)) {
5391 /* Floating point conditional compare */
5392 disas_fp_ccomp(s
, insn
);
5395 /* Floating point data-processing (2 source) */
5396 disas_fp_2src(s
, insn
);
5399 /* Floating point conditional select */
5400 disas_fp_csel(s
, insn
);
5403 switch (ctz32(extract32(insn
, 12, 4))) {
5404 case 0: /* [15:12] == xxx1 */
5405 /* Floating point immediate */
5406 disas_fp_imm(s
, insn
);
5408 case 1: /* [15:12] == xx10 */
5409 /* Floating point compare */
5410 disas_fp_compare(s
, insn
);
5412 case 2: /* [15:12] == x100 */
5413 /* Floating point data-processing (1 source) */
5414 disas_fp_1src(s
, insn
);
5416 case 3: /* [15:12] == 1000 */
5417 unallocated_encoding(s
);
5419 default: /* [15:12] == 0000 */
5420 /* Floating point <-> integer conversions */
5421 disas_fp_int_conv(s
, insn
);
5429 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5432 /* Extract 64 bits from the middle of two concatenated 64 bit
5433 * vector register slices left:right. The extracted bits start
5434 * at 'pos' bits into the right (least significant) side.
5435 * We return the result in tcg_right, and guarantee not to
5438 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5439 assert(pos
> 0 && pos
< 64);
5441 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5442 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5443 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5445 tcg_temp_free_i64(tcg_tmp
);
5449 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5450 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5451 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5452 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5454 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5456 int is_q
= extract32(insn
, 30, 1);
5457 int op2
= extract32(insn
, 22, 2);
5458 int imm4
= extract32(insn
, 11, 4);
5459 int rm
= extract32(insn
, 16, 5);
5460 int rn
= extract32(insn
, 5, 5);
5461 int rd
= extract32(insn
, 0, 5);
5462 int pos
= imm4
<< 3;
5463 TCGv_i64 tcg_resl
, tcg_resh
;
5465 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5466 unallocated_encoding(s
);
5470 if (!fp_access_check(s
)) {
5474 tcg_resh
= tcg_temp_new_i64();
5475 tcg_resl
= tcg_temp_new_i64();
5477 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5478 * either extracting 128 bits from a 128:128 concatenation, or
5479 * extracting 64 bits from a 64:64 concatenation.
5482 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5484 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5485 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5487 tcg_gen_movi_i64(tcg_resh
, 0);
5494 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5495 EltPosns
*elt
= eltposns
;
5502 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5504 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5507 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5508 tcg_hh
= tcg_temp_new_i64();
5509 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5510 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5511 tcg_temp_free_i64(tcg_hh
);
5515 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5516 tcg_temp_free_i64(tcg_resl
);
5517 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5518 tcg_temp_free_i64(tcg_resh
);
5522 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5523 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5524 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5525 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5527 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5529 int op2
= extract32(insn
, 22, 2);
5530 int is_q
= extract32(insn
, 30, 1);
5531 int rm
= extract32(insn
, 16, 5);
5532 int rn
= extract32(insn
, 5, 5);
5533 int rd
= extract32(insn
, 0, 5);
5534 int is_tblx
= extract32(insn
, 12, 1);
5535 int len
= extract32(insn
, 13, 2);
5536 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5537 TCGv_i32 tcg_regno
, tcg_numregs
;
5540 unallocated_encoding(s
);
5544 if (!fp_access_check(s
)) {
5548 /* This does a table lookup: for every byte element in the input
5549 * we index into a table formed from up to four vector registers,
5550 * and then the output is the result of the lookups. Our helper
5551 * function does the lookup operation for a single 64 bit part of
5554 tcg_resl
= tcg_temp_new_i64();
5555 tcg_resh
= tcg_temp_new_i64();
5558 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5560 tcg_gen_movi_i64(tcg_resl
, 0);
5562 if (is_tblx
&& is_q
) {
5563 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5565 tcg_gen_movi_i64(tcg_resh
, 0);
5568 tcg_idx
= tcg_temp_new_i64();
5569 tcg_regno
= tcg_const_i32(rn
);
5570 tcg_numregs
= tcg_const_i32(len
+ 1);
5571 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5572 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5573 tcg_regno
, tcg_numregs
);
5575 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5576 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5577 tcg_regno
, tcg_numregs
);
5579 tcg_temp_free_i64(tcg_idx
);
5580 tcg_temp_free_i32(tcg_regno
);
5581 tcg_temp_free_i32(tcg_numregs
);
5583 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5584 tcg_temp_free_i64(tcg_resl
);
5585 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5586 tcg_temp_free_i64(tcg_resh
);
5590 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5591 * +---+---+-------------+------+---+------+---+------------------+------+
5592 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5593 * +---+---+-------------+------+---+------+---+------------------+------+
5595 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5597 int rd
= extract32(insn
, 0, 5);
5598 int rn
= extract32(insn
, 5, 5);
5599 int rm
= extract32(insn
, 16, 5);
5600 int size
= extract32(insn
, 22, 2);
5601 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5602 * bit 2 indicates 1 vs 2 variant of the insn.
5604 int opcode
= extract32(insn
, 12, 2);
5605 bool part
= extract32(insn
, 14, 1);
5606 bool is_q
= extract32(insn
, 30, 1);
5607 int esize
= 8 << size
;
5609 int datasize
= is_q
? 128 : 64;
5610 int elements
= datasize
/ esize
;
5611 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5613 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5614 unallocated_encoding(s
);
5618 if (!fp_access_check(s
)) {
5622 tcg_resl
= tcg_const_i64(0);
5623 tcg_resh
= tcg_const_i64(0);
5624 tcg_res
= tcg_temp_new_i64();
5626 for (i
= 0; i
< elements
; i
++) {
5628 case 1: /* UZP1/2 */
5630 int midpoint
= elements
/ 2;
5632 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5634 read_vec_element(s
, tcg_res
, rm
,
5635 2 * (i
- midpoint
) + part
, size
);
5639 case 2: /* TRN1/2 */
5641 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5643 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5646 case 3: /* ZIP1/2 */
5648 int base
= part
* elements
/ 2;
5650 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5652 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5657 g_assert_not_reached();
5662 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5663 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5665 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5666 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5670 tcg_temp_free_i64(tcg_res
);
5672 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5673 tcg_temp_free_i64(tcg_resl
);
5674 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5675 tcg_temp_free_i64(tcg_resh
);
5678 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5679 int opc
, bool is_min
, TCGv_ptr fpst
)
5681 /* Helper function for disas_simd_across_lanes: do a single precision
5682 * min/max operation on the specified two inputs,
5683 * and return the result in tcg_elt1.
5687 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5689 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5694 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5696 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5701 /* AdvSIMD across lanes
5702 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5703 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5704 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5705 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5707 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5709 int rd
= extract32(insn
, 0, 5);
5710 int rn
= extract32(insn
, 5, 5);
5711 int size
= extract32(insn
, 22, 2);
5712 int opcode
= extract32(insn
, 12, 5);
5713 bool is_q
= extract32(insn
, 30, 1);
5714 bool is_u
= extract32(insn
, 29, 1);
5716 bool is_min
= false;
5720 TCGv_i64 tcg_res
, tcg_elt
;
5723 case 0x1b: /* ADDV */
5725 unallocated_encoding(s
);
5729 case 0x3: /* SADDLV, UADDLV */
5730 case 0xa: /* SMAXV, UMAXV */
5731 case 0x1a: /* SMINV, UMINV */
5732 if (size
== 3 || (size
== 2 && !is_q
)) {
5733 unallocated_encoding(s
);
5737 case 0xc: /* FMAXNMV, FMINNMV */
5738 case 0xf: /* FMAXV, FMINV */
5739 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5740 unallocated_encoding(s
);
5743 /* Bit 1 of size field encodes min vs max, and actual size is always
5744 * 32 bits: adjust the size variable so following code can rely on it
5746 is_min
= extract32(size
, 1, 1);
5751 unallocated_encoding(s
);
5755 if (!fp_access_check(s
)) {
5760 elements
= (is_q
? 128 : 64) / esize
;
5762 tcg_res
= tcg_temp_new_i64();
5763 tcg_elt
= tcg_temp_new_i64();
5765 /* These instructions operate across all lanes of a vector
5766 * to produce a single result. We can guarantee that a 64
5767 * bit intermediate is sufficient:
5768 * + for [US]ADDLV the maximum element size is 32 bits, and
5769 * the result type is 64 bits
5770 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5771 * same as the element size, which is 32 bits at most
5772 * For the integer operations we can choose to work at 64
5773 * or 32 bits and truncate at the end; for simplicity
5774 * we use 64 bits always. The floating point
5775 * ops do require 32 bit intermediates, though.
5778 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5780 for (i
= 1; i
< elements
; i
++) {
5781 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5784 case 0x03: /* SADDLV / UADDLV */
5785 case 0x1b: /* ADDV */
5786 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5788 case 0x0a: /* SMAXV / UMAXV */
5789 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5791 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5793 case 0x1a: /* SMINV / UMINV */
5794 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5796 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5800 g_assert_not_reached();
5805 /* Floating point ops which work on 32 bit (single) intermediates.
5806 * Note that correct NaN propagation requires that we do these
5807 * operations in exactly the order specified by the pseudocode.
5809 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5810 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5811 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5812 TCGv_ptr fpst
= get_fpstatus_ptr();
5814 assert(esize
== 32);
5815 assert(elements
== 4);
5817 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5818 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5819 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5820 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5822 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5824 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5825 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5826 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5827 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5829 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5831 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5833 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5834 tcg_temp_free_i32(tcg_elt1
);
5835 tcg_temp_free_i32(tcg_elt2
);
5836 tcg_temp_free_i32(tcg_elt3
);
5837 tcg_temp_free_ptr(fpst
);
5840 tcg_temp_free_i64(tcg_elt
);
5842 /* Now truncate the result to the width required for the final output */
5843 if (opcode
== 0x03) {
5844 /* SADDLV, UADDLV: result is 2*esize */
5850 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5853 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5856 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5861 g_assert_not_reached();
5864 write_fp_dreg(s
, rd
, tcg_res
);
5865 tcg_temp_free_i64(tcg_res
);
5868 /* DUP (Element, Vector)
5870 * 31 30 29 21 20 16 15 10 9 5 4 0
5871 * +---+---+-------------------+--------+-------------+------+------+
5872 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5873 * +---+---+-------------------+--------+-------------+------+------+
5875 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5877 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5880 int size
= ctz32(imm5
);
5881 int esize
= 8 << size
;
5882 int elements
= (is_q
? 128 : 64) / esize
;
5886 if (size
> 3 || (size
== 3 && !is_q
)) {
5887 unallocated_encoding(s
);
5891 if (!fp_access_check(s
)) {
5895 index
= imm5
>> (size
+ 1);
5897 tmp
= tcg_temp_new_i64();
5898 read_vec_element(s
, tmp
, rn
, index
, size
);
5900 for (i
= 0; i
< elements
; i
++) {
5901 write_vec_element(s
, tmp
, rd
, i
, size
);
5905 clear_vec_high(s
, rd
);
5908 tcg_temp_free_i64(tmp
);
5911 /* DUP (element, scalar)
5912 * 31 21 20 16 15 10 9 5 4 0
5913 * +-----------------------+--------+-------------+------+------+
5914 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5915 * +-----------------------+--------+-------------+------+------+
5917 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5920 int size
= ctz32(imm5
);
5925 unallocated_encoding(s
);
5929 if (!fp_access_check(s
)) {
5933 index
= imm5
>> (size
+ 1);
5935 /* This instruction just extracts the specified element and
5936 * zero-extends it into the bottom of the destination register.
5938 tmp
= tcg_temp_new_i64();
5939 read_vec_element(s
, tmp
, rn
, index
, size
);
5940 write_fp_dreg(s
, rd
, tmp
);
5941 tcg_temp_free_i64(tmp
);
5946 * 31 30 29 21 20 16 15 10 9 5 4 0
5947 * +---+---+-------------------+--------+-------------+------+------+
5948 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5949 * +---+---+-------------------+--------+-------------+------+------+
5951 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5953 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5956 int size
= ctz32(imm5
);
5957 int esize
= 8 << size
;
5958 int elements
= (is_q
? 128 : 64)/esize
;
5961 if (size
> 3 || ((size
== 3) && !is_q
)) {
5962 unallocated_encoding(s
);
5966 if (!fp_access_check(s
)) {
5970 for (i
= 0; i
< elements
; i
++) {
5971 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5974 clear_vec_high(s
, rd
);
5980 * 31 21 20 16 15 14 11 10 9 5 4 0
5981 * +-----------------------+--------+------------+---+------+------+
5982 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5983 * +-----------------------+--------+------------+---+------+------+
5985 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5986 * index: encoded in imm5<4:size+1>
5988 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5991 int size
= ctz32(imm5
);
5992 int src_index
, dst_index
;
5996 unallocated_encoding(s
);
6000 if (!fp_access_check(s
)) {
6004 dst_index
= extract32(imm5
, 1+size
, 5);
6005 src_index
= extract32(imm4
, size
, 4);
6007 tmp
= tcg_temp_new_i64();
6009 read_vec_element(s
, tmp
, rn
, src_index
, size
);
6010 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
6012 tcg_temp_free_i64(tmp
);
6018 * 31 21 20 16 15 10 9 5 4 0
6019 * +-----------------------+--------+-------------+------+------+
6020 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
6021 * +-----------------------+--------+-------------+------+------+
6023 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6024 * index: encoded in imm5<4:size+1>
6026 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
6028 int size
= ctz32(imm5
);
6032 unallocated_encoding(s
);
6036 if (!fp_access_check(s
)) {
6040 idx
= extract32(imm5
, 1 + size
, 4 - size
);
6041 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
6048 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6049 * +---+---+-------------------+--------+-------------+------+------+
6050 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6051 * +---+---+-------------------+--------+-------------+------+------+
6053 * U: unsigned when set
6054 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6056 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6057 int rn
, int rd
, int imm5
)
6059 int size
= ctz32(imm5
);
6063 /* Check for UnallocatedEncodings */
6065 if (size
> 2 || (size
== 2 && !is_q
)) {
6066 unallocated_encoding(s
);
6071 || (size
< 3 && is_q
)
6072 || (size
== 3 && !is_q
)) {
6073 unallocated_encoding(s
);
6078 if (!fp_access_check(s
)) {
6082 element
= extract32(imm5
, 1+size
, 4);
6084 tcg_rd
= cpu_reg(s
, rd
);
6085 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6086 if (is_signed
&& !is_q
) {
6087 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6092 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6093 * +---+---+----+-----------------+------+---+------+---+------+------+
6094 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6095 * +---+---+----+-----------------+------+---+------+---+------+------+
6097 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6099 int rd
= extract32(insn
, 0, 5);
6100 int rn
= extract32(insn
, 5, 5);
6101 int imm4
= extract32(insn
, 11, 4);
6102 int op
= extract32(insn
, 29, 1);
6103 int is_q
= extract32(insn
, 30, 1);
6104 int imm5
= extract32(insn
, 16, 5);
6109 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6111 unallocated_encoding(s
);
6116 /* DUP (element - vector) */
6117 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6121 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6126 handle_simd_insg(s
, rd
, rn
, imm5
);
6128 unallocated_encoding(s
);
6133 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6134 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6137 unallocated_encoding(s
);
6143 /* AdvSIMD modified immediate
6144 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6145 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6146 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6147 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6149 * There are a number of operations that can be carried out here:
6150 * MOVI - move (shifted) imm into register
6151 * MVNI - move inverted (shifted) imm into register
6152 * ORR - bitwise OR of (shifted) imm with register
6153 * BIC - bitwise clear of (shifted) imm with register
6155 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6157 int rd
= extract32(insn
, 0, 5);
6158 int cmode
= extract32(insn
, 12, 4);
6159 int cmode_3_1
= extract32(cmode
, 1, 3);
6160 int cmode_0
= extract32(cmode
, 0, 1);
6161 int o2
= extract32(insn
, 11, 1);
6162 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6163 bool is_neg
= extract32(insn
, 29, 1);
6164 bool is_q
= extract32(insn
, 30, 1);
6166 TCGv_i64 tcg_rd
, tcg_imm
;
6169 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6170 unallocated_encoding(s
);
6174 if (!fp_access_check(s
)) {
6178 /* See AdvSIMDExpandImm() in ARM ARM */
6179 switch (cmode_3_1
) {
6180 case 0: /* Replicate(Zeros(24):imm8, 2) */
6181 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6182 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6183 case 3: /* Replicate(imm8:Zeros(24), 2) */
6185 int shift
= cmode_3_1
* 8;
6186 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6189 case 4: /* Replicate(Zeros(8):imm8, 4) */
6190 case 5: /* Replicate(imm8:Zeros(8), 4) */
6192 int shift
= (cmode_3_1
& 0x1) * 8;
6193 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6198 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6199 imm
= (abcdefgh
<< 16) | 0xffff;
6201 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6202 imm
= (abcdefgh
<< 8) | 0xff;
6204 imm
= bitfield_replicate(imm
, 32);
6207 if (!cmode_0
&& !is_neg
) {
6208 imm
= bitfield_replicate(abcdefgh
, 8);
6209 } else if (!cmode_0
&& is_neg
) {
6212 for (i
= 0; i
< 8; i
++) {
6213 if ((abcdefgh
) & (1 << i
)) {
6214 imm
|= 0xffULL
<< (i
* 8);
6217 } else if (cmode_0
) {
6219 imm
= (abcdefgh
& 0x3f) << 48;
6220 if (abcdefgh
& 0x80) {
6221 imm
|= 0x8000000000000000ULL
;
6223 if (abcdefgh
& 0x40) {
6224 imm
|= 0x3fc0000000000000ULL
;
6226 imm
|= 0x4000000000000000ULL
;
6229 imm
= (abcdefgh
& 0x3f) << 19;
6230 if (abcdefgh
& 0x80) {
6233 if (abcdefgh
& 0x40) {
6244 if (cmode_3_1
!= 7 && is_neg
) {
6248 tcg_imm
= tcg_const_i64(imm
);
6249 tcg_rd
= new_tmp_a64(s
);
6251 for (i
= 0; i
< 2; i
++) {
6252 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6254 if (i
== 1 && !is_q
) {
6255 /* non-quad ops clear high half of vector */
6256 tcg_gen_movi_i64(tcg_rd
, 0);
6257 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6258 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6261 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6264 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6268 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6270 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6273 tcg_temp_free_i64(tcg_imm
);
6276 /* AdvSIMD scalar copy
6277 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6278 * +-----+----+-----------------+------+---+------+---+------+------+
6279 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6280 * +-----+----+-----------------+------+---+------+---+------+------+
6282 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6284 int rd
= extract32(insn
, 0, 5);
6285 int rn
= extract32(insn
, 5, 5);
6286 int imm4
= extract32(insn
, 11, 4);
6287 int imm5
= extract32(insn
, 16, 5);
6288 int op
= extract32(insn
, 29, 1);
6290 if (op
!= 0 || imm4
!= 0) {
6291 unallocated_encoding(s
);
6295 /* DUP (element, scalar) */
6296 handle_simd_dupes(s
, rd
, rn
, imm5
);
6299 /* AdvSIMD scalar pairwise
6300 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6301 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6302 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6303 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6305 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6307 int u
= extract32(insn
, 29, 1);
6308 int size
= extract32(insn
, 22, 2);
6309 int opcode
= extract32(insn
, 12, 5);
6310 int rn
= extract32(insn
, 5, 5);
6311 int rd
= extract32(insn
, 0, 5);
6314 /* For some ops (the FP ones), size[1] is part of the encoding.
6315 * For ADDP strictly it is not but size[1] is always 1 for valid
6318 opcode
|= (extract32(size
, 1, 1) << 5);
6321 case 0x3b: /* ADDP */
6322 if (u
|| size
!= 3) {
6323 unallocated_encoding(s
);
6326 if (!fp_access_check(s
)) {
6332 case 0xc: /* FMAXNMP */
6333 case 0xd: /* FADDP */
6334 case 0xf: /* FMAXP */
6335 case 0x2c: /* FMINNMP */
6336 case 0x2f: /* FMINP */
6337 /* FP op, size[0] is 32 or 64 bit */
6339 unallocated_encoding(s
);
6342 if (!fp_access_check(s
)) {
6346 size
= extract32(size
, 0, 1) ? 3 : 2;
6347 fpst
= get_fpstatus_ptr();
6350 unallocated_encoding(s
);
6355 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6356 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6357 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6359 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6360 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6363 case 0x3b: /* ADDP */
6364 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6366 case 0xc: /* FMAXNMP */
6367 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6369 case 0xd: /* FADDP */
6370 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6372 case 0xf: /* FMAXP */
6373 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6375 case 0x2c: /* FMINNMP */
6376 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6378 case 0x2f: /* FMINP */
6379 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6382 g_assert_not_reached();
6385 write_fp_dreg(s
, rd
, tcg_res
);
6387 tcg_temp_free_i64(tcg_op1
);
6388 tcg_temp_free_i64(tcg_op2
);
6389 tcg_temp_free_i64(tcg_res
);
6391 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6392 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6393 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6395 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6396 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6399 case 0xc: /* FMAXNMP */
6400 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6402 case 0xd: /* FADDP */
6403 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6405 case 0xf: /* FMAXP */
6406 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6408 case 0x2c: /* FMINNMP */
6409 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6411 case 0x2f: /* FMINP */
6412 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6415 g_assert_not_reached();
6418 write_fp_sreg(s
, rd
, tcg_res
);
6420 tcg_temp_free_i32(tcg_op1
);
6421 tcg_temp_free_i32(tcg_op2
);
6422 tcg_temp_free_i32(tcg_res
);
6426 tcg_temp_free_ptr(fpst
);
6431 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6433 * This code is handles the common shifting code and is used by both
6434 * the vector and scalar code.
6436 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6437 TCGv_i64 tcg_rnd
, bool accumulate
,
6438 bool is_u
, int size
, int shift
)
6440 bool extended_result
= false;
6441 bool round
= tcg_rnd
!= NULL
;
6443 TCGv_i64 tcg_src_hi
;
6445 if (round
&& size
== 3) {
6446 extended_result
= true;
6447 ext_lshift
= 64 - shift
;
6448 tcg_src_hi
= tcg_temp_new_i64();
6449 } else if (shift
== 64) {
6450 if (!accumulate
&& is_u
) {
6451 /* result is zero */
6452 tcg_gen_movi_i64(tcg_res
, 0);
6457 /* Deal with the rounding step */
6459 if (extended_result
) {
6460 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6462 /* take care of sign extending tcg_res */
6463 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6464 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6465 tcg_src
, tcg_src_hi
,
6468 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6472 tcg_temp_free_i64(tcg_zero
);
6474 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6478 /* Now do the shift right */
6479 if (round
&& extended_result
) {
6480 /* extended case, >64 bit precision required */
6481 if (ext_lshift
== 0) {
6482 /* special case, only high bits matter */
6483 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6485 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6486 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6487 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6492 /* essentially shifting in 64 zeros */
6493 tcg_gen_movi_i64(tcg_src
, 0);
6495 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6499 /* effectively extending the sign-bit */
6500 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6502 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6508 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6510 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6513 if (extended_result
) {
6514 tcg_temp_free_i64(tcg_src_hi
);
6518 /* Common SHL/SLI - Shift left with an optional insert */
6519 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6520 bool insert
, int shift
)
6522 if (insert
) { /* SLI */
6523 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6525 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6529 /* SRI: shift right with insert */
6530 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6531 int size
, int shift
)
6533 int esize
= 8 << size
;
6535 /* shift count same as element size is valid but does nothing;
6536 * special case to avoid potential shift by 64.
6538 if (shift
!= esize
) {
6539 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6540 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6544 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6545 static void handle_scalar_simd_shri(DisasContext
*s
,
6546 bool is_u
, int immh
, int immb
,
6547 int opcode
, int rn
, int rd
)
6550 int immhb
= immh
<< 3 | immb
;
6551 int shift
= 2 * (8 << size
) - immhb
;
6552 bool accumulate
= false;
6554 bool insert
= false;
6559 if (!extract32(immh
, 3, 1)) {
6560 unallocated_encoding(s
);
6564 if (!fp_access_check(s
)) {
6569 case 0x02: /* SSRA / USRA (accumulate) */
6572 case 0x04: /* SRSHR / URSHR (rounding) */
6575 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6576 accumulate
= round
= true;
6578 case 0x08: /* SRI */
6584 uint64_t round_const
= 1ULL << (shift
- 1);
6585 tcg_round
= tcg_const_i64(round_const
);
6590 tcg_rn
= read_fp_dreg(s
, rn
);
6591 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6594 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6596 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6597 accumulate
, is_u
, size
, shift
);
6600 write_fp_dreg(s
, rd
, tcg_rd
);
6602 tcg_temp_free_i64(tcg_rn
);
6603 tcg_temp_free_i64(tcg_rd
);
6605 tcg_temp_free_i64(tcg_round
);
6609 /* SHL/SLI - Scalar shift left */
6610 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6611 int immh
, int immb
, int opcode
,
6614 int size
= 32 - clz32(immh
) - 1;
6615 int immhb
= immh
<< 3 | immb
;
6616 int shift
= immhb
- (8 << size
);
6617 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6618 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6620 if (!extract32(immh
, 3, 1)) {
6621 unallocated_encoding(s
);
6625 if (!fp_access_check(s
)) {
6629 tcg_rn
= read_fp_dreg(s
, rn
);
6630 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6632 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6634 write_fp_dreg(s
, rd
, tcg_rd
);
6636 tcg_temp_free_i64(tcg_rn
);
6637 tcg_temp_free_i64(tcg_rd
);
6640 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6641 * (signed/unsigned) narrowing */
6642 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6643 bool is_u_shift
, bool is_u_narrow
,
6644 int immh
, int immb
, int opcode
,
6647 int immhb
= immh
<< 3 | immb
;
6648 int size
= 32 - clz32(immh
) - 1;
6649 int esize
= 8 << size
;
6650 int shift
= (2 * esize
) - immhb
;
6651 int elements
= is_scalar
? 1 : (64 / esize
);
6652 bool round
= extract32(opcode
, 0, 1);
6653 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6654 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6655 TCGv_i32 tcg_rd_narrowed
;
6658 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6659 { gen_helper_neon_narrow_sat_s8
,
6660 gen_helper_neon_unarrow_sat8
},
6661 { gen_helper_neon_narrow_sat_s16
,
6662 gen_helper_neon_unarrow_sat16
},
6663 { gen_helper_neon_narrow_sat_s32
,
6664 gen_helper_neon_unarrow_sat32
},
6667 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6668 gen_helper_neon_narrow_sat_u8
,
6669 gen_helper_neon_narrow_sat_u16
,
6670 gen_helper_neon_narrow_sat_u32
,
6673 NeonGenNarrowEnvFn
*narrowfn
;
6679 if (extract32(immh
, 3, 1)) {
6680 unallocated_encoding(s
);
6684 if (!fp_access_check(s
)) {
6689 narrowfn
= unsigned_narrow_fns
[size
];
6691 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6694 tcg_rn
= tcg_temp_new_i64();
6695 tcg_rd
= tcg_temp_new_i64();
6696 tcg_rd_narrowed
= tcg_temp_new_i32();
6697 tcg_final
= tcg_const_i64(0);
6700 uint64_t round_const
= 1ULL << (shift
- 1);
6701 tcg_round
= tcg_const_i64(round_const
);
6706 for (i
= 0; i
< elements
; i
++) {
6707 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6708 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6709 false, is_u_shift
, size
+1, shift
);
6710 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6711 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6712 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6716 clear_vec_high(s
, rd
);
6717 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6719 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6723 tcg_temp_free_i64(tcg_round
);
6725 tcg_temp_free_i64(tcg_rn
);
6726 tcg_temp_free_i64(tcg_rd
);
6727 tcg_temp_free_i32(tcg_rd_narrowed
);
6728 tcg_temp_free_i64(tcg_final
);
6732 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6733 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6734 bool src_unsigned
, bool dst_unsigned
,
6735 int immh
, int immb
, int rn
, int rd
)
6737 int immhb
= immh
<< 3 | immb
;
6738 int size
= 32 - clz32(immh
) - 1;
6739 int shift
= immhb
- (8 << size
);
6743 assert(!(scalar
&& is_q
));
6746 if (!is_q
&& extract32(immh
, 3, 1)) {
6747 unallocated_encoding(s
);
6751 /* Since we use the variable-shift helpers we must
6752 * replicate the shift count into each element of
6753 * the tcg_shift value.
6757 shift
|= shift
<< 8;
6760 shift
|= shift
<< 16;
6766 g_assert_not_reached();
6770 if (!fp_access_check(s
)) {
6775 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6776 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6777 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6778 { NULL
, gen_helper_neon_qshl_u64
},
6780 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6781 int maxpass
= is_q
? 2 : 1;
6783 for (pass
= 0; pass
< maxpass
; pass
++) {
6784 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6786 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6787 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6788 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6790 tcg_temp_free_i64(tcg_op
);
6792 tcg_temp_free_i64(tcg_shift
);
6795 clear_vec_high(s
, rd
);
6798 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6799 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6801 { gen_helper_neon_qshl_s8
,
6802 gen_helper_neon_qshl_s16
,
6803 gen_helper_neon_qshl_s32
},
6804 { gen_helper_neon_qshlu_s8
,
6805 gen_helper_neon_qshlu_s16
,
6806 gen_helper_neon_qshlu_s32
}
6808 { NULL
, NULL
, NULL
},
6809 { gen_helper_neon_qshl_u8
,
6810 gen_helper_neon_qshl_u16
,
6811 gen_helper_neon_qshl_u32
}
6814 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6815 TCGMemOp memop
= scalar
? size
: MO_32
;
6816 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6818 for (pass
= 0; pass
< maxpass
; pass
++) {
6819 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6821 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6822 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6826 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6829 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6834 g_assert_not_reached();
6836 write_fp_sreg(s
, rd
, tcg_op
);
6838 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6841 tcg_temp_free_i32(tcg_op
);
6843 tcg_temp_free_i32(tcg_shift
);
6845 if (!is_q
&& !scalar
) {
6846 clear_vec_high(s
, rd
);
6851 /* Common vector code for handling integer to FP conversion */
6852 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6853 int elements
, int is_signed
,
6854 int fracbits
, int size
)
6856 bool is_double
= size
== 3 ? true : false;
6857 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6858 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6859 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6860 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6863 for (pass
= 0; pass
< elements
; pass
++) {
6864 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6867 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6869 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6870 tcg_shift
, tcg_fpst
);
6872 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6873 tcg_shift
, tcg_fpst
);
6875 if (elements
== 1) {
6876 write_fp_dreg(s
, rd
, tcg_double
);
6878 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6880 tcg_temp_free_i64(tcg_double
);
6882 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6884 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6885 tcg_shift
, tcg_fpst
);
6887 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6888 tcg_shift
, tcg_fpst
);
6890 if (elements
== 1) {
6891 write_fp_sreg(s
, rd
, tcg_single
);
6893 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6895 tcg_temp_free_i32(tcg_single
);
6899 if (!is_double
&& elements
== 2) {
6900 clear_vec_high(s
, rd
);
6903 tcg_temp_free_i64(tcg_int
);
6904 tcg_temp_free_ptr(tcg_fpst
);
6905 tcg_temp_free_i32(tcg_shift
);
6908 /* UCVTF/SCVTF - Integer to FP conversion */
6909 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6910 bool is_q
, bool is_u
,
6911 int immh
, int immb
, int opcode
,
6914 bool is_double
= extract32(immh
, 3, 1);
6915 int size
= is_double
? MO_64
: MO_32
;
6917 int immhb
= immh
<< 3 | immb
;
6918 int fracbits
= (is_double
? 128 : 64) - immhb
;
6920 if (!extract32(immh
, 2, 2)) {
6921 unallocated_encoding(s
);
6928 elements
= is_double
? 2 : is_q
? 4 : 2;
6929 if (is_double
&& !is_q
) {
6930 unallocated_encoding(s
);
6935 if (!fp_access_check(s
)) {
6939 /* immh == 0 would be a failure of the decode logic */
6942 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6945 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6946 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6947 bool is_q
, bool is_u
,
6948 int immh
, int immb
, int rn
, int rd
)
6950 bool is_double
= extract32(immh
, 3, 1);
6951 int immhb
= immh
<< 3 | immb
;
6952 int fracbits
= (is_double
? 128 : 64) - immhb
;
6954 TCGv_ptr tcg_fpstatus
;
6955 TCGv_i32 tcg_rmode
, tcg_shift
;
6957 if (!extract32(immh
, 2, 2)) {
6958 unallocated_encoding(s
);
6962 if (!is_scalar
&& !is_q
&& is_double
) {
6963 unallocated_encoding(s
);
6967 if (!fp_access_check(s
)) {
6971 assert(!(is_scalar
&& is_q
));
6973 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6974 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6975 tcg_fpstatus
= get_fpstatus_ptr();
6976 tcg_shift
= tcg_const_i32(fracbits
);
6979 int maxpass
= is_scalar
? 1 : 2;
6981 for (pass
= 0; pass
< maxpass
; pass
++) {
6982 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6984 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6986 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6988 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6990 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6991 tcg_temp_free_i64(tcg_op
);
6994 clear_vec_high(s
, rd
);
6997 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6998 for (pass
= 0; pass
< maxpass
; pass
++) {
6999 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7001 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7003 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7005 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7008 write_fp_sreg(s
, rd
, tcg_op
);
7010 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
7012 tcg_temp_free_i32(tcg_op
);
7014 if (!is_q
&& !is_scalar
) {
7015 clear_vec_high(s
, rd
);
7019 tcg_temp_free_ptr(tcg_fpstatus
);
7020 tcg_temp_free_i32(tcg_shift
);
7021 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7022 tcg_temp_free_i32(tcg_rmode
);
7025 /* AdvSIMD scalar shift by immediate
7026 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7027 * +-----+---+-------------+------+------+--------+---+------+------+
7028 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7029 * +-----+---+-------------+------+------+--------+---+------+------+
7031 * This is the scalar version so it works on a fixed sized registers
7033 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
7035 int rd
= extract32(insn
, 0, 5);
7036 int rn
= extract32(insn
, 5, 5);
7037 int opcode
= extract32(insn
, 11, 5);
7038 int immb
= extract32(insn
, 16, 3);
7039 int immh
= extract32(insn
, 19, 4);
7040 bool is_u
= extract32(insn
, 29, 1);
7043 unallocated_encoding(s
);
7048 case 0x08: /* SRI */
7050 unallocated_encoding(s
);
7054 case 0x00: /* SSHR / USHR */
7055 case 0x02: /* SSRA / USRA */
7056 case 0x04: /* SRSHR / URSHR */
7057 case 0x06: /* SRSRA / URSRA */
7058 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7060 case 0x0a: /* SHL / SLI */
7061 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7063 case 0x1c: /* SCVTF, UCVTF */
7064 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7067 case 0x10: /* SQSHRUN, SQSHRUN2 */
7068 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7070 unallocated_encoding(s
);
7073 handle_vec_simd_sqshrn(s
, true, false, false, true,
7074 immh
, immb
, opcode
, rn
, rd
);
7076 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7077 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7078 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7079 immh
, immb
, opcode
, rn
, rd
);
7081 case 0xc: /* SQSHLU */
7083 unallocated_encoding(s
);
7086 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7088 case 0xe: /* SQSHL, UQSHL */
7089 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7091 case 0x1f: /* FCVTZS, FCVTZU */
7092 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7095 unallocated_encoding(s
);
7100 /* AdvSIMD scalar three different
7101 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7102 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7103 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7104 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7106 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7108 bool is_u
= extract32(insn
, 29, 1);
7109 int size
= extract32(insn
, 22, 2);
7110 int opcode
= extract32(insn
, 12, 4);
7111 int rm
= extract32(insn
, 16, 5);
7112 int rn
= extract32(insn
, 5, 5);
7113 int rd
= extract32(insn
, 0, 5);
7116 unallocated_encoding(s
);
7121 case 0x9: /* SQDMLAL, SQDMLAL2 */
7122 case 0xb: /* SQDMLSL, SQDMLSL2 */
7123 case 0xd: /* SQDMULL, SQDMULL2 */
7124 if (size
== 0 || size
== 3) {
7125 unallocated_encoding(s
);
7130 unallocated_encoding(s
);
7134 if (!fp_access_check(s
)) {
7139 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7140 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7141 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7143 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7144 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7146 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7147 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7150 case 0xd: /* SQDMULL, SQDMULL2 */
7152 case 0xb: /* SQDMLSL, SQDMLSL2 */
7153 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7155 case 0x9: /* SQDMLAL, SQDMLAL2 */
7156 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7157 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7161 g_assert_not_reached();
7164 write_fp_dreg(s
, rd
, tcg_res
);
7166 tcg_temp_free_i64(tcg_op1
);
7167 tcg_temp_free_i64(tcg_op2
);
7168 tcg_temp_free_i64(tcg_res
);
7170 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7171 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7172 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7174 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7175 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7177 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7178 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7181 case 0xd: /* SQDMULL, SQDMULL2 */
7183 case 0xb: /* SQDMLSL, SQDMLSL2 */
7184 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7186 case 0x9: /* SQDMLAL, SQDMLAL2 */
7188 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7189 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7190 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7192 tcg_temp_free_i64(tcg_op3
);
7196 g_assert_not_reached();
7199 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7200 write_fp_dreg(s
, rd
, tcg_res
);
7202 tcg_temp_free_i32(tcg_op1
);
7203 tcg_temp_free_i32(tcg_op2
);
7204 tcg_temp_free_i64(tcg_res
);
7208 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7209 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7211 /* Handle 64x64->64 opcodes which are shared between the scalar
7212 * and vector 3-same groups. We cover every opcode where size == 3
7213 * is valid in either the three-reg-same (integer, not pairwise)
7214 * or scalar-three-reg-same groups. (Some opcodes are not yet
7220 case 0x1: /* SQADD */
7222 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7224 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7227 case 0x5: /* SQSUB */
7229 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7231 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7234 case 0x6: /* CMGT, CMHI */
7235 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7236 * We implement this using setcond (test) and then negating.
7238 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7240 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7241 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7243 case 0x7: /* CMGE, CMHS */
7244 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7246 case 0x11: /* CMTST, CMEQ */
7251 /* CMTST : test is "if (X & Y != 0)". */
7252 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7253 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7254 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7256 case 0x8: /* SSHL, USHL */
7258 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7260 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7263 case 0x9: /* SQSHL, UQSHL */
7265 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7267 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7270 case 0xa: /* SRSHL, URSHL */
7272 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7274 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7277 case 0xb: /* SQRSHL, UQRSHL */
7279 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7281 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7284 case 0x10: /* ADD, SUB */
7286 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7288 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7292 g_assert_not_reached();
7296 /* Handle the 3-same-operands float operations; shared by the scalar
7297 * and vector encodings. The caller must filter out any encodings
7298 * not allocated for the encoding it is dealing with.
7300 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7301 int fpopcode
, int rd
, int rn
, int rm
)
7304 TCGv_ptr fpst
= get_fpstatus_ptr();
7306 for (pass
= 0; pass
< elements
; pass
++) {
7309 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7310 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7311 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7313 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7314 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7317 case 0x39: /* FMLS */
7318 /* As usual for ARM, separate negation for fused multiply-add */
7319 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7321 case 0x19: /* FMLA */
7322 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7323 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7326 case 0x18: /* FMAXNM */
7327 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7329 case 0x1a: /* FADD */
7330 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7332 case 0x1b: /* FMULX */
7333 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7335 case 0x1c: /* FCMEQ */
7336 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7338 case 0x1e: /* FMAX */
7339 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7341 case 0x1f: /* FRECPS */
7342 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7344 case 0x38: /* FMINNM */
7345 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7347 case 0x3a: /* FSUB */
7348 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7350 case 0x3e: /* FMIN */
7351 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7353 case 0x3f: /* FRSQRTS */
7354 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7356 case 0x5b: /* FMUL */
7357 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7359 case 0x5c: /* FCMGE */
7360 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7362 case 0x5d: /* FACGE */
7363 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7365 case 0x5f: /* FDIV */
7366 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7368 case 0x7a: /* FABD */
7369 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7370 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7372 case 0x7c: /* FCMGT */
7373 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7375 case 0x7d: /* FACGT */
7376 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7379 g_assert_not_reached();
7382 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7384 tcg_temp_free_i64(tcg_res
);
7385 tcg_temp_free_i64(tcg_op1
);
7386 tcg_temp_free_i64(tcg_op2
);
7389 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7390 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7391 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7393 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7394 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7397 case 0x39: /* FMLS */
7398 /* As usual for ARM, separate negation for fused multiply-add */
7399 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7401 case 0x19: /* FMLA */
7402 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7403 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7406 case 0x1a: /* FADD */
7407 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7409 case 0x1b: /* FMULX */
7410 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7412 case 0x1c: /* FCMEQ */
7413 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7415 case 0x1e: /* FMAX */
7416 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7418 case 0x1f: /* FRECPS */
7419 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7421 case 0x18: /* FMAXNM */
7422 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7424 case 0x38: /* FMINNM */
7425 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7427 case 0x3a: /* FSUB */
7428 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7430 case 0x3e: /* FMIN */
7431 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7433 case 0x3f: /* FRSQRTS */
7434 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7436 case 0x5b: /* FMUL */
7437 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7439 case 0x5c: /* FCMGE */
7440 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7442 case 0x5d: /* FACGE */
7443 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7445 case 0x5f: /* FDIV */
7446 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7448 case 0x7a: /* FABD */
7449 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7450 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7452 case 0x7c: /* FCMGT */
7453 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7455 case 0x7d: /* FACGT */
7456 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7459 g_assert_not_reached();
7462 if (elements
== 1) {
7463 /* scalar single so clear high part */
7464 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7466 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7467 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7468 tcg_temp_free_i64(tcg_tmp
);
7470 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7473 tcg_temp_free_i32(tcg_res
);
7474 tcg_temp_free_i32(tcg_op1
);
7475 tcg_temp_free_i32(tcg_op2
);
7479 tcg_temp_free_ptr(fpst
);
7481 if ((elements
<< size
) < 4) {
7482 /* scalar, or non-quad vector op */
7483 clear_vec_high(s
, rd
);
7487 /* AdvSIMD scalar three same
7488 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7489 * +-----+---+-----------+------+---+------+--------+---+------+------+
7490 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7491 * +-----+---+-----------+------+---+------+--------+---+------+------+
7493 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7495 int rd
= extract32(insn
, 0, 5);
7496 int rn
= extract32(insn
, 5, 5);
7497 int opcode
= extract32(insn
, 11, 5);
7498 int rm
= extract32(insn
, 16, 5);
7499 int size
= extract32(insn
, 22, 2);
7500 bool u
= extract32(insn
, 29, 1);
7503 if (opcode
>= 0x18) {
7504 /* Floating point: U, size[1] and opcode indicate operation */
7505 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7507 case 0x1b: /* FMULX */
7508 case 0x1f: /* FRECPS */
7509 case 0x3f: /* FRSQRTS */
7510 case 0x5d: /* FACGE */
7511 case 0x7d: /* FACGT */
7512 case 0x1c: /* FCMEQ */
7513 case 0x5c: /* FCMGE */
7514 case 0x7c: /* FCMGT */
7515 case 0x7a: /* FABD */
7518 unallocated_encoding(s
);
7522 if (!fp_access_check(s
)) {
7526 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7531 case 0x1: /* SQADD, UQADD */
7532 case 0x5: /* SQSUB, UQSUB */
7533 case 0x9: /* SQSHL, UQSHL */
7534 case 0xb: /* SQRSHL, UQRSHL */
7536 case 0x8: /* SSHL, USHL */
7537 case 0xa: /* SRSHL, URSHL */
7538 case 0x6: /* CMGT, CMHI */
7539 case 0x7: /* CMGE, CMHS */
7540 case 0x11: /* CMTST, CMEQ */
7541 case 0x10: /* ADD, SUB (vector) */
7543 unallocated_encoding(s
);
7547 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7548 if (size
!= 1 && size
!= 2) {
7549 unallocated_encoding(s
);
7554 unallocated_encoding(s
);
7558 if (!fp_access_check(s
)) {
7562 tcg_rd
= tcg_temp_new_i64();
7565 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7566 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7568 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7569 tcg_temp_free_i64(tcg_rn
);
7570 tcg_temp_free_i64(tcg_rm
);
7572 /* Do a single operation on the lowest element in the vector.
7573 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7574 * no side effects for all these operations.
7575 * OPTME: special-purpose helpers would avoid doing some
7576 * unnecessary work in the helper for the 8 and 16 bit cases.
7578 NeonGenTwoOpEnvFn
*genenvfn
;
7579 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7580 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7581 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7583 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7584 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7587 case 0x1: /* SQADD, UQADD */
7589 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7590 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7591 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7592 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7594 genenvfn
= fns
[size
][u
];
7597 case 0x5: /* SQSUB, UQSUB */
7599 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7600 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7601 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7602 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7604 genenvfn
= fns
[size
][u
];
7607 case 0x9: /* SQSHL, UQSHL */
7609 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7610 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7611 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7612 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7614 genenvfn
= fns
[size
][u
];
7617 case 0xb: /* SQRSHL, UQRSHL */
7619 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7620 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7621 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7622 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7624 genenvfn
= fns
[size
][u
];
7627 case 0x16: /* SQDMULH, SQRDMULH */
7629 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7630 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7631 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7633 assert(size
== 1 || size
== 2);
7634 genenvfn
= fns
[size
- 1][u
];
7638 g_assert_not_reached();
7641 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7642 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7643 tcg_temp_free_i32(tcg_rd32
);
7644 tcg_temp_free_i32(tcg_rn
);
7645 tcg_temp_free_i32(tcg_rm
);
7648 write_fp_dreg(s
, rd
, tcg_rd
);
7650 tcg_temp_free_i64(tcg_rd
);
7653 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7654 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7655 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7657 /* Handle 64->64 opcodes which are shared between the scalar and
7658 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7659 * is valid in either group and also the double-precision fp ops.
7660 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7666 case 0x4: /* CLS, CLZ */
7668 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7670 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7674 /* This opcode is shared with CNT and RBIT but we have earlier
7675 * enforced that size == 3 if and only if this is the NOT insn.
7677 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7679 case 0x7: /* SQABS, SQNEG */
7681 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7683 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7686 case 0xa: /* CMLT */
7687 /* 64 bit integer comparison against zero, result is
7688 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7693 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7694 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7696 case 0x8: /* CMGT, CMGE */
7697 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7699 case 0x9: /* CMEQ, CMLE */
7700 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7702 case 0xb: /* ABS, NEG */
7704 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7706 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7707 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7708 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7710 tcg_temp_free_i64(tcg_zero
);
7713 case 0x2f: /* FABS */
7714 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7716 case 0x6f: /* FNEG */
7717 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7719 case 0x7f: /* FSQRT */
7720 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7722 case 0x1a: /* FCVTNS */
7723 case 0x1b: /* FCVTMS */
7724 case 0x1c: /* FCVTAS */
7725 case 0x3a: /* FCVTPS */
7726 case 0x3b: /* FCVTZS */
7728 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7729 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7730 tcg_temp_free_i32(tcg_shift
);
7733 case 0x5a: /* FCVTNU */
7734 case 0x5b: /* FCVTMU */
7735 case 0x5c: /* FCVTAU */
7736 case 0x7a: /* FCVTPU */
7737 case 0x7b: /* FCVTZU */
7739 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7740 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7741 tcg_temp_free_i32(tcg_shift
);
7744 case 0x18: /* FRINTN */
7745 case 0x19: /* FRINTM */
7746 case 0x38: /* FRINTP */
7747 case 0x39: /* FRINTZ */
7748 case 0x58: /* FRINTA */
7749 case 0x79: /* FRINTI */
7750 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7752 case 0x59: /* FRINTX */
7753 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7756 g_assert_not_reached();
7760 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7761 bool is_scalar
, bool is_u
, bool is_q
,
7762 int size
, int rn
, int rd
)
7764 bool is_double
= (size
== 3);
7767 if (!fp_access_check(s
)) {
7771 fpst
= get_fpstatus_ptr();
7774 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7775 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7776 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7777 NeonGenTwoDoubleOPFn
*genfn
;
7782 case 0x2e: /* FCMLT (zero) */
7785 case 0x2c: /* FCMGT (zero) */
7786 genfn
= gen_helper_neon_cgt_f64
;
7788 case 0x2d: /* FCMEQ (zero) */
7789 genfn
= gen_helper_neon_ceq_f64
;
7791 case 0x6d: /* FCMLE (zero) */
7794 case 0x6c: /* FCMGE (zero) */
7795 genfn
= gen_helper_neon_cge_f64
;
7798 g_assert_not_reached();
7801 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7802 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7804 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7806 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7808 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7811 clear_vec_high(s
, rd
);
7814 tcg_temp_free_i64(tcg_res
);
7815 tcg_temp_free_i64(tcg_zero
);
7816 tcg_temp_free_i64(tcg_op
);
7818 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7819 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7820 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7821 NeonGenTwoSingleOPFn
*genfn
;
7823 int pass
, maxpasses
;
7826 case 0x2e: /* FCMLT (zero) */
7829 case 0x2c: /* FCMGT (zero) */
7830 genfn
= gen_helper_neon_cgt_f32
;
7832 case 0x2d: /* FCMEQ (zero) */
7833 genfn
= gen_helper_neon_ceq_f32
;
7835 case 0x6d: /* FCMLE (zero) */
7838 case 0x6c: /* FCMGE (zero) */
7839 genfn
= gen_helper_neon_cge_f32
;
7842 g_assert_not_reached();
7848 maxpasses
= is_q
? 4 : 2;
7851 for (pass
= 0; pass
< maxpasses
; pass
++) {
7852 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7854 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7856 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7859 write_fp_sreg(s
, rd
, tcg_res
);
7861 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7864 tcg_temp_free_i32(tcg_res
);
7865 tcg_temp_free_i32(tcg_zero
);
7866 tcg_temp_free_i32(tcg_op
);
7867 if (!is_q
&& !is_scalar
) {
7868 clear_vec_high(s
, rd
);
7872 tcg_temp_free_ptr(fpst
);
7875 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7876 bool is_scalar
, bool is_u
, bool is_q
,
7877 int size
, int rn
, int rd
)
7879 bool is_double
= (size
== 3);
7880 TCGv_ptr fpst
= get_fpstatus_ptr();
7883 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7884 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7887 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7888 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7890 case 0x3d: /* FRECPE */
7891 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7893 case 0x3f: /* FRECPX */
7894 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7896 case 0x7d: /* FRSQRTE */
7897 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7900 g_assert_not_reached();
7902 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7905 clear_vec_high(s
, rd
);
7908 tcg_temp_free_i64(tcg_res
);
7909 tcg_temp_free_i64(tcg_op
);
7911 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7912 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7913 int pass
, maxpasses
;
7918 maxpasses
= is_q
? 4 : 2;
7921 for (pass
= 0; pass
< maxpasses
; pass
++) {
7922 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7925 case 0x3c: /* URECPE */
7926 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7928 case 0x3d: /* FRECPE */
7929 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7931 case 0x3f: /* FRECPX */
7932 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7934 case 0x7d: /* FRSQRTE */
7935 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7938 g_assert_not_reached();
7942 write_fp_sreg(s
, rd
, tcg_res
);
7944 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7947 tcg_temp_free_i32(tcg_res
);
7948 tcg_temp_free_i32(tcg_op
);
7949 if (!is_q
&& !is_scalar
) {
7950 clear_vec_high(s
, rd
);
7953 tcg_temp_free_ptr(fpst
);
7956 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7957 int opcode
, bool u
, bool is_q
,
7958 int size
, int rn
, int rd
)
7960 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7961 * in the source becomes a size element in the destination).
7964 TCGv_i32 tcg_res
[2];
7965 int destelt
= is_q
? 2 : 0;
7966 int passes
= scalar
? 1 : 2;
7969 tcg_res
[1] = tcg_const_i32(0);
7972 for (pass
= 0; pass
< passes
; pass
++) {
7973 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7974 NeonGenNarrowFn
*genfn
= NULL
;
7975 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7978 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7980 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7982 tcg_res
[pass
] = tcg_temp_new_i32();
7985 case 0x12: /* XTN, SQXTUN */
7987 static NeonGenNarrowFn
* const xtnfns
[3] = {
7988 gen_helper_neon_narrow_u8
,
7989 gen_helper_neon_narrow_u16
,
7990 tcg_gen_extrl_i64_i32
,
7992 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7993 gen_helper_neon_unarrow_sat8
,
7994 gen_helper_neon_unarrow_sat16
,
7995 gen_helper_neon_unarrow_sat32
,
7998 genenvfn
= sqxtunfns
[size
];
8000 genfn
= xtnfns
[size
];
8004 case 0x14: /* SQXTN, UQXTN */
8006 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
8007 { gen_helper_neon_narrow_sat_s8
,
8008 gen_helper_neon_narrow_sat_u8
},
8009 { gen_helper_neon_narrow_sat_s16
,
8010 gen_helper_neon_narrow_sat_u16
},
8011 { gen_helper_neon_narrow_sat_s32
,
8012 gen_helper_neon_narrow_sat_u32
},
8014 genenvfn
= fns
[size
][u
];
8017 case 0x16: /* FCVTN, FCVTN2 */
8018 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
8020 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
8022 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
8023 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
8024 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
8025 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
8026 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
8027 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
8028 tcg_temp_free_i32(tcg_lo
);
8029 tcg_temp_free_i32(tcg_hi
);
8032 case 0x56: /* FCVTXN, FCVTXN2 */
8033 /* 64 bit to 32 bit float conversion
8034 * with von Neumann rounding (round to odd)
8037 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
8040 g_assert_not_reached();
8044 genfn(tcg_res
[pass
], tcg_op
);
8045 } else if (genenvfn
) {
8046 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
8049 tcg_temp_free_i64(tcg_op
);
8052 for (pass
= 0; pass
< 2; pass
++) {
8053 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
8054 tcg_temp_free_i32(tcg_res
[pass
]);
8057 clear_vec_high(s
, rd
);
8061 /* Remaining saturating accumulating ops */
8062 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
8063 bool is_q
, int size
, int rn
, int rd
)
8065 bool is_double
= (size
== 3);
8068 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
8069 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8072 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8073 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
8074 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8076 if (is_u
) { /* USQADD */
8077 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8078 } else { /* SUQADD */
8079 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8081 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8084 clear_vec_high(s
, rd
);
8087 tcg_temp_free_i64(tcg_rd
);
8088 tcg_temp_free_i64(tcg_rn
);
8090 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8091 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8092 int pass
, maxpasses
;
8097 maxpasses
= is_q
? 4 : 2;
8100 for (pass
= 0; pass
< maxpasses
; pass
++) {
8102 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8103 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8105 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8106 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8109 if (is_u
) { /* USQADD */
8112 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8115 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8118 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8121 g_assert_not_reached();
8123 } else { /* SUQADD */
8126 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8129 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8132 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8135 g_assert_not_reached();
8140 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8141 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8142 tcg_temp_free_i64(tcg_zero
);
8144 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8148 clear_vec_high(s
, rd
);
8151 tcg_temp_free_i32(tcg_rd
);
8152 tcg_temp_free_i32(tcg_rn
);
8156 /* AdvSIMD scalar two reg misc
8157 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8158 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8159 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8160 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8162 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8164 int rd
= extract32(insn
, 0, 5);
8165 int rn
= extract32(insn
, 5, 5);
8166 int opcode
= extract32(insn
, 12, 5);
8167 int size
= extract32(insn
, 22, 2);
8168 bool u
= extract32(insn
, 29, 1);
8169 bool is_fcvt
= false;
8172 TCGv_ptr tcg_fpstatus
;
8175 case 0x3: /* USQADD / SUQADD*/
8176 if (!fp_access_check(s
)) {
8179 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8181 case 0x7: /* SQABS / SQNEG */
8183 case 0xa: /* CMLT */
8185 unallocated_encoding(s
);
8189 case 0x8: /* CMGT, CMGE */
8190 case 0x9: /* CMEQ, CMLE */
8191 case 0xb: /* ABS, NEG */
8193 unallocated_encoding(s
);
8197 case 0x12: /* SQXTUN */
8199 unallocated_encoding(s
);
8203 case 0x14: /* SQXTN, UQXTN */
8205 unallocated_encoding(s
);
8208 if (!fp_access_check(s
)) {
8211 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8216 /* Floating point: U, size[1] and opcode indicate operation;
8217 * size[0] indicates single or double precision.
8219 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8220 size
= extract32(size
, 0, 1) ? 3 : 2;
8222 case 0x2c: /* FCMGT (zero) */
8223 case 0x2d: /* FCMEQ (zero) */
8224 case 0x2e: /* FCMLT (zero) */
8225 case 0x6c: /* FCMGE (zero) */
8226 case 0x6d: /* FCMLE (zero) */
8227 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8229 case 0x1d: /* SCVTF */
8230 case 0x5d: /* UCVTF */
8232 bool is_signed
= (opcode
== 0x1d);
8233 if (!fp_access_check(s
)) {
8236 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8239 case 0x3d: /* FRECPE */
8240 case 0x3f: /* FRECPX */
8241 case 0x7d: /* FRSQRTE */
8242 if (!fp_access_check(s
)) {
8245 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8247 case 0x1a: /* FCVTNS */
8248 case 0x1b: /* FCVTMS */
8249 case 0x3a: /* FCVTPS */
8250 case 0x3b: /* FCVTZS */
8251 case 0x5a: /* FCVTNU */
8252 case 0x5b: /* FCVTMU */
8253 case 0x7a: /* FCVTPU */
8254 case 0x7b: /* FCVTZU */
8256 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8258 case 0x1c: /* FCVTAS */
8259 case 0x5c: /* FCVTAU */
8260 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8262 rmode
= FPROUNDING_TIEAWAY
;
8264 case 0x56: /* FCVTXN, FCVTXN2 */
8266 unallocated_encoding(s
);
8269 if (!fp_access_check(s
)) {
8272 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8275 unallocated_encoding(s
);
8280 unallocated_encoding(s
);
8284 if (!fp_access_check(s
)) {
8289 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8290 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8291 tcg_fpstatus
= get_fpstatus_ptr();
8294 tcg_fpstatus
= NULL
;
8298 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8299 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8301 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8302 write_fp_dreg(s
, rd
, tcg_rd
);
8303 tcg_temp_free_i64(tcg_rd
);
8304 tcg_temp_free_i64(tcg_rn
);
8306 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8307 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8309 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8312 case 0x7: /* SQABS, SQNEG */
8314 NeonGenOneOpEnvFn
*genfn
;
8315 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8316 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8317 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8318 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8320 genfn
= fns
[size
][u
];
8321 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8324 case 0x1a: /* FCVTNS */
8325 case 0x1b: /* FCVTMS */
8326 case 0x1c: /* FCVTAS */
8327 case 0x3a: /* FCVTPS */
8328 case 0x3b: /* FCVTZS */
8330 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8331 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8332 tcg_temp_free_i32(tcg_shift
);
8335 case 0x5a: /* FCVTNU */
8336 case 0x5b: /* FCVTMU */
8337 case 0x5c: /* FCVTAU */
8338 case 0x7a: /* FCVTPU */
8339 case 0x7b: /* FCVTZU */
8341 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8342 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8343 tcg_temp_free_i32(tcg_shift
);
8347 g_assert_not_reached();
8350 write_fp_sreg(s
, rd
, tcg_rd
);
8351 tcg_temp_free_i32(tcg_rd
);
8352 tcg_temp_free_i32(tcg_rn
);
8356 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8357 tcg_temp_free_i32(tcg_rmode
);
8358 tcg_temp_free_ptr(tcg_fpstatus
);
8362 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8363 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8364 int immh
, int immb
, int opcode
, int rn
, int rd
)
8366 int size
= 32 - clz32(immh
) - 1;
8367 int immhb
= immh
<< 3 | immb
;
8368 int shift
= 2 * (8 << size
) - immhb
;
8369 bool accumulate
= false;
8371 bool insert
= false;
8372 int dsize
= is_q
? 128 : 64;
8373 int esize
= 8 << size
;
8374 int elements
= dsize
/esize
;
8375 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8376 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8377 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8381 if (extract32(immh
, 3, 1) && !is_q
) {
8382 unallocated_encoding(s
);
8386 if (size
> 3 && !is_q
) {
8387 unallocated_encoding(s
);
8391 if (!fp_access_check(s
)) {
8396 case 0x02: /* SSRA / USRA (accumulate) */
8399 case 0x04: /* SRSHR / URSHR (rounding) */
8402 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8403 accumulate
= round
= true;
8405 case 0x08: /* SRI */
8411 uint64_t round_const
= 1ULL << (shift
- 1);
8412 tcg_round
= tcg_const_i64(round_const
);
8417 for (i
= 0; i
< elements
; i
++) {
8418 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8419 if (accumulate
|| insert
) {
8420 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8424 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8426 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8427 accumulate
, is_u
, size
, shift
);
8430 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8434 clear_vec_high(s
, rd
);
8438 tcg_temp_free_i64(tcg_round
);
8442 /* SHL/SLI - Vector shift left */
8443 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8444 int immh
, int immb
, int opcode
, int rn
, int rd
)
8446 int size
= 32 - clz32(immh
) - 1;
8447 int immhb
= immh
<< 3 | immb
;
8448 int shift
= immhb
- (8 << size
);
8449 int dsize
= is_q
? 128 : 64;
8450 int esize
= 8 << size
;
8451 int elements
= dsize
/esize
;
8452 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8453 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8456 if (extract32(immh
, 3, 1) && !is_q
) {
8457 unallocated_encoding(s
);
8461 if (size
> 3 && !is_q
) {
8462 unallocated_encoding(s
);
8466 if (!fp_access_check(s
)) {
8470 for (i
= 0; i
< elements
; i
++) {
8471 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8473 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8476 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8478 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8482 clear_vec_high(s
, rd
);
8486 /* USHLL/SHLL - Vector shift left with widening */
8487 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8488 int immh
, int immb
, int opcode
, int rn
, int rd
)
8490 int size
= 32 - clz32(immh
) - 1;
8491 int immhb
= immh
<< 3 | immb
;
8492 int shift
= immhb
- (8 << size
);
8494 int esize
= 8 << size
;
8495 int elements
= dsize
/esize
;
8496 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8497 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8501 unallocated_encoding(s
);
8505 if (!fp_access_check(s
)) {
8509 /* For the LL variants the store is larger than the load,
8510 * so if rd == rn we would overwrite parts of our input.
8511 * So load everything right now and use shifts in the main loop.
8513 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8515 for (i
= 0; i
< elements
; i
++) {
8516 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8517 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8518 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8519 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8523 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8524 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8525 int immh
, int immb
, int opcode
, int rn
, int rd
)
8527 int immhb
= immh
<< 3 | immb
;
8528 int size
= 32 - clz32(immh
) - 1;
8530 int esize
= 8 << size
;
8531 int elements
= dsize
/esize
;
8532 int shift
= (2 * esize
) - immhb
;
8533 bool round
= extract32(opcode
, 0, 1);
8534 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8538 if (extract32(immh
, 3, 1)) {
8539 unallocated_encoding(s
);
8543 if (!fp_access_check(s
)) {
8547 tcg_rn
= tcg_temp_new_i64();
8548 tcg_rd
= tcg_temp_new_i64();
8549 tcg_final
= tcg_temp_new_i64();
8550 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8553 uint64_t round_const
= 1ULL << (shift
- 1);
8554 tcg_round
= tcg_const_i64(round_const
);
8559 for (i
= 0; i
< elements
; i
++) {
8560 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8561 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8562 false, true, size
+1, shift
);
8564 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8568 clear_vec_high(s
, rd
);
8569 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8571 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8575 tcg_temp_free_i64(tcg_round
);
8577 tcg_temp_free_i64(tcg_rn
);
8578 tcg_temp_free_i64(tcg_rd
);
8579 tcg_temp_free_i64(tcg_final
);
8584 /* AdvSIMD shift by immediate
8585 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8586 * +---+---+---+-------------+------+------+--------+---+------+------+
8587 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8588 * +---+---+---+-------------+------+------+--------+---+------+------+
8590 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8592 int rd
= extract32(insn
, 0, 5);
8593 int rn
= extract32(insn
, 5, 5);
8594 int opcode
= extract32(insn
, 11, 5);
8595 int immb
= extract32(insn
, 16, 3);
8596 int immh
= extract32(insn
, 19, 4);
8597 bool is_u
= extract32(insn
, 29, 1);
8598 bool is_q
= extract32(insn
, 30, 1);
8601 case 0x08: /* SRI */
8603 unallocated_encoding(s
);
8607 case 0x00: /* SSHR / USHR */
8608 case 0x02: /* SSRA / USRA (accumulate) */
8609 case 0x04: /* SRSHR / URSHR (rounding) */
8610 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8611 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8613 case 0x0a: /* SHL / SLI */
8614 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8616 case 0x10: /* SHRN */
8617 case 0x11: /* RSHRN / SQRSHRUN */
8619 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8622 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8625 case 0x12: /* SQSHRN / UQSHRN */
8626 case 0x13: /* SQRSHRN / UQRSHRN */
8627 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8630 case 0x14: /* SSHLL / USHLL */
8631 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8633 case 0x1c: /* SCVTF / UCVTF */
8634 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8637 case 0xc: /* SQSHLU */
8639 unallocated_encoding(s
);
8642 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8644 case 0xe: /* SQSHL, UQSHL */
8645 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8647 case 0x1f: /* FCVTZS/ FCVTZU */
8648 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8651 unallocated_encoding(s
);
8656 /* Generate code to do a "long" addition or subtraction, ie one done in
8657 * TCGv_i64 on vector lanes twice the width specified by size.
8659 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8660 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8662 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8663 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8664 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8665 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8667 NeonGenTwo64OpFn
*genfn
;
8670 genfn
= fns
[size
][is_sub
];
8671 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8674 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8675 int opcode
, int rd
, int rn
, int rm
)
8677 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8678 TCGv_i64 tcg_res
[2];
8681 tcg_res
[0] = tcg_temp_new_i64();
8682 tcg_res
[1] = tcg_temp_new_i64();
8684 /* Does this op do an adding accumulate, a subtracting accumulate,
8685 * or no accumulate at all?
8703 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8704 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8707 /* size == 2 means two 32x32->64 operations; this is worth special
8708 * casing because we can generally handle it inline.
8711 for (pass
= 0; pass
< 2; pass
++) {
8712 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8713 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8714 TCGv_i64 tcg_passres
;
8715 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8717 int elt
= pass
+ is_q
* 2;
8719 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8720 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8723 tcg_passres
= tcg_res
[pass
];
8725 tcg_passres
= tcg_temp_new_i64();
8729 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8730 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8732 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8733 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8735 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8736 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8738 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8739 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8741 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8742 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8743 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8745 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8746 tcg_temp_free_i64(tcg_tmp1
);
8747 tcg_temp_free_i64(tcg_tmp2
);
8750 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8751 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8752 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8753 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8755 case 9: /* SQDMLAL, SQDMLAL2 */
8756 case 11: /* SQDMLSL, SQDMLSL2 */
8757 case 13: /* SQDMULL, SQDMULL2 */
8758 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8759 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8760 tcg_passres
, tcg_passres
);
8763 g_assert_not_reached();
8766 if (opcode
== 9 || opcode
== 11) {
8767 /* saturating accumulate ops */
8769 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8771 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8772 tcg_res
[pass
], tcg_passres
);
8773 } else if (accop
> 0) {
8774 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8775 } else if (accop
< 0) {
8776 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8780 tcg_temp_free_i64(tcg_passres
);
8783 tcg_temp_free_i64(tcg_op1
);
8784 tcg_temp_free_i64(tcg_op2
);
8787 /* size 0 or 1, generally helper functions */
8788 for (pass
= 0; pass
< 2; pass
++) {
8789 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8790 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8791 TCGv_i64 tcg_passres
;
8792 int elt
= pass
+ is_q
* 2;
8794 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8795 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8798 tcg_passres
= tcg_res
[pass
];
8800 tcg_passres
= tcg_temp_new_i64();
8804 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8805 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8807 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8808 static NeonGenWidenFn
* const widenfns
[2][2] = {
8809 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8810 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8812 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8814 widenfn(tcg_op2_64
, tcg_op2
);
8815 widenfn(tcg_passres
, tcg_op1
);
8816 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8817 tcg_passres
, tcg_op2_64
);
8818 tcg_temp_free_i64(tcg_op2_64
);
8821 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8822 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8825 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8827 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8831 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8833 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8837 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8838 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8839 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8842 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8844 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8848 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8850 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8854 case 9: /* SQDMLAL, SQDMLAL2 */
8855 case 11: /* SQDMLSL, SQDMLSL2 */
8856 case 13: /* SQDMULL, SQDMULL2 */
8858 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8859 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8860 tcg_passres
, tcg_passres
);
8862 case 14: /* PMULL */
8864 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8867 g_assert_not_reached();
8869 tcg_temp_free_i32(tcg_op1
);
8870 tcg_temp_free_i32(tcg_op2
);
8873 if (opcode
== 9 || opcode
== 11) {
8874 /* saturating accumulate ops */
8876 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8878 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8882 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8883 tcg_res
[pass
], tcg_passres
);
8885 tcg_temp_free_i64(tcg_passres
);
8890 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8891 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8892 tcg_temp_free_i64(tcg_res
[0]);
8893 tcg_temp_free_i64(tcg_res
[1]);
8896 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8897 int opcode
, int rd
, int rn
, int rm
)
8899 TCGv_i64 tcg_res
[2];
8900 int part
= is_q
? 2 : 0;
8903 for (pass
= 0; pass
< 2; pass
++) {
8904 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8905 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8906 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8907 static NeonGenWidenFn
* const widenfns
[3][2] = {
8908 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8909 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8910 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8912 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8914 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8915 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8916 widenfn(tcg_op2_wide
, tcg_op2
);
8917 tcg_temp_free_i32(tcg_op2
);
8918 tcg_res
[pass
] = tcg_temp_new_i64();
8919 gen_neon_addl(size
, (opcode
== 3),
8920 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8921 tcg_temp_free_i64(tcg_op1
);
8922 tcg_temp_free_i64(tcg_op2_wide
);
8925 for (pass
= 0; pass
< 2; pass
++) {
8926 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8927 tcg_temp_free_i64(tcg_res
[pass
]);
8931 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8933 tcg_gen_addi_i64(in
, in
, 1U << 31);
8934 tcg_gen_extrh_i64_i32(res
, in
);
8937 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8938 int opcode
, int rd
, int rn
, int rm
)
8940 TCGv_i32 tcg_res
[2];
8941 int part
= is_q
? 2 : 0;
8944 for (pass
= 0; pass
< 2; pass
++) {
8945 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8946 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8947 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8948 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8949 { gen_helper_neon_narrow_high_u8
,
8950 gen_helper_neon_narrow_round_high_u8
},
8951 { gen_helper_neon_narrow_high_u16
,
8952 gen_helper_neon_narrow_round_high_u16
},
8953 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8955 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8957 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8958 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8960 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8962 tcg_temp_free_i64(tcg_op1
);
8963 tcg_temp_free_i64(tcg_op2
);
8965 tcg_res
[pass
] = tcg_temp_new_i32();
8966 gennarrow(tcg_res
[pass
], tcg_wideres
);
8967 tcg_temp_free_i64(tcg_wideres
);
8970 for (pass
= 0; pass
< 2; pass
++) {
8971 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8972 tcg_temp_free_i32(tcg_res
[pass
]);
8975 clear_vec_high(s
, rd
);
8979 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8981 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8982 * is the only three-reg-diff instruction which produces a
8983 * 128-bit wide result from a single operation. However since
8984 * it's possible to calculate the two halves more or less
8985 * separately we just use two helper calls.
8987 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8988 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8989 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8991 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8992 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8993 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8994 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8995 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8996 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8998 tcg_temp_free_i64(tcg_op1
);
8999 tcg_temp_free_i64(tcg_op2
);
9000 tcg_temp_free_i64(tcg_res
);
9003 /* AdvSIMD three different
9004 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9005 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
9006 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9007 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
9009 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9011 /* Instructions in this group fall into three basic classes
9012 * (in each case with the operation working on each element in
9013 * the input vectors):
9014 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
9016 * (2) wide 64 x 128 -> 128
9017 * (3) narrowing 128 x 128 -> 64
9018 * Here we do initial decode, catch unallocated cases and
9019 * dispatch to separate functions for each class.
9021 int is_q
= extract32(insn
, 30, 1);
9022 int is_u
= extract32(insn
, 29, 1);
9023 int size
= extract32(insn
, 22, 2);
9024 int opcode
= extract32(insn
, 12, 4);
9025 int rm
= extract32(insn
, 16, 5);
9026 int rn
= extract32(insn
, 5, 5);
9027 int rd
= extract32(insn
, 0, 5);
9030 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
9031 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
9032 /* 64 x 128 -> 128 */
9034 unallocated_encoding(s
);
9037 if (!fp_access_check(s
)) {
9040 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9042 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
9043 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
9044 /* 128 x 128 -> 64 */
9046 unallocated_encoding(s
);
9049 if (!fp_access_check(s
)) {
9052 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9054 case 14: /* PMULL, PMULL2 */
9055 if (is_u
|| size
== 1 || size
== 2) {
9056 unallocated_encoding(s
);
9060 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
9061 unallocated_encoding(s
);
9064 if (!fp_access_check(s
)) {
9067 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
9071 case 9: /* SQDMLAL, SQDMLAL2 */
9072 case 11: /* SQDMLSL, SQDMLSL2 */
9073 case 13: /* SQDMULL, SQDMULL2 */
9074 if (is_u
|| size
== 0) {
9075 unallocated_encoding(s
);
9079 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9080 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9081 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9082 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9083 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9084 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9085 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9086 /* 64 x 64 -> 128 */
9088 unallocated_encoding(s
);
9092 if (!fp_access_check(s
)) {
9096 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9099 /* opcode 15 not allocated */
9100 unallocated_encoding(s
);
9105 static void gen_bsl_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
9107 tcg_gen_xor_i64(rn
, rn
, rm
);
9108 tcg_gen_and_i64(rn
, rn
, rd
);
9109 tcg_gen_xor_i64(rd
, rm
, rn
);
9112 static void gen_bit_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
9114 tcg_gen_xor_i64(rn
, rn
, rd
);
9115 tcg_gen_and_i64(rn
, rn
, rm
);
9116 tcg_gen_xor_i64(rd
, rd
, rn
);
9119 static void gen_bif_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
9121 tcg_gen_xor_i64(rn
, rn
, rd
);
9122 tcg_gen_andc_i64(rn
, rn
, rm
);
9123 tcg_gen_xor_i64(rd
, rd
, rn
);
9126 static void gen_bsl_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
9128 tcg_gen_xor_vec(vece
, rn
, rn
, rm
);
9129 tcg_gen_and_vec(vece
, rn
, rn
, rd
);
9130 tcg_gen_xor_vec(vece
, rd
, rm
, rn
);
9133 static void gen_bit_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
9135 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
9136 tcg_gen_and_vec(vece
, rn
, rn
, rm
);
9137 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
9140 static void gen_bif_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
9142 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
9143 tcg_gen_andc_vec(vece
, rn
, rn
, rm
);
9144 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
9147 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9148 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9150 static const GVecGen3 bsl_op
= {
9151 .fni8
= gen_bsl_i64
,
9152 .fniv
= gen_bsl_vec
,
9153 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9156 static const GVecGen3 bit_op
= {
9157 .fni8
= gen_bit_i64
,
9158 .fniv
= gen_bit_vec
,
9159 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9162 static const GVecGen3 bif_op
= {
9163 .fni8
= gen_bif_i64
,
9164 .fniv
= gen_bif_vec
,
9165 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9169 int rd
= extract32(insn
, 0, 5);
9170 int rn
= extract32(insn
, 5, 5);
9171 int rm
= extract32(insn
, 16, 5);
9172 int size
= extract32(insn
, 22, 2);
9173 bool is_u
= extract32(insn
, 29, 1);
9174 bool is_q
= extract32(insn
, 30, 1);
9176 if (!fp_access_check(s
)) {
9180 switch (size
+ 4 * is_u
) {
9182 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
9185 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
9188 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
9191 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
9194 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
9197 case 5: /* BSL bitwise select */
9198 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
9200 case 6: /* BIT, bitwise insert if true */
9201 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
9203 case 7: /* BIF, bitwise insert if false */
9204 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
9208 g_assert_not_reached();
9212 /* Helper functions for 32 bit comparisons */
9213 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9215 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9218 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9220 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9223 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9225 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9228 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9230 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9233 /* Pairwise op subgroup of C3.6.16.
9235 * This is called directly or via the handle_3same_float for float pairwise
9236 * operations where the opcode and size are calculated differently.
9238 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9239 int size
, int rn
, int rm
, int rd
)
9244 /* Floating point operations need fpst */
9245 if (opcode
>= 0x58) {
9246 fpst
= get_fpstatus_ptr();
9251 if (!fp_access_check(s
)) {
9255 /* These operations work on the concatenated rm:rn, with each pair of
9256 * adjacent elements being operated on to produce an element in the result.
9259 TCGv_i64 tcg_res
[2];
9261 for (pass
= 0; pass
< 2; pass
++) {
9262 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9263 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9264 int passreg
= (pass
== 0) ? rn
: rm
;
9266 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9267 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9268 tcg_res
[pass
] = tcg_temp_new_i64();
9271 case 0x17: /* ADDP */
9272 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9274 case 0x58: /* FMAXNMP */
9275 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9277 case 0x5a: /* FADDP */
9278 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9280 case 0x5e: /* FMAXP */
9281 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9283 case 0x78: /* FMINNMP */
9284 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9286 case 0x7e: /* FMINP */
9287 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9290 g_assert_not_reached();
9293 tcg_temp_free_i64(tcg_op1
);
9294 tcg_temp_free_i64(tcg_op2
);
9297 for (pass
= 0; pass
< 2; pass
++) {
9298 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9299 tcg_temp_free_i64(tcg_res
[pass
]);
9302 int maxpass
= is_q
? 4 : 2;
9303 TCGv_i32 tcg_res
[4];
9305 for (pass
= 0; pass
< maxpass
; pass
++) {
9306 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9307 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9308 NeonGenTwoOpFn
*genfn
= NULL
;
9309 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9310 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9312 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9313 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9314 tcg_res
[pass
] = tcg_temp_new_i32();
9317 case 0x17: /* ADDP */
9319 static NeonGenTwoOpFn
* const fns
[3] = {
9320 gen_helper_neon_padd_u8
,
9321 gen_helper_neon_padd_u16
,
9327 case 0x14: /* SMAXP, UMAXP */
9329 static NeonGenTwoOpFn
* const fns
[3][2] = {
9330 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9331 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9332 { gen_max_s32
, gen_max_u32
},
9334 genfn
= fns
[size
][u
];
9337 case 0x15: /* SMINP, UMINP */
9339 static NeonGenTwoOpFn
* const fns
[3][2] = {
9340 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9341 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9342 { gen_min_s32
, gen_min_u32
},
9344 genfn
= fns
[size
][u
];
9347 /* The FP operations are all on single floats (32 bit) */
9348 case 0x58: /* FMAXNMP */
9349 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9351 case 0x5a: /* FADDP */
9352 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9354 case 0x5e: /* FMAXP */
9355 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9357 case 0x78: /* FMINNMP */
9358 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9360 case 0x7e: /* FMINP */
9361 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9364 g_assert_not_reached();
9367 /* FP ops called directly, otherwise call now */
9369 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9372 tcg_temp_free_i32(tcg_op1
);
9373 tcg_temp_free_i32(tcg_op2
);
9376 for (pass
= 0; pass
< maxpass
; pass
++) {
9377 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9378 tcg_temp_free_i32(tcg_res
[pass
]);
9381 clear_vec_high(s
, rd
);
9386 tcg_temp_free_ptr(fpst
);
9390 /* Floating point op subgroup of C3.6.16. */
9391 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9393 /* For floating point ops, the U, size[1] and opcode bits
9394 * together indicate the operation. size[0] indicates single
9397 int fpopcode
= extract32(insn
, 11, 5)
9398 | (extract32(insn
, 23, 1) << 5)
9399 | (extract32(insn
, 29, 1) << 6);
9400 int is_q
= extract32(insn
, 30, 1);
9401 int size
= extract32(insn
, 22, 1);
9402 int rm
= extract32(insn
, 16, 5);
9403 int rn
= extract32(insn
, 5, 5);
9404 int rd
= extract32(insn
, 0, 5);
9406 int datasize
= is_q
? 128 : 64;
9407 int esize
= 32 << size
;
9408 int elements
= datasize
/ esize
;
9410 if (size
== 1 && !is_q
) {
9411 unallocated_encoding(s
);
9416 case 0x58: /* FMAXNMP */
9417 case 0x5a: /* FADDP */
9418 case 0x5e: /* FMAXP */
9419 case 0x78: /* FMINNMP */
9420 case 0x7e: /* FMINP */
9421 if (size
&& !is_q
) {
9422 unallocated_encoding(s
);
9425 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9428 case 0x1b: /* FMULX */
9429 case 0x1f: /* FRECPS */
9430 case 0x3f: /* FRSQRTS */
9431 case 0x5d: /* FACGE */
9432 case 0x7d: /* FACGT */
9433 case 0x19: /* FMLA */
9434 case 0x39: /* FMLS */
9435 case 0x18: /* FMAXNM */
9436 case 0x1a: /* FADD */
9437 case 0x1c: /* FCMEQ */
9438 case 0x1e: /* FMAX */
9439 case 0x38: /* FMINNM */
9440 case 0x3a: /* FSUB */
9441 case 0x3e: /* FMIN */
9442 case 0x5b: /* FMUL */
9443 case 0x5c: /* FCMGE */
9444 case 0x5f: /* FDIV */
9445 case 0x7a: /* FABD */
9446 case 0x7c: /* FCMGT */
9447 if (!fp_access_check(s
)) {
9451 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9454 unallocated_encoding(s
);
9459 /* Integer op subgroup of C3.6.16. */
9460 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9462 int is_q
= extract32(insn
, 30, 1);
9463 int u
= extract32(insn
, 29, 1);
9464 int size
= extract32(insn
, 22, 2);
9465 int opcode
= extract32(insn
, 11, 5);
9466 int rm
= extract32(insn
, 16, 5);
9467 int rn
= extract32(insn
, 5, 5);
9468 int rd
= extract32(insn
, 0, 5);
9472 case 0x13: /* MUL, PMUL */
9473 if (u
&& size
!= 0) {
9474 unallocated_encoding(s
);
9478 case 0x0: /* SHADD, UHADD */
9479 case 0x2: /* SRHADD, URHADD */
9480 case 0x4: /* SHSUB, UHSUB */
9481 case 0xc: /* SMAX, UMAX */
9482 case 0xd: /* SMIN, UMIN */
9483 case 0xe: /* SABD, UABD */
9484 case 0xf: /* SABA, UABA */
9485 case 0x12: /* MLA, MLS */
9487 unallocated_encoding(s
);
9491 case 0x16: /* SQDMULH, SQRDMULH */
9492 if (size
== 0 || size
== 3) {
9493 unallocated_encoding(s
);
9498 if (size
== 3 && !is_q
) {
9499 unallocated_encoding(s
);
9505 if (!fp_access_check(s
)) {
9510 case 0x10: /* ADD, SUB */
9512 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
9514 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
9521 for (pass
= 0; pass
< 2; pass
++) {
9522 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9523 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9524 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9526 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9527 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9529 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9531 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9533 tcg_temp_free_i64(tcg_res
);
9534 tcg_temp_free_i64(tcg_op1
);
9535 tcg_temp_free_i64(tcg_op2
);
9538 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9539 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9540 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9541 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9542 NeonGenTwoOpFn
*genfn
= NULL
;
9543 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9545 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9546 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9549 case 0x0: /* SHADD, UHADD */
9551 static NeonGenTwoOpFn
* const fns
[3][2] = {
9552 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9553 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9554 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9556 genfn
= fns
[size
][u
];
9559 case 0x1: /* SQADD, UQADD */
9561 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9562 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9563 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9564 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9566 genenvfn
= fns
[size
][u
];
9569 case 0x2: /* SRHADD, URHADD */
9571 static NeonGenTwoOpFn
* const fns
[3][2] = {
9572 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9573 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9574 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9576 genfn
= fns
[size
][u
];
9579 case 0x4: /* SHSUB, UHSUB */
9581 static NeonGenTwoOpFn
* const fns
[3][2] = {
9582 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9583 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9584 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9586 genfn
= fns
[size
][u
];
9589 case 0x5: /* SQSUB, UQSUB */
9591 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9592 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9593 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9594 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9596 genenvfn
= fns
[size
][u
];
9599 case 0x6: /* CMGT, CMHI */
9601 static NeonGenTwoOpFn
* const fns
[3][2] = {
9602 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9603 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9604 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9606 genfn
= fns
[size
][u
];
9609 case 0x7: /* CMGE, CMHS */
9611 static NeonGenTwoOpFn
* const fns
[3][2] = {
9612 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9613 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9614 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9616 genfn
= fns
[size
][u
];
9619 case 0x8: /* SSHL, USHL */
9621 static NeonGenTwoOpFn
* const fns
[3][2] = {
9622 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9623 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9624 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9626 genfn
= fns
[size
][u
];
9629 case 0x9: /* SQSHL, UQSHL */
9631 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9632 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9633 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9634 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9636 genenvfn
= fns
[size
][u
];
9639 case 0xa: /* SRSHL, URSHL */
9641 static NeonGenTwoOpFn
* const fns
[3][2] = {
9642 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9643 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9644 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9646 genfn
= fns
[size
][u
];
9649 case 0xb: /* SQRSHL, UQRSHL */
9651 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9652 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9653 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9654 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9656 genenvfn
= fns
[size
][u
];
9659 case 0xc: /* SMAX, UMAX */
9661 static NeonGenTwoOpFn
* const fns
[3][2] = {
9662 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9663 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9664 { gen_max_s32
, gen_max_u32
},
9666 genfn
= fns
[size
][u
];
9670 case 0xd: /* SMIN, UMIN */
9672 static NeonGenTwoOpFn
* const fns
[3][2] = {
9673 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9674 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9675 { gen_min_s32
, gen_min_u32
},
9677 genfn
= fns
[size
][u
];
9680 case 0xe: /* SABD, UABD */
9681 case 0xf: /* SABA, UABA */
9683 static NeonGenTwoOpFn
* const fns
[3][2] = {
9684 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9685 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9686 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9688 genfn
= fns
[size
][u
];
9691 case 0x11: /* CMTST, CMEQ */
9693 static NeonGenTwoOpFn
* const fns
[3][2] = {
9694 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9695 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9696 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9698 genfn
= fns
[size
][u
];
9701 case 0x13: /* MUL, PMUL */
9705 genfn
= gen_helper_neon_mul_p8
;
9708 /* fall through : MUL */
9709 case 0x12: /* MLA, MLS */
9711 static NeonGenTwoOpFn
* const fns
[3] = {
9712 gen_helper_neon_mul_u8
,
9713 gen_helper_neon_mul_u16
,
9719 case 0x16: /* SQDMULH, SQRDMULH */
9721 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9722 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9723 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9725 assert(size
== 1 || size
== 2);
9726 genenvfn
= fns
[size
- 1][u
];
9730 g_assert_not_reached();
9734 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9736 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9739 if (opcode
== 0xf || opcode
== 0x12) {
9740 /* SABA, UABA, MLA, MLS: accumulating ops */
9741 static NeonGenTwoOpFn
* const fns
[3][2] = {
9742 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9743 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9744 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9746 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9748 genfn
= fns
[size
][is_sub
];
9749 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9750 genfn(tcg_res
, tcg_op1
, tcg_res
);
9753 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9755 tcg_temp_free_i32(tcg_res
);
9756 tcg_temp_free_i32(tcg_op1
);
9757 tcg_temp_free_i32(tcg_op2
);
9762 clear_vec_high(s
, rd
);
9766 /* AdvSIMD three same
9767 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9768 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9769 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9770 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9772 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9774 int opcode
= extract32(insn
, 11, 5);
9777 case 0x3: /* logic ops */
9778 disas_simd_3same_logic(s
, insn
);
9780 case 0x17: /* ADDP */
9781 case 0x14: /* SMAXP, UMAXP */
9782 case 0x15: /* SMINP, UMINP */
9784 /* Pairwise operations */
9785 int is_q
= extract32(insn
, 30, 1);
9786 int u
= extract32(insn
, 29, 1);
9787 int size
= extract32(insn
, 22, 2);
9788 int rm
= extract32(insn
, 16, 5);
9789 int rn
= extract32(insn
, 5, 5);
9790 int rd
= extract32(insn
, 0, 5);
9791 if (opcode
== 0x17) {
9792 if (u
|| (size
== 3 && !is_q
)) {
9793 unallocated_encoding(s
);
9798 unallocated_encoding(s
);
9802 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9806 /* floating point ops, sz[1] and U are part of opcode */
9807 disas_simd_3same_float(s
, insn
);
9810 disas_simd_3same_int(s
, insn
);
9815 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9816 int size
, int rn
, int rd
)
9818 /* Handle 2-reg-misc ops which are widening (so each size element
9819 * in the source becomes a 2*size element in the destination.
9820 * The only instruction like this is FCVTL.
9825 /* 32 -> 64 bit fp conversion */
9826 TCGv_i64 tcg_res
[2];
9827 int srcelt
= is_q
? 2 : 0;
9829 for (pass
= 0; pass
< 2; pass
++) {
9830 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9831 tcg_res
[pass
] = tcg_temp_new_i64();
9833 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9834 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9835 tcg_temp_free_i32(tcg_op
);
9837 for (pass
= 0; pass
< 2; pass
++) {
9838 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9839 tcg_temp_free_i64(tcg_res
[pass
]);
9842 /* 16 -> 32 bit fp conversion */
9843 int srcelt
= is_q
? 4 : 0;
9844 TCGv_i32 tcg_res
[4];
9846 for (pass
= 0; pass
< 4; pass
++) {
9847 tcg_res
[pass
] = tcg_temp_new_i32();
9849 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9850 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9853 for (pass
= 0; pass
< 4; pass
++) {
9854 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9855 tcg_temp_free_i32(tcg_res
[pass
]);
9860 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9861 bool is_q
, int size
, int rn
, int rd
)
9863 int op
= (opcode
<< 1) | u
;
9864 int opsz
= op
+ size
;
9865 int grp_size
= 3 - opsz
;
9866 int dsize
= is_q
? 128 : 64;
9870 unallocated_encoding(s
);
9874 if (!fp_access_check(s
)) {
9879 /* Special case bytes, use bswap op on each group of elements */
9880 int groups
= dsize
/ (8 << grp_size
);
9882 for (i
= 0; i
< groups
; i
++) {
9883 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9885 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9888 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9891 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9894 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9897 g_assert_not_reached();
9899 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9900 tcg_temp_free_i64(tcg_tmp
);
9903 clear_vec_high(s
, rd
);
9906 int revmask
= (1 << grp_size
) - 1;
9907 int esize
= 8 << size
;
9908 int elements
= dsize
/ esize
;
9909 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9910 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9911 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9913 for (i
= 0; i
< elements
; i
++) {
9914 int e_rev
= (i
& 0xf) ^ revmask
;
9915 int off
= e_rev
* esize
;
9916 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9918 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9919 tcg_rn
, off
- 64, esize
);
9921 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9924 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9925 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9927 tcg_temp_free_i64(tcg_rd_hi
);
9928 tcg_temp_free_i64(tcg_rd
);
9929 tcg_temp_free_i64(tcg_rn
);
9933 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9934 bool is_q
, int size
, int rn
, int rd
)
9936 /* Implement the pairwise operations from 2-misc:
9937 * SADDLP, UADDLP, SADALP, UADALP.
9938 * These all add pairs of elements in the input to produce a
9939 * double-width result element in the output (possibly accumulating).
9941 bool accum
= (opcode
== 0x6);
9942 int maxpass
= is_q
? 2 : 1;
9944 TCGv_i64 tcg_res
[2];
9947 /* 32 + 32 -> 64 op */
9948 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9950 for (pass
= 0; pass
< maxpass
; pass
++) {
9951 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9952 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9954 tcg_res
[pass
] = tcg_temp_new_i64();
9956 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9957 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9958 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9960 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9961 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9964 tcg_temp_free_i64(tcg_op1
);
9965 tcg_temp_free_i64(tcg_op2
);
9968 for (pass
= 0; pass
< maxpass
; pass
++) {
9969 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9970 NeonGenOneOpFn
*genfn
;
9971 static NeonGenOneOpFn
* const fns
[2][2] = {
9972 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9973 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9976 genfn
= fns
[size
][u
];
9978 tcg_res
[pass
] = tcg_temp_new_i64();
9980 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9981 genfn(tcg_res
[pass
], tcg_op
);
9984 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9986 gen_helper_neon_addl_u16(tcg_res
[pass
],
9987 tcg_res
[pass
], tcg_op
);
9989 gen_helper_neon_addl_u32(tcg_res
[pass
],
9990 tcg_res
[pass
], tcg_op
);
9993 tcg_temp_free_i64(tcg_op
);
9997 tcg_res
[1] = tcg_const_i64(0);
9999 for (pass
= 0; pass
< 2; pass
++) {
10000 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10001 tcg_temp_free_i64(tcg_res
[pass
]);
10005 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
10007 /* Implement SHLL and SHLL2 */
10009 int part
= is_q
? 2 : 0;
10010 TCGv_i64 tcg_res
[2];
10012 for (pass
= 0; pass
< 2; pass
++) {
10013 static NeonGenWidenFn
* const widenfns
[3] = {
10014 gen_helper_neon_widen_u8
,
10015 gen_helper_neon_widen_u16
,
10016 tcg_gen_extu_i32_i64
,
10018 NeonGenWidenFn
*widenfn
= widenfns
[size
];
10019 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10021 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
10022 tcg_res
[pass
] = tcg_temp_new_i64();
10023 widenfn(tcg_res
[pass
], tcg_op
);
10024 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
10026 tcg_temp_free_i32(tcg_op
);
10029 for (pass
= 0; pass
< 2; pass
++) {
10030 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10031 tcg_temp_free_i64(tcg_res
[pass
]);
10035 /* AdvSIMD two reg misc
10036 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10037 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
10038 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10039 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
10041 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10043 int size
= extract32(insn
, 22, 2);
10044 int opcode
= extract32(insn
, 12, 5);
10045 bool u
= extract32(insn
, 29, 1);
10046 bool is_q
= extract32(insn
, 30, 1);
10047 int rn
= extract32(insn
, 5, 5);
10048 int rd
= extract32(insn
, 0, 5);
10049 bool need_fpstatus
= false;
10050 bool need_rmode
= false;
10052 TCGv_i32 tcg_rmode
;
10053 TCGv_ptr tcg_fpstatus
;
10056 case 0x0: /* REV64, REV32 */
10057 case 0x1: /* REV16 */
10058 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
10060 case 0x5: /* CNT, NOT, RBIT */
10061 if (u
&& size
== 0) {
10062 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
10065 } else if (u
&& size
== 1) {
10068 } else if (!u
&& size
== 0) {
10072 unallocated_encoding(s
);
10074 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
10075 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
10077 unallocated_encoding(s
);
10080 if (!fp_access_check(s
)) {
10084 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
10086 case 0x4: /* CLS, CLZ */
10088 unallocated_encoding(s
);
10092 case 0x2: /* SADDLP, UADDLP */
10093 case 0x6: /* SADALP, UADALP */
10095 unallocated_encoding(s
);
10098 if (!fp_access_check(s
)) {
10101 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
10103 case 0x13: /* SHLL, SHLL2 */
10104 if (u
== 0 || size
== 3) {
10105 unallocated_encoding(s
);
10108 if (!fp_access_check(s
)) {
10111 handle_shll(s
, is_q
, size
, rn
, rd
);
10113 case 0xa: /* CMLT */
10115 unallocated_encoding(s
);
10119 case 0x8: /* CMGT, CMGE */
10120 case 0x9: /* CMEQ, CMLE */
10121 case 0xb: /* ABS, NEG */
10122 if (size
== 3 && !is_q
) {
10123 unallocated_encoding(s
);
10127 case 0x3: /* SUQADD, USQADD */
10128 if (size
== 3 && !is_q
) {
10129 unallocated_encoding(s
);
10132 if (!fp_access_check(s
)) {
10135 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10137 case 0x7: /* SQABS, SQNEG */
10138 if (size
== 3 && !is_q
) {
10139 unallocated_encoding(s
);
10144 case 0x16 ... 0x1d:
10147 /* Floating point: U, size[1] and opcode indicate operation;
10148 * size[0] indicates single or double precision.
10150 int is_double
= extract32(size
, 0, 1);
10151 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10152 size
= is_double
? 3 : 2;
10154 case 0x2f: /* FABS */
10155 case 0x6f: /* FNEG */
10156 if (size
== 3 && !is_q
) {
10157 unallocated_encoding(s
);
10161 case 0x1d: /* SCVTF */
10162 case 0x5d: /* UCVTF */
10164 bool is_signed
= (opcode
== 0x1d) ? true : false;
10165 int elements
= is_double
? 2 : is_q
? 4 : 2;
10166 if (is_double
&& !is_q
) {
10167 unallocated_encoding(s
);
10170 if (!fp_access_check(s
)) {
10173 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10176 case 0x2c: /* FCMGT (zero) */
10177 case 0x2d: /* FCMEQ (zero) */
10178 case 0x2e: /* FCMLT (zero) */
10179 case 0x6c: /* FCMGE (zero) */
10180 case 0x6d: /* FCMLE (zero) */
10181 if (size
== 3 && !is_q
) {
10182 unallocated_encoding(s
);
10185 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10187 case 0x7f: /* FSQRT */
10188 if (size
== 3 && !is_q
) {
10189 unallocated_encoding(s
);
10193 case 0x1a: /* FCVTNS */
10194 case 0x1b: /* FCVTMS */
10195 case 0x3a: /* FCVTPS */
10196 case 0x3b: /* FCVTZS */
10197 case 0x5a: /* FCVTNU */
10198 case 0x5b: /* FCVTMU */
10199 case 0x7a: /* FCVTPU */
10200 case 0x7b: /* FCVTZU */
10201 need_fpstatus
= true;
10203 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10204 if (size
== 3 && !is_q
) {
10205 unallocated_encoding(s
);
10209 case 0x5c: /* FCVTAU */
10210 case 0x1c: /* FCVTAS */
10211 need_fpstatus
= true;
10213 rmode
= FPROUNDING_TIEAWAY
;
10214 if (size
== 3 && !is_q
) {
10215 unallocated_encoding(s
);
10219 case 0x3c: /* URECPE */
10221 unallocated_encoding(s
);
10225 case 0x3d: /* FRECPE */
10226 case 0x7d: /* FRSQRTE */
10227 if (size
== 3 && !is_q
) {
10228 unallocated_encoding(s
);
10231 if (!fp_access_check(s
)) {
10234 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10236 case 0x56: /* FCVTXN, FCVTXN2 */
10238 unallocated_encoding(s
);
10242 case 0x16: /* FCVTN, FCVTN2 */
10243 /* handle_2misc_narrow does a 2*size -> size operation, but these
10244 * instructions encode the source size rather than dest size.
10246 if (!fp_access_check(s
)) {
10249 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10251 case 0x17: /* FCVTL, FCVTL2 */
10252 if (!fp_access_check(s
)) {
10255 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10257 case 0x18: /* FRINTN */
10258 case 0x19: /* FRINTM */
10259 case 0x38: /* FRINTP */
10260 case 0x39: /* FRINTZ */
10262 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10264 case 0x59: /* FRINTX */
10265 case 0x79: /* FRINTI */
10266 need_fpstatus
= true;
10267 if (size
== 3 && !is_q
) {
10268 unallocated_encoding(s
);
10272 case 0x58: /* FRINTA */
10274 rmode
= FPROUNDING_TIEAWAY
;
10275 need_fpstatus
= true;
10276 if (size
== 3 && !is_q
) {
10277 unallocated_encoding(s
);
10281 case 0x7c: /* URSQRTE */
10283 unallocated_encoding(s
);
10286 need_fpstatus
= true;
10289 unallocated_encoding(s
);
10295 unallocated_encoding(s
);
10299 if (!fp_access_check(s
)) {
10303 if (need_fpstatus
) {
10304 tcg_fpstatus
= get_fpstatus_ptr();
10306 tcg_fpstatus
= NULL
;
10309 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10310 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10316 /* All 64-bit element operations can be shared with scalar 2misc */
10319 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10320 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10321 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10323 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10325 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10326 tcg_rmode
, tcg_fpstatus
);
10328 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10330 tcg_temp_free_i64(tcg_res
);
10331 tcg_temp_free_i64(tcg_op
);
10336 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10337 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10338 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10341 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10344 /* Special cases for 32 bit elements */
10346 case 0xa: /* CMLT */
10347 /* 32 bit integer comparison against zero, result is
10348 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10351 cond
= TCG_COND_LT
;
10353 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10354 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10356 case 0x8: /* CMGT, CMGE */
10357 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10359 case 0x9: /* CMEQ, CMLE */
10360 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10362 case 0x4: /* CLS */
10364 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10366 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10369 case 0x7: /* SQABS, SQNEG */
10371 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10373 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10376 case 0xb: /* ABS, NEG */
10378 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10380 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10381 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10382 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10383 tcg_zero
, tcg_op
, tcg_res
);
10384 tcg_temp_free_i32(tcg_zero
);
10387 case 0x2f: /* FABS */
10388 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10390 case 0x6f: /* FNEG */
10391 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10393 case 0x7f: /* FSQRT */
10394 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10396 case 0x1a: /* FCVTNS */
10397 case 0x1b: /* FCVTMS */
10398 case 0x1c: /* FCVTAS */
10399 case 0x3a: /* FCVTPS */
10400 case 0x3b: /* FCVTZS */
10402 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10403 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10404 tcg_shift
, tcg_fpstatus
);
10405 tcg_temp_free_i32(tcg_shift
);
10408 case 0x5a: /* FCVTNU */
10409 case 0x5b: /* FCVTMU */
10410 case 0x5c: /* FCVTAU */
10411 case 0x7a: /* FCVTPU */
10412 case 0x7b: /* FCVTZU */
10414 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10415 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10416 tcg_shift
, tcg_fpstatus
);
10417 tcg_temp_free_i32(tcg_shift
);
10420 case 0x18: /* FRINTN */
10421 case 0x19: /* FRINTM */
10422 case 0x38: /* FRINTP */
10423 case 0x39: /* FRINTZ */
10424 case 0x58: /* FRINTA */
10425 case 0x79: /* FRINTI */
10426 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10428 case 0x59: /* FRINTX */
10429 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10431 case 0x7c: /* URSQRTE */
10432 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10435 g_assert_not_reached();
10438 /* Use helpers for 8 and 16 bit elements */
10440 case 0x5: /* CNT, RBIT */
10441 /* For these two insns size is part of the opcode specifier
10442 * (handled earlier); they always operate on byte elements.
10445 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10447 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10450 case 0x7: /* SQABS, SQNEG */
10452 NeonGenOneOpEnvFn
*genfn
;
10453 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10454 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10455 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10457 genfn
= fns
[size
][u
];
10458 genfn(tcg_res
, cpu_env
, tcg_op
);
10461 case 0x8: /* CMGT, CMGE */
10462 case 0x9: /* CMEQ, CMLE */
10463 case 0xa: /* CMLT */
10465 static NeonGenTwoOpFn
* const fns
[3][2] = {
10466 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10467 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10468 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10470 NeonGenTwoOpFn
*genfn
;
10473 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10475 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10476 comp
= (opcode
- 0x8) * 2 + u
;
10477 /* ...but LE, LT are implemented as reverse GE, GT */
10478 reverse
= (comp
> 2);
10482 genfn
= fns
[comp
][size
];
10484 genfn(tcg_res
, tcg_zero
, tcg_op
);
10486 genfn(tcg_res
, tcg_op
, tcg_zero
);
10488 tcg_temp_free_i32(tcg_zero
);
10491 case 0xb: /* ABS, NEG */
10493 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10495 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10497 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10499 tcg_temp_free_i32(tcg_zero
);
10502 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10504 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10508 case 0x4: /* CLS, CLZ */
10511 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10513 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10517 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10519 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10524 g_assert_not_reached();
10528 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10530 tcg_temp_free_i32(tcg_res
);
10531 tcg_temp_free_i32(tcg_op
);
10535 clear_vec_high(s
, rd
);
10539 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10540 tcg_temp_free_i32(tcg_rmode
);
10542 if (need_fpstatus
) {
10543 tcg_temp_free_ptr(tcg_fpstatus
);
10547 /* AdvSIMD scalar x indexed element
10548 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10549 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10550 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10551 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10552 * AdvSIMD vector x indexed element
10553 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10554 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10555 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10556 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10558 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10560 /* This encoding has two kinds of instruction:
10561 * normal, where we perform elt x idxelt => elt for each
10562 * element in the vector
10563 * long, where we perform elt x idxelt and generate a result of
10564 * double the width of the input element
10565 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10567 bool is_scalar
= extract32(insn
, 28, 1);
10568 bool is_q
= extract32(insn
, 30, 1);
10569 bool u
= extract32(insn
, 29, 1);
10570 int size
= extract32(insn
, 22, 2);
10571 int l
= extract32(insn
, 21, 1);
10572 int m
= extract32(insn
, 20, 1);
10573 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10574 int rm
= extract32(insn
, 16, 4);
10575 int opcode
= extract32(insn
, 12, 4);
10576 int h
= extract32(insn
, 11, 1);
10577 int rn
= extract32(insn
, 5, 5);
10578 int rd
= extract32(insn
, 0, 5);
10579 bool is_long
= false;
10580 bool is_fp
= false;
10585 case 0x0: /* MLA */
10586 case 0x4: /* MLS */
10587 if (!u
|| is_scalar
) {
10588 unallocated_encoding(s
);
10592 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10593 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10594 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10596 unallocated_encoding(s
);
10601 case 0x3: /* SQDMLAL, SQDMLAL2 */
10602 case 0x7: /* SQDMLSL, SQDMLSL2 */
10603 case 0xb: /* SQDMULL, SQDMULL2 */
10606 case 0xc: /* SQDMULH */
10607 case 0xd: /* SQRDMULH */
10609 unallocated_encoding(s
);
10613 case 0x8: /* MUL */
10614 if (u
|| is_scalar
) {
10615 unallocated_encoding(s
);
10619 case 0x1: /* FMLA */
10620 case 0x5: /* FMLS */
10622 unallocated_encoding(s
);
10626 case 0x9: /* FMUL, FMULX */
10627 if (!extract32(size
, 1, 1)) {
10628 unallocated_encoding(s
);
10634 unallocated_encoding(s
);
10639 /* low bit of size indicates single/double */
10640 size
= extract32(size
, 0, 1) ? 3 : 2;
10642 index
= h
<< 1 | l
;
10645 unallocated_encoding(s
);
10654 index
= h
<< 2 | l
<< 1 | m
;
10657 index
= h
<< 1 | l
;
10661 unallocated_encoding(s
);
10666 if (!fp_access_check(s
)) {
10671 fpst
= get_fpstatus_ptr();
10677 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10680 assert(is_fp
&& is_q
&& !is_long
);
10682 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10684 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10685 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10686 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10688 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10691 case 0x5: /* FMLS */
10692 /* As usual for ARM, separate negation for fused multiply-add */
10693 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10695 case 0x1: /* FMLA */
10696 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10697 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10699 case 0x9: /* FMUL, FMULX */
10701 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10703 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10707 g_assert_not_reached();
10710 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10711 tcg_temp_free_i64(tcg_op
);
10712 tcg_temp_free_i64(tcg_res
);
10716 clear_vec_high(s
, rd
);
10719 tcg_temp_free_i64(tcg_idx
);
10720 } else if (!is_long
) {
10721 /* 32 bit floating point, or 16 or 32 bit integer.
10722 * For the 16 bit scalar case we use the usual Neon helpers and
10723 * rely on the fact that 0 op 0 == 0 with no side effects.
10725 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10726 int pass
, maxpasses
;
10731 maxpasses
= is_q
? 4 : 2;
10734 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10736 if (size
== 1 && !is_scalar
) {
10737 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10738 * the index into both halves of the 32 bit tcg_idx and then use
10739 * the usual Neon helpers.
10741 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10744 for (pass
= 0; pass
< maxpasses
; pass
++) {
10745 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10746 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10748 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10751 case 0x0: /* MLA */
10752 case 0x4: /* MLS */
10753 case 0x8: /* MUL */
10755 static NeonGenTwoOpFn
* const fns
[2][2] = {
10756 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10757 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10759 NeonGenTwoOpFn
*genfn
;
10760 bool is_sub
= opcode
== 0x4;
10763 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10765 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10767 if (opcode
== 0x8) {
10770 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10771 genfn
= fns
[size
- 1][is_sub
];
10772 genfn(tcg_res
, tcg_op
, tcg_res
);
10775 case 0x5: /* FMLS */
10776 /* As usual for ARM, separate negation for fused multiply-add */
10777 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10779 case 0x1: /* FMLA */
10780 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10781 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10783 case 0x9: /* FMUL, FMULX */
10785 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10787 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10790 case 0xc: /* SQDMULH */
10792 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10795 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10799 case 0xd: /* SQRDMULH */
10801 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10804 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10809 g_assert_not_reached();
10813 write_fp_sreg(s
, rd
, tcg_res
);
10815 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10818 tcg_temp_free_i32(tcg_op
);
10819 tcg_temp_free_i32(tcg_res
);
10822 tcg_temp_free_i32(tcg_idx
);
10825 clear_vec_high(s
, rd
);
10828 /* long ops: 16x16->32 or 32x32->64 */
10829 TCGv_i64 tcg_res
[2];
10831 bool satop
= extract32(opcode
, 0, 1);
10832 TCGMemOp memop
= MO_32
;
10839 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10841 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10843 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10844 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10845 TCGv_i64 tcg_passres
;
10851 passelt
= pass
+ (is_q
* 2);
10854 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10856 tcg_res
[pass
] = tcg_temp_new_i64();
10858 if (opcode
== 0xa || opcode
== 0xb) {
10859 /* Non-accumulating ops */
10860 tcg_passres
= tcg_res
[pass
];
10862 tcg_passres
= tcg_temp_new_i64();
10865 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10866 tcg_temp_free_i64(tcg_op
);
10869 /* saturating, doubling */
10870 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10871 tcg_passres
, tcg_passres
);
10874 if (opcode
== 0xa || opcode
== 0xb) {
10878 /* Accumulating op: handle accumulate step */
10879 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10882 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10883 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10885 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10886 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10888 case 0x7: /* SQDMLSL, SQDMLSL2 */
10889 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10891 case 0x3: /* SQDMLAL, SQDMLAL2 */
10892 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10897 g_assert_not_reached();
10899 tcg_temp_free_i64(tcg_passres
);
10901 tcg_temp_free_i64(tcg_idx
);
10904 clear_vec_high(s
, rd
);
10907 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10910 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10913 /* The simplest way to handle the 16x16 indexed ops is to
10914 * duplicate the index into both halves of the 32 bit tcg_idx
10915 * and then use the usual Neon helpers.
10917 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10920 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10921 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10922 TCGv_i64 tcg_passres
;
10925 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10927 read_vec_element_i32(s
, tcg_op
, rn
,
10928 pass
+ (is_q
* 2), MO_32
);
10931 tcg_res
[pass
] = tcg_temp_new_i64();
10933 if (opcode
== 0xa || opcode
== 0xb) {
10934 /* Non-accumulating ops */
10935 tcg_passres
= tcg_res
[pass
];
10937 tcg_passres
= tcg_temp_new_i64();
10940 if (memop
& MO_SIGN
) {
10941 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10943 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10946 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10947 tcg_passres
, tcg_passres
);
10949 tcg_temp_free_i32(tcg_op
);
10951 if (opcode
== 0xa || opcode
== 0xb) {
10955 /* Accumulating op: handle accumulate step */
10956 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10959 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10960 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10963 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10964 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10967 case 0x7: /* SQDMLSL, SQDMLSL2 */
10968 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10970 case 0x3: /* SQDMLAL, SQDMLAL2 */
10971 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10976 g_assert_not_reached();
10978 tcg_temp_free_i64(tcg_passres
);
10980 tcg_temp_free_i32(tcg_idx
);
10983 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10988 tcg_res
[1] = tcg_const_i64(0);
10991 for (pass
= 0; pass
< 2; pass
++) {
10992 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10993 tcg_temp_free_i64(tcg_res
[pass
]);
10998 tcg_temp_free_ptr(fpst
);
11003 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11004 * +-----------------+------+-----------+--------+-----+------+------+
11005 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11006 * +-----------------+------+-----------+--------+-----+------+------+
11008 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
11010 int size
= extract32(insn
, 22, 2);
11011 int opcode
= extract32(insn
, 12, 5);
11012 int rn
= extract32(insn
, 5, 5);
11013 int rd
= extract32(insn
, 0, 5);
11015 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
11016 TCGv_i32 tcg_decrypt
;
11017 CryptoThreeOpIntFn
*genfn
;
11019 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
11021 unallocated_encoding(s
);
11026 case 0x4: /* AESE */
11028 genfn
= gen_helper_crypto_aese
;
11030 case 0x6: /* AESMC */
11032 genfn
= gen_helper_crypto_aesmc
;
11034 case 0x5: /* AESD */
11036 genfn
= gen_helper_crypto_aese
;
11038 case 0x7: /* AESIMC */
11040 genfn
= gen_helper_crypto_aesmc
;
11043 unallocated_encoding(s
);
11047 if (!fp_access_check(s
)) {
11051 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
11052 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
11053 tcg_decrypt
= tcg_const_i32(decrypt
);
11055 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
11057 tcg_temp_free_ptr(tcg_rd_ptr
);
11058 tcg_temp_free_ptr(tcg_rn_ptr
);
11059 tcg_temp_free_i32(tcg_decrypt
);
11062 /* Crypto three-reg SHA
11063 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
11064 * +-----------------+------+---+------+---+--------+-----+------+------+
11065 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
11066 * +-----------------+------+---+------+---+--------+-----+------+------+
11068 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
11070 int size
= extract32(insn
, 22, 2);
11071 int opcode
= extract32(insn
, 12, 3);
11072 int rm
= extract32(insn
, 16, 5);
11073 int rn
= extract32(insn
, 5, 5);
11074 int rd
= extract32(insn
, 0, 5);
11075 CryptoThreeOpFn
*genfn
;
11076 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
11077 int feature
= ARM_FEATURE_V8_SHA256
;
11080 unallocated_encoding(s
);
11085 case 0: /* SHA1C */
11086 case 1: /* SHA1P */
11087 case 2: /* SHA1M */
11088 case 3: /* SHA1SU0 */
11090 feature
= ARM_FEATURE_V8_SHA1
;
11092 case 4: /* SHA256H */
11093 genfn
= gen_helper_crypto_sha256h
;
11095 case 5: /* SHA256H2 */
11096 genfn
= gen_helper_crypto_sha256h2
;
11098 case 6: /* SHA256SU1 */
11099 genfn
= gen_helper_crypto_sha256su1
;
11102 unallocated_encoding(s
);
11106 if (!arm_dc_feature(s
, feature
)) {
11107 unallocated_encoding(s
);
11111 if (!fp_access_check(s
)) {
11115 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
11116 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
11117 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
11120 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
11122 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11124 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
11125 tcg_rm_ptr
, tcg_opcode
);
11126 tcg_temp_free_i32(tcg_opcode
);
11129 tcg_temp_free_ptr(tcg_rd_ptr
);
11130 tcg_temp_free_ptr(tcg_rn_ptr
);
11131 tcg_temp_free_ptr(tcg_rm_ptr
);
11134 /* Crypto two-reg SHA
11135 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11136 * +-----------------+------+-----------+--------+-----+------+------+
11137 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11138 * +-----------------+------+-----------+--------+-----+------+------+
11140 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11142 int size
= extract32(insn
, 22, 2);
11143 int opcode
= extract32(insn
, 12, 5);
11144 int rn
= extract32(insn
, 5, 5);
11145 int rd
= extract32(insn
, 0, 5);
11146 CryptoTwoOpFn
*genfn
;
11148 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
11151 unallocated_encoding(s
);
11156 case 0: /* SHA1H */
11157 feature
= ARM_FEATURE_V8_SHA1
;
11158 genfn
= gen_helper_crypto_sha1h
;
11160 case 1: /* SHA1SU1 */
11161 feature
= ARM_FEATURE_V8_SHA1
;
11162 genfn
= gen_helper_crypto_sha1su1
;
11164 case 2: /* SHA256SU0 */
11165 feature
= ARM_FEATURE_V8_SHA256
;
11166 genfn
= gen_helper_crypto_sha256su0
;
11169 unallocated_encoding(s
);
11173 if (!arm_dc_feature(s
, feature
)) {
11174 unallocated_encoding(s
);
11178 if (!fp_access_check(s
)) {
11182 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
11183 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
11185 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
11187 tcg_temp_free_ptr(tcg_rd_ptr
);
11188 tcg_temp_free_ptr(tcg_rn_ptr
);
11191 /* C3.6 Data processing - SIMD, inc Crypto
11193 * As the decode gets a little complex we are using a table based
11194 * approach for this part of the decode.
11196 static const AArch64DecodeTable data_proc_simd
[] = {
11197 /* pattern , mask , fn */
11198 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11199 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11200 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11201 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11202 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11203 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11204 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11205 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11206 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11207 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11208 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11209 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11210 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11211 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11212 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11213 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11214 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11215 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11216 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11217 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11218 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11219 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11220 { 0x00000000, 0x00000000, NULL
}
11223 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11225 /* Note that this is called with all non-FP cases from
11226 * table C3-6 so it must UNDEF for entries not specifically
11227 * allocated to instructions in that table.
11229 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11233 unallocated_encoding(s
);
11237 /* C3.6 Data processing - SIMD and floating point */
11238 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11240 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11241 disas_data_proc_fp(s
, insn
);
11243 /* SIMD, including crypto */
11244 disas_data_proc_simd(s
, insn
);
11248 /* C3.1 A64 instruction index by encoding */
11249 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11253 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11257 s
->fp_access_checked
= false;
11259 switch (extract32(insn
, 25, 4)) {
11260 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11261 unallocated_encoding(s
);
11263 case 0x8: case 0x9: /* Data processing - immediate */
11264 disas_data_proc_imm(s
, insn
);
11266 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11267 disas_b_exc_sys(s
, insn
);
11272 case 0xe: /* Loads and stores */
11273 disas_ldst(s
, insn
);
11276 case 0xd: /* Data processing - register */
11277 disas_data_proc_reg(s
, insn
);
11280 case 0xf: /* Data processing - SIMD and floating point */
11281 disas_data_proc_simd_fp(s
, insn
);
11284 assert(FALSE
); /* all 15 cases should be handled above */
11288 /* if we allocated any temporaries, free them here */
11292 static int aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
11293 CPUState
*cpu
, int max_insns
)
11295 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11296 CPUARMState
*env
= cpu
->env_ptr
;
11297 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
11300 dc
->pc
= dc
->base
.pc_first
;
11304 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11305 * there is no secure EL1, so we route exceptions to EL3.
11307 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11308 !arm_el_is_aa64(env
, 3);
11311 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
11312 dc
->condexec_mask
= 0;
11313 dc
->condexec_cond
= 0;
11314 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
11315 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
11316 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
11317 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11318 #if !defined(CONFIG_USER_ONLY)
11319 dc
->user
= (dc
->current_el
== 0);
11321 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
11323 dc
->vec_stride
= 0;
11324 dc
->cp_regs
= arm_cpu
->cp_regs
;
11325 dc
->features
= env
->features
;
11327 /* Single step state. The code-generation logic here is:
11329 * generate code with no special handling for single-stepping (except
11330 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11331 * this happens anyway because those changes are all system register or
11333 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11334 * emit code for one insn
11335 * emit code to clear PSTATE.SS
11336 * emit code to generate software step exception for completed step
11337 * end TB (as usual for having generated an exception)
11338 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11339 * emit code to generate a software step exception
11342 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
11343 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
11344 dc
->is_ldex
= false;
11345 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11347 /* Bound the number of insns to execute to those left on the page. */
11348 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
11350 /* If architectural single step active, limit to 1. */
11351 if (dc
->ss_active
) {
11354 max_insns
= MIN(max_insns
, bound
);
11356 init_tmp_a64_array(dc
);
11361 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
11363 tcg_clear_temp_count();
11366 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
11368 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11370 tcg_gen_insn_start(dc
->pc
, 0, 0);
11371 dc
->insn_start
= tcg_last_op();
11374 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
11375 const CPUBreakpoint
*bp
)
11377 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11379 if (bp
->flags
& BP_CPU
) {
11380 gen_a64_set_pc_im(dc
->pc
);
11381 gen_helper_check_breakpoints(cpu_env
);
11382 /* End the TB early; it likely won't be executed */
11383 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
11385 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11386 /* The address covered by the breakpoint must be
11387 included in [tb->pc, tb->pc + tb->size) in order
11388 to for it to be properly cleared -- thus we
11389 increment the PC here so that the logic setting
11390 tb->size below does the right thing. */
11392 dc
->base
.is_jmp
= DISAS_NORETURN
;
11398 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
11400 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11401 CPUARMState
*env
= cpu
->env_ptr
;
11403 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11404 /* Singlestep state is Active-pending.
11405 * If we're in this state at the start of a TB then either
11406 * a) we just took an exception to an EL which is being debugged
11407 * and this is the first insn in the exception handler
11408 * b) debug exceptions were masked and we just unmasked them
11409 * without changing EL (eg by clearing PSTATE.D)
11410 * In either case we're going to take a swstep exception in the
11411 * "did not step an insn" case, and so the syndrome ISV and EX
11412 * bits should be zero.
11414 assert(dc
->base
.num_insns
== 1);
11415 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11416 default_exception_el(dc
));
11417 dc
->base
.is_jmp
= DISAS_NORETURN
;
11419 disas_a64_insn(env
, dc
);
11422 dc
->base
.pc_next
= dc
->pc
;
11423 translator_loop_temp_check(&dc
->base
);
11426 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
11428 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11430 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
11431 /* Note that this means single stepping WFI doesn't halt the CPU.
11432 * For conditional branch insns this is harmless unreachable code as
11433 * gen_goto_tb() has already handled emitting the debug exception
11434 * (and thus a tb-jump is not possible when singlestepping).
11436 switch (dc
->base
.is_jmp
) {
11438 gen_a64_set_pc_im(dc
->pc
);
11442 if (dc
->base
.singlestep_enabled
) {
11443 gen_exception_internal(EXCP_DEBUG
);
11445 gen_step_complete_exception(dc
);
11448 case DISAS_NORETURN
:
11452 switch (dc
->base
.is_jmp
) {
11454 case DISAS_TOO_MANY
:
11455 gen_goto_tb(dc
, 1, dc
->pc
);
11459 gen_a64_set_pc_im(dc
->pc
);
11462 tcg_gen_lookup_and_goto_ptr();
11465 tcg_gen_exit_tb(0);
11467 case DISAS_NORETURN
:
11471 gen_a64_set_pc_im(dc
->pc
);
11472 gen_helper_wfe(cpu_env
);
11475 gen_a64_set_pc_im(dc
->pc
);
11476 gen_helper_yield(cpu_env
);
11480 /* This is a special case because we don't want to just halt the CPU
11481 * if trying to debug across a WFI.
11483 TCGv_i32 tmp
= tcg_const_i32(4);
11485 gen_a64_set_pc_im(dc
->pc
);
11486 gen_helper_wfi(cpu_env
, tmp
);
11487 tcg_temp_free_i32(tmp
);
11488 /* The helper doesn't necessarily throw an exception, but we
11489 * must go back to the main loop to check for interrupts anyway.
11491 tcg_gen_exit_tb(0);
11497 /* Functions above can change dc->pc, so re-align db->pc_next */
11498 dc
->base
.pc_next
= dc
->pc
;
11501 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
11504 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11506 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
11507 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
11510 const TranslatorOps aarch64_translator_ops
= {
11511 .init_disas_context
= aarch64_tr_init_disas_context
,
11512 .tb_start
= aarch64_tr_tb_start
,
11513 .insn_start
= aarch64_tr_insn_start
,
11514 .breakpoint_check
= aarch64_tr_breakpoint_check
,
11515 .translate_insn
= aarch64_tr_translate_insn
,
11516 .tb_stop
= aarch64_tr_tb_stop
,
11517 .disas_log
= aarch64_tr_disas_log
,