target/riscv/fpu_helper.c

   1 /*
   2  * RISC-V FPU Emulation Helpers for QEMU.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/helper-proto.h"
  24 #include "fpu/softfloat.h"
  25 #include "internals.h"
  26
  27 target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
  28 {
  29     int soft = get_float_exception_flags(&env->fp_status);
  30     target_ulong hard = 0;
  31
  32     hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0;
  33     hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0;
  34     hard |= (soft & float_flag_overflow) ? FPEXC_OF : 0;
  35     hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0;
  36     hard |= (soft & float_flag_invalid) ? FPEXC_NV : 0;
  37
  38     return hard;
  39 }
  40
  41 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
  42 {
  43     int soft = 0;
  44
  45     soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0;
  46     soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0;
  47     soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0;
  48     soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0;
  49     soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0;
  50
  51     set_float_exception_flags(soft, &env->fp_status);
  52 }
  53
  54 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
  55 {
  56     int softrm;
  57
  58     if (rm == 7) {
  59         rm = env->frm;
  60     }
  61     switch (rm) {
  62     case 0:
  63         softrm = float_round_nearest_even;
  64         break;
  65     case 1:
  66         softrm = float_round_to_zero;
  67         break;
  68     case 2:
  69         softrm = float_round_down;
  70         break;
  71     case 3:
  72         softrm = float_round_up;
  73         break;
  74     case 4:
  75         softrm = float_round_ties_away;
  76         break;
  77     default:
  78         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
  79     }
  80
  81     set_float_rounding_mode(softrm, &env->fp_status);
  82 }
  83
  84 uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
  85                         uint64_t frs3)
  86 {
  87     return float32_muladd(frs1, frs2, frs3, 0, &env->fp_status);
  88 }
  89
  90 uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
  91                         uint64_t frs3)
  92 {
  93     return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status);
  94 }
  95
  96 uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
  97                         uint64_t frs3)
  98 {
  99     return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c,
 100                           &env->fp_status);
 101 }
 102
 103 uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
 104                         uint64_t frs3)
 105 {
 106     return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c,
 107                           &env->fp_status);
 108 }
 109
 110 uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
 111                          uint64_t frs3)
 112 {
 113     return float32_muladd(frs1, frs2, frs3, float_muladd_negate_product,
 114                           &env->fp_status);
 115 }
 116
 117 uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
 118                          uint64_t frs3)
 119 {
 120     return float64_muladd(frs1, frs2, frs3, float_muladd_negate_product,
 121                           &env->fp_status);
 122 }
 123
 124 uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
 125                          uint64_t frs3)
 126 {
 127     return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c |
 128                           float_muladd_negate_product, &env->fp_status);
 129 }
 130
 131 uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
 132                          uint64_t frs3)
 133 {
 134     return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c |
 135                           float_muladd_negate_product, &env->fp_status);
 136 }
 137
 138 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 139 {
 140     return float32_add(frs1, frs2, &env->fp_status);
 141 }
 142
 143 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 144 {
 145     return float32_sub(frs1, frs2, &env->fp_status);
 146 }
 147
 148 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 149 {
 150     return float32_mul(frs1, frs2, &env->fp_status);
 151 }
 152
 153 uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 154 {
 155     return float32_div(frs1, frs2, &env->fp_status);
 156 }
 157
 158 uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 159 {
 160     return float32_minnum(frs1, frs2, &env->fp_status);
 161 }
 162
 163 uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 164 {
 165     return float32_maxnum(frs1, frs2, &env->fp_status);
 166 }
 167
 168 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1)
 169 {
 170     return float32_sqrt(frs1, &env->fp_status);
 171 }
 172
 173 target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 174 {
 175     return float32_le(frs1, frs2, &env->fp_status);
 176 }
 177
 178 target_ulong helper_flt_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 179 {
 180     return float32_lt(frs1, frs2, &env->fp_status);
 181 }
 182
 183 target_ulong helper_feq_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 184 {
 185     return float32_eq_quiet(frs1, frs2, &env->fp_status);
 186 }
 187
 188 target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t frs1)
 189 {
 190     return float32_to_int32(frs1, &env->fp_status);
 191 }
 192
 193 target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t frs1)
 194 {
 195     return (int32_t)float32_to_uint32(frs1, &env->fp_status);
 196 }
 197
 198 #if defined(TARGET_RISCV64)
 199 uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t frs1)
 200 {
 201     return float32_to_int64(frs1, &env->fp_status);
 202 }
 203
 204 uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1)
 205 {
 206     return float32_to_uint64(frs1, &env->fp_status);
 207 }
 208 #endif
 209
 210 uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
 211 {
 212     return int32_to_float32((int32_t)rs1, &env->fp_status);
 213 }
 214
 215 uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
 216 {
 217     return uint32_to_float32((uint32_t)rs1, &env->fp_status);
 218 }
 219
 220 #if defined(TARGET_RISCV64)
 221 uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
 222 {
 223     return int64_to_float32(rs1, &env->fp_status);
 224 }
 225
 226 uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
 227 {
 228     return uint64_to_float32(rs1, &env->fp_status);
 229 }
 230 #endif
 231
 232 target_ulong helper_fclass_s(uint64_t frs1)
 233 {
 234     return fclass_s(frs1);
 235 }
 236
 237 uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 238 {
 239     return float64_add(frs1, frs2, &env->fp_status);
 240 }
 241
 242 uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 243 {
 244     return float64_sub(frs1, frs2, &env->fp_status);
 245 }
 246
 247 uint64_t helper_fmul_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 248 {
 249     return float64_mul(frs1, frs2, &env->fp_status);
 250 }
 251
 252 uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 253 {
 254     return float64_div(frs1, frs2, &env->fp_status);
 255 }
 256
 257 uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 258 {
 259     return float64_minnum(frs1, frs2, &env->fp_status);
 260 }
 261
 262 uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 263 {
 264     return float64_maxnum(frs1, frs2, &env->fp_status);
 265 }
 266
 267 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
 268 {
 269     return float64_to_float32(rs1, &env->fp_status);
 270 }
 271
 272 uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1)
 273 {
 274     return float32_to_float64(rs1, &env->fp_status);
 275 }
 276
 277 uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1)
 278 {
 279     return float64_sqrt(frs1, &env->fp_status);
 280 }
 281
 282 target_ulong helper_fle_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 283 {
 284     return float64_le(frs1, frs2, &env->fp_status);
 285 }
 286
 287 target_ulong helper_flt_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 288 {
 289     return float64_lt(frs1, frs2, &env->fp_status);
 290 }
 291
 292 target_ulong helper_feq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 293 {
 294     return float64_eq_quiet(frs1, frs2, &env->fp_status);
 295 }
 296
 297 target_ulong helper_fcvt_w_d(CPURISCVState *env, uint64_t frs1)
 298 {
 299     return float64_to_int32(frs1, &env->fp_status);
 300 }
 301
 302 target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
 303 {
 304     return (int32_t)float64_to_uint32(frs1, &env->fp_status);
 305 }
 306
 307 #if defined(TARGET_RISCV64)
 308 uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
 309 {
 310     return float64_to_int64(frs1, &env->fp_status);
 311 }
 312
 313 uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
 314 {
 315     return float64_to_uint64(frs1, &env->fp_status);
 316 }
 317 #endif
 318
 319 uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1)
 320 {
 321     return int32_to_float64((int32_t)rs1, &env->fp_status);
 322 }
 323
 324 uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
 325 {
 326     return uint32_to_float64((uint32_t)rs1, &env->fp_status);
 327 }
 328
 329 #if defined(TARGET_RISCV64)
 330 uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
 331 {
 332     return int64_to_float64(rs1, &env->fp_status);
 333 }
 334
 335 uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
 336 {
 337     return uint64_to_float64(rs1, &env->fp_status);
 338 }
 339 #endif
 340
 341 target_ulong helper_fclass_d(uint64_t frs1)
 342 {
 343     return fclass_d(frs1);
 344 }