hw/arm/iotkit: Wire up MPC interrupt lines
[qemu/ar7.git] / tests / pnv-xscom-test.c
blobefb7c838b5c06ac4a28f9530e0c30872aa171f3b
1 /*
2 * QTest testcase for PowerNV XSCOM bus
4 * Copyright (c) 2016, IBM Corporation.
6 * This work is licensed under the terms of the GNU GPL, version 2 or
7 * later. See the COPYING file in the top-level directory.
8 */
9 #include "qemu/osdep.h"
11 #include "libqtest.h"
13 typedef enum PnvChipType {
14 PNV_CHIP_POWER8E, /* AKA Murano (default) */
15 PNV_CHIP_POWER8, /* AKA Venice */
16 PNV_CHIP_POWER8NVL, /* AKA Naples */
17 PNV_CHIP_POWER9, /* AKA Nimbus */
18 } PnvChipType;
20 typedef struct PnvChip {
21 PnvChipType chip_type;
22 const char *cpu_model;
23 uint64_t xscom_base;
24 uint64_t cfam_id;
25 uint32_t first_core;
26 } PnvChip;
28 static const PnvChip pnv_chips[] = {
30 .chip_type = PNV_CHIP_POWER8,
31 .cpu_model = "POWER8",
32 .xscom_base = 0x0003fc0000000000ull,
33 .cfam_id = 0x220ea04980000000ull,
34 .first_core = 0x1,
35 }, {
36 .chip_type = PNV_CHIP_POWER8NVL,
37 .cpu_model = "POWER8NVL",
38 .xscom_base = 0x0003fc0000000000ull,
39 .cfam_id = 0x120d304980000000ull,
40 .first_core = 0x1,
42 #if 0 /* POWER9 support is not ready yet */
44 .chip_type = PNV_CHIP_POWER9,
45 .cpu_model = "POWER9",
46 .xscom_base = 0x000603fc00000000ull,
47 .cfam_id = 0x220d104900008000ull,
48 .first_core = 0x0,
50 #endif
53 static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
55 uint64_t addr = chip->xscom_base;
57 if (chip->chip_type == PNV_CHIP_POWER9) {
58 addr |= ((uint64_t) pcba << 3);
59 } else {
60 addr |= (((uint64_t) pcba << 4) & ~0xffull) |
61 (((uint64_t) pcba << 3) & 0x78);
63 return addr;
66 static uint64_t pnv_xscom_read(const PnvChip *chip, uint32_t pcba)
68 return readq(pnv_xscom_addr(chip, pcba));
71 static void test_xscom_cfam_id(const PnvChip *chip)
73 uint64_t f000f = pnv_xscom_read(chip, 0xf000f);
75 g_assert_cmphex(f000f, ==, chip->cfam_id);
78 static void test_cfam_id(const void *data)
80 const PnvChip *chip = data;
82 global_qtest = qtest_startf("-M powernv,accel=tcg -cpu %s",
83 chip->cpu_model);
84 test_xscom_cfam_id(chip);
85 qtest_quit(global_qtest);
89 #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
90 #define PNV_XSCOM_EX_BASE(core) \
91 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
92 #define PNV_XSCOM_P9_EC_BASE(core) \
93 ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
95 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
97 static void test_xscom_core(const PnvChip *chip)
99 uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
100 uint64_t dts0;
102 if (chip->chip_type != PNV_CHIP_POWER9) {
103 first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
104 } else {
105 first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
108 dts0 = pnv_xscom_read(chip, first_core_dts0);
110 g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
113 static void test_core(const void *data)
115 const PnvChip *chip = data;
117 global_qtest = qtest_startf("-M powernv,accel=tcg -cpu %s",
118 chip->cpu_model);
119 test_xscom_core(chip);
120 qtest_quit(global_qtest);
123 static void add_test(const char *name, void (*test)(const void *data))
125 int i;
127 for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
128 char *tname = g_strdup_printf("pnv-xscom/%s/%s", name,
129 pnv_chips[i].cpu_model);
130 qtest_add_data_func(tname, &pnv_chips[i], test);
131 g_free(tname);
135 int main(int argc, char **argv)
137 g_test_init(&argc, &argv, NULL);
139 add_test("cfam_id", test_cfam_id);
140 add_test("core", test_core);
141 return g_test_run();