2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011, 2016 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 /* Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
23 * Without assertions, the interpreter runs much faster. */
24 #if defined(CONFIG_DEBUG_TCG)
25 # define tci_assert(cond) assert(cond)
27 # define tci_assert(cond) ((void)0)
30 #include "qemu-common.h"
31 #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
32 #include "exec/cpu_ldst.h"
33 #include "tcg/tcg-op.h"
34 #include "qemu/compiler.h"
36 #if MAX_OPC_PARAM_IARGS != 6
37 # error Fix needed, number of supported input arguments changed!
39 #if TCG_TARGET_REG_BITS == 32
40 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
41 tcg_target_ulong
, tcg_target_ulong
,
42 tcg_target_ulong
, tcg_target_ulong
,
43 tcg_target_ulong
, tcg_target_ulong
,
44 tcg_target_ulong
, tcg_target_ulong
,
45 tcg_target_ulong
, tcg_target_ulong
);
47 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
48 tcg_target_ulong
, tcg_target_ulong
,
49 tcg_target_ulong
, tcg_target_ulong
);
52 __thread
uintptr_t tci_tb_ptr
;
54 static tcg_target_ulong
tci_read_reg(const tcg_target_ulong
*regs
, TCGReg index
)
56 tci_assert(index
< TCG_TARGET_NB_REGS
);
60 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
61 static int8_t tci_read_reg8s(const tcg_target_ulong
*regs
, TCGReg index
)
63 return (int8_t)tci_read_reg(regs
, index
);
67 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
68 static int16_t tci_read_reg16s(const tcg_target_ulong
*regs
, TCGReg index
)
70 return (int16_t)tci_read_reg(regs
, index
);
74 #if TCG_TARGET_REG_BITS == 64
75 static int32_t tci_read_reg32s(const tcg_target_ulong
*regs
, TCGReg index
)
77 return (int32_t)tci_read_reg(regs
, index
);
81 static uint8_t tci_read_reg8(const tcg_target_ulong
*regs
, TCGReg index
)
83 return (uint8_t)tci_read_reg(regs
, index
);
86 static uint16_t tci_read_reg16(const tcg_target_ulong
*regs
, TCGReg index
)
88 return (uint16_t)tci_read_reg(regs
, index
);
91 static uint32_t tci_read_reg32(const tcg_target_ulong
*regs
, TCGReg index
)
93 return (uint32_t)tci_read_reg(regs
, index
);
96 #if TCG_TARGET_REG_BITS == 64
97 static uint64_t tci_read_reg64(const tcg_target_ulong
*regs
, TCGReg index
)
99 return tci_read_reg(regs
, index
);
104 tci_write_reg(tcg_target_ulong
*regs
, TCGReg index
, tcg_target_ulong value
)
106 tci_assert(index
< TCG_TARGET_NB_REGS
);
107 tci_assert(index
!= TCG_AREG0
);
108 tci_assert(index
!= TCG_REG_CALL_STACK
);
112 #if TCG_TARGET_REG_BITS == 32
113 static void tci_write_reg64(tcg_target_ulong
*regs
, uint32_t high_index
,
114 uint32_t low_index
, uint64_t value
)
116 tci_write_reg(regs
, low_index
, value
);
117 tci_write_reg(regs
, high_index
, value
>> 32);
121 #if TCG_TARGET_REG_BITS == 32
122 /* Create a 64 bit value from two 32 bit values. */
123 static uint64_t tci_uint64(uint32_t high
, uint32_t low
)
125 return ((uint64_t)high
<< 32) + low
;
129 /* Read constant (native size) from bytecode. */
130 static tcg_target_ulong
tci_read_i(const uint8_t **tb_ptr
)
132 tcg_target_ulong value
= *(const tcg_target_ulong
*)(*tb_ptr
);
133 *tb_ptr
+= sizeof(value
);
137 /* Read unsigned constant (32 bit) from bytecode. */
138 static uint32_t tci_read_i32(const uint8_t **tb_ptr
)
140 uint32_t value
= *(const uint32_t *)(*tb_ptr
);
141 *tb_ptr
+= sizeof(value
);
145 /* Read signed constant (32 bit) from bytecode. */
146 static int32_t tci_read_s32(const uint8_t **tb_ptr
)
148 int32_t value
= *(const int32_t *)(*tb_ptr
);
149 *tb_ptr
+= sizeof(value
);
153 #if TCG_TARGET_REG_BITS == 64
154 /* Read constant (64 bit) from bytecode. */
155 static uint64_t tci_read_i64(const uint8_t **tb_ptr
)
157 uint64_t value
= *(const uint64_t *)(*tb_ptr
);
158 *tb_ptr
+= sizeof(value
);
163 /* Read indexed register (native size) from bytecode. */
164 static tcg_target_ulong
165 tci_read_r(const tcg_target_ulong
*regs
, const uint8_t **tb_ptr
)
167 tcg_target_ulong value
= tci_read_reg(regs
, **tb_ptr
);
172 /* Read indexed register (8 bit) from bytecode. */
173 static uint8_t tci_read_r8(const tcg_target_ulong
*regs
, const uint8_t **tb_ptr
)
175 uint8_t value
= tci_read_reg8(regs
, **tb_ptr
);
180 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
181 /* Read indexed register (8 bit signed) from bytecode. */
182 static int8_t tci_read_r8s(const tcg_target_ulong
*regs
, const uint8_t **tb_ptr
)
184 int8_t value
= tci_read_reg8s(regs
, **tb_ptr
);
190 /* Read indexed register (16 bit) from bytecode. */
191 static uint16_t tci_read_r16(const tcg_target_ulong
*regs
,
192 const uint8_t **tb_ptr
)
194 uint16_t value
= tci_read_reg16(regs
, **tb_ptr
);
199 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
200 /* Read indexed register (16 bit signed) from bytecode. */
201 static int16_t tci_read_r16s(const tcg_target_ulong
*regs
,
202 const uint8_t **tb_ptr
)
204 int16_t value
= tci_read_reg16s(regs
, **tb_ptr
);
210 /* Read indexed register (32 bit) from bytecode. */
211 static uint32_t tci_read_r32(const tcg_target_ulong
*regs
,
212 const uint8_t **tb_ptr
)
214 uint32_t value
= tci_read_reg32(regs
, **tb_ptr
);
219 #if TCG_TARGET_REG_BITS == 32
220 /* Read two indexed registers (2 * 32 bit) from bytecode. */
221 static uint64_t tci_read_r64(const tcg_target_ulong
*regs
,
222 const uint8_t **tb_ptr
)
224 uint32_t low
= tci_read_r32(regs
, tb_ptr
);
225 return tci_uint64(tci_read_r32(regs
, tb_ptr
), low
);
227 #elif TCG_TARGET_REG_BITS == 64
228 /* Read indexed register (32 bit signed) from bytecode. */
229 static int32_t tci_read_r32s(const tcg_target_ulong
*regs
,
230 const uint8_t **tb_ptr
)
232 int32_t value
= tci_read_reg32s(regs
, **tb_ptr
);
237 /* Read indexed register (64 bit) from bytecode. */
238 static uint64_t tci_read_r64(const tcg_target_ulong
*regs
,
239 const uint8_t **tb_ptr
)
241 uint64_t value
= tci_read_reg64(regs
, **tb_ptr
);
247 /* Read indexed register(s) with target address from bytecode. */
249 tci_read_ulong(const tcg_target_ulong
*regs
, const uint8_t **tb_ptr
)
251 target_ulong taddr
= tci_read_r(regs
, tb_ptr
);
252 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
253 taddr
+= (uint64_t)tci_read_r(regs
, tb_ptr
) << 32;
258 static tcg_target_ulong
tci_read_label(const uint8_t **tb_ptr
)
260 tcg_target_ulong label
= tci_read_i(tb_ptr
);
261 tci_assert(label
!= 0);
265 static bool tci_compare32(uint32_t u0
, uint32_t u1
, TCGCond condition
)
302 g_assert_not_reached();
307 static bool tci_compare64(uint64_t u0
, uint64_t u1
, TCGCond condition
)
344 g_assert_not_reached();
349 #ifdef CONFIG_SOFTMMU
350 # define qemu_ld_ub \
351 helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
352 # define qemu_ld_leuw \
353 helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
354 # define qemu_ld_leul \
355 helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
356 # define qemu_ld_leq \
357 helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
358 # define qemu_ld_beuw \
359 helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
360 # define qemu_ld_beul \
361 helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
362 # define qemu_ld_beq \
363 helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
364 # define qemu_st_b(X) \
365 helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
366 # define qemu_st_lew(X) \
367 helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
368 # define qemu_st_lel(X) \
369 helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
370 # define qemu_st_leq(X) \
371 helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
372 # define qemu_st_bew(X) \
373 helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
374 # define qemu_st_bel(X) \
375 helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
376 # define qemu_st_beq(X) \
377 helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
379 # define qemu_ld_ub ldub_p(g2h(taddr))
380 # define qemu_ld_leuw lduw_le_p(g2h(taddr))
381 # define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
382 # define qemu_ld_leq ldq_le_p(g2h(taddr))
383 # define qemu_ld_beuw lduw_be_p(g2h(taddr))
384 # define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
385 # define qemu_ld_beq ldq_be_p(g2h(taddr))
386 # define qemu_st_b(X) stb_p(g2h(taddr), X)
387 # define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
388 # define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
389 # define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
390 # define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
391 # define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
392 # define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
395 #if TCG_TARGET_REG_BITS == 64
396 # define CASE_32_64(x) \
397 case glue(glue(INDEX_op_, x), _i64): \
398 case glue(glue(INDEX_op_, x), _i32):
399 # define CASE_64(x) \
400 case glue(glue(INDEX_op_, x), _i64):
402 # define CASE_32_64(x) \
403 case glue(glue(INDEX_op_, x), _i32):
407 /* Interpret pseudo code in tb. */
409 * Disable CFI checks.
410 * One possible operation in the pseudo code is a call to binary code.
411 * Therefore, disable CFI checks in the interpreter function
413 uintptr_t QEMU_DISABLE_CFI
tcg_qemu_tb_exec(CPUArchState
*env
,
414 const void *v_tb_ptr
)
416 const uint8_t *tb_ptr
= v_tb_ptr
;
417 tcg_target_ulong regs
[TCG_TARGET_NB_REGS
];
418 long tcg_temps
[CPU_TEMP_BUF_NLONGS
];
419 uintptr_t sp_value
= (uintptr_t)(tcg_temps
+ CPU_TEMP_BUF_NLONGS
);
422 regs
[TCG_AREG0
] = (tcg_target_ulong
)env
;
423 regs
[TCG_REG_CALL_STACK
] = sp_value
;
427 TCGOpcode opc
= tb_ptr
[0];
428 #if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
429 uint8_t op_size
= tb_ptr
[1];
430 const uint8_t *old_code_ptr
= tb_ptr
;
435 tcg_target_ulong label
;
442 #if TCG_TARGET_REG_BITS == 32
447 /* Skip opcode and size entry. */
452 t0
= tci_read_i(&tb_ptr
);
453 tci_tb_ptr
= (uintptr_t)tb_ptr
;
454 #if TCG_TARGET_REG_BITS == 32
455 tmp64
= ((helper_function
)t0
)(tci_read_reg(regs
, TCG_REG_R0
),
456 tci_read_reg(regs
, TCG_REG_R1
),
457 tci_read_reg(regs
, TCG_REG_R2
),
458 tci_read_reg(regs
, TCG_REG_R3
),
459 tci_read_reg(regs
, TCG_REG_R4
),
460 tci_read_reg(regs
, TCG_REG_R5
),
461 tci_read_reg(regs
, TCG_REG_R6
),
462 tci_read_reg(regs
, TCG_REG_R7
),
463 tci_read_reg(regs
, TCG_REG_R8
),
464 tci_read_reg(regs
, TCG_REG_R9
),
465 tci_read_reg(regs
, TCG_REG_R10
),
466 tci_read_reg(regs
, TCG_REG_R11
));
467 tci_write_reg(regs
, TCG_REG_R0
, tmp64
);
468 tci_write_reg(regs
, TCG_REG_R1
, tmp64
>> 32);
470 tmp64
= ((helper_function
)t0
)(tci_read_reg(regs
, TCG_REG_R0
),
471 tci_read_reg(regs
, TCG_REG_R1
),
472 tci_read_reg(regs
, TCG_REG_R2
),
473 tci_read_reg(regs
, TCG_REG_R3
),
474 tci_read_reg(regs
, TCG_REG_R4
),
475 tci_read_reg(regs
, TCG_REG_R5
));
476 tci_write_reg(regs
, TCG_REG_R0
, tmp64
);
480 label
= tci_read_label(&tb_ptr
);
481 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
482 tb_ptr
= (uint8_t *)label
;
484 case INDEX_op_setcond_i32
:
486 t1
= tci_read_r32(regs
, &tb_ptr
);
487 t2
= tci_read_r32(regs
, &tb_ptr
);
488 condition
= *tb_ptr
++;
489 tci_write_reg(regs
, t0
, tci_compare32(t1
, t2
, condition
));
491 #if TCG_TARGET_REG_BITS == 32
492 case INDEX_op_setcond2_i32
:
494 tmp64
= tci_read_r64(regs
, &tb_ptr
);
495 v64
= tci_read_r64(regs
, &tb_ptr
);
496 condition
= *tb_ptr
++;
497 tci_write_reg(regs
, t0
, tci_compare64(tmp64
, v64
, condition
));
499 #elif TCG_TARGET_REG_BITS == 64
500 case INDEX_op_setcond_i64
:
502 t1
= tci_read_r64(regs
, &tb_ptr
);
503 t2
= tci_read_r64(regs
, &tb_ptr
);
504 condition
= *tb_ptr
++;
505 tci_write_reg(regs
, t0
, tci_compare64(t1
, t2
, condition
));
508 case INDEX_op_mov_i32
:
510 t1
= tci_read_r32(regs
, &tb_ptr
);
511 tci_write_reg(regs
, t0
, t1
);
513 case INDEX_op_tci_movi_i32
:
515 t1
= tci_read_i32(&tb_ptr
);
516 tci_write_reg(regs
, t0
, t1
);
519 /* Load/store operations (32 bit). */
523 t1
= tci_read_r(regs
, &tb_ptr
);
524 t2
= tci_read_s32(&tb_ptr
);
525 tci_write_reg(regs
, t0
, *(uint8_t *)(t1
+ t2
));
529 t1
= tci_read_r(regs
, &tb_ptr
);
530 t2
= tci_read_s32(&tb_ptr
);
531 tci_write_reg(regs
, t0
, *(int8_t *)(t1
+ t2
));
535 t1
= tci_read_r(regs
, &tb_ptr
);
536 t2
= tci_read_s32(&tb_ptr
);
537 tci_write_reg(regs
, t0
, *(uint16_t *)(t1
+ t2
));
541 t1
= tci_read_r(regs
, &tb_ptr
);
542 t2
= tci_read_s32(&tb_ptr
);
543 tci_write_reg(regs
, t0
, *(int16_t *)(t1
+ t2
));
545 case INDEX_op_ld_i32
:
548 t1
= tci_read_r(regs
, &tb_ptr
);
549 t2
= tci_read_s32(&tb_ptr
);
550 tci_write_reg(regs
, t0
, *(uint32_t *)(t1
+ t2
));
553 t0
= tci_read_r8(regs
, &tb_ptr
);
554 t1
= tci_read_r(regs
, &tb_ptr
);
555 t2
= tci_read_s32(&tb_ptr
);
556 *(uint8_t *)(t1
+ t2
) = t0
;
559 t0
= tci_read_r16(regs
, &tb_ptr
);
560 t1
= tci_read_r(regs
, &tb_ptr
);
561 t2
= tci_read_s32(&tb_ptr
);
562 *(uint16_t *)(t1
+ t2
) = t0
;
564 case INDEX_op_st_i32
:
566 t0
= tci_read_r32(regs
, &tb_ptr
);
567 t1
= tci_read_r(regs
, &tb_ptr
);
568 t2
= tci_read_s32(&tb_ptr
);
569 *(uint32_t *)(t1
+ t2
) = t0
;
572 /* Arithmetic operations (32 bit). */
574 case INDEX_op_add_i32
:
576 t1
= tci_read_r32(regs
, &tb_ptr
);
577 t2
= tci_read_r32(regs
, &tb_ptr
);
578 tci_write_reg(regs
, t0
, t1
+ t2
);
580 case INDEX_op_sub_i32
:
582 t1
= tci_read_r32(regs
, &tb_ptr
);
583 t2
= tci_read_r32(regs
, &tb_ptr
);
584 tci_write_reg(regs
, t0
, t1
- t2
);
586 case INDEX_op_mul_i32
:
588 t1
= tci_read_r32(regs
, &tb_ptr
);
589 t2
= tci_read_r32(regs
, &tb_ptr
);
590 tci_write_reg(regs
, t0
, t1
* t2
);
592 case INDEX_op_div_i32
:
594 t1
= tci_read_r32(regs
, &tb_ptr
);
595 t2
= tci_read_r32(regs
, &tb_ptr
);
596 tci_write_reg(regs
, t0
, (int32_t)t1
/ (int32_t)t2
);
598 case INDEX_op_divu_i32
:
600 t1
= tci_read_r32(regs
, &tb_ptr
);
601 t2
= tci_read_r32(regs
, &tb_ptr
);
602 tci_write_reg(regs
, t0
, t1
/ t2
);
604 case INDEX_op_rem_i32
:
606 t1
= tci_read_r32(regs
, &tb_ptr
);
607 t2
= tci_read_r32(regs
, &tb_ptr
);
608 tci_write_reg(regs
, t0
, (int32_t)t1
% (int32_t)t2
);
610 case INDEX_op_remu_i32
:
612 t1
= tci_read_r32(regs
, &tb_ptr
);
613 t2
= tci_read_r32(regs
, &tb_ptr
);
614 tci_write_reg(regs
, t0
, t1
% t2
);
616 case INDEX_op_and_i32
:
618 t1
= tci_read_r32(regs
, &tb_ptr
);
619 t2
= tci_read_r32(regs
, &tb_ptr
);
620 tci_write_reg(regs
, t0
, t1
& t2
);
622 case INDEX_op_or_i32
:
624 t1
= tci_read_r32(regs
, &tb_ptr
);
625 t2
= tci_read_r32(regs
, &tb_ptr
);
626 tci_write_reg(regs
, t0
, t1
| t2
);
628 case INDEX_op_xor_i32
:
630 t1
= tci_read_r32(regs
, &tb_ptr
);
631 t2
= tci_read_r32(regs
, &tb_ptr
);
632 tci_write_reg(regs
, t0
, t1
^ t2
);
635 /* Shift/rotate operations (32 bit). */
637 case INDEX_op_shl_i32
:
639 t1
= tci_read_r32(regs
, &tb_ptr
);
640 t2
= tci_read_r32(regs
, &tb_ptr
);
641 tci_write_reg(regs
, t0
, t1
<< (t2
& 31));
643 case INDEX_op_shr_i32
:
645 t1
= tci_read_r32(regs
, &tb_ptr
);
646 t2
= tci_read_r32(regs
, &tb_ptr
);
647 tci_write_reg(regs
, t0
, t1
>> (t2
& 31));
649 case INDEX_op_sar_i32
:
651 t1
= tci_read_r32(regs
, &tb_ptr
);
652 t2
= tci_read_r32(regs
, &tb_ptr
);
653 tci_write_reg(regs
, t0
, ((int32_t)t1
>> (t2
& 31)));
655 #if TCG_TARGET_HAS_rot_i32
656 case INDEX_op_rotl_i32
:
658 t1
= tci_read_r32(regs
, &tb_ptr
);
659 t2
= tci_read_r32(regs
, &tb_ptr
);
660 tci_write_reg(regs
, t0
, rol32(t1
, t2
& 31));
662 case INDEX_op_rotr_i32
:
664 t1
= tci_read_r32(regs
, &tb_ptr
);
665 t2
= tci_read_r32(regs
, &tb_ptr
);
666 tci_write_reg(regs
, t0
, ror32(t1
, t2
& 31));
669 #if TCG_TARGET_HAS_deposit_i32
670 case INDEX_op_deposit_i32
:
672 t1
= tci_read_r32(regs
, &tb_ptr
);
673 t2
= tci_read_r32(regs
, &tb_ptr
);
676 tmp32
= (((1 << tmp8
) - 1) << tmp16
);
677 tci_write_reg(regs
, t0
, (t1
& ~tmp32
) | ((t2
<< tmp16
) & tmp32
));
680 case INDEX_op_brcond_i32
:
681 t0
= tci_read_r32(regs
, &tb_ptr
);
682 t1
= tci_read_r32(regs
, &tb_ptr
);
683 condition
= *tb_ptr
++;
684 label
= tci_read_label(&tb_ptr
);
685 if (tci_compare32(t0
, t1
, condition
)) {
686 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
687 tb_ptr
= (uint8_t *)label
;
691 #if TCG_TARGET_REG_BITS == 32
692 case INDEX_op_add2_i32
:
695 tmp64
= tci_read_r64(regs
, &tb_ptr
);
696 tmp64
+= tci_read_r64(regs
, &tb_ptr
);
697 tci_write_reg64(regs
, t1
, t0
, tmp64
);
699 case INDEX_op_sub2_i32
:
702 tmp64
= tci_read_r64(regs
, &tb_ptr
);
703 tmp64
-= tci_read_r64(regs
, &tb_ptr
);
704 tci_write_reg64(regs
, t1
, t0
, tmp64
);
706 case INDEX_op_brcond2_i32
:
707 tmp64
= tci_read_r64(regs
, &tb_ptr
);
708 v64
= tci_read_r64(regs
, &tb_ptr
);
709 condition
= *tb_ptr
++;
710 label
= tci_read_label(&tb_ptr
);
711 if (tci_compare64(tmp64
, v64
, condition
)) {
712 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
713 tb_ptr
= (uint8_t *)label
;
717 case INDEX_op_mulu2_i32
:
720 t2
= tci_read_r32(regs
, &tb_ptr
);
721 tmp64
= tci_read_r32(regs
, &tb_ptr
);
722 tci_write_reg64(regs
, t1
, t0
, t2
* tmp64
);
724 #endif /* TCG_TARGET_REG_BITS == 32 */
725 #if TCG_TARGET_HAS_ext8s_i32
726 case INDEX_op_ext8s_i32
:
728 t1
= tci_read_r8s(regs
, &tb_ptr
);
729 tci_write_reg(regs
, t0
, t1
);
732 #if TCG_TARGET_HAS_ext16s_i32
733 case INDEX_op_ext16s_i32
:
735 t1
= tci_read_r16s(regs
, &tb_ptr
);
736 tci_write_reg(regs
, t0
, t1
);
739 #if TCG_TARGET_HAS_ext8u_i32
740 case INDEX_op_ext8u_i32
:
742 t1
= tci_read_r8(regs
, &tb_ptr
);
743 tci_write_reg(regs
, t0
, t1
);
746 #if TCG_TARGET_HAS_ext16u_i32
747 case INDEX_op_ext16u_i32
:
749 t1
= tci_read_r16(regs
, &tb_ptr
);
750 tci_write_reg(regs
, t0
, t1
);
753 #if TCG_TARGET_HAS_bswap16_i32
754 case INDEX_op_bswap16_i32
:
756 t1
= tci_read_r16(regs
, &tb_ptr
);
757 tci_write_reg(regs
, t0
, bswap16(t1
));
760 #if TCG_TARGET_HAS_bswap32_i32
761 case INDEX_op_bswap32_i32
:
763 t1
= tci_read_r32(regs
, &tb_ptr
);
764 tci_write_reg(regs
, t0
, bswap32(t1
));
767 #if TCG_TARGET_HAS_not_i32
768 case INDEX_op_not_i32
:
770 t1
= tci_read_r32(regs
, &tb_ptr
);
771 tci_write_reg(regs
, t0
, ~t1
);
774 #if TCG_TARGET_HAS_neg_i32
775 case INDEX_op_neg_i32
:
777 t1
= tci_read_r32(regs
, &tb_ptr
);
778 tci_write_reg(regs
, t0
, -t1
);
781 #if TCG_TARGET_REG_BITS == 64
782 case INDEX_op_mov_i64
:
784 t1
= tci_read_r64(regs
, &tb_ptr
);
785 tci_write_reg(regs
, t0
, t1
);
787 case INDEX_op_tci_movi_i64
:
789 t1
= tci_read_i64(&tb_ptr
);
790 tci_write_reg(regs
, t0
, t1
);
793 /* Load/store operations (64 bit). */
795 case INDEX_op_ld32s_i64
:
797 t1
= tci_read_r(regs
, &tb_ptr
);
798 t2
= tci_read_s32(&tb_ptr
);
799 tci_write_reg(regs
, t0
, *(int32_t *)(t1
+ t2
));
801 case INDEX_op_ld_i64
:
803 t1
= tci_read_r(regs
, &tb_ptr
);
804 t2
= tci_read_s32(&tb_ptr
);
805 tci_write_reg(regs
, t0
, *(uint64_t *)(t1
+ t2
));
807 case INDEX_op_st_i64
:
808 t0
= tci_read_r64(regs
, &tb_ptr
);
809 t1
= tci_read_r(regs
, &tb_ptr
);
810 t2
= tci_read_s32(&tb_ptr
);
811 *(uint64_t *)(t1
+ t2
) = t0
;
814 /* Arithmetic operations (64 bit). */
816 case INDEX_op_add_i64
:
818 t1
= tci_read_r64(regs
, &tb_ptr
);
819 t2
= tci_read_r64(regs
, &tb_ptr
);
820 tci_write_reg(regs
, t0
, t1
+ t2
);
822 case INDEX_op_sub_i64
:
824 t1
= tci_read_r64(regs
, &tb_ptr
);
825 t2
= tci_read_r64(regs
, &tb_ptr
);
826 tci_write_reg(regs
, t0
, t1
- t2
);
828 case INDEX_op_mul_i64
:
830 t1
= tci_read_r64(regs
, &tb_ptr
);
831 t2
= tci_read_r64(regs
, &tb_ptr
);
832 tci_write_reg(regs
, t0
, t1
* t2
);
834 case INDEX_op_div_i64
:
836 t1
= tci_read_r64(regs
, &tb_ptr
);
837 t2
= tci_read_r64(regs
, &tb_ptr
);
838 tci_write_reg(regs
, t0
, (int64_t)t1
/ (int64_t)t2
);
840 case INDEX_op_divu_i64
:
842 t1
= tci_read_r64(regs
, &tb_ptr
);
843 t2
= tci_read_r64(regs
, &tb_ptr
);
844 tci_write_reg(regs
, t0
, (uint64_t)t1
/ (uint64_t)t2
);
846 case INDEX_op_rem_i64
:
848 t1
= tci_read_r64(regs
, &tb_ptr
);
849 t2
= tci_read_r64(regs
, &tb_ptr
);
850 tci_write_reg(regs
, t0
, (int64_t)t1
% (int64_t)t2
);
852 case INDEX_op_remu_i64
:
854 t1
= tci_read_r64(regs
, &tb_ptr
);
855 t2
= tci_read_r64(regs
, &tb_ptr
);
856 tci_write_reg(regs
, t0
, (uint64_t)t1
% (uint64_t)t2
);
858 case INDEX_op_and_i64
:
860 t1
= tci_read_r64(regs
, &tb_ptr
);
861 t2
= tci_read_r64(regs
, &tb_ptr
);
862 tci_write_reg(regs
, t0
, t1
& t2
);
864 case INDEX_op_or_i64
:
866 t1
= tci_read_r64(regs
, &tb_ptr
);
867 t2
= tci_read_r64(regs
, &tb_ptr
);
868 tci_write_reg(regs
, t0
, t1
| t2
);
870 case INDEX_op_xor_i64
:
872 t1
= tci_read_r64(regs
, &tb_ptr
);
873 t2
= tci_read_r64(regs
, &tb_ptr
);
874 tci_write_reg(regs
, t0
, t1
^ t2
);
877 /* Shift/rotate operations (64 bit). */
879 case INDEX_op_shl_i64
:
881 t1
= tci_read_r64(regs
, &tb_ptr
);
882 t2
= tci_read_r64(regs
, &tb_ptr
);
883 tci_write_reg(regs
, t0
, t1
<< (t2
& 63));
885 case INDEX_op_shr_i64
:
887 t1
= tci_read_r64(regs
, &tb_ptr
);
888 t2
= tci_read_r64(regs
, &tb_ptr
);
889 tci_write_reg(regs
, t0
, t1
>> (t2
& 63));
891 case INDEX_op_sar_i64
:
893 t1
= tci_read_r64(regs
, &tb_ptr
);
894 t2
= tci_read_r64(regs
, &tb_ptr
);
895 tci_write_reg(regs
, t0
, ((int64_t)t1
>> (t2
& 63)));
897 #if TCG_TARGET_HAS_rot_i64
898 case INDEX_op_rotl_i64
:
900 t1
= tci_read_r64(regs
, &tb_ptr
);
901 t2
= tci_read_r64(regs
, &tb_ptr
);
902 tci_write_reg(regs
, t0
, rol64(t1
, t2
& 63));
904 case INDEX_op_rotr_i64
:
906 t1
= tci_read_r64(regs
, &tb_ptr
);
907 t2
= tci_read_r64(regs
, &tb_ptr
);
908 tci_write_reg(regs
, t0
, ror64(t1
, t2
& 63));
911 #if TCG_TARGET_HAS_deposit_i64
912 case INDEX_op_deposit_i64
:
914 t1
= tci_read_r64(regs
, &tb_ptr
);
915 t2
= tci_read_r64(regs
, &tb_ptr
);
918 tmp64
= (((1ULL << tmp8
) - 1) << tmp16
);
919 tci_write_reg(regs
, t0
, (t1
& ~tmp64
) | ((t2
<< tmp16
) & tmp64
));
922 case INDEX_op_brcond_i64
:
923 t0
= tci_read_r64(regs
, &tb_ptr
);
924 t1
= tci_read_r64(regs
, &tb_ptr
);
925 condition
= *tb_ptr
++;
926 label
= tci_read_label(&tb_ptr
);
927 if (tci_compare64(t0
, t1
, condition
)) {
928 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
929 tb_ptr
= (uint8_t *)label
;
933 #if TCG_TARGET_HAS_ext8u_i64
934 case INDEX_op_ext8u_i64
:
936 t1
= tci_read_r8(regs
, &tb_ptr
);
937 tci_write_reg(regs
, t0
, t1
);
940 #if TCG_TARGET_HAS_ext8s_i64
941 case INDEX_op_ext8s_i64
:
943 t1
= tci_read_r8s(regs
, &tb_ptr
);
944 tci_write_reg(regs
, t0
, t1
);
947 #if TCG_TARGET_HAS_ext16s_i64
948 case INDEX_op_ext16s_i64
:
950 t1
= tci_read_r16s(regs
, &tb_ptr
);
951 tci_write_reg(regs
, t0
, t1
);
954 #if TCG_TARGET_HAS_ext16u_i64
955 case INDEX_op_ext16u_i64
:
957 t1
= tci_read_r16(regs
, &tb_ptr
);
958 tci_write_reg(regs
, t0
, t1
);
961 #if TCG_TARGET_HAS_ext32s_i64
962 case INDEX_op_ext32s_i64
:
964 case INDEX_op_ext_i32_i64
:
966 t1
= tci_read_r32s(regs
, &tb_ptr
);
967 tci_write_reg(regs
, t0
, t1
);
969 #if TCG_TARGET_HAS_ext32u_i64
970 case INDEX_op_ext32u_i64
:
972 case INDEX_op_extu_i32_i64
:
974 t1
= tci_read_r32(regs
, &tb_ptr
);
975 tci_write_reg(regs
, t0
, t1
);
977 #if TCG_TARGET_HAS_bswap16_i64
978 case INDEX_op_bswap16_i64
:
980 t1
= tci_read_r16(regs
, &tb_ptr
);
981 tci_write_reg(regs
, t0
, bswap16(t1
));
984 #if TCG_TARGET_HAS_bswap32_i64
985 case INDEX_op_bswap32_i64
:
987 t1
= tci_read_r32(regs
, &tb_ptr
);
988 tci_write_reg(regs
, t0
, bswap32(t1
));
991 #if TCG_TARGET_HAS_bswap64_i64
992 case INDEX_op_bswap64_i64
:
994 t1
= tci_read_r64(regs
, &tb_ptr
);
995 tci_write_reg(regs
, t0
, bswap64(t1
));
998 #if TCG_TARGET_HAS_not_i64
999 case INDEX_op_not_i64
:
1001 t1
= tci_read_r64(regs
, &tb_ptr
);
1002 tci_write_reg(regs
, t0
, ~t1
);
1005 #if TCG_TARGET_HAS_neg_i64
1006 case INDEX_op_neg_i64
:
1008 t1
= tci_read_r64(regs
, &tb_ptr
);
1009 tci_write_reg(regs
, t0
, -t1
);
1012 #endif /* TCG_TARGET_REG_BITS == 64 */
1014 /* QEMU specific operations. */
1016 case INDEX_op_exit_tb
:
1017 ret
= *(uint64_t *)tb_ptr
;
1020 case INDEX_op_goto_tb
:
1021 /* Jump address is aligned */
1022 tb_ptr
= QEMU_ALIGN_PTR_UP(tb_ptr
, 4);
1023 t0
= qatomic_read((int32_t *)tb_ptr
);
1024 tb_ptr
+= sizeof(int32_t);
1025 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
1026 tb_ptr
+= (int32_t)t0
;
1028 case INDEX_op_qemu_ld_i32
:
1030 taddr
= tci_read_ulong(regs
, &tb_ptr
);
1031 oi
= tci_read_i(&tb_ptr
);
1032 switch (get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
)) {
1037 tmp32
= (int8_t)qemu_ld_ub
;
1040 tmp32
= qemu_ld_leuw
;
1043 tmp32
= (int16_t)qemu_ld_leuw
;
1046 tmp32
= qemu_ld_leul
;
1049 tmp32
= qemu_ld_beuw
;
1052 tmp32
= (int16_t)qemu_ld_beuw
;
1055 tmp32
= qemu_ld_beul
;
1058 g_assert_not_reached();
1060 tci_write_reg(regs
, t0
, tmp32
);
1062 case INDEX_op_qemu_ld_i64
:
1064 if (TCG_TARGET_REG_BITS
== 32) {
1067 taddr
= tci_read_ulong(regs
, &tb_ptr
);
1068 oi
= tci_read_i(&tb_ptr
);
1069 switch (get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
)) {
1074 tmp64
= (int8_t)qemu_ld_ub
;
1077 tmp64
= qemu_ld_leuw
;
1080 tmp64
= (int16_t)qemu_ld_leuw
;
1083 tmp64
= qemu_ld_leul
;
1086 tmp64
= (int32_t)qemu_ld_leul
;
1089 tmp64
= qemu_ld_leq
;
1092 tmp64
= qemu_ld_beuw
;
1095 tmp64
= (int16_t)qemu_ld_beuw
;
1098 tmp64
= qemu_ld_beul
;
1101 tmp64
= (int32_t)qemu_ld_beul
;
1104 tmp64
= qemu_ld_beq
;
1107 g_assert_not_reached();
1109 tci_write_reg(regs
, t0
, tmp64
);
1110 if (TCG_TARGET_REG_BITS
== 32) {
1111 tci_write_reg(regs
, t1
, tmp64
>> 32);
1114 case INDEX_op_qemu_st_i32
:
1115 t0
= tci_read_r(regs
, &tb_ptr
);
1116 taddr
= tci_read_ulong(regs
, &tb_ptr
);
1117 oi
= tci_read_i(&tb_ptr
);
1118 switch (get_memop(oi
) & (MO_BSWAP
| MO_SIZE
)) {
1135 g_assert_not_reached();
1138 case INDEX_op_qemu_st_i64
:
1139 tmp64
= tci_read_r64(regs
, &tb_ptr
);
1140 taddr
= tci_read_ulong(regs
, &tb_ptr
);
1141 oi
= tci_read_i(&tb_ptr
);
1142 switch (get_memop(oi
) & (MO_BSWAP
| MO_SIZE
)) {
1165 g_assert_not_reached();
1169 /* Ensure ordering for all kinds */
1173 g_assert_not_reached();
1175 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);