2 * PowerPC implementation of KVM hooks
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
17 #include "qemu/osdep.h"
19 #include <sys/ioctl.h>
22 #include <linux/kvm.h>
24 #include "qemu-common.h"
25 #include "qapi/error.h"
26 #include "qemu/error-report.h"
28 #include "cpu-models.h"
29 #include "qemu/timer.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/hw_accel.h"
33 #include "sysemu/cpus.h"
34 #include "sysemu/device_tree.h"
35 #include "mmu-hash64.h"
37 #include "hw/sysbus.h"
38 #include "hw/ppc/spapr.h"
39 #include "hw/ppc/spapr_cpu_core.h"
40 #include "hw/ppc/ppc.h"
41 #include "sysemu/watchdog.h"
43 #include "exec/gdbstub.h"
44 #include "exec/memattrs.h"
45 #include "exec/ram_addr.h"
46 #include "sysemu/hostmem.h"
47 #include "qemu/cutils.h"
48 #include "qemu/mmap-alloc.h"
50 #include "sysemu/kvm_int.h"
52 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
54 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
58 static int cap_interrupt_unset
;
59 static int cap_interrupt_level
;
60 static int cap_segstate
;
61 static int cap_booke_sregs
;
62 static int cap_ppc_smt
;
63 static int cap_ppc_smt_possible
;
64 static int cap_spapr_tce
;
65 static int cap_spapr_tce_64
;
66 static int cap_spapr_multitce
;
67 static int cap_spapr_vfio
;
69 static int cap_one_reg
;
71 static int cap_ppc_watchdog
;
73 static int cap_htab_fd
;
74 static int cap_fixup_hcalls
;
75 static int cap_htm
; /* Hardware transactional memory support */
76 static int cap_mmu_radix
;
77 static int cap_mmu_hash_v3
;
79 static int cap_resize_hpt
;
80 static int cap_ppc_pvr_compat
;
81 static int cap_ppc_safe_cache
;
82 static int cap_ppc_safe_bounds_check
;
83 static int cap_ppc_safe_indirect_branch
;
84 static int cap_ppc_count_cache_flush_assist
;
85 static int cap_ppc_nested_kvm_hv
;
86 static int cap_large_decr
;
88 static uint32_t debug_inst_opcode
;
91 * XXX We have a race condition where we actually have a level triggered
92 * interrupt, but the infrastructure can't expose that yet, so the guest
93 * takes but ignores it, goes to sleep and never gets notified that there's
94 * still an interrupt pending.
96 * As a quick workaround, let's just wake up again 20 ms after we injected
97 * an interrupt. That way we can assure that we're always reinjecting
98 * interrupts in case the guest swallowed them.
100 static QEMUTimer
*idle_timer
;
102 static void kvm_kick_cpu(void *opaque
)
104 PowerPCCPU
*cpu
= opaque
;
106 qemu_cpu_kick(CPU(cpu
));
110 * Check whether we are running with KVM-PR (instead of KVM-HV). This
111 * should only be used for fallback tests - generally we should use
112 * explicit capabilities for the features we want, rather than
113 * assuming what is/isn't available depending on the KVM variant.
115 static bool kvmppc_is_pr(KVMState
*ks
)
117 /* Assume KVM-PR if the GET_PVINFO capability is available */
118 return kvm_vm_check_extension(ks
, KVM_CAP_PPC_GET_PVINFO
) != 0;
121 static int kvm_ppc_register_host_cpu_type(MachineState
*ms
);
122 static void kvmppc_get_cpu_characteristics(KVMState
*s
);
123 static int kvmppc_get_dec_bits(void);
125 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
127 cap_interrupt_unset
= kvm_check_extension(s
, KVM_CAP_PPC_UNSET_IRQ
);
128 cap_interrupt_level
= kvm_check_extension(s
, KVM_CAP_PPC_IRQ_LEVEL
);
129 cap_segstate
= kvm_check_extension(s
, KVM_CAP_PPC_SEGSTATE
);
130 cap_booke_sregs
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_SREGS
);
131 cap_ppc_smt_possible
= kvm_vm_check_extension(s
, KVM_CAP_PPC_SMT_POSSIBLE
);
132 cap_spapr_tce
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE
);
133 cap_spapr_tce_64
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE_64
);
134 cap_spapr_multitce
= kvm_check_extension(s
, KVM_CAP_SPAPR_MULTITCE
);
135 cap_spapr_vfio
= kvm_vm_check_extension(s
, KVM_CAP_SPAPR_TCE_VFIO
);
136 cap_one_reg
= kvm_check_extension(s
, KVM_CAP_ONE_REG
);
137 cap_hior
= kvm_check_extension(s
, KVM_CAP_PPC_HIOR
);
138 cap_epr
= kvm_check_extension(s
, KVM_CAP_PPC_EPR
);
139 cap_ppc_watchdog
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_WATCHDOG
);
141 * Note: we don't set cap_papr here, because this capability is
142 * only activated after this by kvmppc_set_papr()
144 cap_htab_fd
= kvm_vm_check_extension(s
, KVM_CAP_PPC_HTAB_FD
);
145 cap_fixup_hcalls
= kvm_check_extension(s
, KVM_CAP_PPC_FIXUP_HCALL
);
146 cap_ppc_smt
= kvm_vm_check_extension(s
, KVM_CAP_PPC_SMT
);
147 cap_htm
= kvm_vm_check_extension(s
, KVM_CAP_PPC_HTM
);
148 cap_mmu_radix
= kvm_vm_check_extension(s
, KVM_CAP_PPC_MMU_RADIX
);
149 cap_mmu_hash_v3
= kvm_vm_check_extension(s
, KVM_CAP_PPC_MMU_HASH_V3
);
150 cap_xive
= kvm_vm_check_extension(s
, KVM_CAP_PPC_IRQ_XIVE
);
151 cap_resize_hpt
= kvm_vm_check_extension(s
, KVM_CAP_SPAPR_RESIZE_HPT
);
152 kvmppc_get_cpu_characteristics(s
);
153 cap_ppc_nested_kvm_hv
= kvm_vm_check_extension(s
, KVM_CAP_PPC_NESTED_HV
);
154 cap_large_decr
= kvmppc_get_dec_bits();
156 * Note: setting it to false because there is not such capability
157 * in KVM at this moment.
159 * TODO: call kvm_vm_check_extension() with the right capability
160 * after the kernel starts implementing it.
162 cap_ppc_pvr_compat
= false;
164 if (!cap_interrupt_level
) {
165 fprintf(stderr
, "KVM: Couldn't find level irq capability. Expect the "
166 "VM to stall at times!\n");
169 kvm_ppc_register_host_cpu_type(ms
);
174 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
179 static int kvm_arch_sync_sregs(PowerPCCPU
*cpu
)
181 CPUPPCState
*cenv
= &cpu
->env
;
182 CPUState
*cs
= CPU(cpu
);
183 struct kvm_sregs sregs
;
186 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
188 * What we're really trying to say is "if we're on BookE, we
189 * use the native PVR for now". This is the only sane way to
190 * check it though, so we potentially confuse users that they
191 * can run BookE guests on BookS. Let's hope nobody dares
197 fprintf(stderr
, "kvm error: missing PVR setting capability\n");
202 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_SREGS
, &sregs
);
207 sregs
.pvr
= cenv
->spr
[SPR_PVR
];
208 return kvm_vcpu_ioctl(cs
, KVM_SET_SREGS
, &sregs
);
211 /* Set up a shared TLB array with KVM */
212 static int kvm_booke206_tlb_init(PowerPCCPU
*cpu
)
214 CPUPPCState
*env
= &cpu
->env
;
215 CPUState
*cs
= CPU(cpu
);
216 struct kvm_book3e_206_tlb_params params
= {};
217 struct kvm_config_tlb cfg
= {};
218 unsigned int entries
= 0;
221 if (!kvm_enabled() ||
222 !kvm_check_extension(cs
->kvm_state
, KVM_CAP_SW_TLB
)) {
226 assert(ARRAY_SIZE(params
.tlb_sizes
) == BOOKE206_MAX_TLBN
);
228 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
229 params
.tlb_sizes
[i
] = booke206_tlb_size(env
, i
);
230 params
.tlb_ways
[i
] = booke206_tlb_ways(env
, i
);
231 entries
+= params
.tlb_sizes
[i
];
234 assert(entries
== env
->nb_tlb
);
235 assert(sizeof(struct kvm_book3e_206_tlb_entry
) == sizeof(ppcmas_tlb_t
));
237 env
->tlb_dirty
= true;
239 cfg
.array
= (uintptr_t)env
->tlb
.tlbm
;
240 cfg
.array_len
= sizeof(ppcmas_tlb_t
) * entries
;
241 cfg
.params
= (uintptr_t)¶ms
;
242 cfg
.mmu_type
= KVM_MMU_FSL_BOOKE_NOHV
;
244 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_SW_TLB
, 0, (uintptr_t)&cfg
);
246 fprintf(stderr
, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
247 __func__
, strerror(-ret
));
251 env
->kvm_sw_tlb
= true;
256 #if defined(TARGET_PPC64)
257 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info
*info
, Error
**errp
)
261 assert(kvm_state
!= NULL
);
263 if (!kvm_check_extension(kvm_state
, KVM_CAP_PPC_GET_SMMU_INFO
)) {
264 error_setg(errp
, "KVM doesn't expose the MMU features it supports");
265 error_append_hint(errp
, "Consider switching to a newer KVM\n");
269 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_GET_SMMU_INFO
, info
);
274 error_setg_errno(errp
, -ret
,
275 "KVM failed to provide the MMU features it supports");
278 struct ppc_radix_page_info
*kvm_get_radix_page_info(void)
280 KVMState
*s
= KVM_STATE(current_machine
->accelerator
);
281 struct ppc_radix_page_info
*radix_page_info
;
282 struct kvm_ppc_rmmu_info rmmu_info
;
285 if (!kvm_check_extension(s
, KVM_CAP_PPC_MMU_RADIX
)) {
288 if (kvm_vm_ioctl(s
, KVM_PPC_GET_RMMU_INFO
, &rmmu_info
)) {
291 radix_page_info
= g_malloc0(sizeof(*radix_page_info
));
292 radix_page_info
->count
= 0;
293 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
294 if (rmmu_info
.ap_encodings
[i
]) {
295 radix_page_info
->entries
[i
] = rmmu_info
.ap_encodings
[i
];
296 radix_page_info
->count
++;
299 return radix_page_info
;
302 target_ulong
kvmppc_configure_v3_mmu(PowerPCCPU
*cpu
,
303 bool radix
, bool gtse
,
306 CPUState
*cs
= CPU(cpu
);
309 struct kvm_ppc_mmuv3_cfg cfg
= {
310 .process_table
= proc_tbl
,
314 flags
|= KVM_PPC_MMUV3_RADIX
;
317 flags
|= KVM_PPC_MMUV3_GTSE
;
320 ret
= kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_CONFIGURE_V3_MMU
, &cfg
);
327 return H_NOT_AVAILABLE
;
333 bool kvmppc_hpt_needs_host_contiguous_pages(void)
335 static struct kvm_ppc_smmu_info smmu_info
;
337 if (!kvm_enabled()) {
341 kvm_get_smmu_info(&smmu_info
, &error_fatal
);
342 return !!(smmu_info
.flags
& KVM_PPC_PAGE_SIZES_REAL
);
345 void kvm_check_mmu(PowerPCCPU
*cpu
, Error
**errp
)
347 struct kvm_ppc_smmu_info smmu_info
;
349 Error
*local_err
= NULL
;
351 /* For now, we only have anything to check on hash64 MMUs */
352 if (!cpu
->hash64_opts
|| !kvm_enabled()) {
356 kvm_get_smmu_info(&smmu_info
, &local_err
);
358 error_propagate(errp
, local_err
);
362 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)
363 && !(smmu_info
.flags
& KVM_PPC_1T_SEGMENTS
)) {
365 "KVM does not support 1TiB segments which guest expects");
369 if (smmu_info
.slb_size
< cpu
->hash64_opts
->slb_size
) {
370 error_setg(errp
, "KVM only supports %u SLB entries, but guest needs %u",
371 smmu_info
.slb_size
, cpu
->hash64_opts
->slb_size
);
376 * Verify that every pagesize supported by the cpu model is
377 * supported by KVM with the same encodings
379 for (iq
= 0; iq
< ARRAY_SIZE(cpu
->hash64_opts
->sps
); iq
++) {
380 PPCHash64SegmentPageSizes
*qsps
= &cpu
->hash64_opts
->sps
[iq
];
381 struct kvm_ppc_one_seg_page_size
*ksps
;
383 for (ik
= 0; ik
< ARRAY_SIZE(smmu_info
.sps
); ik
++) {
384 if (qsps
->page_shift
== smmu_info
.sps
[ik
].page_shift
) {
388 if (ik
>= ARRAY_SIZE(smmu_info
.sps
)) {
389 error_setg(errp
, "KVM doesn't support for base page shift %u",
394 ksps
= &smmu_info
.sps
[ik
];
395 if (ksps
->slb_enc
!= qsps
->slb_enc
) {
397 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
398 ksps
->slb_enc
, ksps
->page_shift
, qsps
->slb_enc
);
402 for (jq
= 0; jq
< ARRAY_SIZE(qsps
->enc
); jq
++) {
403 for (jk
= 0; jk
< ARRAY_SIZE(ksps
->enc
); jk
++) {
404 if (qsps
->enc
[jq
].page_shift
== ksps
->enc
[jk
].page_shift
) {
409 if (jk
>= ARRAY_SIZE(ksps
->enc
)) {
410 error_setg(errp
, "KVM doesn't support page shift %u/%u",
411 qsps
->enc
[jq
].page_shift
, qsps
->page_shift
);
414 if (qsps
->enc
[jq
].pte_enc
!= ksps
->enc
[jk
].pte_enc
) {
416 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
417 ksps
->enc
[jk
].pte_enc
, qsps
->enc
[jq
].page_shift
,
418 qsps
->page_shift
, qsps
->enc
[jq
].pte_enc
);
424 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
426 * Mostly what guest pagesizes we can use are related to the
427 * host pages used to map guest RAM, which is handled in the
428 * platform code. Cache-Inhibited largepages (64k) however are
429 * used for I/O, so if they're mapped to the host at all it
430 * will be a normal mapping, not a special hugepage one used
433 if (getpagesize() < 0x10000) {
435 "KVM can't supply 64kiB CI pages, which guest expects");
439 #endif /* !defined (TARGET_PPC64) */
441 unsigned long kvm_arch_vcpu_id(CPUState
*cpu
)
443 return POWERPC_CPU(cpu
)->vcpu_id
;
447 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
448 * only 1 watchpoint, so array size of 4 is sufficient for now.
450 #define MAX_HW_BKPTS 4
452 static struct HWBreakpoint
{
455 } hw_debug_points
[MAX_HW_BKPTS
];
457 static CPUWatchpoint hw_watchpoint
;
459 /* Default there is no breakpoint and watchpoint supported */
460 static int max_hw_breakpoint
;
461 static int max_hw_watchpoint
;
462 static int nb_hw_breakpoint
;
463 static int nb_hw_watchpoint
;
465 static void kvmppc_hw_debug_points_init(CPUPPCState
*cenv
)
467 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
468 max_hw_breakpoint
= 2;
469 max_hw_watchpoint
= 2;
472 if ((max_hw_breakpoint
+ max_hw_watchpoint
) > MAX_HW_BKPTS
) {
473 fprintf(stderr
, "Error initializing h/w breakpoints\n");
478 int kvm_arch_init_vcpu(CPUState
*cs
)
480 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
481 CPUPPCState
*cenv
= &cpu
->env
;
484 /* Synchronize sregs with kvm */
485 ret
= kvm_arch_sync_sregs(cpu
);
487 if (ret
== -EINVAL
) {
488 error_report("Register sync failed... If you're using kvm-hv.ko,"
489 " only \"-cpu host\" is possible");
494 idle_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, kvm_kick_cpu
, cpu
);
496 switch (cenv
->mmu_model
) {
497 case POWERPC_MMU_BOOKE206
:
498 /* This target supports access to KVM's guest TLB */
499 ret
= kvm_booke206_tlb_init(cpu
);
501 case POWERPC_MMU_2_07
:
502 if (!cap_htm
&& !kvmppc_is_pr(cs
->kvm_state
)) {
504 * KVM-HV has transactional memory on POWER8 also without
505 * the KVM_CAP_PPC_HTM extension, so enable it here
506 * instead as long as it's availble to userspace on the
509 if (qemu_getauxval(AT_HWCAP2
) & PPC_FEATURE2_HAS_HTM
) {
518 kvm_get_one_reg(cs
, KVM_REG_PPC_DEBUG_INST
, &debug_inst_opcode
);
519 kvmppc_hw_debug_points_init(cenv
);
524 static void kvm_sw_tlb_put(PowerPCCPU
*cpu
)
526 CPUPPCState
*env
= &cpu
->env
;
527 CPUState
*cs
= CPU(cpu
);
528 struct kvm_dirty_tlb dirty_tlb
;
529 unsigned char *bitmap
;
532 if (!env
->kvm_sw_tlb
) {
536 bitmap
= g_malloc((env
->nb_tlb
+ 7) / 8);
537 memset(bitmap
, 0xFF, (env
->nb_tlb
+ 7) / 8);
539 dirty_tlb
.bitmap
= (uintptr_t)bitmap
;
540 dirty_tlb
.num_dirty
= env
->nb_tlb
;
542 ret
= kvm_vcpu_ioctl(cs
, KVM_DIRTY_TLB
, &dirty_tlb
);
544 fprintf(stderr
, "%s: KVM_DIRTY_TLB: %s\n",
545 __func__
, strerror(-ret
));
551 static void kvm_get_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
553 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
554 CPUPPCState
*env
= &cpu
->env
;
559 struct kvm_one_reg reg
= {
561 .addr
= (uintptr_t) &val
,
565 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
567 trace_kvm_failed_spr_get(spr
, strerror(errno
));
569 switch (id
& KVM_REG_SIZE_MASK
) {
570 case KVM_REG_SIZE_U32
:
571 env
->spr
[spr
] = val
.u32
;
574 case KVM_REG_SIZE_U64
:
575 env
->spr
[spr
] = val
.u64
;
579 /* Don't handle this size yet */
585 static void kvm_put_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
587 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
588 CPUPPCState
*env
= &cpu
->env
;
593 struct kvm_one_reg reg
= {
595 .addr
= (uintptr_t) &val
,
599 switch (id
& KVM_REG_SIZE_MASK
) {
600 case KVM_REG_SIZE_U32
:
601 val
.u32
= env
->spr
[spr
];
604 case KVM_REG_SIZE_U64
:
605 val
.u64
= env
->spr
[spr
];
609 /* Don't handle this size yet */
613 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
615 trace_kvm_failed_spr_set(spr
, strerror(errno
));
619 static int kvm_put_fp(CPUState
*cs
)
621 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
622 CPUPPCState
*env
= &cpu
->env
;
623 struct kvm_one_reg reg
;
627 if (env
->insns_flags
& PPC_FLOAT
) {
628 uint64_t fpscr
= env
->fpscr
;
629 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
631 reg
.id
= KVM_REG_PPC_FPSCR
;
632 reg
.addr
= (uintptr_t)&fpscr
;
633 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
635 trace_kvm_failed_fpscr_set(strerror(errno
));
639 for (i
= 0; i
< 32; i
++) {
641 uint64_t *fpr
= cpu_fpr_ptr(&cpu
->env
, i
);
642 uint64_t *vsrl
= cpu_vsrl_ptr(&cpu
->env
, i
);
644 #ifdef HOST_WORDS_BIGENDIAN
645 vsr
[0] = float64_val(*fpr
);
649 vsr
[1] = float64_val(*fpr
);
651 reg
.addr
= (uintptr_t) &vsr
;
652 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
654 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
656 trace_kvm_failed_fp_set(vsx
? "VSR" : "FPR", i
,
663 if (env
->insns_flags
& PPC_ALTIVEC
) {
664 reg
.id
= KVM_REG_PPC_VSCR
;
665 reg
.addr
= (uintptr_t)&env
->vscr
;
666 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
668 trace_kvm_failed_vscr_set(strerror(errno
));
672 for (i
= 0; i
< 32; i
++) {
673 reg
.id
= KVM_REG_PPC_VR(i
);
674 reg
.addr
= (uintptr_t)cpu_avr_ptr(env
, i
);
675 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
677 trace_kvm_failed_vr_set(i
, strerror(errno
));
686 static int kvm_get_fp(CPUState
*cs
)
688 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
689 CPUPPCState
*env
= &cpu
->env
;
690 struct kvm_one_reg reg
;
694 if (env
->insns_flags
& PPC_FLOAT
) {
696 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
698 reg
.id
= KVM_REG_PPC_FPSCR
;
699 reg
.addr
= (uintptr_t)&fpscr
;
700 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
702 trace_kvm_failed_fpscr_get(strerror(errno
));
708 for (i
= 0; i
< 32; i
++) {
710 uint64_t *fpr
= cpu_fpr_ptr(&cpu
->env
, i
);
711 uint64_t *vsrl
= cpu_vsrl_ptr(&cpu
->env
, i
);
713 reg
.addr
= (uintptr_t) &vsr
;
714 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
716 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
718 trace_kvm_failed_fp_get(vsx
? "VSR" : "FPR", i
,
722 #ifdef HOST_WORDS_BIGENDIAN
737 if (env
->insns_flags
& PPC_ALTIVEC
) {
738 reg
.id
= KVM_REG_PPC_VSCR
;
739 reg
.addr
= (uintptr_t)&env
->vscr
;
740 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
742 trace_kvm_failed_vscr_get(strerror(errno
));
746 for (i
= 0; i
< 32; i
++) {
747 reg
.id
= KVM_REG_PPC_VR(i
);
748 reg
.addr
= (uintptr_t)cpu_avr_ptr(env
, i
);
749 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
751 trace_kvm_failed_vr_get(i
, strerror(errno
));
760 #if defined(TARGET_PPC64)
761 static int kvm_get_vpa(CPUState
*cs
)
763 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
764 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
765 struct kvm_one_reg reg
;
768 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
769 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
770 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
772 trace_kvm_failed_vpa_addr_get(strerror(errno
));
776 assert((uintptr_t)&spapr_cpu
->slb_shadow_size
777 == ((uintptr_t)&spapr_cpu
->slb_shadow_addr
+ 8));
778 reg
.id
= KVM_REG_PPC_VPA_SLB
;
779 reg
.addr
= (uintptr_t)&spapr_cpu
->slb_shadow_addr
;
780 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
782 trace_kvm_failed_slb_get(strerror(errno
));
786 assert((uintptr_t)&spapr_cpu
->dtl_size
787 == ((uintptr_t)&spapr_cpu
->dtl_addr
+ 8));
788 reg
.id
= KVM_REG_PPC_VPA_DTL
;
789 reg
.addr
= (uintptr_t)&spapr_cpu
->dtl_addr
;
790 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
792 trace_kvm_failed_dtl_get(strerror(errno
));
799 static int kvm_put_vpa(CPUState
*cs
)
801 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
802 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
803 struct kvm_one_reg reg
;
807 * SLB shadow or DTL can't be registered unless a master VPA is
808 * registered. That means when restoring state, if a VPA *is*
809 * registered, we need to set that up first. If not, we need to
810 * deregister the others before deregistering the master VPA
812 assert(spapr_cpu
->vpa_addr
813 || !(spapr_cpu
->slb_shadow_addr
|| spapr_cpu
->dtl_addr
));
815 if (spapr_cpu
->vpa_addr
) {
816 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
817 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
818 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
820 trace_kvm_failed_vpa_addr_set(strerror(errno
));
825 assert((uintptr_t)&spapr_cpu
->slb_shadow_size
826 == ((uintptr_t)&spapr_cpu
->slb_shadow_addr
+ 8));
827 reg
.id
= KVM_REG_PPC_VPA_SLB
;
828 reg
.addr
= (uintptr_t)&spapr_cpu
->slb_shadow_addr
;
829 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
831 trace_kvm_failed_slb_set(strerror(errno
));
835 assert((uintptr_t)&spapr_cpu
->dtl_size
836 == ((uintptr_t)&spapr_cpu
->dtl_addr
+ 8));
837 reg
.id
= KVM_REG_PPC_VPA_DTL
;
838 reg
.addr
= (uintptr_t)&spapr_cpu
->dtl_addr
;
839 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
841 trace_kvm_failed_dtl_set(strerror(errno
));
845 if (!spapr_cpu
->vpa_addr
) {
846 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
847 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
848 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
850 trace_kvm_failed_null_vpa_addr_set(strerror(errno
));
857 #endif /* TARGET_PPC64 */
859 int kvmppc_put_books_sregs(PowerPCCPU
*cpu
)
861 CPUPPCState
*env
= &cpu
->env
;
862 struct kvm_sregs sregs
;
865 sregs
.pvr
= env
->spr
[SPR_PVR
];
868 PPCVirtualHypervisorClass
*vhc
=
869 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
870 sregs
.u
.s
.sdr1
= vhc
->encode_hpt_for_kvm_pr(cpu
->vhyp
);
872 sregs
.u
.s
.sdr1
= env
->spr
[SPR_SDR1
];
877 for (i
= 0; i
< ARRAY_SIZE(env
->slb
); i
++) {
878 sregs
.u
.s
.ppc64
.slb
[i
].slbe
= env
->slb
[i
].esid
;
879 if (env
->slb
[i
].esid
& SLB_ESID_V
) {
880 sregs
.u
.s
.ppc64
.slb
[i
].slbe
|= i
;
882 sregs
.u
.s
.ppc64
.slb
[i
].slbv
= env
->slb
[i
].vsid
;
887 for (i
= 0; i
< 16; i
++) {
888 sregs
.u
.s
.ppc32
.sr
[i
] = env
->sr
[i
];
892 for (i
= 0; i
< 8; i
++) {
893 /* Beware. We have to swap upper and lower bits here */
894 sregs
.u
.s
.ppc32
.dbat
[i
] = ((uint64_t)env
->DBAT
[0][i
] << 32)
896 sregs
.u
.s
.ppc32
.ibat
[i
] = ((uint64_t)env
->IBAT
[0][i
] << 32)
900 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
903 int kvm_arch_put_registers(CPUState
*cs
, int level
)
905 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
906 CPUPPCState
*env
= &cpu
->env
;
907 struct kvm_regs regs
;
911 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
918 regs
.xer
= cpu_read_xer(env
);
922 regs
.srr0
= env
->spr
[SPR_SRR0
];
923 regs
.srr1
= env
->spr
[SPR_SRR1
];
925 regs
.sprg0
= env
->spr
[SPR_SPRG0
];
926 regs
.sprg1
= env
->spr
[SPR_SPRG1
];
927 regs
.sprg2
= env
->spr
[SPR_SPRG2
];
928 regs
.sprg3
= env
->spr
[SPR_SPRG3
];
929 regs
.sprg4
= env
->spr
[SPR_SPRG4
];
930 regs
.sprg5
= env
->spr
[SPR_SPRG5
];
931 regs
.sprg6
= env
->spr
[SPR_SPRG6
];
932 regs
.sprg7
= env
->spr
[SPR_SPRG7
];
934 regs
.pid
= env
->spr
[SPR_BOOKE_PID
];
936 for (i
= 0; i
< 32; i
++) {
937 regs
.gpr
[i
] = env
->gpr
[i
];
941 for (i
= 0; i
< 8; i
++) {
942 regs
.cr
|= (env
->crf
[i
] & 15) << (4 * (7 - i
));
945 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
952 if (env
->tlb_dirty
) {
954 env
->tlb_dirty
= false;
957 if (cap_segstate
&& (level
>= KVM_PUT_RESET_STATE
)) {
958 ret
= kvmppc_put_books_sregs(cpu
);
964 if (cap_hior
&& (level
>= KVM_PUT_RESET_STATE
)) {
965 kvm_put_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
972 * We deliberately ignore errors here, for kernels which have
973 * the ONE_REG calls, but don't support the specific
974 * registers, there's a reasonable chance things will still
975 * work, at least until we try to migrate.
977 for (i
= 0; i
< 1024; i
++) {
978 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
981 kvm_put_one_spr(cs
, id
, i
);
987 for (i
= 0; i
< ARRAY_SIZE(env
->tm_gpr
); i
++) {
988 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_GPR(i
), &env
->tm_gpr
[i
]);
990 for (i
= 0; i
< ARRAY_SIZE(env
->tm_vsr
); i
++) {
991 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VSR(i
), &env
->tm_vsr
[i
]);
993 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_CR
, &env
->tm_cr
);
994 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_LR
, &env
->tm_lr
);
995 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_CTR
, &env
->tm_ctr
);
996 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_FPSCR
, &env
->tm_fpscr
);
997 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_AMR
, &env
->tm_amr
);
998 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_PPR
, &env
->tm_ppr
);
999 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VRSAVE
, &env
->tm_vrsave
);
1000 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VSCR
, &env
->tm_vscr
);
1001 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_DSCR
, &env
->tm_dscr
);
1002 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_TAR
, &env
->tm_tar
);
1006 if (kvm_put_vpa(cs
) < 0) {
1007 trace_kvm_failed_put_vpa();
1011 kvm_set_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &env
->tb_env
->tb_offset
);
1012 #endif /* TARGET_PPC64 */
1018 static void kvm_sync_excp(CPUPPCState
*env
, int vector
, int ivor
)
1020 env
->excp_vectors
[vector
] = env
->spr
[ivor
] + env
->spr
[SPR_BOOKE_IVPR
];
1023 static int kvmppc_get_booke_sregs(PowerPCCPU
*cpu
)
1025 CPUPPCState
*env
= &cpu
->env
;
1026 struct kvm_sregs sregs
;
1029 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1034 if (sregs
.u
.e
.features
& KVM_SREGS_E_BASE
) {
1035 env
->spr
[SPR_BOOKE_CSRR0
] = sregs
.u
.e
.csrr0
;
1036 env
->spr
[SPR_BOOKE_CSRR1
] = sregs
.u
.e
.csrr1
;
1037 env
->spr
[SPR_BOOKE_ESR
] = sregs
.u
.e
.esr
;
1038 env
->spr
[SPR_BOOKE_DEAR
] = sregs
.u
.e
.dear
;
1039 env
->spr
[SPR_BOOKE_MCSR
] = sregs
.u
.e
.mcsr
;
1040 env
->spr
[SPR_BOOKE_TSR
] = sregs
.u
.e
.tsr
;
1041 env
->spr
[SPR_BOOKE_TCR
] = sregs
.u
.e
.tcr
;
1042 env
->spr
[SPR_DECR
] = sregs
.u
.e
.dec
;
1043 env
->spr
[SPR_TBL
] = sregs
.u
.e
.tb
& 0xffffffff;
1044 env
->spr
[SPR_TBU
] = sregs
.u
.e
.tb
>> 32;
1045 env
->spr
[SPR_VRSAVE
] = sregs
.u
.e
.vrsave
;
1048 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206
) {
1049 env
->spr
[SPR_BOOKE_PIR
] = sregs
.u
.e
.pir
;
1050 env
->spr
[SPR_BOOKE_MCSRR0
] = sregs
.u
.e
.mcsrr0
;
1051 env
->spr
[SPR_BOOKE_MCSRR1
] = sregs
.u
.e
.mcsrr1
;
1052 env
->spr
[SPR_BOOKE_DECAR
] = sregs
.u
.e
.decar
;
1053 env
->spr
[SPR_BOOKE_IVPR
] = sregs
.u
.e
.ivpr
;
1056 if (sregs
.u
.e
.features
& KVM_SREGS_E_64
) {
1057 env
->spr
[SPR_BOOKE_EPCR
] = sregs
.u
.e
.epcr
;
1060 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPRG8
) {
1061 env
->spr
[SPR_BOOKE_SPRG8
] = sregs
.u
.e
.sprg8
;
1064 if (sregs
.u
.e
.features
& KVM_SREGS_E_IVOR
) {
1065 env
->spr
[SPR_BOOKE_IVOR0
] = sregs
.u
.e
.ivor_low
[0];
1066 kvm_sync_excp(env
, POWERPC_EXCP_CRITICAL
, SPR_BOOKE_IVOR0
);
1067 env
->spr
[SPR_BOOKE_IVOR1
] = sregs
.u
.e
.ivor_low
[1];
1068 kvm_sync_excp(env
, POWERPC_EXCP_MCHECK
, SPR_BOOKE_IVOR1
);
1069 env
->spr
[SPR_BOOKE_IVOR2
] = sregs
.u
.e
.ivor_low
[2];
1070 kvm_sync_excp(env
, POWERPC_EXCP_DSI
, SPR_BOOKE_IVOR2
);
1071 env
->spr
[SPR_BOOKE_IVOR3
] = sregs
.u
.e
.ivor_low
[3];
1072 kvm_sync_excp(env
, POWERPC_EXCP_ISI
, SPR_BOOKE_IVOR3
);
1073 env
->spr
[SPR_BOOKE_IVOR4
] = sregs
.u
.e
.ivor_low
[4];
1074 kvm_sync_excp(env
, POWERPC_EXCP_EXTERNAL
, SPR_BOOKE_IVOR4
);
1075 env
->spr
[SPR_BOOKE_IVOR5
] = sregs
.u
.e
.ivor_low
[5];
1076 kvm_sync_excp(env
, POWERPC_EXCP_ALIGN
, SPR_BOOKE_IVOR5
);
1077 env
->spr
[SPR_BOOKE_IVOR6
] = sregs
.u
.e
.ivor_low
[6];
1078 kvm_sync_excp(env
, POWERPC_EXCP_PROGRAM
, SPR_BOOKE_IVOR6
);
1079 env
->spr
[SPR_BOOKE_IVOR7
] = sregs
.u
.e
.ivor_low
[7];
1080 kvm_sync_excp(env
, POWERPC_EXCP_FPU
, SPR_BOOKE_IVOR7
);
1081 env
->spr
[SPR_BOOKE_IVOR8
] = sregs
.u
.e
.ivor_low
[8];
1082 kvm_sync_excp(env
, POWERPC_EXCP_SYSCALL
, SPR_BOOKE_IVOR8
);
1083 env
->spr
[SPR_BOOKE_IVOR9
] = sregs
.u
.e
.ivor_low
[9];
1084 kvm_sync_excp(env
, POWERPC_EXCP_APU
, SPR_BOOKE_IVOR9
);
1085 env
->spr
[SPR_BOOKE_IVOR10
] = sregs
.u
.e
.ivor_low
[10];
1086 kvm_sync_excp(env
, POWERPC_EXCP_DECR
, SPR_BOOKE_IVOR10
);
1087 env
->spr
[SPR_BOOKE_IVOR11
] = sregs
.u
.e
.ivor_low
[11];
1088 kvm_sync_excp(env
, POWERPC_EXCP_FIT
, SPR_BOOKE_IVOR11
);
1089 env
->spr
[SPR_BOOKE_IVOR12
] = sregs
.u
.e
.ivor_low
[12];
1090 kvm_sync_excp(env
, POWERPC_EXCP_WDT
, SPR_BOOKE_IVOR12
);
1091 env
->spr
[SPR_BOOKE_IVOR13
] = sregs
.u
.e
.ivor_low
[13];
1092 kvm_sync_excp(env
, POWERPC_EXCP_DTLB
, SPR_BOOKE_IVOR13
);
1093 env
->spr
[SPR_BOOKE_IVOR14
] = sregs
.u
.e
.ivor_low
[14];
1094 kvm_sync_excp(env
, POWERPC_EXCP_ITLB
, SPR_BOOKE_IVOR14
);
1095 env
->spr
[SPR_BOOKE_IVOR15
] = sregs
.u
.e
.ivor_low
[15];
1096 kvm_sync_excp(env
, POWERPC_EXCP_DEBUG
, SPR_BOOKE_IVOR15
);
1098 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPE
) {
1099 env
->spr
[SPR_BOOKE_IVOR32
] = sregs
.u
.e
.ivor_high
[0];
1100 kvm_sync_excp(env
, POWERPC_EXCP_SPEU
, SPR_BOOKE_IVOR32
);
1101 env
->spr
[SPR_BOOKE_IVOR33
] = sregs
.u
.e
.ivor_high
[1];
1102 kvm_sync_excp(env
, POWERPC_EXCP_EFPDI
, SPR_BOOKE_IVOR33
);
1103 env
->spr
[SPR_BOOKE_IVOR34
] = sregs
.u
.e
.ivor_high
[2];
1104 kvm_sync_excp(env
, POWERPC_EXCP_EFPRI
, SPR_BOOKE_IVOR34
);
1107 if (sregs
.u
.e
.features
& KVM_SREGS_E_PM
) {
1108 env
->spr
[SPR_BOOKE_IVOR35
] = sregs
.u
.e
.ivor_high
[3];
1109 kvm_sync_excp(env
, POWERPC_EXCP_EPERFM
, SPR_BOOKE_IVOR35
);
1112 if (sregs
.u
.e
.features
& KVM_SREGS_E_PC
) {
1113 env
->spr
[SPR_BOOKE_IVOR36
] = sregs
.u
.e
.ivor_high
[4];
1114 kvm_sync_excp(env
, POWERPC_EXCP_DOORI
, SPR_BOOKE_IVOR36
);
1115 env
->spr
[SPR_BOOKE_IVOR37
] = sregs
.u
.e
.ivor_high
[5];
1116 kvm_sync_excp(env
, POWERPC_EXCP_DOORCI
, SPR_BOOKE_IVOR37
);
1120 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206_MMU
) {
1121 env
->spr
[SPR_BOOKE_MAS0
] = sregs
.u
.e
.mas0
;
1122 env
->spr
[SPR_BOOKE_MAS1
] = sregs
.u
.e
.mas1
;
1123 env
->spr
[SPR_BOOKE_MAS2
] = sregs
.u
.e
.mas2
;
1124 env
->spr
[SPR_BOOKE_MAS3
] = sregs
.u
.e
.mas7_3
& 0xffffffff;
1125 env
->spr
[SPR_BOOKE_MAS4
] = sregs
.u
.e
.mas4
;
1126 env
->spr
[SPR_BOOKE_MAS6
] = sregs
.u
.e
.mas6
;
1127 env
->spr
[SPR_BOOKE_MAS7
] = sregs
.u
.e
.mas7_3
>> 32;
1128 env
->spr
[SPR_MMUCFG
] = sregs
.u
.e
.mmucfg
;
1129 env
->spr
[SPR_BOOKE_TLB0CFG
] = sregs
.u
.e
.tlbcfg
[0];
1130 env
->spr
[SPR_BOOKE_TLB1CFG
] = sregs
.u
.e
.tlbcfg
[1];
1133 if (sregs
.u
.e
.features
& KVM_SREGS_EXP
) {
1134 env
->spr
[SPR_BOOKE_EPR
] = sregs
.u
.e
.epr
;
1137 if (sregs
.u
.e
.features
& KVM_SREGS_E_PD
) {
1138 env
->spr
[SPR_BOOKE_EPLC
] = sregs
.u
.e
.eplc
;
1139 env
->spr
[SPR_BOOKE_EPSC
] = sregs
.u
.e
.epsc
;
1142 if (sregs
.u
.e
.impl_id
== KVM_SREGS_E_IMPL_FSL
) {
1143 env
->spr
[SPR_E500_SVR
] = sregs
.u
.e
.impl
.fsl
.svr
;
1144 env
->spr
[SPR_Exxx_MCAR
] = sregs
.u
.e
.impl
.fsl
.mcar
;
1145 env
->spr
[SPR_HID0
] = sregs
.u
.e
.impl
.fsl
.hid0
;
1147 if (sregs
.u
.e
.impl
.fsl
.features
& KVM_SREGS_E_FSL_PIDn
) {
1148 env
->spr
[SPR_BOOKE_PID1
] = sregs
.u
.e
.impl
.fsl
.pid1
;
1149 env
->spr
[SPR_BOOKE_PID2
] = sregs
.u
.e
.impl
.fsl
.pid2
;
1156 static int kvmppc_get_books_sregs(PowerPCCPU
*cpu
)
1158 CPUPPCState
*env
= &cpu
->env
;
1159 struct kvm_sregs sregs
;
1163 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1169 ppc_store_sdr1(env
, sregs
.u
.s
.sdr1
);
1175 * The packed SLB array we get from KVM_GET_SREGS only contains
1176 * information about valid entries. So we flush our internal copy
1177 * to get rid of stale ones, then put all valid SLB entries back
1180 memset(env
->slb
, 0, sizeof(env
->slb
));
1181 for (i
= 0; i
< ARRAY_SIZE(env
->slb
); i
++) {
1182 target_ulong rb
= sregs
.u
.s
.ppc64
.slb
[i
].slbe
;
1183 target_ulong rs
= sregs
.u
.s
.ppc64
.slb
[i
].slbv
;
1185 * Only restore valid entries
1187 if (rb
& SLB_ESID_V
) {
1188 ppc_store_slb(cpu
, rb
& 0xfff, rb
& ~0xfffULL
, rs
);
1194 for (i
= 0; i
< 16; i
++) {
1195 env
->sr
[i
] = sregs
.u
.s
.ppc32
.sr
[i
];
1199 for (i
= 0; i
< 8; i
++) {
1200 env
->DBAT
[0][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] & 0xffffffff;
1201 env
->DBAT
[1][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] >> 32;
1202 env
->IBAT
[0][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] & 0xffffffff;
1203 env
->IBAT
[1][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] >> 32;
1209 int kvm_arch_get_registers(CPUState
*cs
)
1211 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1212 CPUPPCState
*env
= &cpu
->env
;
1213 struct kvm_regs regs
;
1217 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
1223 for (i
= 7; i
>= 0; i
--) {
1224 env
->crf
[i
] = cr
& 15;
1228 env
->ctr
= regs
.ctr
;
1230 cpu_write_xer(env
, regs
.xer
);
1231 env
->msr
= regs
.msr
;
1234 env
->spr
[SPR_SRR0
] = regs
.srr0
;
1235 env
->spr
[SPR_SRR1
] = regs
.srr1
;
1237 env
->spr
[SPR_SPRG0
] = regs
.sprg0
;
1238 env
->spr
[SPR_SPRG1
] = regs
.sprg1
;
1239 env
->spr
[SPR_SPRG2
] = regs
.sprg2
;
1240 env
->spr
[SPR_SPRG3
] = regs
.sprg3
;
1241 env
->spr
[SPR_SPRG4
] = regs
.sprg4
;
1242 env
->spr
[SPR_SPRG5
] = regs
.sprg5
;
1243 env
->spr
[SPR_SPRG6
] = regs
.sprg6
;
1244 env
->spr
[SPR_SPRG7
] = regs
.sprg7
;
1246 env
->spr
[SPR_BOOKE_PID
] = regs
.pid
;
1248 for (i
= 0; i
< 32; i
++) {
1249 env
->gpr
[i
] = regs
.gpr
[i
];
1254 if (cap_booke_sregs
) {
1255 ret
= kvmppc_get_booke_sregs(cpu
);
1262 ret
= kvmppc_get_books_sregs(cpu
);
1269 kvm_get_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
1276 * We deliberately ignore errors here, for kernels which have
1277 * the ONE_REG calls, but don't support the specific
1278 * registers, there's a reasonable chance things will still
1279 * work, at least until we try to migrate.
1281 for (i
= 0; i
< 1024; i
++) {
1282 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
1285 kvm_get_one_spr(cs
, id
, i
);
1291 for (i
= 0; i
< ARRAY_SIZE(env
->tm_gpr
); i
++) {
1292 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_GPR(i
), &env
->tm_gpr
[i
]);
1294 for (i
= 0; i
< ARRAY_SIZE(env
->tm_vsr
); i
++) {
1295 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VSR(i
), &env
->tm_vsr
[i
]);
1297 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_CR
, &env
->tm_cr
);
1298 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_LR
, &env
->tm_lr
);
1299 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_CTR
, &env
->tm_ctr
);
1300 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_FPSCR
, &env
->tm_fpscr
);
1301 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_AMR
, &env
->tm_amr
);
1302 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_PPR
, &env
->tm_ppr
);
1303 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VRSAVE
, &env
->tm_vrsave
);
1304 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VSCR
, &env
->tm_vscr
);
1305 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_DSCR
, &env
->tm_dscr
);
1306 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_TAR
, &env
->tm_tar
);
1310 if (kvm_get_vpa(cs
) < 0) {
1311 trace_kvm_failed_get_vpa();
1315 kvm_get_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &env
->tb_env
->tb_offset
);
1322 int kvmppc_set_interrupt(PowerPCCPU
*cpu
, int irq
, int level
)
1324 unsigned virq
= level
? KVM_INTERRUPT_SET_LEVEL
: KVM_INTERRUPT_UNSET
;
1326 if (irq
!= PPC_INTERRUPT_EXT
) {
1330 if (!kvm_enabled() || !cap_interrupt_unset
|| !cap_interrupt_level
) {
1334 kvm_vcpu_ioctl(CPU(cpu
), KVM_INTERRUPT
, &virq
);
1339 #if defined(TARGET_PPC64)
1340 #define PPC_INPUT_INT PPC970_INPUT_INT
1342 #define PPC_INPUT_INT PPC6xx_INPUT_INT
1345 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
1347 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1348 CPUPPCState
*env
= &cpu
->env
;
1352 qemu_mutex_lock_iothread();
1355 * PowerPC QEMU tracks the various core input pins (interrupt,
1356 * critical interrupt, reset, etc) in PPC-specific
1357 * env->irq_input_state.
1359 if (!cap_interrupt_level
&&
1360 run
->ready_for_interrupt_injection
&&
1361 (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1362 (env
->irq_input_state
& (1 << PPC_INPUT_INT
)))
1365 * For now KVM disregards the 'irq' argument. However, in the
1366 * future KVM could cache it in-kernel to avoid a heavyweight
1367 * exit when reading the UIC.
1369 irq
= KVM_INTERRUPT_SET
;
1371 trace_kvm_injected_interrupt(irq
);
1372 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &irq
);
1374 printf("cpu %d fail inject %x\n", cs
->cpu_index
, irq
);
1377 /* Always wake up soon in case the interrupt was level based */
1378 timer_mod(idle_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1379 (NANOSECONDS_PER_SECOND
/ 50));
1383 * We don't know if there are more interrupts pending after
1384 * this. However, the guest will return to userspace in the course
1385 * of handling this one anyways, so we will get a chance to
1389 qemu_mutex_unlock_iothread();
1392 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
1394 return MEMTXATTRS_UNSPECIFIED
;
1397 int kvm_arch_process_async_events(CPUState
*cs
)
1402 static int kvmppc_handle_halt(PowerPCCPU
*cpu
)
1404 CPUState
*cs
= CPU(cpu
);
1405 CPUPPCState
*env
= &cpu
->env
;
1407 if (!(cs
->interrupt_request
& CPU_INTERRUPT_HARD
) && (msr_ee
)) {
1409 cs
->exception_index
= EXCP_HLT
;
1415 /* map dcr access to existing qemu dcr emulation */
1416 static int kvmppc_handle_dcr_read(CPUPPCState
*env
,
1417 uint32_t dcrn
, uint32_t *data
)
1419 if (ppc_dcr_read(env
->dcr_env
, dcrn
, data
) < 0) {
1420 fprintf(stderr
, "Read to unhandled DCR (0x%x)\n", dcrn
);
1426 static int kvmppc_handle_dcr_write(CPUPPCState
*env
,
1427 uint32_t dcrn
, uint32_t data
)
1429 if (ppc_dcr_write(env
->dcr_env
, dcrn
, data
) < 0) {
1430 fprintf(stderr
, "Write to unhandled DCR (0x%x)\n", dcrn
);
1436 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1438 /* Mixed endian case is not handled */
1439 uint32_t sc
= debug_inst_opcode
;
1441 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
,
1443 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&sc
, sizeof(sc
), 1)) {
1450 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1454 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&sc
, sizeof(sc
), 0) ||
1455 sc
!= debug_inst_opcode
||
1456 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
,
1464 static int find_hw_breakpoint(target_ulong addr
, int type
)
1468 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
)
1469 <= ARRAY_SIZE(hw_debug_points
));
1471 for (n
= 0; n
< nb_hw_breakpoint
+ nb_hw_watchpoint
; n
++) {
1472 if (hw_debug_points
[n
].addr
== addr
&&
1473 hw_debug_points
[n
].type
== type
) {
1481 static int find_hw_watchpoint(target_ulong addr
, int *flag
)
1485 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_ACCESS
);
1487 *flag
= BP_MEM_ACCESS
;
1491 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_WRITE
);
1493 *flag
= BP_MEM_WRITE
;
1497 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_READ
);
1499 *flag
= BP_MEM_READ
;
1506 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1507 target_ulong len
, int type
)
1509 if ((nb_hw_breakpoint
+ nb_hw_watchpoint
) >= ARRAY_SIZE(hw_debug_points
)) {
1513 hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
].addr
= addr
;
1514 hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
].type
= type
;
1517 case GDB_BREAKPOINT_HW
:
1518 if (nb_hw_breakpoint
>= max_hw_breakpoint
) {
1522 if (find_hw_breakpoint(addr
, type
) >= 0) {
1529 case GDB_WATCHPOINT_WRITE
:
1530 case GDB_WATCHPOINT_READ
:
1531 case GDB_WATCHPOINT_ACCESS
:
1532 if (nb_hw_watchpoint
>= max_hw_watchpoint
) {
1536 if (find_hw_breakpoint(addr
, type
) >= 0) {
1550 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1551 target_ulong len
, int type
)
1555 n
= find_hw_breakpoint(addr
, type
);
1561 case GDB_BREAKPOINT_HW
:
1565 case GDB_WATCHPOINT_WRITE
:
1566 case GDB_WATCHPOINT_READ
:
1567 case GDB_WATCHPOINT_ACCESS
:
1574 hw_debug_points
[n
] = hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
];
1579 void kvm_arch_remove_all_hw_breakpoints(void)
1581 nb_hw_breakpoint
= nb_hw_watchpoint
= 0;
1584 void kvm_arch_update_guest_debug(CPUState
*cs
, struct kvm_guest_debug
*dbg
)
1588 /* Software Breakpoint updates */
1589 if (kvm_sw_breakpoints_active(cs
)) {
1590 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1593 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
)
1594 <= ARRAY_SIZE(hw_debug_points
));
1595 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
) <= ARRAY_SIZE(dbg
->arch
.bp
));
1597 if (nb_hw_breakpoint
+ nb_hw_watchpoint
> 0) {
1598 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1599 memset(dbg
->arch
.bp
, 0, sizeof(dbg
->arch
.bp
));
1600 for (n
= 0; n
< nb_hw_breakpoint
+ nb_hw_watchpoint
; n
++) {
1601 switch (hw_debug_points
[n
].type
) {
1602 case GDB_BREAKPOINT_HW
:
1603 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_BREAKPOINT
;
1605 case GDB_WATCHPOINT_WRITE
:
1606 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_WRITE
;
1608 case GDB_WATCHPOINT_READ
:
1609 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_READ
;
1611 case GDB_WATCHPOINT_ACCESS
:
1612 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_WRITE
|
1613 KVMPPC_DEBUG_WATCH_READ
;
1616 cpu_abort(cs
, "Unsupported breakpoint type\n");
1618 dbg
->arch
.bp
[n
].addr
= hw_debug_points
[n
].addr
;
1623 static int kvm_handle_hw_breakpoint(CPUState
*cs
,
1624 struct kvm_debug_exit_arch
*arch_info
)
1630 if (nb_hw_breakpoint
+ nb_hw_watchpoint
> 0) {
1631 if (arch_info
->status
& KVMPPC_DEBUG_BREAKPOINT
) {
1632 n
= find_hw_breakpoint(arch_info
->address
, GDB_BREAKPOINT_HW
);
1636 } else if (arch_info
->status
& (KVMPPC_DEBUG_WATCH_READ
|
1637 KVMPPC_DEBUG_WATCH_WRITE
)) {
1638 n
= find_hw_watchpoint(arch_info
->address
, &flag
);
1641 cs
->watchpoint_hit
= &hw_watchpoint
;
1642 hw_watchpoint
.vaddr
= hw_debug_points
[n
].addr
;
1643 hw_watchpoint
.flags
= flag
;
1650 static int kvm_handle_singlestep(void)
1655 static int kvm_handle_sw_breakpoint(void)
1660 static int kvm_handle_debug(PowerPCCPU
*cpu
, struct kvm_run
*run
)
1662 CPUState
*cs
= CPU(cpu
);
1663 CPUPPCState
*env
= &cpu
->env
;
1664 struct kvm_debug_exit_arch
*arch_info
= &run
->debug
.arch
;
1666 if (cs
->singlestep_enabled
) {
1667 return kvm_handle_singlestep();
1670 if (arch_info
->status
) {
1671 return kvm_handle_hw_breakpoint(cs
, arch_info
);
1674 if (kvm_find_sw_breakpoint(cs
, arch_info
->address
)) {
1675 return kvm_handle_sw_breakpoint();
1679 * QEMU is not able to handle debug exception, so inject
1680 * program exception to guest;
1681 * Yes program exception NOT debug exception !!
1682 * When QEMU is using debug resources then debug exception must
1683 * be always set. To achieve this we set MSR_DE and also set
1684 * MSRP_DEP so guest cannot change MSR_DE.
1685 * When emulating debug resource for guest we want guest
1686 * to control MSR_DE (enable/disable debug interrupt on need).
1687 * Supporting both configurations are NOT possible.
1688 * So the result is that we cannot share debug resources
1689 * between QEMU and Guest on BOOKE architecture.
1690 * In the current design QEMU gets the priority over guest,
1691 * this means that if QEMU is using debug resources then guest
1693 * For software breakpoint QEMU uses a privileged instruction;
1694 * So there cannot be any reason that we are here for guest
1695 * set debug exception, only possibility is guest executed a
1696 * privileged / illegal instruction and that's why we are
1697 * injecting a program interrupt.
1699 cpu_synchronize_state(cs
);
1701 * env->nip is PC, so increment this by 4 to use
1702 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1705 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
1706 env
->error_code
= POWERPC_EXCP_INVAL
;
1707 ppc_cpu_do_interrupt(cs
);
1712 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
1714 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1715 CPUPPCState
*env
= &cpu
->env
;
1718 qemu_mutex_lock_iothread();
1720 switch (run
->exit_reason
) {
1722 if (run
->dcr
.is_write
) {
1723 trace_kvm_handle_dcr_write();
1724 ret
= kvmppc_handle_dcr_write(env
, run
->dcr
.dcrn
, run
->dcr
.data
);
1726 trace_kvm_handle_dcr_read();
1727 ret
= kvmppc_handle_dcr_read(env
, run
->dcr
.dcrn
, &run
->dcr
.data
);
1731 trace_kvm_handle_halt();
1732 ret
= kvmppc_handle_halt(cpu
);
1734 #if defined(TARGET_PPC64)
1735 case KVM_EXIT_PAPR_HCALL
:
1736 trace_kvm_handle_papr_hcall();
1737 run
->papr_hcall
.ret
= spapr_hypercall(cpu
,
1739 run
->papr_hcall
.args
);
1744 trace_kvm_handle_epr();
1745 run
->epr
.epr
= ldl_phys(cs
->as
, env
->mpic_iack
);
1748 case KVM_EXIT_WATCHDOG
:
1749 trace_kvm_handle_watchdog_expiry();
1750 watchdog_perform_action();
1754 case KVM_EXIT_DEBUG
:
1755 trace_kvm_handle_debug_exception();
1756 if (kvm_handle_debug(cpu
, run
)) {
1760 /* re-enter, this exception was guest-internal */
1765 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
1770 qemu_mutex_unlock_iothread();
1774 int kvmppc_or_tsr_bits(PowerPCCPU
*cpu
, uint32_t tsr_bits
)
1776 CPUState
*cs
= CPU(cpu
);
1777 uint32_t bits
= tsr_bits
;
1778 struct kvm_one_reg reg
= {
1779 .id
= KVM_REG_PPC_OR_TSR
,
1780 .addr
= (uintptr_t) &bits
,
1783 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1786 int kvmppc_clear_tsr_bits(PowerPCCPU
*cpu
, uint32_t tsr_bits
)
1789 CPUState
*cs
= CPU(cpu
);
1790 uint32_t bits
= tsr_bits
;
1791 struct kvm_one_reg reg
= {
1792 .id
= KVM_REG_PPC_CLEAR_TSR
,
1793 .addr
= (uintptr_t) &bits
,
1796 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1799 int kvmppc_set_tcr(PowerPCCPU
*cpu
)
1801 CPUState
*cs
= CPU(cpu
);
1802 CPUPPCState
*env
= &cpu
->env
;
1803 uint32_t tcr
= env
->spr
[SPR_BOOKE_TCR
];
1805 struct kvm_one_reg reg
= {
1806 .id
= KVM_REG_PPC_TCR
,
1807 .addr
= (uintptr_t) &tcr
,
1810 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1813 int kvmppc_booke_watchdog_enable(PowerPCCPU
*cpu
)
1815 CPUState
*cs
= CPU(cpu
);
1818 if (!kvm_enabled()) {
1822 if (!cap_ppc_watchdog
) {
1823 printf("warning: KVM does not support watchdog");
1827 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_BOOKE_WATCHDOG
, 0);
1829 fprintf(stderr
, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1830 __func__
, strerror(-ret
));
1837 static int read_cpuinfo(const char *field
, char *value
, int len
)
1841 int field_len
= strlen(field
);
1844 f
= fopen("/proc/cpuinfo", "r");
1850 if (!fgets(line
, sizeof(line
), f
)) {
1853 if (!strncmp(line
, field
, field_len
)) {
1854 pstrcpy(value
, len
, line
);
1865 uint32_t kvmppc_get_tbfreq(void)
1869 uint32_t retval
= NANOSECONDS_PER_SECOND
;
1871 if (read_cpuinfo("timebase", line
, sizeof(line
))) {
1875 ns
= strchr(line
, ':');
1885 bool kvmppc_get_host_serial(char **value
)
1887 return g_file_get_contents("/proc/device-tree/system-id", value
, NULL
,
1891 bool kvmppc_get_host_model(char **value
)
1893 return g_file_get_contents("/proc/device-tree/model", value
, NULL
, NULL
);
1896 /* Try to find a device tree node for a CPU with clock-frequency property */
1897 static int kvmppc_find_cpu_dt(char *buf
, int buf_len
)
1899 struct dirent
*dirp
;
1902 dp
= opendir(PROC_DEVTREE_CPU
);
1904 printf("Can't open directory " PROC_DEVTREE_CPU
"\n");
1909 while ((dirp
= readdir(dp
)) != NULL
) {
1911 snprintf(buf
, buf_len
, "%s%s/clock-frequency", PROC_DEVTREE_CPU
,
1913 f
= fopen(buf
, "r");
1915 snprintf(buf
, buf_len
, "%s%s", PROC_DEVTREE_CPU
, dirp
->d_name
);
1922 if (buf
[0] == '\0') {
1923 printf("Unknown host!\n");
1930 static uint64_t kvmppc_read_int_dt(const char *filename
)
1939 f
= fopen(filename
, "rb");
1944 len
= fread(&u
, 1, sizeof(u
), f
);
1948 /* property is a 32-bit quantity */
1949 return be32_to_cpu(u
.v32
);
1951 return be64_to_cpu(u
.v64
);
1958 * Read a CPU node property from the host device tree that's a single
1959 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1960 * (can't find or open the property, or doesn't understand the format)
1962 static uint64_t kvmppc_read_int_cpu_dt(const char *propname
)
1964 char buf
[PATH_MAX
], *tmp
;
1967 if (kvmppc_find_cpu_dt(buf
, sizeof(buf
))) {
1971 tmp
= g_strdup_printf("%s/%s", buf
, propname
);
1972 val
= kvmppc_read_int_dt(tmp
);
1978 uint64_t kvmppc_get_clockfreq(void)
1980 return kvmppc_read_int_cpu_dt("clock-frequency");
1983 static int kvmppc_get_dec_bits(void)
1985 int nr_bits
= kvmppc_read_int_cpu_dt("ibm,dec-bits");
1993 static int kvmppc_get_pvinfo(CPUPPCState
*env
, struct kvm_ppc_pvinfo
*pvinfo
)
1995 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
1996 CPUState
*cs
= CPU(cpu
);
1998 if (kvm_vm_check_extension(cs
->kvm_state
, KVM_CAP_PPC_GET_PVINFO
) &&
1999 !kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_GET_PVINFO
, pvinfo
)) {
2006 int kvmppc_get_hasidle(CPUPPCState
*env
)
2008 struct kvm_ppc_pvinfo pvinfo
;
2010 if (!kvmppc_get_pvinfo(env
, &pvinfo
) &&
2011 (pvinfo
.flags
& KVM_PPC_PVINFO_FLAGS_EV_IDLE
)) {
2018 int kvmppc_get_hypercall(CPUPPCState
*env
, uint8_t *buf
, int buf_len
)
2020 uint32_t *hc
= (uint32_t *)buf
;
2021 struct kvm_ppc_pvinfo pvinfo
;
2023 if (!kvmppc_get_pvinfo(env
, &pvinfo
)) {
2024 memcpy(buf
, pvinfo
.hcall
, buf_len
);
2029 * Fallback to always fail hypercalls regardless of endianness:
2031 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
2033 * b .+8 (becomes nop in wrong endian)
2034 * bswap32(li r3, -1)
2037 hc
[0] = cpu_to_be32(0x08000048);
2038 hc
[1] = cpu_to_be32(0x3860ffff);
2039 hc
[2] = cpu_to_be32(0x48000008);
2040 hc
[3] = cpu_to_be32(bswap32(0x3860ffff));
2045 static inline int kvmppc_enable_hcall(KVMState
*s
, target_ulong hcall
)
2047 return kvm_vm_enable_cap(s
, KVM_CAP_PPC_ENABLE_HCALL
, 0, hcall
, 1);
2050 void kvmppc_enable_logical_ci_hcalls(void)
2053 * FIXME: it would be nice if we could detect the cases where
2054 * we're using a device which requires the in kernel
2055 * implementation of these hcalls, but the kernel lacks them and
2056 * produce a warning.
2058 kvmppc_enable_hcall(kvm_state
, H_LOGICAL_CI_LOAD
);
2059 kvmppc_enable_hcall(kvm_state
, H_LOGICAL_CI_STORE
);
2062 void kvmppc_enable_set_mode_hcall(void)
2064 kvmppc_enable_hcall(kvm_state
, H_SET_MODE
);
2067 void kvmppc_enable_clear_ref_mod_hcalls(void)
2069 kvmppc_enable_hcall(kvm_state
, H_CLEAR_REF
);
2070 kvmppc_enable_hcall(kvm_state
, H_CLEAR_MOD
);
2073 void kvmppc_enable_h_page_init(void)
2075 kvmppc_enable_hcall(kvm_state
, H_PAGE_INIT
);
2078 void kvmppc_set_papr(PowerPCCPU
*cpu
)
2080 CPUState
*cs
= CPU(cpu
);
2083 if (!kvm_enabled()) {
2087 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_PAPR
, 0);
2089 error_report("This vCPU type or KVM version does not support PAPR");
2094 * Update the capability flag so we sync the right information
2100 int kvmppc_set_compat(PowerPCCPU
*cpu
, uint32_t compat_pvr
)
2102 return kvm_set_one_reg(CPU(cpu
), KVM_REG_PPC_ARCH_COMPAT
, &compat_pvr
);
2105 void kvmppc_set_mpic_proxy(PowerPCCPU
*cpu
, int mpic_proxy
)
2107 CPUState
*cs
= CPU(cpu
);
2110 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_EPR
, 0, mpic_proxy
);
2111 if (ret
&& mpic_proxy
) {
2112 error_report("This KVM version does not support EPR");
2117 int kvmppc_smt_threads(void)
2119 return cap_ppc_smt
? cap_ppc_smt
: 1;
2122 int kvmppc_set_smt_threads(int smt
)
2126 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_SMT
, 0, smt
, 0);
2133 void kvmppc_hint_smt_possible(Error
**errp
)
2139 assert(kvm_enabled());
2140 if (cap_ppc_smt_possible
) {
2141 g
= g_string_new("Available VSMT modes:");
2142 for (i
= 63; i
>= 0; i
--) {
2143 if ((1UL << i
) & cap_ppc_smt_possible
) {
2144 g_string_append_printf(g
, " %lu", (1UL << i
));
2147 s
= g_string_free(g
, false);
2148 error_append_hint(errp
, "%s.\n", s
);
2151 error_append_hint(errp
,
2152 "This KVM seems to be too old to support VSMT.\n");
2158 uint64_t kvmppc_rma_size(uint64_t current_size
, unsigned int hash_shift
)
2160 struct kvm_ppc_smmu_info info
;
2161 long rampagesize
, best_page_shift
;
2165 * Find the largest hardware supported page size that's less than
2166 * or equal to the (logical) backing page size of guest RAM
2168 kvm_get_smmu_info(&info
, &error_fatal
);
2169 rampagesize
= qemu_minrampagesize();
2170 best_page_shift
= 0;
2172 for (i
= 0; i
< KVM_PPC_PAGE_SIZES_MAX_SZ
; i
++) {
2173 struct kvm_ppc_one_seg_page_size
*sps
= &info
.sps
[i
];
2175 if (!sps
->page_shift
) {
2179 if ((sps
->page_shift
> best_page_shift
)
2180 && ((1UL << sps
->page_shift
) <= rampagesize
)) {
2181 best_page_shift
= sps
->page_shift
;
2185 return MIN(current_size
,
2186 1ULL << (best_page_shift
+ hash_shift
- 7));
2190 bool kvmppc_spapr_use_multitce(void)
2192 return cap_spapr_multitce
;
2195 int kvmppc_spapr_enable_inkernel_multitce(void)
2199 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_ENABLE_HCALL
, 0,
2200 H_PUT_TCE_INDIRECT
, 1);
2202 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_ENABLE_HCALL
, 0,
2209 void *kvmppc_create_spapr_tce(uint32_t liobn
, uint32_t page_shift
,
2210 uint64_t bus_offset
, uint32_t nb_table
,
2211 int *pfd
, bool need_vfio
)
2218 * Must set fd to -1 so we don't try to munmap when called for
2219 * destroying the table, which the upper layers -will- do
2222 if (!cap_spapr_tce
|| (need_vfio
&& !cap_spapr_vfio
)) {
2226 if (cap_spapr_tce_64
) {
2227 struct kvm_create_spapr_tce_64 args
= {
2229 .page_shift
= page_shift
,
2230 .offset
= bus_offset
>> page_shift
,
2234 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE_64
, &args
);
2237 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2241 } else if (cap_spapr_tce
) {
2242 uint64_t window_size
= (uint64_t) nb_table
<< page_shift
;
2243 struct kvm_create_spapr_tce args
= {
2245 .window_size
= window_size
,
2247 if ((window_size
!= args
.window_size
) || bus_offset
) {
2250 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE
, &args
);
2252 fprintf(stderr
, "KVM: Failed to create TCE table for liobn 0x%x\n",
2260 len
= nb_table
* sizeof(uint64_t);
2261 /* FIXME: round this up to page size */
2263 table
= mmap(NULL
, len
, PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, 0);
2264 if (table
== MAP_FAILED
) {
2265 fprintf(stderr
, "KVM: Failed to map TCE table for liobn 0x%x\n",
2275 int kvmppc_remove_spapr_tce(void *table
, int fd
, uint32_t nb_table
)
2283 len
= nb_table
* sizeof(uint64_t);
2284 if ((munmap(table
, len
) < 0) ||
2286 fprintf(stderr
, "KVM: Unexpected error removing TCE table: %s",
2288 /* Leak the table */
2294 int kvmppc_reset_htab(int shift_hint
)
2296 uint32_t shift
= shift_hint
;
2298 if (!kvm_enabled()) {
2299 /* Full emulation, tell caller to allocate htab itself */
2302 if (kvm_vm_check_extension(kvm_state
, KVM_CAP_PPC_ALLOC_HTAB
)) {
2304 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_ALLOCATE_HTAB
, &shift
);
2305 if (ret
== -ENOTTY
) {
2307 * At least some versions of PR KVM advertise the
2308 * capability, but don't implement the ioctl(). Oops.
2309 * Return 0 so that we allocate the htab in qemu, as is
2313 } else if (ret
< 0) {
2320 * We have a kernel that predates the htab reset calls. For PR
2321 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2322 * this era, it has allocated a 16MB fixed size hash table
2325 if (kvmppc_is_pr(kvm_state
)) {
2326 /* PR - tell caller to allocate htab */
2329 /* HV - assume 16MB kernel allocated htab */
2334 static inline uint32_t mfpvr(void)
2343 static void alter_insns(uint64_t *word
, uint64_t flags
, bool on
)
2352 static void kvmppc_host_cpu_class_init(ObjectClass
*oc
, void *data
)
2354 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2355 uint32_t dcache_size
= kvmppc_read_int_cpu_dt("d-cache-size");
2356 uint32_t icache_size
= kvmppc_read_int_cpu_dt("i-cache-size");
2358 /* Now fix up the class with information we can query from the host */
2361 alter_insns(&pcc
->insns_flags
, PPC_ALTIVEC
,
2362 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_ALTIVEC
);
2363 alter_insns(&pcc
->insns_flags2
, PPC2_VSX
,
2364 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_VSX
);
2365 alter_insns(&pcc
->insns_flags2
, PPC2_DFP
,
2366 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_DFP
);
2368 if (dcache_size
!= -1) {
2369 pcc
->l1_dcache_size
= dcache_size
;
2372 if (icache_size
!= -1) {
2373 pcc
->l1_icache_size
= icache_size
;
2376 #if defined(TARGET_PPC64)
2377 pcc
->radix_page_info
= kvm_get_radix_page_info();
2379 if ((pcc
->pvr
& 0xffffff00) == CPU_POWERPC_POWER9_DD1
) {
2381 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2382 * compliant. More importantly, advertising ISA 3.00
2383 * architected mode may prevent guests from activating
2384 * necessary DD1 workarounds.
2386 pcc
->pcr_supported
&= ~(PCR_COMPAT_3_00
| PCR_COMPAT_2_07
2387 | PCR_COMPAT_2_06
| PCR_COMPAT_2_05
);
2389 #endif /* defined(TARGET_PPC64) */
2392 bool kvmppc_has_cap_epr(void)
2397 bool kvmppc_has_cap_fixup_hcalls(void)
2399 return cap_fixup_hcalls
;
2402 bool kvmppc_has_cap_htm(void)
2407 bool kvmppc_has_cap_mmu_radix(void)
2409 return cap_mmu_radix
;
2412 bool kvmppc_has_cap_mmu_hash_v3(void)
2414 return cap_mmu_hash_v3
;
2417 static bool kvmppc_power8_host(void)
2422 uint32_t base_pvr
= CPU_POWERPC_POWER_SERVER_MASK
& mfpvr();
2423 ret
= (base_pvr
== CPU_POWERPC_POWER8E_BASE
) ||
2424 (base_pvr
== CPU_POWERPC_POWER8NVL_BASE
) ||
2425 (base_pvr
== CPU_POWERPC_POWER8_BASE
);
2427 #endif /* TARGET_PPC64 */
2431 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c
)
2433 bool l1d_thread_priv_req
= !kvmppc_power8_host();
2435 if (~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_L1D_FLUSH_PR
) {
2437 } else if ((!l1d_thread_priv_req
||
2438 c
.character
& c
.character_mask
& H_CPU_CHAR_L1D_THREAD_PRIV
) &&
2439 (c
.character
& c
.character_mask
2440 & (H_CPU_CHAR_L1D_FLUSH_ORI30
| H_CPU_CHAR_L1D_FLUSH_TRIG2
))) {
2447 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c
)
2449 if (~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_BNDS_CHK_SPEC_BAR
) {
2451 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_SPEC_BAR_ORI31
) {
2458 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c
)
2460 if ((~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_FLUSH_COUNT_CACHE
) &&
2461 (~c
.character
& c
.character_mask
& H_CPU_CHAR_CACHE_COUNT_DIS
) &&
2462 (~c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTRL_SERIALISED
)) {
2463 return SPAPR_CAP_FIXED_NA
;
2464 } else if (c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_FLUSH_COUNT_CACHE
) {
2465 return SPAPR_CAP_WORKAROUND
;
2466 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_CACHE_COUNT_DIS
) {
2467 return SPAPR_CAP_FIXED_CCD
;
2468 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTRL_SERIALISED
) {
2469 return SPAPR_CAP_FIXED_IBS
;
2475 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c
)
2477 if (c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTR_FLUSH_ASSIST
) {
2483 bool kvmppc_has_cap_xive(void)
2488 static void kvmppc_get_cpu_characteristics(KVMState
*s
)
2490 struct kvm_ppc_cpu_char c
;
2494 cap_ppc_safe_cache
= 0;
2495 cap_ppc_safe_bounds_check
= 0;
2496 cap_ppc_safe_indirect_branch
= 0;
2498 ret
= kvm_vm_check_extension(s
, KVM_CAP_PPC_GET_CPU_CHAR
);
2502 ret
= kvm_vm_ioctl(s
, KVM_PPC_GET_CPU_CHAR
, &c
);
2507 cap_ppc_safe_cache
= parse_cap_ppc_safe_cache(c
);
2508 cap_ppc_safe_bounds_check
= parse_cap_ppc_safe_bounds_check(c
);
2509 cap_ppc_safe_indirect_branch
= parse_cap_ppc_safe_indirect_branch(c
);
2510 cap_ppc_count_cache_flush_assist
=
2511 parse_cap_ppc_count_cache_flush_assist(c
);
2514 int kvmppc_get_cap_safe_cache(void)
2516 return cap_ppc_safe_cache
;
2519 int kvmppc_get_cap_safe_bounds_check(void)
2521 return cap_ppc_safe_bounds_check
;
2524 int kvmppc_get_cap_safe_indirect_branch(void)
2526 return cap_ppc_safe_indirect_branch
;
2529 int kvmppc_get_cap_count_cache_flush_assist(void)
2531 return cap_ppc_count_cache_flush_assist
;
2534 bool kvmppc_has_cap_nested_kvm_hv(void)
2536 return !!cap_ppc_nested_kvm_hv
;
2539 int kvmppc_set_cap_nested_kvm_hv(int enable
)
2541 return kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_NESTED_HV
, 0, enable
);
2544 bool kvmppc_has_cap_spapr_vfio(void)
2546 return cap_spapr_vfio
;
2549 int kvmppc_get_cap_large_decr(void)
2551 return cap_large_decr
;
2554 int kvmppc_enable_cap_large_decr(PowerPCCPU
*cpu
, int enable
)
2556 CPUState
*cs
= CPU(cpu
);
2559 kvm_get_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2560 /* Do we need to modify the LPCR? */
2561 if (!!(lpcr
& LPCR_LD
) != !!enable
) {
2567 kvm_set_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2568 kvm_get_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2570 if (!!(lpcr
& LPCR_LD
) != !!enable
) {
2578 PowerPCCPUClass
*kvm_ppc_get_host_cpu_class(void)
2580 uint32_t host_pvr
= mfpvr();
2581 PowerPCCPUClass
*pvr_pcc
;
2583 pvr_pcc
= ppc_cpu_class_by_pvr(host_pvr
);
2584 if (pvr_pcc
== NULL
) {
2585 pvr_pcc
= ppc_cpu_class_by_pvr_mask(host_pvr
);
2591 static int kvm_ppc_register_host_cpu_type(MachineState
*ms
)
2593 TypeInfo type_info
= {
2594 .name
= TYPE_HOST_POWERPC_CPU
,
2595 .class_init
= kvmppc_host_cpu_class_init
,
2597 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2598 PowerPCCPUClass
*pvr_pcc
;
2603 pvr_pcc
= kvm_ppc_get_host_cpu_class();
2604 if (pvr_pcc
== NULL
) {
2607 type_info
.parent
= object_class_get_name(OBJECT_CLASS(pvr_pcc
));
2608 type_register(&type_info
);
2609 if (object_dynamic_cast(OBJECT(ms
), TYPE_SPAPR_MACHINE
)) {
2610 /* override TCG default cpu type with 'host' cpu model */
2611 mc
->default_cpu_type
= TYPE_HOST_POWERPC_CPU
;
2614 oc
= object_class_by_name(type_info
.name
);
2618 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2619 * we want "POWER8" to be a "family" alias that points to the current
2620 * host CPU type, too)
2622 dc
= DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc
));
2623 for (i
= 0; ppc_cpu_aliases
[i
].alias
!= NULL
; i
++) {
2624 if (strcasecmp(ppc_cpu_aliases
[i
].alias
, dc
->desc
) == 0) {
2627 ppc_cpu_aliases
[i
].model
= g_strdup(object_class_get_name(oc
));
2628 suffix
= strstr(ppc_cpu_aliases
[i
].model
, POWERPC_CPU_TYPE_SUFFIX
);
2639 int kvmppc_define_rtas_kernel_token(uint32_t token
, const char *function
)
2641 struct kvm_rtas_token_args args
= {
2645 if (!kvm_check_extension(kvm_state
, KVM_CAP_PPC_RTAS
)) {
2649 strncpy(args
.name
, function
, sizeof(args
.name
));
2651 return kvm_vm_ioctl(kvm_state
, KVM_PPC_RTAS_DEFINE_TOKEN
, &args
);
2654 int kvmppc_get_htab_fd(bool write
, uint64_t index
, Error
**errp
)
2656 struct kvm_get_htab_fd s
= {
2657 .flags
= write
? KVM_GET_HTAB_WRITE
: 0,
2658 .start_index
= index
,
2663 error_setg(errp
, "KVM version doesn't support %s the HPT",
2664 write
? "writing" : "reading");
2668 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_GET_HTAB_FD
, &s
);
2670 error_setg(errp
, "Unable to open fd for %s HPT %s KVM: %s",
2671 write
? "writing" : "reading", write
? "to" : "from",
2679 int kvmppc_save_htab(QEMUFile
*f
, int fd
, size_t bufsize
, int64_t max_ns
)
2681 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2682 uint8_t buf
[bufsize
];
2686 rc
= read(fd
, buf
, bufsize
);
2688 fprintf(stderr
, "Error reading data from KVM HTAB fd: %s\n",
2692 uint8_t *buffer
= buf
;
2695 struct kvm_get_htab_header
*head
=
2696 (struct kvm_get_htab_header
*) buffer
;
2697 size_t chunksize
= sizeof(*head
) +
2698 HASH_PTE_SIZE_64
* head
->n_valid
;
2700 qemu_put_be32(f
, head
->index
);
2701 qemu_put_be16(f
, head
->n_valid
);
2702 qemu_put_be16(f
, head
->n_invalid
);
2703 qemu_put_buffer(f
, (void *)(head
+ 1),
2704 HASH_PTE_SIZE_64
* head
->n_valid
);
2706 buffer
+= chunksize
;
2712 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) < max_ns
)));
2714 return (rc
== 0) ? 1 : 0;
2717 int kvmppc_load_htab_chunk(QEMUFile
*f
, int fd
, uint32_t index
,
2718 uint16_t n_valid
, uint16_t n_invalid
)
2720 struct kvm_get_htab_header
*buf
;
2721 size_t chunksize
= sizeof(*buf
) + n_valid
* HASH_PTE_SIZE_64
;
2724 buf
= alloca(chunksize
);
2726 buf
->n_valid
= n_valid
;
2727 buf
->n_invalid
= n_invalid
;
2729 qemu_get_buffer(f
, (void *)(buf
+ 1), HASH_PTE_SIZE_64
* n_valid
);
2731 rc
= write(fd
, buf
, chunksize
);
2733 fprintf(stderr
, "Error writing KVM hash table: %s\n",
2737 if (rc
!= chunksize
) {
2738 /* We should never get a short write on a single chunk */
2739 fprintf(stderr
, "Short write, restoring KVM hash table\n");
2745 bool kvm_arch_stop_on_emulation_error(CPUState
*cpu
)
2750 void kvm_arch_init_irq_routing(KVMState
*s
)
2754 void kvmppc_read_hptes(ppc_hash_pte64_t
*hptes
, hwaddr ptex
, int n
)
2759 fd
= kvmppc_get_htab_fd(false, ptex
, &error_abort
);
2763 struct kvm_get_htab_header
*hdr
;
2764 int m
= n
< HPTES_PER_GROUP
? n
: HPTES_PER_GROUP
;
2765 char buf
[sizeof(*hdr
) + m
* HASH_PTE_SIZE_64
];
2767 rc
= read(fd
, buf
, sizeof(buf
));
2769 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2772 hdr
= (struct kvm_get_htab_header
*)buf
;
2773 while ((i
< n
) && ((char *)hdr
< (buf
+ rc
))) {
2774 int invalid
= hdr
->n_invalid
, valid
= hdr
->n_valid
;
2776 if (hdr
->index
!= (ptex
+ i
)) {
2777 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2778 " != (%"HWADDR_PRIu
" + %d", hdr
->index
, ptex
, i
);
2781 if (n
- i
< valid
) {
2784 memcpy(hptes
+ i
, hdr
+ 1, HASH_PTE_SIZE_64
* valid
);
2787 if ((n
- i
) < invalid
) {
2790 memset(hptes
+ i
, 0, invalid
* HASH_PTE_SIZE_64
);
2793 hdr
= (struct kvm_get_htab_header
*)
2794 ((char *)(hdr
+ 1) + HASH_PTE_SIZE_64
* hdr
->n_valid
);
2801 void kvmppc_write_hpte(hwaddr ptex
, uint64_t pte0
, uint64_t pte1
)
2805 struct kvm_get_htab_header hdr
;
2810 fd
= kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort
);
2812 buf
.hdr
.n_valid
= 1;
2813 buf
.hdr
.n_invalid
= 0;
2814 buf
.hdr
.index
= ptex
;
2815 buf
.pte0
= cpu_to_be64(pte0
);
2816 buf
.pte1
= cpu_to_be64(pte1
);
2818 rc
= write(fd
, &buf
, sizeof(buf
));
2819 if (rc
!= sizeof(buf
)) {
2820 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2825 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
2826 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
2831 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
2832 int vector
, PCIDevice
*dev
)
2837 int kvm_arch_release_virq_post(int virq
)
2842 int kvm_arch_msi_data_to_gsi(uint32_t data
)
2844 return data
& 0xffff;
2847 int kvmppc_enable_hwrng(void)
2849 if (!kvm_enabled() || !kvm_check_extension(kvm_state
, KVM_CAP_PPC_HWRNG
)) {
2853 return kvmppc_enable_hcall(kvm_state
, H_RANDOM
);
2856 void kvmppc_check_papr_resize_hpt(Error
**errp
)
2858 if (!kvm_enabled()) {
2859 return; /* No KVM, we're good */
2862 if (cap_resize_hpt
) {
2863 return; /* Kernel has explicit support, we're good */
2866 /* Otherwise fallback on looking for PR KVM */
2867 if (kvmppc_is_pr(kvm_state
)) {
2872 "Hash page table resizing not available with this KVM version");
2875 int kvmppc_resize_hpt_prepare(PowerPCCPU
*cpu
, target_ulong flags
, int shift
)
2877 CPUState
*cs
= CPU(cpu
);
2878 struct kvm_ppc_resize_hpt rhpt
= {
2883 if (!cap_resize_hpt
) {
2887 return kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_RESIZE_HPT_PREPARE
, &rhpt
);
2890 int kvmppc_resize_hpt_commit(PowerPCCPU
*cpu
, target_ulong flags
, int shift
)
2892 CPUState
*cs
= CPU(cpu
);
2893 struct kvm_ppc_resize_hpt rhpt
= {
2898 if (!cap_resize_hpt
) {
2902 return kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_RESIZE_HPT_COMMIT
, &rhpt
);
2906 * This is a helper function to detect a post migration scenario
2907 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2908 * the guest kernel can't handle a PVR value other than the actual host
2909 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2911 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2912 * (so, we're HV), return true. The workaround itself is done in
2915 * The order here is important: we'll only check for KVM PR as a
2916 * fallback if the guest kernel can't handle the situation itself.
2917 * We need to avoid as much as possible querying the running KVM type
2920 bool kvmppc_pvr_workaround_required(PowerPCCPU
*cpu
)
2922 CPUState
*cs
= CPU(cpu
);
2924 if (!kvm_enabled()) {
2928 if (cap_ppc_pvr_compat
) {
2932 return !kvmppc_is_pr(cs
->kvm_state
);
2935 void kvmppc_set_reg_ppc_online(PowerPCCPU
*cpu
, unsigned int online
)
2937 CPUState
*cs
= CPU(cpu
);
2939 if (kvm_enabled()) {
2940 kvm_set_one_reg(cs
, KVM_REG_PPC_ONLINE
, &online
);