target/cris/cpu.c

   1 /*
   2  * QEMU CRIS CPU
   3  *
   4  * Copyright (c) 2008 AXIS Communications AB
   5  * Written by Edgar E. Iglesias.
   6  *
   7  * Copyright (c) 2012 SUSE LINUX Products GmbH
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu/qemu-print.h"
  27 #include "cpu.h"
  28 #include "mmu.h"
  29
  30
  31 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
  32 {
  33     CRISCPU *cpu = CRIS_CPU(cs);
  34
  35     cpu->env.pc = value;
  36 }
  37
  38 static vaddr cris_cpu_get_pc(CPUState *cs)
  39 {
  40     CRISCPU *cpu = CRIS_CPU(cs);
  41
  42     return cpu->env.pc;
  43 }
  44
  45 static bool cris_cpu_has_work(CPUState *cs)
  46 {
  47     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  48 }
  49
  50 static void cris_cpu_reset(DeviceState *dev)
  51 {
  52     CPUState *s = CPU(dev);
  53     CRISCPU *cpu = CRIS_CPU(s);
  54     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
  55     CPUCRISState *env = &cpu->env;
  56     uint32_t vr;
  57
  58     ccc->parent_reset(dev);
  59
  60     vr = env->pregs[PR_VR];
  61     memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
  62     env->pregs[PR_VR] = vr;
  63
  64 #if defined(CONFIG_USER_ONLY)
  65     /* start in user mode with interrupts enabled.  */
  66     env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
  67 #else
  68     cris_mmu_init(env);
  69     env->pregs[PR_CCS] = 0;
  70 #endif
  71 }
  72
  73 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
  74 {
  75     ObjectClass *oc;
  76     char *typename;
  77
  78 #if defined(CONFIG_USER_ONLY)
  79     if (strcasecmp(cpu_model, "any") == 0) {
  80         return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
  81     }
  82 #endif
  83
  84     typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
  85     oc = object_class_by_name(typename);
  86     g_free(typename);
  87     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
  88                        object_class_is_abstract(oc))) {
  89         oc = NULL;
  90     }
  91     return oc;
  92 }
  93
  94 /* Sort alphabetically by VR. */
  95 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
  96 {
  97     CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
  98     CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
  99
 100     /*  */
 101     if (ccc_a->vr > ccc_b->vr) {
 102         return 1;
 103     } else if (ccc_a->vr < ccc_b->vr) {
 104         return -1;
 105     } else {
 106         return 0;
 107     }
 108 }
 109
 110 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
 111 {
 112     ObjectClass *oc = data;
 113     const char *typename = object_class_get_name(oc);
 114     char *name;
 115
 116     name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX));
 117     qemu_printf("  %s\n", name);
 118     g_free(name);
 119 }
 120
 121 void cris_cpu_list(void)
 122 {
 123     GSList *list;
 124
 125     list = object_class_get_list(TYPE_CRIS_CPU, false);
 126     list = g_slist_sort(list, cris_cpu_list_compare);
 127     qemu_printf("Available CPUs:\n");
 128     g_slist_foreach(list, cris_cpu_list_entry, NULL);
 129     g_slist_free(list);
 130 }
 131
 132 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
 133 {
 134     CPUState *cs = CPU(dev);
 135     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
 136     Error *local_err = NULL;
 137
 138     cpu_exec_realizefn(cs, &local_err);
 139     if (local_err != NULL) {
 140         error_propagate(errp, local_err);
 141         return;
 142     }
 143
 144     cpu_reset(cs);
 145     qemu_init_vcpu(cs);
 146
 147     ccc->parent_realize(dev, errp);
 148 }
 149
 150 #ifndef CONFIG_USER_ONLY
 151 static void cris_cpu_set_irq(void *opaque, int irq, int level)
 152 {
 153     CRISCPU *cpu = opaque;
 154     CPUState *cs = CPU(cpu);
 155     int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
 156
 157     if (irq == CRIS_CPU_IRQ) {
 158         /*
 159          * The PIC passes us the vector for the IRQ as the value it sends
 160          * over the qemu_irq line
 161          */
 162         cpu->env.interrupt_vector = level;
 163     }
 164
 165     if (level) {
 166         cpu_interrupt(cs, type);
 167     } else {
 168         cpu_reset_interrupt(cs, type);
 169     }
 170 }
 171 #endif
 172
 173 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
 174 {
 175     CRISCPU *cc = CRIS_CPU(cpu);
 176     CPUCRISState *env = &cc->env;
 177
 178     if (env->pregs[PR_VR] != 32) {
 179         info->mach = bfd_mach_cris_v0_v10;
 180         info->print_insn = print_insn_crisv10;
 181     } else {
 182         info->mach = bfd_mach_cris_v32;
 183         info->print_insn = print_insn_crisv32;
 184     }
 185 }
 186
 187 static void cris_cpu_initfn(Object *obj)
 188 {
 189     CRISCPU *cpu = CRIS_CPU(obj);
 190     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
 191     CPUCRISState *env = &cpu->env;
 192
 193     cpu_set_cpustate_pointers(cpu);
 194
 195     env->pregs[PR_VR] = ccc->vr;
 196
 197 #ifndef CONFIG_USER_ONLY
 198     /* IRQ and NMI lines.  */
 199     qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
 200 #endif
 201 }
 202
 203 #ifndef CONFIG_USER_ONLY
 204 #include "hw/core/sysemu-cpu-ops.h"
 205
 206 static const struct SysemuCPUOps cris_sysemu_ops = {
 207     .get_phys_page_debug = cris_cpu_get_phys_page_debug,
 208 };
 209 #endif
 210
 211 #include "hw/core/tcg-cpu-ops.h"
 212
 213 static const struct TCGCPUOps crisv10_tcg_ops = {
 214     .initialize = cris_initialize_crisv10_tcg,
 215
 216 #ifndef CONFIG_USER_ONLY
 217     .tlb_fill = cris_cpu_tlb_fill,
 218     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
 219     .do_interrupt = crisv10_cpu_do_interrupt,
 220 #endif /* !CONFIG_USER_ONLY */
 221 };
 222
 223 static const struct TCGCPUOps crisv32_tcg_ops = {
 224     .initialize = cris_initialize_tcg,
 225
 226 #ifndef CONFIG_USER_ONLY
 227     .tlb_fill = cris_cpu_tlb_fill,
 228     .cpu_exec_interrupt = cris_cpu_exec_interrupt,
 229     .do_interrupt = cris_cpu_do_interrupt,
 230 #endif /* !CONFIG_USER_ONLY */
 231 };
 232
 233 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
 234 {
 235     CPUClass *cc = CPU_CLASS(oc);
 236     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 237
 238     ccc->vr = 8;
 239     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 240     cc->tcg_ops = &crisv10_tcg_ops;
 241 }
 242
 243 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
 244 {
 245     CPUClass *cc = CPU_CLASS(oc);
 246     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 247
 248     ccc->vr = 9;
 249     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 250     cc->tcg_ops = &crisv10_tcg_ops;
 251 }
 252
 253 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
 254 {
 255     CPUClass *cc = CPU_CLASS(oc);
 256     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 257
 258     ccc->vr = 10;
 259     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 260     cc->tcg_ops = &crisv10_tcg_ops;
 261 }
 262
 263 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
 264 {
 265     CPUClass *cc = CPU_CLASS(oc);
 266     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 267
 268     ccc->vr = 11;
 269     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 270     cc->tcg_ops = &crisv10_tcg_ops;
 271 }
 272
 273 static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
 274 {
 275     CPUClass *cc = CPU_CLASS(oc);
 276     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 277
 278     ccc->vr = 17;
 279     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 280     cc->tcg_ops = &crisv10_tcg_ops;
 281 }
 282
 283 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
 284 {
 285     CPUClass *cc = CPU_CLASS(oc);
 286     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 287
 288     ccc->vr = 32;
 289     cc->tcg_ops = &crisv32_tcg_ops;
 290 }
 291
 292 static void cris_cpu_class_init(ObjectClass *oc, void *data)
 293 {
 294     DeviceClass *dc = DEVICE_CLASS(oc);
 295     CPUClass *cc = CPU_CLASS(oc);
 296     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 297
 298     device_class_set_parent_realize(dc, cris_cpu_realizefn,
 299                                     &ccc->parent_realize);
 300
 301     device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
 302
 303     cc->class_by_name = cris_cpu_class_by_name;
 304     cc->has_work = cris_cpu_has_work;
 305     cc->dump_state = cris_cpu_dump_state;
 306     cc->set_pc = cris_cpu_set_pc;
 307     cc->get_pc = cris_cpu_get_pc;
 308     cc->gdb_read_register = cris_cpu_gdb_read_register;
 309     cc->gdb_write_register = cris_cpu_gdb_write_register;
 310 #ifndef CONFIG_USER_ONLY
 311     dc->vmsd = &vmstate_cris_cpu;
 312     cc->sysemu_ops = &cris_sysemu_ops;
 313 #endif
 314
 315     cc->gdb_num_core_regs = 49;
 316     cc->gdb_stop_before_watchpoint = true;
 317
 318     cc->disas_set_info = cris_disas_set_info;
 319 }
 320
 321 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
 322      {                                          \
 323          .parent = TYPE_CRIS_CPU,               \
 324          .class_init = initfn,                  \
 325          .name = CRIS_CPU_TYPE_NAME(cpu_model), \
 326      }
 327
 328 static const TypeInfo cris_cpu_model_type_infos[] = {
 329     {
 330         .name = TYPE_CRIS_CPU,
 331         .parent = TYPE_CPU,
 332         .instance_size = sizeof(CRISCPU),
 333         .instance_init = cris_cpu_initfn,
 334         .abstract = true,
 335         .class_size = sizeof(CRISCPUClass),
 336         .class_init = cris_cpu_class_init,
 337     },
 338     DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init),
 339     DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init),
 340     DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init),
 341     DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init),
 342     DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init),
 343     DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init),
 344 };
 345
 346 DEFINE_TYPES(cris_cpu_model_type_infos)