include/hw/intc/arm_gic_common.h

   1 /*
   2  * ARM GIC support
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef HW_ARM_GIC_COMMON_H
  22 #define HW_ARM_GIC_COMMON_H
  23
  24 #include "hw/sysbus.h"
  25 #include "qom/object.h"
  26
  27 /* Maximum number of possible interrupts, determined by the GIC architecture */
  28 #define GIC_MAXIRQ 1020
  29 /* First 32 are private to each CPU (SGIs and PPIs). */
  30 #define GIC_INTERNAL 32
  31 #define GIC_NR_SGIS 16
  32 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
  33 #define GIC_NCPU 8
  34 /* Maximum number of possible CPU interfaces with their respective vCPU */
  35 #define GIC_NCPU_VCPU (GIC_NCPU * 2)
  36
  37 #define MAX_NR_GROUP_PRIO 128
  38 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
  39
  40 #define GIC_MIN_BPR 0
  41 #define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
  42
  43 /* Architectural maximum number of list registers in the virtual interface */
  44 #define GIC_MAX_LR 64
  45
  46 /* Only 32 priority levels and 32 preemption levels in the vCPU interfaces */
  47 #define GIC_VIRT_MAX_GROUP_PRIO_BITS 5
  48 #define GIC_VIRT_MAX_NR_GROUP_PRIO (1 << GIC_VIRT_MAX_GROUP_PRIO_BITS)
  49 #define GIC_VIRT_NR_APRS (GIC_VIRT_MAX_NR_GROUP_PRIO / 32)
  50
  51 #define GIC_VIRT_MIN_BPR 2
  52 #define GIC_VIRT_MIN_ABPR (GIC_VIRT_MIN_BPR + 1)
  53
  54 typedef struct gic_irq_state {
  55     /* The enable bits are only banked for per-cpu interrupts.  */
  56     uint8_t enabled;
  57     uint8_t pending;
  58     uint8_t active;
  59     uint8_t level;
  60     bool model; /* 0 = N:N, 1 = 1:N */
  61     bool edge_trigger; /* true: edge-triggered, false: level-triggered  */
  62     uint8_t group;
  63 } gic_irq_state;
  64
  65 struct GICState {
  66     /*< private >*/
  67     SysBusDevice parent_obj;
  68     /*< public >*/
  69
  70     qemu_irq parent_irq[GIC_NCPU];
  71     qemu_irq parent_fiq[GIC_NCPU];
  72     qemu_irq parent_virq[GIC_NCPU];
  73     qemu_irq parent_vfiq[GIC_NCPU];
  74     qemu_irq maintenance_irq[GIC_NCPU];
  75
  76     /* GICD_CTLR; for a GIC with the security extensions the NS banked version
  77      * of this register is just an alias of bit 1 of the S banked version.
  78      */
  79     uint32_t ctlr;
  80     /* GICC_CTLR; again, the NS banked version is just aliases of bits of
  81      * the S banked register, so our state only needs to store the S version.
  82      */
  83     uint32_t cpu_ctlr[GIC_NCPU_VCPU];
  84
  85     gic_irq_state irq_state[GIC_MAXIRQ];
  86     uint8_t irq_target[GIC_MAXIRQ];
  87     uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
  88     uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
  89     /* For each SGI on the target CPU, we store 8 bits
  90      * indicating which source CPUs have made this SGI
  91      * pending on the target CPU. These correspond to
  92      * the bytes in the GIC_SPENDSGIR* registers as
  93      * read by the target CPU.
  94      */
  95     uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
  96
  97     uint16_t priority_mask[GIC_NCPU_VCPU];
  98     uint16_t running_priority[GIC_NCPU_VCPU];
  99     uint16_t current_pending[GIC_NCPU_VCPU];
 100     uint32_t n_prio_bits;
 101
 102     /* If we present the GICv2 without security extensions to a guest,
 103      * the guest can configure the GICC_CTLR to configure group 1 binary point
 104      * in the abpr.
 105      * For a GIC with Security Extensions we use use bpr for the
 106      * secure copy and abpr as storage for the non-secure copy of the register.
 107      */
 108     uint8_t  bpr[GIC_NCPU_VCPU];
 109     uint8_t  abpr[GIC_NCPU_VCPU];
 110
 111     /* The APR is implementation defined, so we choose a layout identical to
 112      * the KVM ABI layout for QEMU's implementation of the gic:
 113      * If an interrupt for preemption level X is active, then
 114      *   APRn[X mod 32] == 0b1,  where n = X / 32
 115      * otherwise the bit is clear.
 116      */
 117     uint32_t apr[GIC_NR_APRS][GIC_NCPU];
 118     uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
 119
 120     /* Virtual interface control registers */
 121     uint32_t h_hcr[GIC_NCPU];
 122     uint32_t h_misr[GIC_NCPU];
 123     uint32_t h_lr[GIC_MAX_LR][GIC_NCPU];
 124     uint32_t h_apr[GIC_NCPU];
 125
 126     /* Number of LRs implemented in this GIC instance */
 127     uint32_t num_lrs;
 128
 129     uint32_t num_cpu;
 130
 131     MemoryRegion iomem; /* Distributor */
 132     /* This is just so we can have an opaque pointer which identifies
 133      * both this GIC and which CPU interface we should be accessing.
 134      */
 135     struct GICState *backref[GIC_NCPU];
 136     MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
 137     MemoryRegion vifaceiomem[GIC_NCPU + 1]; /* Virtual interfaces */
 138     MemoryRegion vcpuiomem; /* vCPU interface */
 139
 140     uint32_t num_irq;
 141     uint32_t revision;
 142     bool security_extn;
 143     bool virt_extn;
 144     bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
 145     int dev_fd; /* kvm device fd if backed by kvm vgic support */
 146     Error *migration_blocker;
 147 };
 148 typedef struct GICState GICState;
 149
 150 #define TYPE_ARM_GIC_COMMON "arm_gic_common"
 151 typedef struct ARMGICCommonClass ARMGICCommonClass;
 152 DECLARE_OBJ_CHECKERS(GICState, ARMGICCommonClass,
 153                      ARM_GIC_COMMON, TYPE_ARM_GIC_COMMON)
 154
 155 struct ARMGICCommonClass {
 156     /*< private >*/
 157     SysBusDeviceClass parent_class;
 158     /*< public >*/
 159
 160     void (*pre_save)(GICState *s);
 161     void (*post_load)(GICState *s);
 162 };
 163
 164 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
 165                             const MemoryRegionOps *ops,
 166                             const MemoryRegionOps *virt_ops);
 167
 168 #endif