2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * This source file covers the following FPGA images, for TrustZone cores:
17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
22 * Links to the TRM for the board itself and to the various Application
23 * Notes which document the FPGA images can be found here:
24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
27 * https://developer.arm.com/documentation/100112/latest/
28 * Application Note AN505:
29 * https://developer.arm.com/documentation/dai0505/latest/
30 * Application Note AN521:
31 * https://developer.arm.com/documentation/dai0521/latest/
32 * Application Note AN524:
33 * https://developer.arm.com/documentation/dai0524/latest/
34 * Application Note AN547:
35 * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf
37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
38 * (ARM ECM0601256) for the details of some of the device layout:
39 * https://developer.arm.com/documentation/ecm0601256/latest
40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
41 * most of the device layout:
42 * https://developer.arm.com/documentation/101104/latest/
43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
44 * https://developer.arm.com/documentation/101773/latest/
47 #include "qemu/osdep.h"
48 #include "qemu/units.h"
49 #include "qemu/cutils.h"
50 #include "qapi/error.h"
51 #include "qemu/error-report.h"
52 #include "hw/arm/boot.h"
53 #include "hw/arm/armv7m.h"
54 #include "hw/or-irq.h"
55 #include "hw/boards.h"
56 #include "exec/address-spaces.h"
57 #include "sysemu/sysemu.h"
58 #include "hw/misc/unimp.h"
59 #include "hw/char/cmsdk-apb-uart.h"
60 #include "hw/timer/cmsdk-apb-timer.h"
61 #include "hw/misc/mps2-scc.h"
62 #include "hw/misc/mps2-fpgaio.h"
63 #include "hw/misc/tz-mpc.h"
64 #include "hw/misc/tz-msc.h"
65 #include "hw/arm/armsse.h"
66 #include "hw/dma/pl080.h"
67 #include "hw/rtc/pl031.h"
68 #include "hw/ssi/pl022.h"
69 #include "hw/i2c/arm_sbcon_i2c.h"
70 #include "hw/net/lan9118.h"
72 #include "hw/core/split-irq.h"
73 #include "hw/qdev-clock.h"
74 #include "qom/object.h"
76 #define MPS2TZ_NUMIRQ_MAX 96
77 #define MPS2TZ_RAM_MAX 5
79 typedef enum MPS2TZFPGAType
{
87 * Define the layout of RAM in a board, including which parts are
89 * mrindex specifies the index into mms->ram[] to use for the backing RAM;
90 * -1 means "use the system RAM".
92 typedef struct RAMInfo
{
96 int mpc
; /* MPC number, -1 for "not behind an MPC" */
103 * IS_ALIAS: this RAM area is an alias to the upstream end of the
104 * MPC specified by its .mpc value
105 * IS_ROM: this RAM area is read-only
110 struct MPS2TZMachineClass
{
112 MPS2TZFPGAType fpga_type
;
114 uint32_t sysclk_frq
; /* Main SYSCLK frequency in Hz */
115 uint32_t apb_periph_frq
; /* APB peripheral frequency in Hz */
117 const uint32_t *oscclk
;
118 uint32_t fpgaio_num_leds
; /* Number of LEDs in FPGAIO LED0 register */
119 bool fpgaio_has_switches
; /* Does FPGAIO have SWITCH register? */
120 bool fpgaio_has_dbgctrl
; /* Does FPGAIO have DBGCTRL register? */
121 int numirq
; /* Number of external interrupts */
122 int uart_overflow_irq
; /* number of the combined UART overflow IRQ */
123 uint32_t init_svtor
; /* init-svtor setting for SSE */
124 const RAMInfo
*raminfo
;
125 const char *armsse_type
;
128 struct MPS2TZMachineState
{
132 MemoryRegion ram
[MPS2TZ_RAM_MAX
];
133 MemoryRegion eth_usb_container
;
140 ArmSbconI2CState i2c
[5];
141 UnimplementedDeviceState i2s_audio
;
142 UnimplementedDeviceState gpio
[4];
143 UnimplementedDeviceState gfx
;
144 UnimplementedDeviceState cldc
;
145 UnimplementedDeviceState usb
;
149 CMSDKAPBUART uart
[6];
150 SplitIRQ sec_resp_splitter
;
151 qemu_or_irq uart_irq_orgate
;
152 DeviceState
*lan9118
;
153 SplitIRQ cpu_irq_splitter
[MPS2TZ_NUMIRQ_MAX
];
158 #define TYPE_MPS2TZ_MACHINE "mps2tz"
159 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
160 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
161 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
162 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547")
164 OBJECT_DECLARE_TYPE(MPS2TZMachineState
, MPS2TZMachineClass
, MPS2TZ_MACHINE
)
166 /* Slow 32Khz S32KCLK frequency in Hz */
167 #define S32KCLK_FRQ (32 * 1000)
170 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit
171 * emulation of that much guest RAM, so artificially make it smaller.
173 #if HOST_LONG_BITS == 32
174 #define MPS3_DDR_SIZE (1 * GiB)
176 #define MPS3_DDR_SIZE (2 * GiB)
179 static const uint32_t an505_oscclk
[] = {
185 static const uint32_t an524_oscclk
[] = {
194 static const RAMInfo an505_raminfo
[] = { {
213 .name
= "ssram-0-alias",
220 /* Use the largest bit of contiguous RAM as our "system memory" */
231 static const RAMInfo an524_raminfo
[] = { {
240 .size
= 32 * 4 * KiB
,
244 /* We don't model QSPI flash yet; for now expose it as simple ROM */
254 .size
= MPS3_DDR_SIZE
,
262 static const RAMInfo an547_raminfo
[] = { {
277 .size
= 4 * 128 * KiB
,
287 /* We don't model QSPI flash yet; for now expose it as simple ROM */
297 .size
= MPS3_DDR_SIZE
,
305 static const RAMInfo
*find_raminfo_for_mpc(MPS2TZMachineState
*mms
, int mpc
)
307 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
309 const RAMInfo
*found
= NULL
;
311 for (p
= mmc
->raminfo
; p
->name
; p
++) {
312 if (p
->mpc
== mpc
&& !(p
->flags
& IS_ALIAS
)) {
313 /* There should only be one entry in the array for this MPC */
318 /* if raminfo array doesn't have an entry for each MPC this is a bug */
323 static MemoryRegion
*mr_for_raminfo(MPS2TZMachineState
*mms
,
324 const RAMInfo
*raminfo
)
326 /* Return an initialized MemoryRegion for the RAMInfo. */
329 if (raminfo
->mrindex
< 0) {
330 /* Means this RAMInfo is for QEMU's "system memory" */
331 MachineState
*machine
= MACHINE(mms
);
332 assert(!(raminfo
->flags
& IS_ROM
));
336 assert(raminfo
->mrindex
< MPS2TZ_RAM_MAX
);
337 ram
= &mms
->ram
[raminfo
->mrindex
];
339 memory_region_init_ram(ram
, NULL
, raminfo
->name
,
340 raminfo
->size
, &error_fatal
);
341 if (raminfo
->flags
& IS_ROM
) {
342 memory_region_set_readonly(ram
, true);
347 /* Create an alias of an entire original MemoryRegion @orig
348 * located at @base in the memory map.
350 static void make_ram_alias(MemoryRegion
*mr
, const char *name
,
351 MemoryRegion
*orig
, hwaddr base
)
353 memory_region_init_alias(mr
, NULL
, name
, orig
, 0,
354 memory_region_size(orig
));
355 memory_region_add_subregion(get_system_memory(), base
, mr
);
358 static qemu_irq
get_sse_irq_in(MPS2TZMachineState
*mms
, int irqno
)
361 * Return a qemu_irq which will signal IRQ n to all CPUs in the
362 * SSE. The irqno should be as the CPU sees it, so the first
363 * external-to-the-SSE interrupt is 32.
365 MachineClass
*mc
= MACHINE_GET_CLASS(mms
);
366 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
368 assert(irqno
>= 32 && irqno
< (mmc
->numirq
+ 32));
371 * Convert from "CPU irq number" (as listed in the FPGA image
372 * documentation) to the SSE external-interrupt number.
376 if (mc
->max_cpus
> 1) {
377 return qdev_get_gpio_in(DEVICE(&mms
->cpu_irq_splitter
[irqno
]), 0);
379 return qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
), "EXP_IRQ", irqno
);
383 /* Most of the devices in the AN505 FPGA image sit behind
384 * Peripheral Protection Controllers. These data structures
385 * define the layout of which devices sit behind which PPCs.
386 * The devfn for each port is a function which creates, configures
387 * and initializes the device, returning the MemoryRegion which
388 * needs to be plugged into the downstream end of the PPC port.
390 typedef MemoryRegion
*MakeDevFn(MPS2TZMachineState
*mms
, void *opaque
,
391 const char *name
, hwaddr size
,
394 typedef struct PPCPortInfo
{
400 int irqs
[3]; /* currently no device needs more IRQ lines than this */
403 typedef struct PPCInfo
{
405 PPCPortInfo ports
[TZ_NUM_PORTS
];
408 static MemoryRegion
*make_unimp_dev(MPS2TZMachineState
*mms
,
410 const char *name
, hwaddr size
,
413 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
414 * and return a pointer to its MemoryRegion.
416 UnimplementedDeviceState
*uds
= opaque
;
418 object_initialize_child(OBJECT(mms
), name
, uds
, TYPE_UNIMPLEMENTED_DEVICE
);
419 qdev_prop_set_string(DEVICE(uds
), "name", name
);
420 qdev_prop_set_uint64(DEVICE(uds
), "size", size
);
421 sysbus_realize(SYS_BUS_DEVICE(uds
), &error_fatal
);
422 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds
), 0);
425 static MemoryRegion
*make_uart(MPS2TZMachineState
*mms
, void *opaque
,
426 const char *name
, hwaddr size
,
429 /* The irq[] array is tx, rx, combined, in that order */
430 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
431 CMSDKAPBUART
*uart
= opaque
;
432 int i
= uart
- &mms
->uart
[0];
434 DeviceState
*orgate_dev
= DEVICE(&mms
->uart_irq_orgate
);
436 object_initialize_child(OBJECT(mms
), name
, uart
, TYPE_CMSDK_APB_UART
);
437 qdev_prop_set_chr(DEVICE(uart
), "chardev", serial_hd(i
));
438 qdev_prop_set_uint32(DEVICE(uart
), "pclk-frq", mmc
->apb_periph_frq
);
439 sysbus_realize(SYS_BUS_DEVICE(uart
), &error_fatal
);
440 s
= SYS_BUS_DEVICE(uart
);
441 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
442 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqs
[1]));
443 sysbus_connect_irq(s
, 2, qdev_get_gpio_in(orgate_dev
, i
* 2));
444 sysbus_connect_irq(s
, 3, qdev_get_gpio_in(orgate_dev
, i
* 2 + 1));
445 sysbus_connect_irq(s
, 4, get_sse_irq_in(mms
, irqs
[2]));
446 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart
), 0);
449 static MemoryRegion
*make_scc(MPS2TZMachineState
*mms
, void *opaque
,
450 const char *name
, hwaddr size
,
453 MPS2SCC
*scc
= opaque
;
455 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
458 object_initialize_child(OBJECT(mms
), "scc", scc
, TYPE_MPS2_SCC
);
459 sccdev
= DEVICE(scc
);
460 qdev_prop_set_uint32(sccdev
, "scc-cfg4", 0x2);
461 qdev_prop_set_uint32(sccdev
, "scc-aid", 0x00200008);
462 qdev_prop_set_uint32(sccdev
, "scc-id", mmc
->scc_id
);
463 qdev_prop_set_uint32(sccdev
, "len-oscclk", mmc
->len_oscclk
);
464 for (i
= 0; i
< mmc
->len_oscclk
; i
++) {
465 g_autofree
char *propname
= g_strdup_printf("oscclk[%u]", i
);
466 qdev_prop_set_uint32(sccdev
, propname
, mmc
->oscclk
[i
]);
468 sysbus_realize(SYS_BUS_DEVICE(scc
), &error_fatal
);
469 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev
), 0);
472 static MemoryRegion
*make_fpgaio(MPS2TZMachineState
*mms
, void *opaque
,
473 const char *name
, hwaddr size
,
476 MPS2FPGAIO
*fpgaio
= opaque
;
477 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
479 object_initialize_child(OBJECT(mms
), "fpgaio", fpgaio
, TYPE_MPS2_FPGAIO
);
480 qdev_prop_set_uint32(DEVICE(fpgaio
), "num-leds", mmc
->fpgaio_num_leds
);
481 qdev_prop_set_bit(DEVICE(fpgaio
), "has-switches", mmc
->fpgaio_has_switches
);
482 qdev_prop_set_bit(DEVICE(fpgaio
), "has-dbgctrl", mmc
->fpgaio_has_dbgctrl
);
483 sysbus_realize(SYS_BUS_DEVICE(fpgaio
), &error_fatal
);
484 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio
), 0);
487 static MemoryRegion
*make_eth_dev(MPS2TZMachineState
*mms
, void *opaque
,
488 const char *name
, hwaddr size
,
492 NICInfo
*nd
= &nd_table
[0];
494 /* In hardware this is a LAN9220; the LAN9118 is software compatible
495 * except that it doesn't support the checksum-offload feature.
497 qemu_check_nic_model(nd
, "lan9118");
498 mms
->lan9118
= qdev_new(TYPE_LAN9118
);
499 qdev_set_nic_properties(mms
->lan9118
, nd
);
501 s
= SYS_BUS_DEVICE(mms
->lan9118
);
502 sysbus_realize_and_unref(s
, &error_fatal
);
503 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
504 return sysbus_mmio_get_region(s
, 0);
507 static MemoryRegion
*make_eth_usb(MPS2TZMachineState
*mms
, void *opaque
,
508 const char *name
, hwaddr size
,
512 * The AN524 makes the ethernet and USB share a PPC port.
513 * irqs[] is the ethernet IRQ.
516 NICInfo
*nd
= &nd_table
[0];
518 memory_region_init(&mms
->eth_usb_container
, OBJECT(mms
),
519 "mps2-tz-eth-usb-container", 0x200000);
522 * In hardware this is a LAN9220; the LAN9118 is software compatible
523 * except that it doesn't support the checksum-offload feature.
525 qemu_check_nic_model(nd
, "lan9118");
526 mms
->lan9118
= qdev_new(TYPE_LAN9118
);
527 qdev_set_nic_properties(mms
->lan9118
, nd
);
529 s
= SYS_BUS_DEVICE(mms
->lan9118
);
530 sysbus_realize_and_unref(s
, &error_fatal
);
531 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
533 memory_region_add_subregion(&mms
->eth_usb_container
,
534 0, sysbus_mmio_get_region(s
, 0));
536 /* The USB OTG controller is an ISP1763; we don't have a model of it. */
537 object_initialize_child(OBJECT(mms
), "usb-otg",
538 &mms
->usb
, TYPE_UNIMPLEMENTED_DEVICE
);
539 qdev_prop_set_string(DEVICE(&mms
->usb
), "name", "usb-otg");
540 qdev_prop_set_uint64(DEVICE(&mms
->usb
), "size", 0x100000);
541 s
= SYS_BUS_DEVICE(&mms
->usb
);
542 sysbus_realize(s
, &error_fatal
);
544 memory_region_add_subregion(&mms
->eth_usb_container
,
545 0x100000, sysbus_mmio_get_region(s
, 0));
547 return &mms
->eth_usb_container
;
550 static MemoryRegion
*make_mpc(MPS2TZMachineState
*mms
, void *opaque
,
551 const char *name
, hwaddr size
,
555 int i
= mpc
- &mms
->mpc
[0];
556 MemoryRegion
*upstream
;
557 const RAMInfo
*raminfo
= find_raminfo_for_mpc(mms
, i
);
558 MemoryRegion
*ram
= mr_for_raminfo(mms
, raminfo
);
560 object_initialize_child(OBJECT(mms
), name
, mpc
, TYPE_TZ_MPC
);
561 object_property_set_link(OBJECT(mpc
), "downstream", OBJECT(ram
),
563 sysbus_realize(SYS_BUS_DEVICE(mpc
), &error_fatal
);
564 /* Map the upstream end of the MPC into system memory */
565 upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 1);
566 memory_region_add_subregion(get_system_memory(), raminfo
->base
, upstream
);
567 /* and connect its interrupt to the IoTKit */
568 qdev_connect_gpio_out_named(DEVICE(mpc
), "irq", 0,
569 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
570 "mpcexp_status", i
));
572 /* Return the register interface MR for our caller to map behind the PPC */
573 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 0);
576 static MemoryRegion
*make_dma(MPS2TZMachineState
*mms
, void *opaque
,
577 const char *name
, hwaddr size
,
580 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */
581 PL080State
*dma
= opaque
;
582 int i
= dma
- &mms
->dma
[0];
584 char *mscname
= g_strdup_printf("%s-msc", name
);
585 TZMSC
*msc
= &mms
->msc
[i
];
586 DeviceState
*iotkitdev
= DEVICE(&mms
->iotkit
);
587 MemoryRegion
*msc_upstream
;
588 MemoryRegion
*msc_downstream
;
591 * Each DMA device is a PL081 whose transaction master interface
592 * is guarded by a Master Security Controller. The downstream end of
593 * the MSC connects to the IoTKit AHB Slave Expansion port, so the
594 * DMA devices can see all devices and memory that the CPU does.
596 object_initialize_child(OBJECT(mms
), mscname
, msc
, TYPE_TZ_MSC
);
597 msc_downstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms
->iotkit
), 0);
598 object_property_set_link(OBJECT(msc
), "downstream",
599 OBJECT(msc_downstream
), &error_fatal
);
600 object_property_set_link(OBJECT(msc
), "idau", OBJECT(mms
), &error_fatal
);
601 sysbus_realize(SYS_BUS_DEVICE(msc
), &error_fatal
);
603 qdev_connect_gpio_out_named(DEVICE(msc
), "irq", 0,
604 qdev_get_gpio_in_named(iotkitdev
,
605 "mscexp_status", i
));
606 qdev_connect_gpio_out_named(iotkitdev
, "mscexp_clear", i
,
607 qdev_get_gpio_in_named(DEVICE(msc
),
609 qdev_connect_gpio_out_named(iotkitdev
, "mscexp_ns", i
,
610 qdev_get_gpio_in_named(DEVICE(msc
),
612 qdev_connect_gpio_out(DEVICE(&mms
->sec_resp_splitter
),
613 ARRAY_SIZE(mms
->ppc
) + i
,
614 qdev_get_gpio_in_named(DEVICE(msc
),
616 msc_upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(msc
), 0);
618 object_initialize_child(OBJECT(mms
), name
, dma
, TYPE_PL081
);
619 object_property_set_link(OBJECT(dma
), "downstream", OBJECT(msc_upstream
),
621 sysbus_realize(SYS_BUS_DEVICE(dma
), &error_fatal
);
623 s
= SYS_BUS_DEVICE(dma
);
624 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
625 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
626 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqs
[1]));
627 sysbus_connect_irq(s
, 2, get_sse_irq_in(mms
, irqs
[2]));
630 return sysbus_mmio_get_region(s
, 0);
633 static MemoryRegion
*make_spi(MPS2TZMachineState
*mms
, void *opaque
,
634 const char *name
, hwaddr size
,
638 * The AN505 has five PL022 SPI controllers.
639 * One of these should have the LCD controller behind it; the others
640 * are connected only to the FPGA's "general purpose SPI connector"
641 * or "shield" expansion connectors.
642 * Note that if we do implement devices behind SPI, the chip select
643 * lines are set via the "MISC" register in the MPS2 FPGAIO device.
645 PL022State
*spi
= opaque
;
648 object_initialize_child(OBJECT(mms
), name
, spi
, TYPE_PL022
);
649 sysbus_realize(SYS_BUS_DEVICE(spi
), &error_fatal
);
650 s
= SYS_BUS_DEVICE(spi
);
651 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
652 return sysbus_mmio_get_region(s
, 0);
655 static MemoryRegion
*make_i2c(MPS2TZMachineState
*mms
, void *opaque
,
656 const char *name
, hwaddr size
,
659 ArmSbconI2CState
*i2c
= opaque
;
662 object_initialize_child(OBJECT(mms
), name
, i2c
, TYPE_ARM_SBCON_I2C
);
663 s
= SYS_BUS_DEVICE(i2c
);
664 sysbus_realize(s
, &error_fatal
);
665 return sysbus_mmio_get_region(s
, 0);
668 static MemoryRegion
*make_rtc(MPS2TZMachineState
*mms
, void *opaque
,
669 const char *name
, hwaddr size
,
672 PL031State
*pl031
= opaque
;
675 object_initialize_child(OBJECT(mms
), name
, pl031
, TYPE_PL031
);
676 s
= SYS_BUS_DEVICE(pl031
);
677 sysbus_realize(s
, &error_fatal
);
679 * The board docs don't give an IRQ number for the PL031, so
680 * presumably it is not connected.
682 return sysbus_mmio_get_region(s
, 0);
685 static void create_non_mpc_ram(MPS2TZMachineState
*mms
)
688 * Handle the RAMs which are either not behind MPCs or which are
689 * aliases to another MPC.
692 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
694 for (p
= mmc
->raminfo
; p
->name
; p
++) {
695 if (p
->flags
& IS_ALIAS
) {
696 SysBusDevice
*mpc_sbd
= SYS_BUS_DEVICE(&mms
->mpc
[p
->mpc
]);
697 MemoryRegion
*upstream
= sysbus_mmio_get_region(mpc_sbd
, 1);
698 make_ram_alias(&mms
->ram
[p
->mrindex
], p
->name
, upstream
, p
->base
);
699 } else if (p
->mpc
== -1) {
700 /* RAM not behind an MPC */
701 MemoryRegion
*mr
= mr_for_raminfo(mms
, p
);
702 memory_region_add_subregion(get_system_memory(), p
->base
, mr
);
707 static uint32_t boot_ram_size(MPS2TZMachineState
*mms
)
709 /* Return the size of the RAM block at guest address zero */
711 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
713 for (p
= mmc
->raminfo
; p
->name
; p
++) {
718 g_assert_not_reached();
721 static void mps2tz_common_init(MachineState
*machine
)
723 MPS2TZMachineState
*mms
= MPS2TZ_MACHINE(machine
);
724 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
725 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
726 MemoryRegion
*system_memory
= get_system_memory();
727 DeviceState
*iotkitdev
;
728 DeviceState
*dev_splitter
;
733 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
734 error_report("This board can only be used with CPU %s",
735 mc
->default_cpu_type
);
739 if (machine
->ram_size
!= mc
->default_ram_size
) {
740 char *sz
= size_to_str(mc
->default_ram_size
);
741 error_report("Invalid RAM size, should be %s", sz
);
746 /* These clocks don't need migration because they are fixed-frequency */
747 mms
->sysclk
= clock_new(OBJECT(machine
), "SYSCLK");
748 clock_set_hz(mms
->sysclk
, mmc
->sysclk_frq
);
749 mms
->s32kclk
= clock_new(OBJECT(machine
), "S32KCLK");
750 clock_set_hz(mms
->s32kclk
, S32KCLK_FRQ
);
752 object_initialize_child(OBJECT(machine
), TYPE_IOTKIT
, &mms
->iotkit
,
754 iotkitdev
= DEVICE(&mms
->iotkit
);
755 object_property_set_link(OBJECT(&mms
->iotkit
), "memory",
756 OBJECT(system_memory
), &error_abort
);
757 qdev_prop_set_uint32(iotkitdev
, "EXP_NUMIRQ", mmc
->numirq
);
758 qdev_prop_set_uint32(iotkitdev
, "init-svtor", mmc
->init_svtor
);
759 qdev_connect_clock_in(iotkitdev
, "MAINCLK", mms
->sysclk
);
760 qdev_connect_clock_in(iotkitdev
, "S32KCLK", mms
->s32kclk
);
761 sysbus_realize(SYS_BUS_DEVICE(&mms
->iotkit
), &error_fatal
);
764 * If this board has more than one CPU, then we need to create splitters
765 * to feed the IRQ inputs for each CPU in the SSE from each device in the
766 * board. If there is only one CPU, we can just wire the device IRQ
767 * directly to the SSE's IRQ input.
769 assert(mmc
->numirq
<= MPS2TZ_NUMIRQ_MAX
);
770 if (mc
->max_cpus
> 1) {
771 for (i
= 0; i
< mmc
->numirq
; i
++) {
772 char *name
= g_strdup_printf("mps2-irq-splitter%d", i
);
773 SplitIRQ
*splitter
= &mms
->cpu_irq_splitter
[i
];
775 object_initialize_child_with_props(OBJECT(machine
), name
,
776 splitter
, sizeof(*splitter
),
777 TYPE_SPLIT_IRQ
, &error_fatal
,
781 object_property_set_int(OBJECT(splitter
), "num-lines", 2,
783 qdev_realize(DEVICE(splitter
), NULL
, &error_fatal
);
784 qdev_connect_gpio_out(DEVICE(splitter
), 0,
785 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
787 qdev_connect_gpio_out(DEVICE(splitter
), 1,
788 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
793 /* The sec_resp_cfg output from the IoTKit must be split into multiple
794 * lines, one for each of the PPCs we create here, plus one per MSC.
796 object_initialize_child(OBJECT(machine
), "sec-resp-splitter",
797 &mms
->sec_resp_splitter
, TYPE_SPLIT_IRQ
);
798 object_property_set_int(OBJECT(&mms
->sec_resp_splitter
), "num-lines",
799 ARRAY_SIZE(mms
->ppc
) + ARRAY_SIZE(mms
->msc
),
801 qdev_realize(DEVICE(&mms
->sec_resp_splitter
), NULL
, &error_fatal
);
802 dev_splitter
= DEVICE(&mms
->sec_resp_splitter
);
803 qdev_connect_gpio_out_named(iotkitdev
, "sec_resp_cfg", 0,
804 qdev_get_gpio_in(dev_splitter
, 0));
807 * The IoTKit sets up much of the memory layout, including
808 * the aliases between secure and non-secure regions in the
809 * address space, and also most of the devices in the system.
810 * The FPGA itself contains various RAMs and some additional devices.
811 * The FPGA images have an odd combination of different RAMs,
812 * because in hardware they are different implementations and
813 * connected to different buses, giving varying performance/size
814 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
815 * call the largest lump our "system memory".
819 * The overflow IRQs for all UARTs are ORed together.
820 * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
821 * Create the OR gate for this: it has one input for the TX overflow
822 * and one for the RX overflow for each UART we might have.
823 * (If the board has fewer than the maximum possible number of UARTs
824 * those inputs are never wired up and are treated as always-zero.)
826 object_initialize_child(OBJECT(mms
), "uart-irq-orgate",
827 &mms
->uart_irq_orgate
, TYPE_OR_IRQ
);
828 object_property_set_int(OBJECT(&mms
->uart_irq_orgate
), "num-lines",
829 2 * ARRAY_SIZE(mms
->uart
),
831 qdev_realize(DEVICE(&mms
->uart_irq_orgate
), NULL
, &error_fatal
);
832 qdev_connect_gpio_out(DEVICE(&mms
->uart_irq_orgate
), 0,
833 get_sse_irq_in(mms
, mmc
->uart_overflow_irq
));
835 /* Most of the devices in the FPGA are behind Peripheral Protection
836 * Controllers. The required order for initializing things is:
837 * + initialize the PPC
838 * + initialize, configure and realize downstream devices
839 * + connect downstream device MemoryRegions to the PPC
841 * + map the PPC's MemoryRegions to the places in the address map
842 * where the downstream devices should appear
843 * + wire up the PPC's control lines to the IoTKit object
846 const PPCInfo an505_ppcs
[] = { {
847 .name
= "apb_ppcexp0",
849 { "ssram-0-mpc", make_mpc
, &mms
->mpc
[0], 0x58007000, 0x1000 },
850 { "ssram-1-mpc", make_mpc
, &mms
->mpc
[1], 0x58008000, 0x1000 },
851 { "ssram-2-mpc", make_mpc
, &mms
->mpc
[2], 0x58009000, 0x1000 },
854 .name
= "apb_ppcexp1",
856 { "spi0", make_spi
, &mms
->spi
[0], 0x40205000, 0x1000, { 51 } },
857 { "spi1", make_spi
, &mms
->spi
[1], 0x40206000, 0x1000, { 52 } },
858 { "spi2", make_spi
, &mms
->spi
[2], 0x40209000, 0x1000, { 53 } },
859 { "spi3", make_spi
, &mms
->spi
[3], 0x4020a000, 0x1000, { 54 } },
860 { "spi4", make_spi
, &mms
->spi
[4], 0x4020b000, 0x1000, { 55 } },
861 { "uart0", make_uart
, &mms
->uart
[0], 0x40200000, 0x1000, { 32, 33, 42 } },
862 { "uart1", make_uart
, &mms
->uart
[1], 0x40201000, 0x1000, { 34, 35, 43 } },
863 { "uart2", make_uart
, &mms
->uart
[2], 0x40202000, 0x1000, { 36, 37, 44 } },
864 { "uart3", make_uart
, &mms
->uart
[3], 0x40203000, 0x1000, { 38, 39, 45 } },
865 { "uart4", make_uart
, &mms
->uart
[4], 0x40204000, 0x1000, { 40, 41, 46 } },
866 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x40207000, 0x1000 },
867 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x40208000, 0x1000 },
868 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x4020c000, 0x1000 },
869 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x4020d000, 0x1000 },
872 .name
= "apb_ppcexp2",
874 { "scc", make_scc
, &mms
->scc
, 0x40300000, 0x1000 },
875 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
,
876 0x40301000, 0x1000 },
877 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x40302000, 0x1000 },
880 .name
= "ahb_ppcexp0",
882 { "gfx", make_unimp_dev
, &mms
->gfx
, 0x41000000, 0x140000 },
883 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x40100000, 0x1000 },
884 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x40101000, 0x1000 },
885 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x40102000, 0x1000 },
886 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x40103000, 0x1000 },
887 { "eth", make_eth_dev
, NULL
, 0x42000000, 0x100000, { 48 } },
890 .name
= "ahb_ppcexp1",
892 { "dma0", make_dma
, &mms
->dma
[0], 0x40110000, 0x1000, { 58, 56, 57 } },
893 { "dma1", make_dma
, &mms
->dma
[1], 0x40111000, 0x1000, { 61, 59, 60 } },
894 { "dma2", make_dma
, &mms
->dma
[2], 0x40112000, 0x1000, { 64, 62, 63 } },
895 { "dma3", make_dma
, &mms
->dma
[3], 0x40113000, 0x1000, { 67, 65, 66 } },
900 const PPCInfo an524_ppcs
[] = { {
901 .name
= "apb_ppcexp0",
903 { "bram-mpc", make_mpc
, &mms
->mpc
[0], 0x58007000, 0x1000 },
904 { "qspi-mpc", make_mpc
, &mms
->mpc
[1], 0x58008000, 0x1000 },
905 { "ddr-mpc", make_mpc
, &mms
->mpc
[2], 0x58009000, 0x1000 },
908 .name
= "apb_ppcexp1",
910 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x41200000, 0x1000 },
911 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x41201000, 0x1000 },
912 { "spi0", make_spi
, &mms
->spi
[0], 0x41202000, 0x1000, { 52 } },
913 { "spi1", make_spi
, &mms
->spi
[1], 0x41203000, 0x1000, { 53 } },
914 { "spi2", make_spi
, &mms
->spi
[2], 0x41204000, 0x1000, { 54 } },
915 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x41205000, 0x1000 },
916 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x41206000, 0x1000 },
917 { /* port 7 reserved */ },
918 { "i2c4", make_i2c
, &mms
->i2c
[4], 0x41208000, 0x1000 },
921 .name
= "apb_ppcexp2",
923 { "scc", make_scc
, &mms
->scc
, 0x41300000, 0x1000 },
924 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
,
925 0x41301000, 0x1000 },
926 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x41302000, 0x1000 },
927 { "uart0", make_uart
, &mms
->uart
[0], 0x41303000, 0x1000, { 32, 33, 42 } },
928 { "uart1", make_uart
, &mms
->uart
[1], 0x41304000, 0x1000, { 34, 35, 43 } },
929 { "uart2", make_uart
, &mms
->uart
[2], 0x41305000, 0x1000, { 36, 37, 44 } },
930 { "uart3", make_uart
, &mms
->uart
[3], 0x41306000, 0x1000, { 38, 39, 45 } },
931 { "uart4", make_uart
, &mms
->uart
[4], 0x41307000, 0x1000, { 40, 41, 46 } },
932 { "uart5", make_uart
, &mms
->uart
[5], 0x41308000, 0x1000, { 124, 125, 126 } },
934 { /* port 9 reserved */ },
935 { "clcd", make_unimp_dev
, &mms
->cldc
, 0x4130a000, 0x1000 },
936 { "rtc", make_rtc
, &mms
->rtc
, 0x4130b000, 0x1000 },
939 .name
= "ahb_ppcexp0",
941 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x41100000, 0x1000 },
942 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x41101000, 0x1000 },
943 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x41102000, 0x1000 },
944 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x41103000, 0x1000 },
945 { "eth-usb", make_eth_usb
, NULL
, 0x41400000, 0x200000, { 48 } },
950 const PPCInfo an547_ppcs
[] = { {
951 .name
= "apb_ppcexp0",
953 { "ssram-mpc", make_mpc
, &mms
->mpc
[0], 0x57000000, 0x1000 },
954 { "qspi-mpc", make_mpc
, &mms
->mpc
[1], 0x57001000, 0x1000 },
955 { "ddr-mpc", make_mpc
, &mms
->mpc
[2], 0x57002000, 0x1000 },
958 .name
= "apb_ppcexp1",
960 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x49200000, 0x1000 },
961 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x49201000, 0x1000 },
962 { "spi0", make_spi
, &mms
->spi
[0], 0x49202000, 0x1000, { 53 } },
963 { "spi1", make_spi
, &mms
->spi
[1], 0x49203000, 0x1000, { 54 } },
964 { "spi2", make_spi
, &mms
->spi
[2], 0x49204000, 0x1000, { 55 } },
965 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x49205000, 0x1000 },
966 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x49206000, 0x1000 },
967 { /* port 7 reserved */ },
968 { "i2c4", make_i2c
, &mms
->i2c
[4], 0x49208000, 0x1000 },
971 .name
= "apb_ppcexp2",
973 { "scc", make_scc
, &mms
->scc
, 0x49300000, 0x1000 },
974 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
, 0x49301000, 0x1000 },
975 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x49302000, 0x1000 },
976 { "uart0", make_uart
, &mms
->uart
[0], 0x49303000, 0x1000, { 33, 34, 43 } },
977 { "uart1", make_uart
, &mms
->uart
[1], 0x49304000, 0x1000, { 35, 36, 44 } },
978 { "uart2", make_uart
, &mms
->uart
[2], 0x49305000, 0x1000, { 37, 38, 45 } },
979 { "uart3", make_uart
, &mms
->uart
[3], 0x49306000, 0x1000, { 39, 40, 46 } },
980 { "uart4", make_uart
, &mms
->uart
[4], 0x49307000, 0x1000, { 41, 42, 47 } },
981 { "uart5", make_uart
, &mms
->uart
[5], 0x49308000, 0x1000, { 125, 126, 127 } },
983 { /* port 9 reserved */ },
984 { "clcd", make_unimp_dev
, &mms
->cldc
, 0x4930a000, 0x1000 },
985 { "rtc", make_rtc
, &mms
->rtc
, 0x4930b000, 0x1000 },
988 .name
= "ahb_ppcexp0",
990 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x41100000, 0x1000 },
991 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x41101000, 0x1000 },
992 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x41102000, 0x1000 },
993 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x41103000, 0x1000 },
994 { "eth-usb", make_eth_usb
, NULL
, 0x41400000, 0x200000, { 49 } },
999 switch (mmc
->fpga_type
) {
1003 num_ppcs
= ARRAY_SIZE(an505_ppcs
);
1007 num_ppcs
= ARRAY_SIZE(an524_ppcs
);
1011 num_ppcs
= ARRAY_SIZE(an547_ppcs
);
1014 g_assert_not_reached();
1017 for (i
= 0; i
< num_ppcs
; i
++) {
1018 const PPCInfo
*ppcinfo
= &ppcs
[i
];
1019 TZPPC
*ppc
= &mms
->ppc
[i
];
1020 DeviceState
*ppcdev
;
1024 object_initialize_child(OBJECT(machine
), ppcinfo
->name
, ppc
,
1026 ppcdev
= DEVICE(ppc
);
1028 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
1029 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
1033 if (!pinfo
->devfn
) {
1037 mr
= pinfo
->devfn(mms
, pinfo
->opaque
, pinfo
->name
, pinfo
->size
,
1039 portname
= g_strdup_printf("port[%d]", port
);
1040 object_property_set_link(OBJECT(ppc
), portname
, OBJECT(mr
),
1045 sysbus_realize(SYS_BUS_DEVICE(ppc
), &error_fatal
);
1047 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
1048 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
1050 if (!pinfo
->devfn
) {
1053 sysbus_mmio_map(SYS_BUS_DEVICE(ppc
), port
, pinfo
->addr
);
1055 gpioname
= g_strdup_printf("%s_nonsec", ppcinfo
->name
);
1056 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, port
,
1057 qdev_get_gpio_in_named(ppcdev
,
1061 gpioname
= g_strdup_printf("%s_ap", ppcinfo
->name
);
1062 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, port
,
1063 qdev_get_gpio_in_named(ppcdev
,
1068 gpioname
= g_strdup_printf("%s_irq_enable", ppcinfo
->name
);
1069 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, 0,
1070 qdev_get_gpio_in_named(ppcdev
,
1073 gpioname
= g_strdup_printf("%s_irq_clear", ppcinfo
->name
);
1074 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, 0,
1075 qdev_get_gpio_in_named(ppcdev
,
1078 gpioname
= g_strdup_printf("%s_irq_status", ppcinfo
->name
);
1079 qdev_connect_gpio_out_named(ppcdev
, "irq", 0,
1080 qdev_get_gpio_in_named(iotkitdev
,
1084 qdev_connect_gpio_out(dev_splitter
, i
,
1085 qdev_get_gpio_in_named(ppcdev
,
1086 "cfg_sec_resp", 0));
1089 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
1091 if (mmc
->fpga_type
== FPGA_AN547
) {
1092 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000);
1093 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000);
1096 create_non_mpc_ram(mms
);
1098 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
,
1099 boot_ram_size(mms
));
1102 static void mps2_tz_idau_check(IDAUInterface
*ii
, uint32_t address
,
1103 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
1106 * The MPS2 TZ FPGA images have IDAUs in them which are connected to
1107 * the Master Security Controllers. Thes have the same logic as
1108 * is used by the IoTKit for the IDAU connected to the CPU, except
1109 * that MSCs don't care about the NSC attribute.
1111 int region
= extract32(address
, 28, 4);
1113 *ns
= !(region
& 1);
1115 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1116 *exempt
= (address
& 0xeff00000) == 0xe0000000;
1120 static void mps2tz_class_init(ObjectClass
*oc
, void *data
)
1122 MachineClass
*mc
= MACHINE_CLASS(oc
);
1123 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(oc
);
1125 mc
->init
= mps2tz_common_init
;
1126 iic
->check
= mps2_tz_idau_check
;
1129 static void mps2tz_set_default_ram_info(MPS2TZMachineClass
*mmc
)
1132 * Set mc->default_ram_size and default_ram_id from the
1133 * information in mmc->raminfo.
1135 MachineClass
*mc
= MACHINE_CLASS(mmc
);
1138 for (p
= mmc
->raminfo
; p
->name
; p
++) {
1139 if (p
->mrindex
< 0) {
1140 /* Found the entry for "system memory" */
1141 mc
->default_ram_size
= p
->size
;
1142 mc
->default_ram_id
= p
->name
;
1146 g_assert_not_reached();
1149 static void mps2tz_an505_class_init(ObjectClass
*oc
, void *data
)
1151 MachineClass
*mc
= MACHINE_CLASS(oc
);
1152 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1154 mc
->desc
= "ARM MPS2 with AN505 FPGA image for Cortex-M33";
1155 mc
->default_cpus
= 1;
1156 mc
->min_cpus
= mc
->default_cpus
;
1157 mc
->max_cpus
= mc
->default_cpus
;
1158 mmc
->fpga_type
= FPGA_AN505
;
1159 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1160 mmc
->scc_id
= 0x41045050;
1161 mmc
->sysclk_frq
= 20 * 1000 * 1000; /* 20MHz */
1162 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1163 mmc
->oscclk
= an505_oscclk
;
1164 mmc
->len_oscclk
= ARRAY_SIZE(an505_oscclk
);
1165 mmc
->fpgaio_num_leds
= 2;
1166 mmc
->fpgaio_has_switches
= false;
1167 mmc
->fpgaio_has_dbgctrl
= false;
1169 mmc
->uart_overflow_irq
= 47;
1170 mmc
->init_svtor
= 0x10000000;
1171 mmc
->raminfo
= an505_raminfo
;
1172 mmc
->armsse_type
= TYPE_IOTKIT
;
1173 mps2tz_set_default_ram_info(mmc
);
1176 static void mps2tz_an521_class_init(ObjectClass
*oc
, void *data
)
1178 MachineClass
*mc
= MACHINE_CLASS(oc
);
1179 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1181 mc
->desc
= "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
1182 mc
->default_cpus
= 2;
1183 mc
->min_cpus
= mc
->default_cpus
;
1184 mc
->max_cpus
= mc
->default_cpus
;
1185 mmc
->fpga_type
= FPGA_AN521
;
1186 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1187 mmc
->scc_id
= 0x41045210;
1188 mmc
->sysclk_frq
= 20 * 1000 * 1000; /* 20MHz */
1189 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1190 mmc
->oscclk
= an505_oscclk
; /* AN521 is the same as AN505 here */
1191 mmc
->len_oscclk
= ARRAY_SIZE(an505_oscclk
);
1192 mmc
->fpgaio_num_leds
= 2;
1193 mmc
->fpgaio_has_switches
= false;
1194 mmc
->fpgaio_has_dbgctrl
= false;
1196 mmc
->uart_overflow_irq
= 47;
1197 mmc
->init_svtor
= 0x10000000;
1198 mmc
->raminfo
= an505_raminfo
; /* AN521 is the same as AN505 here */
1199 mmc
->armsse_type
= TYPE_SSE200
;
1200 mps2tz_set_default_ram_info(mmc
);
1203 static void mps3tz_an524_class_init(ObjectClass
*oc
, void *data
)
1205 MachineClass
*mc
= MACHINE_CLASS(oc
);
1206 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1208 mc
->desc
= "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
1209 mc
->default_cpus
= 2;
1210 mc
->min_cpus
= mc
->default_cpus
;
1211 mc
->max_cpus
= mc
->default_cpus
;
1212 mmc
->fpga_type
= FPGA_AN524
;
1213 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1214 mmc
->scc_id
= 0x41045240;
1215 mmc
->sysclk_frq
= 32 * 1000 * 1000; /* 32MHz */
1216 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1217 mmc
->oscclk
= an524_oscclk
;
1218 mmc
->len_oscclk
= ARRAY_SIZE(an524_oscclk
);
1219 mmc
->fpgaio_num_leds
= 10;
1220 mmc
->fpgaio_has_switches
= true;
1221 mmc
->fpgaio_has_dbgctrl
= false;
1223 mmc
->uart_overflow_irq
= 47;
1224 mmc
->init_svtor
= 0x10000000;
1225 mmc
->raminfo
= an524_raminfo
;
1226 mmc
->armsse_type
= TYPE_SSE200
;
1227 mps2tz_set_default_ram_info(mmc
);
1230 static void mps3tz_an547_class_init(ObjectClass
*oc
, void *data
)
1232 MachineClass
*mc
= MACHINE_CLASS(oc
);
1233 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1235 mc
->desc
= "ARM MPS3 with AN547 FPGA image for Cortex-M55";
1236 mc
->default_cpus
= 1;
1237 mc
->min_cpus
= mc
->default_cpus
;
1238 mc
->max_cpus
= mc
->default_cpus
;
1239 mmc
->fpga_type
= FPGA_AN547
;
1240 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m55");
1241 mmc
->scc_id
= 0x41055470;
1242 mmc
->sysclk_frq
= 32 * 1000 * 1000; /* 32MHz */
1243 mmc
->apb_periph_frq
= 25 * 1000 * 1000; /* 25MHz */
1244 mmc
->oscclk
= an524_oscclk
; /* same as AN524 */
1245 mmc
->len_oscclk
= ARRAY_SIZE(an524_oscclk
);
1246 mmc
->fpgaio_num_leds
= 10;
1247 mmc
->fpgaio_has_switches
= true;
1248 mmc
->fpgaio_has_dbgctrl
= true;
1250 mmc
->uart_overflow_irq
= 48;
1251 mmc
->init_svtor
= 0x00000000;
1252 mmc
->raminfo
= an547_raminfo
;
1253 mmc
->armsse_type
= TYPE_SSE300
;
1254 mps2tz_set_default_ram_info(mmc
);
1257 static const TypeInfo mps2tz_info
= {
1258 .name
= TYPE_MPS2TZ_MACHINE
,
1259 .parent
= TYPE_MACHINE
,
1261 .instance_size
= sizeof(MPS2TZMachineState
),
1262 .class_size
= sizeof(MPS2TZMachineClass
),
1263 .class_init
= mps2tz_class_init
,
1264 .interfaces
= (InterfaceInfo
[]) {
1265 { TYPE_IDAU_INTERFACE
},
1270 static const TypeInfo mps2tz_an505_info
= {
1271 .name
= TYPE_MPS2TZ_AN505_MACHINE
,
1272 .parent
= TYPE_MPS2TZ_MACHINE
,
1273 .class_init
= mps2tz_an505_class_init
,
1276 static const TypeInfo mps2tz_an521_info
= {
1277 .name
= TYPE_MPS2TZ_AN521_MACHINE
,
1278 .parent
= TYPE_MPS2TZ_MACHINE
,
1279 .class_init
= mps2tz_an521_class_init
,
1282 static const TypeInfo mps3tz_an524_info
= {
1283 .name
= TYPE_MPS3TZ_AN524_MACHINE
,
1284 .parent
= TYPE_MPS2TZ_MACHINE
,
1285 .class_init
= mps3tz_an524_class_init
,
1288 static const TypeInfo mps3tz_an547_info
= {
1289 .name
= TYPE_MPS3TZ_AN547_MACHINE
,
1290 .parent
= TYPE_MPS2TZ_MACHINE
,
1291 .class_init
= mps3tz_an547_class_init
,
1294 static void mps2tz_machine_init(void)
1296 type_register_static(&mps2tz_info
);
1297 type_register_static(&mps2tz_an505_info
);
1298 type_register_static(&mps2tz_an521_info
);
1299 type_register_static(&mps3tz_an524_info
);
1300 type_register_static(&mps3tz_an547_info
);
1303 type_init(mps2tz_machine_init
);