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qga: fix guest-get-disks regression
[qemu/ar7.git] / hw / arm / aspeed_ast2600.c
blobbc87e754a3cc94e4ecf56bd0f356d8752c116e59
1 /*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "cpu.h"
13 #include "exec/address-spaces.h"
14 #include "hw/misc/unimp.h"
15 #include "hw/arm/aspeed_soc.h"
16 #include "hw/char/serial.h"
17 #include "qemu/log.h"
18 #include "qemu/module.h"
19 #include "qemu/error-report.h"
20 #include "hw/i2c/aspeed_i2c.h"
21 #include "net/net.h"
22 #include "sysemu/sysemu.h"
23
24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
25
26 static const hwaddr aspeed_soc_ast2600_memmap[] = {
27 [ASPEED_DEV_SRAM] = 0x10000000,
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
29 [ASPEED_DEV_IOMEM] = 0x1E600000,
30 [ASPEED_DEV_PWM] = 0x1E610000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_SPI2] = 0x1E641000,
34 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
35 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
36 [ASPEED_DEV_MII1] = 0x1E650000,
37 [ASPEED_DEV_MII2] = 0x1E650008,
38 [ASPEED_DEV_MII3] = 0x1E650010,
39 [ASPEED_DEV_MII4] = 0x1E650018,
40 [ASPEED_DEV_ETH1] = 0x1E660000,
41 [ASPEED_DEV_ETH3] = 0x1E670000,
42 [ASPEED_DEV_ETH2] = 0x1E680000,
43 [ASPEED_DEV_ETH4] = 0x1E690000,
44 [ASPEED_DEV_VIC] = 0x1E6C0000,
45 [ASPEED_DEV_SDMC] = 0x1E6E0000,
46 [ASPEED_DEV_SCU] = 0x1E6E2000,
47 [ASPEED_DEV_XDMA] = 0x1E6E7000,
48 [ASPEED_DEV_ADC] = 0x1E6E9000,
49 [ASPEED_DEV_VIDEO] = 0x1E700000,
50 [ASPEED_DEV_SDHCI] = 0x1E740000,
51 [ASPEED_DEV_EMMC] = 0x1E750000,
52 [ASPEED_DEV_GPIO] = 0x1E780000,
53 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
54 [ASPEED_DEV_RTC] = 0x1E781000,
55 [ASPEED_DEV_TIMER1] = 0x1E782000,
56 [ASPEED_DEV_WDT] = 0x1E785000,
57 [ASPEED_DEV_LPC] = 0x1E789000,
58 [ASPEED_DEV_IBT] = 0x1E789140,
59 [ASPEED_DEV_I2C] = 0x1E78A000,
60 [ASPEED_DEV_UART1] = 0x1E783000,
61 [ASPEED_DEV_UART5] = 0x1E784000,
62 [ASPEED_DEV_VUART] = 0x1E787000,
63 [ASPEED_DEV_SDRAM] = 0x80000000,
64 };
65
66 #define ASPEED_A7MPCORE_ADDR 0x40460000
67
68 #define AST2600_MAX_IRQ 197
69
70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
71 static const int aspeed_soc_ast2600_irqmap[] = {
72 [ASPEED_DEV_UART1] = 47,
73 [ASPEED_DEV_UART2] = 48,
74 [ASPEED_DEV_UART3] = 49,
75 [ASPEED_DEV_UART4] = 50,
76 [ASPEED_DEV_UART5] = 8,
77 [ASPEED_DEV_VUART] = 8,
78 [ASPEED_DEV_FMC] = 39,
79 [ASPEED_DEV_SDMC] = 0,
80 [ASPEED_DEV_SCU] = 12,
81 [ASPEED_DEV_ADC] = 78,
82 [ASPEED_DEV_XDMA] = 6,
83 [ASPEED_DEV_SDHCI] = 43,
84 [ASPEED_DEV_EHCI1] = 5,
85 [ASPEED_DEV_EHCI2] = 9,
86 [ASPEED_DEV_EMMC] = 15,
87 [ASPEED_DEV_GPIO] = 40,
88 [ASPEED_DEV_GPIO_1_8V] = 11,
89 [ASPEED_DEV_RTC] = 13,
90 [ASPEED_DEV_TIMER1] = 16,
91 [ASPEED_DEV_TIMER2] = 17,
92 [ASPEED_DEV_TIMER3] = 18,
93 [ASPEED_DEV_TIMER4] = 19,
94 [ASPEED_DEV_TIMER5] = 20,
95 [ASPEED_DEV_TIMER6] = 21,
96 [ASPEED_DEV_TIMER7] = 22,
97 [ASPEED_DEV_TIMER8] = 23,
98 [ASPEED_DEV_WDT] = 24,
99 [ASPEED_DEV_PWM] = 44,
100 [ASPEED_DEV_LPC] = 35,
101 [ASPEED_DEV_IBT] = 143,
102 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
103 [ASPEED_DEV_ETH1] = 2,
104 [ASPEED_DEV_ETH2] = 3,
105 [ASPEED_DEV_ETH3] = 32,
106 [ASPEED_DEV_ETH4] = 33,
107 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
108 };
109
110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
111 {
112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
113
114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
115 }
116
117 static void aspeed_soc_ast2600_init(Object *obj)
118 {
119 AspeedSoCState *s = ASPEED_SOC(obj);
120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
121 int i;
122 char socname[8];
123 char typename[64];
124
125 if (sscanf(sc->name, "%7s", socname) != 1) {
126 g_assert_not_reached();
127 }
128
129 for (i = 0; i < sc->num_cpus; i++) {
130 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
131 }
132
133 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
134 object_initialize_child(obj, "scu", &s->scu, typename);
135 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
136 sc->silicon_rev);
137 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
138 "hw-strap1");
139 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
140 "hw-strap2");
141 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
142 "hw-prot-key");
143
144 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
145 TYPE_A15MPCORE_PRIV);
146
147 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
148
149 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
150 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
151
152 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
153 object_initialize_child(obj, "i2c", &s->i2c, typename);
154
155 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
156 object_initialize_child(obj, "fmc", &s->fmc, typename);
157 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
158
159 for (i = 0; i < sc->spis_num; i++) {
160 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
161 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
162 }
163
164 for (i = 0; i < sc->ehcis_num; i++) {
165 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
166 TYPE_PLATFORM_EHCI);
167 }
168
169 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
170 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
171 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
172 "ram-size");
173 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
174 "max-ram-size");
175
176 for (i = 0; i < sc->wdts_num; i++) {
177 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
178 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
179 }
180
181 for (i = 0; i < sc->macs_num; i++) {
182 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
183 TYPE_FTGMAC100);
184
185 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
186 }
187
188 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA);
189
190 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
191 object_initialize_child(obj, "gpio", &s->gpio, typename);
192
193 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
194 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
195
196 object_initialize_child(obj, "sd-controller", &s->sdhci,
197 TYPE_ASPEED_SDHCI);
198
199 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
200
201 /* Init sd card slot class here so that they're under the correct parent */
202 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
203 object_initialize_child(obj, "sd-controller.sdhci[*]",
204 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
205 }
206
207 object_initialize_child(obj, "emmc-controller", &s->emmc,
208 TYPE_ASPEED_SDHCI);
209
210 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
211
212 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
213 TYPE_SYSBUS_SDHCI);
214
215 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
216 }
217
218 /*
219 * ASPEED ast2600 has 0xf as cluster ID
220 *
221 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
222 */
223 static uint64_t aspeed_calc_affinity(int cpu)
224 {
225 return (0xf << ARM_AFF1_SHIFT) | cpu;
226 }
227
228 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
229 {
230 int i;
231 AspeedSoCState *s = ASPEED_SOC(dev);
232 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
233 Error *err = NULL;
234 qemu_irq irq;
235
236 /* IO space */
237 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM],
238 ASPEED_SOC_IOMEM_SIZE);
239
240 /* Video engine stub */
241 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO],
242 0x1000);
243
244 /* CPU */
245 for (i = 0; i < sc->num_cpus; i++) {
246 if (sc->num_cpus > 1) {
247 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
248 ASPEED_A7MPCORE_ADDR, &error_abort);
249 }
250 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
251 aspeed_calc_affinity(i), &error_abort);
252
253 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
254 &error_abort);
255
256 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
257 return;
258 }
259 }
260
261 /* A7MPCORE */
262 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
263 &error_abort);
264 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
265 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
266 &error_abort);
267
268 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
269 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
270
271 for (i = 0; i < sc->num_cpus; i++) {
272 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
273 DeviceState *d = DEVICE(qemu_get_cpu(i));
274
275 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
276 sysbus_connect_irq(sbd, i, irq);
277 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
278 sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
279 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
280 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
281 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
282 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
283 }
284
285 /* SRAM */
286 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
287 sc->sram_size, &err);
288 if (err) {
289 error_propagate(errp, err);
290 return;
291 }
292 memory_region_add_subregion(get_system_memory(),
293 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
294
295 /* SCU */
296 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
297 return;
298 }
299 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
300
301 /* RTC */
302 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
303 return;
304 }
305 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
306 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
307 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
308
309 /* Timer */
310 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
311 &error_abort);
312 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
313 return;
314 }
315 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
316 sc->memmap[ASPEED_DEV_TIMER1]);
317 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
318 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
319 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
320 }
321
322 /* UART - attach an 8250 to the IO space as our UART5 */
323 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
324 aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
325 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
326
327 /* I2C */
328 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
329 &error_abort);
330 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
331 return;
332 }
333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
334 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
335 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
336 sc->irqmap[ASPEED_DEV_I2C] + i);
337 /*
338 * The AST2600 SoC has one IRQ per I2C bus. Skip the common
339 * IRQ (AST2400 and AST2500) and connect all bussses.
340 */
341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
342 }
343
344 /* FMC, The number of CS is set at the board level */
345 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
346 &error_abort);
347 if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base",
348 sc->memmap[ASPEED_DEV_SDRAM], errp)) {
349 return;
350 }
351 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
352 return;
353 }
354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
356 s->fmc.ctrl->flash_window_base);
357 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
358 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
359
360 /* SPI */
361 for (i = 0; i < sc->spis_num; i++) {
362 object_property_set_link(OBJECT(&s->spi[i]), "dram",
363 OBJECT(s->dram_mr), &error_abort);
364 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort);
365 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
366 return;
367 }
368 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
369 sc->memmap[ASPEED_DEV_SPI1 + i]);
370 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
371 s->spi[i].ctrl->flash_window_base);
372 }
373
374 /* EHCI */
375 for (i = 0; i < sc->ehcis_num; i++) {
376 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
377 return;
378 }
379 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
380 sc->memmap[ASPEED_DEV_EHCI1 + i]);
381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
382 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
383 }
384
385 /* SDMC - SDRAM Memory Controller */
386 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
387 return;
388 }
389 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]);
390
391 /* Watch dog */
392 for (i = 0; i < sc->wdts_num; i++) {
393 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
394
395 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
396 &error_abort);
397 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
398 return;
399 }
400 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
401 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
402 }
403
404 /* Net */
405 for (i = 0; i < sc->macs_num; i++) {
406 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
407 &error_abort);
408 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
409 return;
410 }
411 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
412 sc->memmap[ASPEED_DEV_ETH1 + i]);
413 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
414 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
415
416 object_property_set_link(OBJECT(&s->mii[i]), "nic",
417 OBJECT(&s->ftgmac100[i]), &error_abort);
418 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
419 return;
420 }
421
422 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
423 sc->memmap[ASPEED_DEV_MII1 + i]);
424 }
425
426 /* XDMA */
427 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
428 return;
429 }
430 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
431 sc->memmap[ASPEED_DEV_XDMA]);
432 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
433 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
434
435 /* GPIO */
436 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
437 return;
438 }
439 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
441 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
442
443 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
444 return;
445 }
446 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
447 sc->memmap[ASPEED_DEV_GPIO_1_8V]);
448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
449 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
450
451 /* SDHCI */
452 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
453 return;
454 }
455 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
456 sc->memmap[ASPEED_DEV_SDHCI]);
457 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
458 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
459
460 /* eMMC */
461 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
462 return;
463 }
464 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]);
465 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
466 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
467
468 /* LPC */
469 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
470 return;
471 }
472 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
473
474 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
475 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
476 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
477
478 /*
479 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
480 *
481 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
482 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
483 * shared across the subdevices, and the shared IRQ output to the VIC is at
484 * offset 0.
485 */
486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
487 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
488 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
489
490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
491 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
492 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
493
494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
495 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
496 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
497
498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
499 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
500 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
501 }
502
503 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
504 {
505 DeviceClass *dc = DEVICE_CLASS(oc);
506 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
507
508 dc->realize = aspeed_soc_ast2600_realize;
509
510 sc->name = "ast2600-a1";
511 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
512 sc->silicon_rev = AST2600_A1_SILICON_REV;
513 sc->sram_size = 0x16400;
514 sc->spis_num = 2;
515 sc->ehcis_num = 2;
516 sc->wdts_num = 4;
517 sc->macs_num = 4;
518 sc->irqmap = aspeed_soc_ast2600_irqmap;
519 sc->memmap = aspeed_soc_ast2600_memmap;
520 sc->num_cpus = 2;
521 }
522
523 static const TypeInfo aspeed_soc_ast2600_type_info = {
524 .name = "ast2600-a1",
525 .parent = TYPE_ASPEED_SOC,
526 .instance_size = sizeof(AspeedSoCState),
527 .instance_init = aspeed_soc_ast2600_init,
528 .class_init = aspeed_soc_ast2600_class_init,
529 .class_size = sizeof(AspeedSoCClass),
530 };
531
532 static void aspeed_soc_register_types(void)
533 {
534 type_register_static(&aspeed_soc_ast2600_type_info);
535 };
536
537 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU