hw/i2c/versatile_i2c.c

   1 /*
   2  * ARM SBCon two-wire serial bus interface (I2C bitbang)
   3  * a.k.a. ARM Versatile I2C controller
   4  *
   5  * Copyright (c) 2006-2007 CodeSourcery.
   6  * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
   7  *
   8  * This file is derived from hw/realview.c by Paul Brook
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  22  *
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/i2c/arm_sbcon_i2c.h"
  27 #include "hw/registerfields.h"
  28 #include "qemu/log.h"
  29 #include "qemu/module.h"
  30
  31 #define VERSATILE_I2C(obj) \
  32     OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C)
  33
  34 typedef ArmSbconI2CState VersatileI2CState;
  35
  36
  37 REG32(CONTROL_GET, 0)
  38 REG32(CONTROL_SET, 0)
  39 REG32(CONTROL_CLR, 4)
  40
  41 #define SCL BIT(0)
  42 #define SDA BIT(1)
  43
  44 static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
  45                                    unsigned size)
  46 {
  47     VersatileI2CState *s = (VersatileI2CState *)opaque;
  48
  49     switch (offset) {
  50     case A_CONTROL_SET:
  51         return (s->out & 1) | (s->in << 1);
  52     default:
  53         qemu_log_mask(LOG_GUEST_ERROR,
  54                       "%s: Bad offset 0x%x\n", __func__, (int)offset);
  55         return -1;
  56     }
  57 }
  58
  59 static void versatile_i2c_write(void *opaque, hwaddr offset,
  60                                 uint64_t value, unsigned size)
  61 {
  62     VersatileI2CState *s = (VersatileI2CState *)opaque;
  63
  64     switch (offset) {
  65     case A_CONTROL_SET:
  66         s->out |= value & 3;
  67         break;
  68     case A_CONTROL_CLR:
  69         s->out &= ~value;
  70         break;
  71     default:
  72         qemu_log_mask(LOG_GUEST_ERROR,
  73                       "%s: Bad offset 0x%x\n", __func__, (int)offset);
  74     }
  75     bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0);
  76     s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
  77 }
  78
  79 static const MemoryRegionOps versatile_i2c_ops = {
  80     .read = versatile_i2c_read,
  81     .write = versatile_i2c_write,
  82     .endianness = DEVICE_NATIVE_ENDIAN,
  83 };
  84
  85 static void versatile_i2c_init(Object *obj)
  86 {
  87     DeviceState *dev = DEVICE(obj);
  88     VersatileI2CState *s = VERSATILE_I2C(obj);
  89     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  90     I2CBus *bus;
  91
  92     bus = i2c_init_bus(dev, "i2c");
  93     bitbang_i2c_init(&s->bitbang, bus);
  94     memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
  95                           "arm_sbcon_i2c", 0x1000);
  96     sysbus_init_mmio(sbd, &s->iomem);
  97 }
  98
  99 static const TypeInfo versatile_i2c_info = {
 100     .name          = TYPE_VERSATILE_I2C,
 101     .parent        = TYPE_SYS_BUS_DEVICE,
 102     .instance_size = sizeof(VersatileI2CState),
 103     .instance_init = versatile_i2c_init,
 104 };
 105
 106 static void versatile_i2c_register_types(void)
 107 {
 108     type_register_static(&versatile_i2c_info);
 109 }
 110
 111 type_init(versatile_i2c_register_types)