hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7 #include "memory.h"
   8 #include "dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  79
  80 #define FMT_PCIBUS                      PRIx64
  81
  82 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  83                                 uint32_t address, uint32_t data, int len);
  84 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  85                                    uint32_t address, int len);
  86 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  87                                 pcibus_t addr, pcibus_t size, int type);
  88 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
  89
  90 typedef struct PCIIORegion {
  91     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  92 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  93     pcibus_t size;
  94     uint8_t type;
  95     MemoryRegion *memory;
  96     MemoryRegion *address_space;
  97 } PCIIORegion;
  98
  99 #define PCI_ROM_SLOT 6
 100 #define PCI_NUM_REGIONS 7
 101
 102 #include "pci_regs.h"
 103
 104 /* PCI HEADER_TYPE */
 105 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 106
 107 /* Size of the standard PCI config header */
 108 #define PCI_CONFIG_HEADER_SIZE 0x40
 109 /* Size of the standard PCI config space */
 110 #define PCI_CONFIG_SPACE_SIZE 0x100
 111 /* Size of the standart PCIe config space: 4KB */
 112 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 113
 114 #define PCI_NUM_PINS 4 /* A-D */
 115
 116 /* Bits in cap_present field. */
 117 enum {
 118     QEMU_PCI_CAP_MSI = 0x1,
 119     QEMU_PCI_CAP_MSIX = 0x2,
 120     QEMU_PCI_CAP_EXPRESS = 0x4,
 121
 122     /* multifunction capable device */
 123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 124     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 125
 126     /* command register SERR bit enabled */
 127 #define QEMU_PCI_CAP_SERR_BITNR 4
 128     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 129     /* Standard hot plug controller. */
 130 #define QEMU_PCI_SHPC_BITNR 5
 131     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 132 #define QEMU_PCI_SLOTID_BITNR 6
 133     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 134 };
 135
 136 #define TYPE_PCI_DEVICE "pci-device"
 137 #define PCI_DEVICE(obj) \
 138      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 139 #define PCI_DEVICE_CLASS(klass) \
 140      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 141 #define PCI_DEVICE_GET_CLASS(obj) \
 142      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 143
 144 typedef struct PCIINTxRoute {
 145     enum {
 146         PCI_INTX_ENABLED,
 147         PCI_INTX_INVERTED,
 148         PCI_INTX_DISABLED,
 149     } mode;
 150     int irq;
 151 } PCIINTxRoute;
 152
 153 typedef struct PCIDeviceClass {
 154     DeviceClass parent_class;
 155
 156     int (*init)(PCIDevice *dev);
 157     PCIUnregisterFunc *exit;
 158     PCIConfigReadFunc *config_read;
 159     PCIConfigWriteFunc *config_write;
 160
 161     uint16_t vendor_id;
 162     uint16_t device_id;
 163     uint8_t revision;
 164     uint16_t class_id;
 165     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 166     uint16_t subsystem_id;              /* only for header type = 0 */
 167
 168     /*
 169      * pci-to-pci bridge or normal device.
 170      * This doesn't mean pci host switch.
 171      * When card bus bridge is supported, this would be enhanced.
 172      */
 173     int is_bridge;
 174
 175     /* pcie stuff */
 176     int is_express;   /* is this device pci express? */
 177
 178     /* device isn't hot-pluggable */
 179     int no_hotplug;
 180
 181     /* rom bar */
 182     const char *romfile;
 183 } PCIDeviceClass;
 184
 185 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 186 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 187                                       MSIMessage msg);
 188 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 189
 190 struct PCIDevice {
 191     DeviceState qdev;
 192
 193     /* PCI config space */
 194     uint8_t *config;
 195
 196     /* Used to enable config checks on load. Note that writable bits are
 197      * never checked even if set in cmask. */
 198     uint8_t *cmask;
 199
 200     /* Used to implement R/W bytes */
 201     uint8_t *wmask;
 202
 203     /* Used to implement RW1C(Write 1 to Clear) bytes */
 204     uint8_t *w1cmask;
 205
 206     /* Used to allocate config space for capabilities. */
 207     uint8_t *used;
 208
 209     /* the following fields are read only */
 210     PCIBus *bus;
 211     int32_t devfn;
 212     char name[64];
 213     PCIIORegion io_regions[PCI_NUM_REGIONS];
 214     DMAContext *dma;
 215
 216     /* do not access the following fields */
 217     PCIConfigReadFunc *config_read;
 218     PCIConfigWriteFunc *config_write;
 219
 220     /* IRQ objects for the INTA-INTD pins.  */
 221     qemu_irq *irq;
 222
 223     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 224     uint8_t irq_state;
 225
 226     /* Capability bits */
 227     uint32_t cap_present;
 228
 229     /* Offset of MSI-X capability in config space */
 230     uint8_t msix_cap;
 231
 232     /* MSI-X entries */
 233     int msix_entries_nr;
 234
 235     /* Space to store MSIX table & pending bit array */
 236     uint8_t *msix_table;
 237     uint8_t *msix_pba;
 238     /* MemoryRegion container for msix exclusive BAR setup */
 239     MemoryRegion msix_exclusive_bar;
 240     /* Memory Regions for MSIX table and pending bit entries. */
 241     MemoryRegion msix_table_mmio;
 242     MemoryRegion msix_pba_mmio;
 243     /* Reference-count for entries actually in use by driver. */
 244     unsigned *msix_entry_used;
 245     /* MSIX function mask set or MSIX disabled */
 246     bool msix_function_masked;
 247     /* Version id needed for VMState */
 248     int32_t version_id;
 249
 250     /* Offset of MSI capability in config space */
 251     uint8_t msi_cap;
 252
 253     /* PCI Express */
 254     PCIExpressDevice exp;
 255
 256     /* SHPC */
 257     SHPCDevice *shpc;
 258
 259     /* Location of option rom */
 260     char *romfile;
 261     bool has_rom;
 262     MemoryRegion rom;
 263     uint32_t rom_bar;
 264
 265     /* INTx routing notifier */
 266     PCIINTxRoutingNotifier intx_routing_notifier;
 267
 268     /* MSI-X notifiers */
 269     MSIVectorUseNotifier msix_vector_use_notifier;
 270     MSIVectorReleaseNotifier msix_vector_release_notifier;
 271 };
 272
 273 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 274                       uint8_t attr, MemoryRegion *memory);
 275 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 276
 277 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 278                        uint8_t offset, uint8_t size);
 279
 280 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 281
 282 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 283
 284
 285 uint32_t pci_default_read_config(PCIDevice *d,
 286                                  uint32_t address, int len);
 287 void pci_default_write_config(PCIDevice *d,
 288                               uint32_t address, uint32_t val, int len);
 289 void pci_device_save(PCIDevice *s, QEMUFile *f);
 290 int pci_device_load(PCIDevice *s, QEMUFile *f);
 291 MemoryRegion *pci_address_space(PCIDevice *dev);
 292 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 293
 294 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 295 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 296 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 297
 298 typedef enum {
 299     PCI_HOTPLUG_DISABLED,
 300     PCI_HOTPLUG_ENABLED,
 301     PCI_COLDPLUG_ENABLED,
 302 } PCIHotplugState;
 303
 304 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 305                               PCIHotplugState state);
 306 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 307                          const char *name,
 308                          MemoryRegion *address_space_mem,
 309                          MemoryRegion *address_space_io,
 310                          uint8_t devfn_min);
 311 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 312                     MemoryRegion *address_space_mem,
 313                     MemoryRegion *address_space_io,
 314                     uint8_t devfn_min);
 315 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 316                   void *irq_opaque, int nirq);
 317 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 318 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 319 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 320                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 321                          void *irq_opaque,
 322                          MemoryRegion *address_space_mem,
 323                          MemoryRegion *address_space_io,
 324                          uint8_t devfn_min, int nirq);
 325 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 326 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 327 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 328 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 329                                           PCIINTxRoutingNotifier notifier);
 330 void pci_device_reset(PCIDevice *dev);
 331 void pci_bus_reset(PCIBus *bus);
 332
 333 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 334                         const char *default_devaddr);
 335 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 336                                const char *default_devaddr);
 337
 338 PCIDevice *pci_vga_init(PCIBus *bus);
 339
 340 int pci_bus_num(PCIBus *s);
 341 void pci_for_each_device(PCIBus *bus, int bus_num,
 342                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 343                          void *opaque);
 344 PCIBus *pci_find_root_bus(int domain);
 345 int pci_find_domain(const PCIBus *bus);
 346 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 347 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 348 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 349
 350 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 351                      unsigned *slotp);
 352
 353 void pci_device_deassert_intx(PCIDevice *dev);
 354
 355 typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int);
 356
 357 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque);
 358
 359 static inline void
 360 pci_set_byte(uint8_t *config, uint8_t val)
 361 {
 362     *config = val;
 363 }
 364
 365 static inline uint8_t
 366 pci_get_byte(const uint8_t *config)
 367 {
 368     return *config;
 369 }
 370
 371 static inline void
 372 pci_set_word(uint8_t *config, uint16_t val)
 373 {
 374     cpu_to_le16wu((uint16_t *)config, val);
 375 }
 376
 377 static inline uint16_t
 378 pci_get_word(const uint8_t *config)
 379 {
 380     return le16_to_cpupu((const uint16_t *)config);
 381 }
 382
 383 static inline void
 384 pci_set_long(uint8_t *config, uint32_t val)
 385 {
 386     cpu_to_le32wu((uint32_t *)config, val);
 387 }
 388
 389 static inline uint32_t
 390 pci_get_long(const uint8_t *config)
 391 {
 392     return le32_to_cpupu((const uint32_t *)config);
 393 }
 394
 395 static inline void
 396 pci_set_quad(uint8_t *config, uint64_t val)
 397 {
 398     cpu_to_le64w((uint64_t *)config, val);
 399 }
 400
 401 static inline uint64_t
 402 pci_get_quad(const uint8_t *config)
 403 {
 404     return le64_to_cpup((const uint64_t *)config);
 405 }
 406
 407 static inline void
 408 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 409 {
 410     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 411 }
 412
 413 static inline void
 414 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 415 {
 416     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 417 }
 418
 419 static inline void
 420 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 421 {
 422     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 423 }
 424
 425 static inline void
 426 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 427 {
 428     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 429 }
 430
 431 static inline void
 432 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 433 {
 434     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 435 }
 436
 437 static inline void
 438 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 439 {
 440     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 441 }
 442
 443 /*
 444  * helper functions to do bit mask operation on configuration space.
 445  * Just to set bit, use test-and-set and discard returned value.
 446  * Just to clear bit, use test-and-clear and discard returned value.
 447  * NOTE: They aren't atomic.
 448  */
 449 static inline uint8_t
 450 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 451 {
 452     uint8_t val = pci_get_byte(config);
 453     pci_set_byte(config, val & ~mask);
 454     return val & mask;
 455 }
 456
 457 static inline uint8_t
 458 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 459 {
 460     uint8_t val = pci_get_byte(config);
 461     pci_set_byte(config, val | mask);
 462     return val & mask;
 463 }
 464
 465 static inline uint16_t
 466 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 467 {
 468     uint16_t val = pci_get_word(config);
 469     pci_set_word(config, val & ~mask);
 470     return val & mask;
 471 }
 472
 473 static inline uint16_t
 474 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 475 {
 476     uint16_t val = pci_get_word(config);
 477     pci_set_word(config, val | mask);
 478     return val & mask;
 479 }
 480
 481 static inline uint32_t
 482 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 483 {
 484     uint32_t val = pci_get_long(config);
 485     pci_set_long(config, val & ~mask);
 486     return val & mask;
 487 }
 488
 489 static inline uint32_t
 490 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 491 {
 492     uint32_t val = pci_get_long(config);
 493     pci_set_long(config, val | mask);
 494     return val & mask;
 495 }
 496
 497 static inline uint64_t
 498 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 499 {
 500     uint64_t val = pci_get_quad(config);
 501     pci_set_quad(config, val & ~mask);
 502     return val & mask;
 503 }
 504
 505 static inline uint64_t
 506 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 507 {
 508     uint64_t val = pci_get_quad(config);
 509     pci_set_quad(config, val | mask);
 510     return val & mask;
 511 }
 512
 513 /* Access a register specified by a mask */
 514 static inline void
 515 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 516 {
 517     uint8_t val = pci_get_byte(config);
 518     uint8_t rval = reg << (ffs(mask) - 1);
 519     pci_set_byte(config, (~mask & val) | (mask & rval));
 520 }
 521
 522 static inline uint8_t
 523 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 524 {
 525     uint8_t val = pci_get_byte(config);
 526     return (val & mask) >> (ffs(mask) - 1);
 527 }
 528
 529 static inline void
 530 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 531 {
 532     uint16_t val = pci_get_word(config);
 533     uint16_t rval = reg << (ffs(mask) - 1);
 534     pci_set_word(config, (~mask & val) | (mask & rval));
 535 }
 536
 537 static inline uint16_t
 538 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 539 {
 540     uint16_t val = pci_get_word(config);
 541     return (val & mask) >> (ffs(mask) - 1);
 542 }
 543
 544 static inline void
 545 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 546 {
 547     uint32_t val = pci_get_long(config);
 548     uint32_t rval = reg << (ffs(mask) - 1);
 549     pci_set_long(config, (~mask & val) | (mask & rval));
 550 }
 551
 552 static inline uint32_t
 553 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 554 {
 555     uint32_t val = pci_get_long(config);
 556     return (val & mask) >> (ffs(mask) - 1);
 557 }
 558
 559 static inline void
 560 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 561 {
 562     uint64_t val = pci_get_quad(config);
 563     uint64_t rval = reg << (ffs(mask) - 1);
 564     pci_set_quad(config, (~mask & val) | (mask & rval));
 565 }
 566
 567 static inline uint64_t
 568 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 569 {
 570     uint64_t val = pci_get_quad(config);
 571     return (val & mask) >> (ffs(mask) - 1);
 572 }
 573
 574 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 575                                     const char *name);
 576 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 577                                            bool multifunction,
 578                                            const char *name);
 579 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 580 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 581
 582 static inline int pci_is_express(const PCIDevice *d)
 583 {
 584     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 585 }
 586
 587 static inline uint32_t pci_config_size(const PCIDevice *d)
 588 {
 589     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 590 }
 591
 592 /* DMA access functions */
 593 static inline DMAContext *pci_dma_context(PCIDevice *dev)
 594 {
 595     return dev->dma;
 596 }
 597
 598 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 599                              void *buf, dma_addr_t len, DMADirection dir)
 600 {
 601     dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir);
 602     return 0;
 603 }
 604
 605 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 606                                void *buf, dma_addr_t len)
 607 {
 608     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 609 }
 610
 611 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 612                                 const void *buf, dma_addr_t len)
 613 {
 614     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 615 }
 616
 617 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 618     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 619                                                    dma_addr_t addr)     \
 620     {                                                                   \
 621         return ld##_l##_dma(pci_dma_context(dev), addr);                \
 622     }                                                                   \
 623     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 624                                         dma_addr_t addr, uint##_bits##_t val) \
 625     {                                                                   \
 626         st##_s##_dma(pci_dma_context(dev), addr, val);                  \
 627     }
 628
 629 PCI_DMA_DEFINE_LDST(ub, b, 8);
 630 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 631 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 632 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 633 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 634 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 635 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 636
 637 #undef PCI_DMA_DEFINE_LDST
 638
 639 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 640                                 dma_addr_t *plen, DMADirection dir)
 641 {
 642     void *buf;
 643
 644     buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir);
 645     return buf;
 646 }
 647
 648 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 649                                  DMADirection dir, dma_addr_t access_len)
 650 {
 651     dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len);
 652 }
 653
 654 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 655                                        int alloc_hint)
 656 {
 657     qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev));
 658 }
 659
 660 extern const VMStateDescription vmstate_pci_device;
 661
 662 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 663     .name       = (stringify(_field)),                               \
 664     .size       = sizeof(PCIDevice),                                 \
 665     .vmsd       = &vmstate_pci_device,                               \
 666     .flags      = VMS_STRUCT,                                        \
 667     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 668 }
 669
 670 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 671     .name       = (stringify(_field)),                               \
 672     .size       = sizeof(PCIDevice),                                 \
 673     .vmsd       = &vmstate_pci_device,                               \
 674     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 675     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 676 }
 677
 678 #endif