4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
132 fprintf_function cpu_fprintf
, int flags
)
134 ARMCPU
*cpu
= ARM_CPU(cs
);
135 CPUARMState
*env
= &cpu
->env
;
136 uint32_t psr
= pstate_read(env
);
138 int el
= arm_current_el(env
);
139 const char *ns_status
;
141 cpu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
142 for (i
= 0; i
< 32; i
++) {
144 cpu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
146 cpu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
147 (i
+ 2) % 3 ? " " : "\n");
151 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
152 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
156 cpu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
158 psr
& PSTATE_N
? 'N' : '-',
159 psr
& PSTATE_Z
? 'Z' : '-',
160 psr
& PSTATE_C
? 'C' : '-',
161 psr
& PSTATE_V
? 'V' : '-',
164 psr
& PSTATE_SP
? 'h' : 't');
166 if (!(flags
& CPU_DUMP_FPU
)) {
167 cpu_fprintf(f
, "\n");
170 if (fp_exception_el(env
, el
) != 0) {
171 cpu_fprintf(f
, " FPU disabled\n");
174 cpu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
175 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
177 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
178 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
180 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
182 if (i
== FFR_PRED_NUM
) {
183 cpu_fprintf(f
, "FFR=");
184 /* It's last, so end the line. */
187 cpu_fprintf(f
, "P%02d=", i
);
200 /* More than one quadword per predicate. */
205 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
207 if (j
* 4 + 4 <= zcr_len
+ 1) {
210 digits
= (zcr_len
% 4 + 1) * 4;
212 cpu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
213 env
->vfp
.pregs
[i
].p
[j
],
214 j
? ":" : eol
? "\n" : " ");
218 for (i
= 0; i
< 32; i
++) {
220 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
221 i
, env
->vfp
.zregs
[i
].d
[1],
222 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
223 } else if (zcr_len
== 1) {
224 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
225 ":%016" PRIx64
":%016" PRIx64
"\n",
226 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
227 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
229 for (j
= zcr_len
; j
>= 0; j
--) {
230 bool odd
= (zcr_len
- j
) % 2 != 0;
232 cpu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
235 cpu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
237 cpu_fprintf(f
, " [%x]=", j
);
240 cpu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
241 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
242 env
->vfp
.zregs
[i
].d
[j
* 2],
243 odd
|| j
== 0 ? "\n" : ":");
248 for (i
= 0; i
< 32; i
++) {
249 uint64_t *q
= aa64_vfp_qreg(env
, i
);
250 cpu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
251 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
256 void gen_a64_set_pc_im(uint64_t val
)
258 tcg_gen_movi_i64(cpu_pc
, val
);
261 /* Load the PC from a generic TCG variable.
263 * If address tagging is enabled via the TCR TBI bits, then loading
264 * an address into the PC will clear out any tag in the it:
265 * + for EL2 and EL3 there is only one TBI bit, and if it is set
266 * then the address is zero-extended, clearing bits [63:56]
267 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
268 * and TBI1 controls addressses with bit 55 == 1.
269 * If the appropriate TBI bit is set for the address then
270 * the address is sign-extended from bit 55 into bits [63:56]
272 * We can avoid doing this for relative-branches, because the
273 * PC + offset can never overflow into the tag bits (assuming
274 * that virtual addresses are less than 56 bits wide, as they
275 * are currently), but we must handle it for branch-to-register.
277 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
280 if (s
->current_el
<= 1) {
281 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
282 * examine bit 55 of address, can just generate code.
283 * If mixed, then test via generated code
285 if (s
->tbi0
&& s
->tbi1
) {
286 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
287 /* Both bits set, sign extension from bit 55 into [63:56] will
290 tcg_gen_shli_i64(tmp_reg
, src
, 8);
291 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
292 tcg_temp_free_i64(tmp_reg
);
293 } else if (!s
->tbi0
&& !s
->tbi1
) {
294 /* Neither bit set, just load it as-is */
295 tcg_gen_mov_i64(cpu_pc
, src
);
297 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
298 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
299 TCGv_i64 tcg_zero
= tcg_const_i64(0);
301 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
304 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
305 tcg_gen_andi_i64(tcg_tmpval
, src
,
306 0x00FFFFFFFFFFFFFFull
);
307 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
310 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
311 tcg_gen_ori_i64(tcg_tmpval
, src
,
312 0xFF00000000000000ull
);
313 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
316 tcg_temp_free_i64(tcg_zero
);
317 tcg_temp_free_i64(tcg_bit55
);
318 tcg_temp_free_i64(tcg_tmpval
);
320 } else { /* EL > 1 */
322 /* Force tag byte to all zero */
323 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
325 /* Load unmodified address */
326 tcg_gen_mov_i64(cpu_pc
, src
);
331 typedef struct DisasCompare64
{
336 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
340 arm_test_cc(&c32
, cc
);
342 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
343 * properly. The NE/EQ comparisons are also fine with this choice. */
344 c64
->cond
= c32
.cond
;
345 c64
->value
= tcg_temp_new_i64();
346 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
351 static void a64_free_cc(DisasCompare64
*c64
)
353 tcg_temp_free_i64(c64
->value
);
356 static void gen_exception_internal(int excp
)
358 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
360 assert(excp_is_internal(excp
));
361 gen_helper_exception_internal(cpu_env
, tcg_excp
);
362 tcg_temp_free_i32(tcg_excp
);
365 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
367 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
368 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
369 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
371 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
373 tcg_temp_free_i32(tcg_el
);
374 tcg_temp_free_i32(tcg_syn
);
375 tcg_temp_free_i32(tcg_excp
);
378 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
380 gen_a64_set_pc_im(s
->pc
- offset
);
381 gen_exception_internal(excp
);
382 s
->base
.is_jmp
= DISAS_NORETURN
;
385 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
386 uint32_t syndrome
, uint32_t target_el
)
388 gen_a64_set_pc_im(s
->pc
- offset
);
389 gen_exception(excp
, syndrome
, target_el
);
390 s
->base
.is_jmp
= DISAS_NORETURN
;
393 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
398 gen_a64_set_pc_im(s
->pc
- offset
);
399 tcg_syn
= tcg_const_i32(syndrome
);
400 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
401 tcg_temp_free_i32(tcg_syn
);
402 s
->base
.is_jmp
= DISAS_NORETURN
;
405 static void gen_ss_advance(DisasContext
*s
)
407 /* If the singlestep state is Active-not-pending, advance to
412 gen_helper_clear_pstate_ss(cpu_env
);
416 static void gen_step_complete_exception(DisasContext
*s
)
418 /* We just completed step of an insn. Move from Active-not-pending
419 * to Active-pending, and then also take the swstep exception.
420 * This corresponds to making the (IMPDEF) choice to prioritize
421 * swstep exceptions over asynchronous exceptions taken to an exception
422 * level where debug is disabled. This choice has the advantage that
423 * we do not need to maintain internal state corresponding to the
424 * ISV/EX syndrome bits between completion of the step and generation
425 * of the exception, and our syndrome information is always correct.
428 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
429 default_exception_el(s
));
430 s
->base
.is_jmp
= DISAS_NORETURN
;
433 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
435 /* No direct tb linking with singlestep (either QEMU's or the ARM
436 * debug architecture kind) or deterministic io
438 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
439 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
443 #ifndef CONFIG_USER_ONLY
444 /* Only link tbs from inside the same guest page */
445 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
453 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
455 TranslationBlock
*tb
;
458 if (use_goto_tb(s
, n
, dest
)) {
460 gen_a64_set_pc_im(dest
);
461 tcg_gen_exit_tb(tb
, n
);
462 s
->base
.is_jmp
= DISAS_NORETURN
;
464 gen_a64_set_pc_im(dest
);
466 gen_step_complete_exception(s
);
467 } else if (s
->base
.singlestep_enabled
) {
468 gen_exception_internal(EXCP_DEBUG
);
470 tcg_gen_lookup_and_goto_ptr();
471 s
->base
.is_jmp
= DISAS_NORETURN
;
476 void unallocated_encoding(DisasContext
*s
)
478 /* Unallocated and reserved encodings are uncategorized */
479 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
480 default_exception_el(s
));
483 static void init_tmp_a64_array(DisasContext
*s
)
485 #ifdef CONFIG_DEBUG_TCG
486 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
488 s
->tmp_a64_count
= 0;
491 static void free_tmp_a64(DisasContext
*s
)
494 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
495 tcg_temp_free_i64(s
->tmp_a64
[i
]);
497 init_tmp_a64_array(s
);
500 TCGv_i64
new_tmp_a64(DisasContext
*s
)
502 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
503 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
506 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
508 TCGv_i64 t
= new_tmp_a64(s
);
509 tcg_gen_movi_i64(t
, 0);
514 * Register access functions
516 * These functions are used for directly accessing a register in where
517 * changes to the final register value are likely to be made. If you
518 * need to use a register for temporary calculation (e.g. index type
519 * operations) use the read_* form.
521 * B1.2.1 Register mappings
523 * In instruction register encoding 31 can refer to ZR (zero register) or
524 * the SP (stack pointer) depending on context. In QEMU's case we map SP
525 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
526 * This is the point of the _sp forms.
528 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
531 return new_tmp_a64_zero(s
);
537 /* register access for when 31 == SP */
538 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
543 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
544 * representing the register contents. This TCGv is an auto-freed
545 * temporary so it need not be explicitly freed, and may be modified.
547 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
549 TCGv_i64 v
= new_tmp_a64(s
);
552 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
554 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
557 tcg_gen_movi_i64(v
, 0);
562 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
564 TCGv_i64 v
= new_tmp_a64(s
);
566 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
568 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
573 /* Return the offset into CPUARMState of a slice (from
574 * the least significant end) of FP register Qn (ie
576 * (Note that this is not the same mapping as for A32; see cpu.h)
578 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
580 return vec_reg_offset(s
, regno
, 0, size
);
583 /* Offset of the high half of the 128 bit vector Qn */
584 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
586 return vec_reg_offset(s
, regno
, 1, MO_64
);
589 /* Convenience accessors for reading and writing single and double
590 * FP registers. Writing clears the upper parts of the associated
591 * 128 bit vector register, as required by the architecture.
592 * Note that unlike the GP register accessors, the values returned
593 * by the read functions must be manually freed.
595 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
597 TCGv_i64 v
= tcg_temp_new_i64();
599 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
603 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
605 TCGv_i32 v
= tcg_temp_new_i32();
607 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
611 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
613 TCGv_i32 v
= tcg_temp_new_i32();
615 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
619 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
620 * If SVE is not enabled, then there are only 128 bits in the vector.
622 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
624 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
625 unsigned vsz
= vec_full_reg_size(s
);
628 TCGv_i64 tcg_zero
= tcg_const_i64(0);
629 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
630 tcg_temp_free_i64(tcg_zero
);
633 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
637 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
639 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
641 tcg_gen_st_i64(v
, cpu_env
, ofs
);
642 clear_vec_high(s
, false, reg
);
645 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
647 TCGv_i64 tmp
= tcg_temp_new_i64();
649 tcg_gen_extu_i32_i64(tmp
, v
);
650 write_fp_dreg(s
, reg
, tmp
);
651 tcg_temp_free_i64(tmp
);
654 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
656 TCGv_ptr statusptr
= tcg_temp_new_ptr();
659 /* In A64 all instructions (both FP and Neon) use the FPCR; there
660 * is no equivalent of the A32 Neon "standard FPSCR value".
661 * However half-precision operations operate under a different
662 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
665 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
667 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
669 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
673 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
674 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
675 GVecGen2Fn
*gvec_fn
, int vece
)
677 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
678 is_q
? 16 : 8, vec_full_reg_size(s
));
681 /* Expand a 2-operand + immediate AdvSIMD vector operation using
682 * an expander function.
684 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
685 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
687 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
688 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
691 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
692 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
693 GVecGen3Fn
*gvec_fn
, int vece
)
695 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
696 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
699 /* Expand a 2-operand + immediate AdvSIMD vector operation using
702 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
703 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
705 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
706 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
709 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
710 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
711 int rn
, int rm
, const GVecGen3
*gvec_op
)
713 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
714 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
715 vec_full_reg_size(s
), gvec_op
);
718 /* Expand a 3-operand operation using an out-of-line helper. */
719 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
720 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
722 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
723 vec_full_reg_offset(s
, rn
),
724 vec_full_reg_offset(s
, rm
),
725 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
728 /* Expand a 3-operand + env pointer operation using
729 * an out-of-line helper.
731 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
732 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
734 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
735 vec_full_reg_offset(s
, rn
),
736 vec_full_reg_offset(s
, rm
), cpu_env
,
737 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
740 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
741 * an out-of-line helper.
743 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
744 int rm
, bool is_fp16
, int data
,
745 gen_helper_gvec_3_ptr
*fn
)
747 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
748 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
749 vec_full_reg_offset(s
, rn
),
750 vec_full_reg_offset(s
, rm
), fpst
,
751 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
752 tcg_temp_free_ptr(fpst
);
755 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
756 * than the 32 bit equivalent.
758 static inline void gen_set_NZ64(TCGv_i64 result
)
760 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
761 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
764 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
765 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
768 gen_set_NZ64(result
);
770 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
771 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
773 tcg_gen_movi_i32(cpu_CF
, 0);
774 tcg_gen_movi_i32(cpu_VF
, 0);
777 /* dest = T0 + T1; compute C, N, V and Z flags */
778 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
781 TCGv_i64 result
, flag
, tmp
;
782 result
= tcg_temp_new_i64();
783 flag
= tcg_temp_new_i64();
784 tmp
= tcg_temp_new_i64();
786 tcg_gen_movi_i64(tmp
, 0);
787 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
789 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
791 gen_set_NZ64(result
);
793 tcg_gen_xor_i64(flag
, result
, t0
);
794 tcg_gen_xor_i64(tmp
, t0
, t1
);
795 tcg_gen_andc_i64(flag
, flag
, tmp
);
796 tcg_temp_free_i64(tmp
);
797 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
799 tcg_gen_mov_i64(dest
, result
);
800 tcg_temp_free_i64(result
);
801 tcg_temp_free_i64(flag
);
803 /* 32 bit arithmetic */
804 TCGv_i32 t0_32
= tcg_temp_new_i32();
805 TCGv_i32 t1_32
= tcg_temp_new_i32();
806 TCGv_i32 tmp
= tcg_temp_new_i32();
808 tcg_gen_movi_i32(tmp
, 0);
809 tcg_gen_extrl_i64_i32(t0_32
, t0
);
810 tcg_gen_extrl_i64_i32(t1_32
, t1
);
811 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
812 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
813 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
814 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
815 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
816 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
818 tcg_temp_free_i32(tmp
);
819 tcg_temp_free_i32(t0_32
);
820 tcg_temp_free_i32(t1_32
);
824 /* dest = T0 - T1; compute C, N, V and Z flags */
825 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
828 /* 64 bit arithmetic */
829 TCGv_i64 result
, flag
, tmp
;
831 result
= tcg_temp_new_i64();
832 flag
= tcg_temp_new_i64();
833 tcg_gen_sub_i64(result
, t0
, t1
);
835 gen_set_NZ64(result
);
837 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
838 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
840 tcg_gen_xor_i64(flag
, result
, t0
);
841 tmp
= tcg_temp_new_i64();
842 tcg_gen_xor_i64(tmp
, t0
, t1
);
843 tcg_gen_and_i64(flag
, flag
, tmp
);
844 tcg_temp_free_i64(tmp
);
845 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
846 tcg_gen_mov_i64(dest
, result
);
847 tcg_temp_free_i64(flag
);
848 tcg_temp_free_i64(result
);
850 /* 32 bit arithmetic */
851 TCGv_i32 t0_32
= tcg_temp_new_i32();
852 TCGv_i32 t1_32
= tcg_temp_new_i32();
855 tcg_gen_extrl_i64_i32(t0_32
, t0
);
856 tcg_gen_extrl_i64_i32(t1_32
, t1
);
857 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
858 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
859 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
860 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
861 tmp
= tcg_temp_new_i32();
862 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
863 tcg_temp_free_i32(t0_32
);
864 tcg_temp_free_i32(t1_32
);
865 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
866 tcg_temp_free_i32(tmp
);
867 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
871 /* dest = T0 + T1 + CF; do not compute flags. */
872 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
874 TCGv_i64 flag
= tcg_temp_new_i64();
875 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
876 tcg_gen_add_i64(dest
, t0
, t1
);
877 tcg_gen_add_i64(dest
, dest
, flag
);
878 tcg_temp_free_i64(flag
);
881 tcg_gen_ext32u_i64(dest
, dest
);
885 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
886 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
889 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
890 result
= tcg_temp_new_i64();
891 cf_64
= tcg_temp_new_i64();
892 vf_64
= tcg_temp_new_i64();
893 tmp
= tcg_const_i64(0);
895 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
896 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
897 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
898 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
899 gen_set_NZ64(result
);
901 tcg_gen_xor_i64(vf_64
, result
, t0
);
902 tcg_gen_xor_i64(tmp
, t0
, t1
);
903 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
904 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
906 tcg_gen_mov_i64(dest
, result
);
908 tcg_temp_free_i64(tmp
);
909 tcg_temp_free_i64(vf_64
);
910 tcg_temp_free_i64(cf_64
);
911 tcg_temp_free_i64(result
);
913 TCGv_i32 t0_32
, t1_32
, tmp
;
914 t0_32
= tcg_temp_new_i32();
915 t1_32
= tcg_temp_new_i32();
916 tmp
= tcg_const_i32(0);
918 tcg_gen_extrl_i64_i32(t0_32
, t0
);
919 tcg_gen_extrl_i64_i32(t1_32
, t1
);
920 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
921 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
923 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
924 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
925 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
926 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
927 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
929 tcg_temp_free_i32(tmp
);
930 tcg_temp_free_i32(t1_32
);
931 tcg_temp_free_i32(t0_32
);
936 * Load/Store generators
940 * Store from GPR register to memory.
942 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
943 TCGv_i64 tcg_addr
, int size
, int memidx
,
945 unsigned int iss_srt
,
946 bool iss_sf
, bool iss_ar
)
949 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
954 syn
= syn_data_abort_with_iss(0,
960 0, 0, 0, 0, 0, false);
961 disas_set_insn_syndrome(s
, syn
);
965 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
966 TCGv_i64 tcg_addr
, int size
,
968 unsigned int iss_srt
,
969 bool iss_sf
, bool iss_ar
)
971 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
972 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
976 * Load from memory to GPR register
978 static void do_gpr_ld_memidx(DisasContext
*s
,
979 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
980 int size
, bool is_signed
,
981 bool extend
, int memidx
,
982 bool iss_valid
, unsigned int iss_srt
,
983 bool iss_sf
, bool iss_ar
)
985 TCGMemOp memop
= s
->be_data
+ size
;
993 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
995 if (extend
&& is_signed
) {
997 tcg_gen_ext32u_i64(dest
, dest
);
1003 syn
= syn_data_abort_with_iss(0,
1009 0, 0, 0, 0, 0, false);
1010 disas_set_insn_syndrome(s
, syn
);
1014 static void do_gpr_ld(DisasContext
*s
,
1015 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1016 int size
, bool is_signed
, bool extend
,
1017 bool iss_valid
, unsigned int iss_srt
,
1018 bool iss_sf
, bool iss_ar
)
1020 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1022 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1026 * Store from FP register to memory
1028 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1030 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1031 TCGv_i64 tmp
= tcg_temp_new_i64();
1032 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1034 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1037 bool be
= s
->be_data
== MO_BE
;
1038 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1040 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1041 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1043 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1044 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1046 tcg_temp_free_i64(tcg_hiaddr
);
1049 tcg_temp_free_i64(tmp
);
1053 * Load from memory to FP register
1055 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1057 /* This always zero-extends and writes to a full 128 bit wide vector */
1058 TCGv_i64 tmplo
= tcg_temp_new_i64();
1062 TCGMemOp memop
= s
->be_data
+ size
;
1063 tmphi
= tcg_const_i64(0);
1064 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1066 bool be
= s
->be_data
== MO_BE
;
1067 TCGv_i64 tcg_hiaddr
;
1069 tmphi
= tcg_temp_new_i64();
1070 tcg_hiaddr
= tcg_temp_new_i64();
1072 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1073 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1075 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1077 tcg_temp_free_i64(tcg_hiaddr
);
1080 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1081 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1083 tcg_temp_free_i64(tmplo
);
1084 tcg_temp_free_i64(tmphi
);
1086 clear_vec_high(s
, true, destidx
);
1090 * Vector load/store helpers.
1092 * The principal difference between this and a FP load is that we don't
1093 * zero extend as we are filling a partial chunk of the vector register.
1094 * These functions don't support 128 bit loads/stores, which would be
1095 * normal load/store operations.
1097 * The _i32 versions are useful when operating on 32 bit quantities
1098 * (eg for floating point single or using Neon helper functions).
1101 /* Get value of an element within a vector register */
1102 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1103 int element
, TCGMemOp memop
)
1105 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1108 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1111 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1114 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1117 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1120 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1123 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1127 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1130 g_assert_not_reached();
1134 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1135 int element
, TCGMemOp memop
)
1137 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1140 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1143 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1146 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1149 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1153 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1156 g_assert_not_reached();
1160 /* Set value of an element within a vector register */
1161 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1162 int element
, TCGMemOp memop
)
1164 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1167 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1170 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1173 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1176 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1179 g_assert_not_reached();
1183 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1184 int destidx
, int element
, TCGMemOp memop
)
1186 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1189 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1192 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1195 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1198 g_assert_not_reached();
1202 /* Store from vector register to memory */
1203 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1204 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1206 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1208 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1209 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1211 tcg_temp_free_i64(tcg_tmp
);
1214 /* Load from memory to vector register */
1215 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1216 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1218 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1220 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1221 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1223 tcg_temp_free_i64(tcg_tmp
);
1226 /* Check that FP/Neon access is enabled. If it is, return
1227 * true. If not, emit code to generate an appropriate exception,
1228 * and return false; the caller should not emit any code for
1229 * the instruction. Note that this check must happen after all
1230 * unallocated-encoding checks (otherwise the syndrome information
1231 * for the resulting exception will be incorrect).
1233 static inline bool fp_access_check(DisasContext
*s
)
1235 assert(!s
->fp_access_checked
);
1236 s
->fp_access_checked
= true;
1238 if (!s
->fp_excp_el
) {
1242 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1247 /* Check that SVE access is enabled. If it is, return true.
1248 * If not, emit code to generate an appropriate exception and return false.
1250 bool sve_access_check(DisasContext
*s
)
1252 if (s
->sve_excp_el
) {
1253 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1257 return fp_access_check(s
);
1261 * This utility function is for doing register extension with an
1262 * optional shift. You will likely want to pass a temporary for the
1263 * destination register. See DecodeRegExtend() in the ARM ARM.
1265 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1266 int option
, unsigned int shift
)
1268 int extsize
= extract32(option
, 0, 2);
1269 bool is_signed
= extract32(option
, 2, 1);
1274 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1277 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1280 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1283 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1289 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1292 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1295 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1298 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1304 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1308 static inline void gen_check_sp_alignment(DisasContext
*s
)
1310 /* The AArch64 architecture mandates that (if enabled via PSTATE
1311 * or SCTLR bits) there is a check that SP is 16-aligned on every
1312 * SP-relative load or store (with an exception generated if it is not).
1313 * In line with general QEMU practice regarding misaligned accesses,
1314 * we omit these checks for the sake of guest program performance.
1315 * This function is provided as a hook so we can more easily add these
1316 * checks in future (possibly as a "favour catching guest program bugs
1317 * over speed" user selectable option).
1322 * This provides a simple table based table lookup decoder. It is
1323 * intended to be used when the relevant bits for decode are too
1324 * awkwardly placed and switch/if based logic would be confusing and
1325 * deeply nested. Since it's a linear search through the table, tables
1326 * should be kept small.
1328 * It returns the first handler where insn & mask == pattern, or
1329 * NULL if there is no match.
1330 * The table is terminated by an empty mask (i.e. 0)
1332 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1335 const AArch64DecodeTable
*tptr
= table
;
1337 while (tptr
->mask
) {
1338 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1339 return tptr
->disas_fn
;
1347 * The instruction disassembly implemented here matches
1348 * the instruction encoding classifications in chapter C4
1349 * of the ARM Architecture Reference Manual (DDI0487B_a);
1350 * classification names and decode diagrams here should generally
1351 * match up with those in the manual.
1354 /* Unconditional branch (immediate)
1356 * +----+-----------+-------------------------------------+
1357 * | op | 0 0 1 0 1 | imm26 |
1358 * +----+-----------+-------------------------------------+
1360 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1362 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1364 if (insn
& (1U << 31)) {
1365 /* BL Branch with link */
1366 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1369 /* B Branch / BL Branch with link */
1370 gen_goto_tb(s
, 0, addr
);
1373 /* Compare and branch (immediate)
1374 * 31 30 25 24 23 5 4 0
1375 * +----+-------------+----+---------------------+--------+
1376 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1377 * +----+-------------+----+---------------------+--------+
1379 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1381 unsigned int sf
, op
, rt
;
1383 TCGLabel
*label_match
;
1386 sf
= extract32(insn
, 31, 1);
1387 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1388 rt
= extract32(insn
, 0, 5);
1389 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1391 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1392 label_match
= gen_new_label();
1394 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1395 tcg_cmp
, 0, label_match
);
1397 gen_goto_tb(s
, 0, s
->pc
);
1398 gen_set_label(label_match
);
1399 gen_goto_tb(s
, 1, addr
);
1402 /* Test and branch (immediate)
1403 * 31 30 25 24 23 19 18 5 4 0
1404 * +----+-------------+----+-------+-------------+------+
1405 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1406 * +----+-------------+----+-------+-------------+------+
1408 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1410 unsigned int bit_pos
, op
, rt
;
1412 TCGLabel
*label_match
;
1415 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1416 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1417 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1418 rt
= extract32(insn
, 0, 5);
1420 tcg_cmp
= tcg_temp_new_i64();
1421 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1422 label_match
= gen_new_label();
1423 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1424 tcg_cmp
, 0, label_match
);
1425 tcg_temp_free_i64(tcg_cmp
);
1426 gen_goto_tb(s
, 0, s
->pc
);
1427 gen_set_label(label_match
);
1428 gen_goto_tb(s
, 1, addr
);
1431 /* Conditional branch (immediate)
1432 * 31 25 24 23 5 4 3 0
1433 * +---------------+----+---------------------+----+------+
1434 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1435 * +---------------+----+---------------------+----+------+
1437 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1442 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1443 unallocated_encoding(s
);
1446 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1447 cond
= extract32(insn
, 0, 4);
1450 /* genuinely conditional branches */
1451 TCGLabel
*label_match
= gen_new_label();
1452 arm_gen_test_cc(cond
, label_match
);
1453 gen_goto_tb(s
, 0, s
->pc
);
1454 gen_set_label(label_match
);
1455 gen_goto_tb(s
, 1, addr
);
1457 /* 0xe and 0xf are both "always" conditions */
1458 gen_goto_tb(s
, 0, addr
);
1462 /* HINT instruction group, including various allocated HINTs */
1463 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1464 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1466 unsigned int selector
= crm
<< 3 | op2
;
1469 unallocated_encoding(s
);
1477 s
->base
.is_jmp
= DISAS_WFI
;
1479 /* When running in MTTCG we don't generate jumps to the yield and
1480 * WFE helpers as it won't affect the scheduling of other vCPUs.
1481 * If we wanted to more completely model WFE/SEV so we don't busy
1482 * spin unnecessarily we would need to do something more involved.
1485 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1486 s
->base
.is_jmp
= DISAS_YIELD
;
1490 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1491 s
->base
.is_jmp
= DISAS_WFE
;
1496 /* we treat all as NOP at least for now */
1499 /* default specified as NOP equivalent */
1504 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1506 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1509 /* CLREX, DSB, DMB, ISB */
1510 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1511 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1516 unallocated_encoding(s
);
1527 case 1: /* MBReqTypes_Reads */
1528 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1530 case 2: /* MBReqTypes_Writes */
1531 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1533 default: /* MBReqTypes_All */
1534 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1540 /* We need to break the TB after this insn to execute
1541 * a self-modified code correctly and also to take
1542 * any pending interrupts immediately.
1544 gen_goto_tb(s
, 0, s
->pc
);
1547 unallocated_encoding(s
);
1552 /* MSR (immediate) - move immediate to processor state field */
1553 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1554 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1556 int op
= op1
<< 3 | op2
;
1558 case 0x05: /* SPSel */
1559 if (s
->current_el
== 0) {
1560 unallocated_encoding(s
);
1564 case 0x1e: /* DAIFSet */
1565 case 0x1f: /* DAIFClear */
1567 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1568 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1569 gen_a64_set_pc_im(s
->pc
- 4);
1570 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1571 tcg_temp_free_i32(tcg_imm
);
1572 tcg_temp_free_i32(tcg_op
);
1573 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1574 gen_a64_set_pc_im(s
->pc
);
1575 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1579 unallocated_encoding(s
);
1584 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1586 TCGv_i32 tmp
= tcg_temp_new_i32();
1587 TCGv_i32 nzcv
= tcg_temp_new_i32();
1589 /* build bit 31, N */
1590 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1591 /* build bit 30, Z */
1592 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1593 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1594 /* build bit 29, C */
1595 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1596 /* build bit 28, V */
1597 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1598 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1599 /* generate result */
1600 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1602 tcg_temp_free_i32(nzcv
);
1603 tcg_temp_free_i32(tmp
);
1606 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1609 TCGv_i32 nzcv
= tcg_temp_new_i32();
1611 /* take NZCV from R[t] */
1612 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1615 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1617 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1618 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1620 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1621 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1623 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1624 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1625 tcg_temp_free_i32(nzcv
);
1628 /* MRS - move from system register
1629 * MSR (register) - move to system register
1632 * These are all essentially the same insn in 'read' and 'write'
1633 * versions, with varying op0 fields.
1635 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1636 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1637 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1639 const ARMCPRegInfo
*ri
;
1642 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1643 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1644 crn
, crm
, op0
, op1
, op2
));
1647 /* Unknown register; this might be a guest error or a QEMU
1648 * unimplemented feature.
1650 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1651 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1652 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1653 unallocated_encoding(s
);
1657 /* Check access permissions */
1658 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1659 unallocated_encoding(s
);
1664 /* Emit code to perform further access permissions checks at
1665 * runtime; this may result in an exception.
1668 TCGv_i32 tcg_syn
, tcg_isread
;
1671 gen_a64_set_pc_im(s
->pc
- 4);
1672 tmpptr
= tcg_const_ptr(ri
);
1673 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1674 tcg_syn
= tcg_const_i32(syndrome
);
1675 tcg_isread
= tcg_const_i32(isread
);
1676 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1677 tcg_temp_free_ptr(tmpptr
);
1678 tcg_temp_free_i32(tcg_syn
);
1679 tcg_temp_free_i32(tcg_isread
);
1682 /* Handle special cases first */
1683 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1687 tcg_rt
= cpu_reg(s
, rt
);
1689 gen_get_nzcv(tcg_rt
);
1691 gen_set_nzcv(tcg_rt
);
1694 case ARM_CP_CURRENTEL
:
1695 /* Reads as current EL value from pstate, which is
1696 * guaranteed to be constant by the tb flags.
1698 tcg_rt
= cpu_reg(s
, rt
);
1699 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1702 /* Writes clear the aligned block of memory which rt points into. */
1703 tcg_rt
= cpu_reg(s
, rt
);
1704 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1709 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1711 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1715 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1719 tcg_rt
= cpu_reg(s
, rt
);
1722 if (ri
->type
& ARM_CP_CONST
) {
1723 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1724 } else if (ri
->readfn
) {
1726 tmpptr
= tcg_const_ptr(ri
);
1727 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1728 tcg_temp_free_ptr(tmpptr
);
1730 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1733 if (ri
->type
& ARM_CP_CONST
) {
1734 /* If not forbidden by access permissions, treat as WI */
1736 } else if (ri
->writefn
) {
1738 tmpptr
= tcg_const_ptr(ri
);
1739 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1740 tcg_temp_free_ptr(tmpptr
);
1742 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1746 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1747 /* I/O operations must end the TB here (whether read or write) */
1749 s
->base
.is_jmp
= DISAS_UPDATE
;
1750 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1751 /* We default to ending the TB on a coprocessor register write,
1752 * but allow this to be suppressed by the register definition
1753 * (usually only necessary to work around guest bugs).
1755 s
->base
.is_jmp
= DISAS_UPDATE
;
1760 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1761 * +---------------------+---+-----+-----+-------+-------+-----+------+
1762 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1763 * +---------------------+---+-----+-----+-------+-------+-----+------+
1765 static void disas_system(DisasContext
*s
, uint32_t insn
)
1767 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1768 l
= extract32(insn
, 21, 1);
1769 op0
= extract32(insn
, 19, 2);
1770 op1
= extract32(insn
, 16, 3);
1771 crn
= extract32(insn
, 12, 4);
1772 crm
= extract32(insn
, 8, 4);
1773 op2
= extract32(insn
, 5, 3);
1774 rt
= extract32(insn
, 0, 5);
1777 if (l
|| rt
!= 31) {
1778 unallocated_encoding(s
);
1782 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1783 handle_hint(s
, insn
, op1
, op2
, crm
);
1785 case 3: /* CLREX, DSB, DMB, ISB */
1786 handle_sync(s
, insn
, op1
, op2
, crm
);
1788 case 4: /* MSR (immediate) */
1789 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1792 unallocated_encoding(s
);
1797 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1800 /* Exception generation
1802 * 31 24 23 21 20 5 4 2 1 0
1803 * +-----------------+-----+------------------------+-----+----+
1804 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1805 * +-----------------------+------------------------+----------+
1807 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1809 int opc
= extract32(insn
, 21, 3);
1810 int op2_ll
= extract32(insn
, 0, 5);
1811 int imm16
= extract32(insn
, 5, 16);
1816 /* For SVC, HVC and SMC we advance the single-step state
1817 * machine before taking the exception. This is architecturally
1818 * mandated, to ensure that single-stepping a system call
1819 * instruction works properly.
1824 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1825 default_exception_el(s
));
1828 if (s
->current_el
== 0) {
1829 unallocated_encoding(s
);
1832 /* The pre HVC helper handles cases when HVC gets trapped
1833 * as an undefined insn by runtime configuration.
1835 gen_a64_set_pc_im(s
->pc
- 4);
1836 gen_helper_pre_hvc(cpu_env
);
1838 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1841 if (s
->current_el
== 0) {
1842 unallocated_encoding(s
);
1845 gen_a64_set_pc_im(s
->pc
- 4);
1846 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1847 gen_helper_pre_smc(cpu_env
, tmp
);
1848 tcg_temp_free_i32(tmp
);
1850 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1853 unallocated_encoding(s
);
1859 unallocated_encoding(s
);
1863 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1867 unallocated_encoding(s
);
1870 /* HLT. This has two purposes.
1871 * Architecturally, it is an external halting debug instruction.
1872 * Since QEMU doesn't implement external debug, we treat this as
1873 * it is required for halting debug disabled: it will UNDEF.
1874 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1876 if (semihosting_enabled() && imm16
== 0xf000) {
1877 #ifndef CONFIG_USER_ONLY
1878 /* In system mode, don't allow userspace access to semihosting,
1879 * to provide some semblance of security (and for consistency
1880 * with our 32-bit semihosting).
1882 if (s
->current_el
== 0) {
1883 unsupported_encoding(s
, insn
);
1887 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1889 unsupported_encoding(s
, insn
);
1893 if (op2_ll
< 1 || op2_ll
> 3) {
1894 unallocated_encoding(s
);
1897 /* DCPS1, DCPS2, DCPS3 */
1898 unsupported_encoding(s
, insn
);
1901 unallocated_encoding(s
);
1906 /* Unconditional branch (register)
1907 * 31 25 24 21 20 16 15 10 9 5 4 0
1908 * +---------------+-------+-------+-------+------+-------+
1909 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1910 * +---------------+-------+-------+-------+------+-------+
1912 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1914 unsigned int opc
, op2
, op3
, rn
, op4
;
1916 opc
= extract32(insn
, 21, 4);
1917 op2
= extract32(insn
, 16, 5);
1918 op3
= extract32(insn
, 10, 6);
1919 rn
= extract32(insn
, 5, 5);
1920 op4
= extract32(insn
, 0, 5);
1922 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1923 unallocated_encoding(s
);
1931 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1932 /* BLR also needs to load return address */
1934 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1938 if (s
->current_el
== 0) {
1939 unallocated_encoding(s
);
1942 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1945 gen_helper_exception_return(cpu_env
);
1946 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1949 /* Must exit loop to check un-masked IRQs */
1950 s
->base
.is_jmp
= DISAS_EXIT
;
1954 unallocated_encoding(s
);
1956 unsupported_encoding(s
, insn
);
1960 unallocated_encoding(s
);
1964 s
->base
.is_jmp
= DISAS_JUMP
;
1967 /* Branches, exception generating and system instructions */
1968 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1970 switch (extract32(insn
, 25, 7)) {
1971 case 0x0a: case 0x0b:
1972 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1973 disas_uncond_b_imm(s
, insn
);
1975 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1976 disas_comp_b_imm(s
, insn
);
1978 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1979 disas_test_b_imm(s
, insn
);
1981 case 0x2a: /* Conditional branch (immediate) */
1982 disas_cond_b_imm(s
, insn
);
1984 case 0x6a: /* Exception generation / System */
1985 if (insn
& (1 << 24)) {
1986 disas_system(s
, insn
);
1991 case 0x6b: /* Unconditional branch (register) */
1992 disas_uncond_b_reg(s
, insn
);
1995 unallocated_encoding(s
);
2001 * Load/Store exclusive instructions are implemented by remembering
2002 * the value/address loaded, and seeing if these are the same
2003 * when the store is performed. This is not actually the architecturally
2004 * mandated semantics, but it works for typical guest code sequences
2005 * and avoids having to monitor regular stores.
2007 * The store exclusive uses the atomic cmpxchg primitives to avoid
2008 * races in multi-threaded linux-user and when MTTCG softmmu is
2011 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2012 TCGv_i64 addr
, int size
, bool is_pair
)
2014 int idx
= get_mem_index(s
);
2015 TCGMemOp memop
= s
->be_data
;
2017 g_assert(size
<= 3);
2019 g_assert(size
>= 2);
2021 /* The pair must be single-copy atomic for the doubleword. */
2022 memop
|= MO_64
| MO_ALIGN
;
2023 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2024 if (s
->be_data
== MO_LE
) {
2025 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2026 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2028 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2029 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2032 /* The pair must be single-copy atomic for *each* doubleword, not
2033 the entire quadword, however it must be quadword aligned. */
2035 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2036 memop
| MO_ALIGN_16
);
2038 TCGv_i64 addr2
= tcg_temp_new_i64();
2039 tcg_gen_addi_i64(addr2
, addr
, 8);
2040 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2041 tcg_temp_free_i64(addr2
);
2043 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2044 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2047 memop
|= size
| MO_ALIGN
;
2048 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2049 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2051 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2054 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2055 TCGv_i64 addr
, int size
, int is_pair
)
2057 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2058 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2061 * [addr + datasize] = {Rt2};
2067 * env->exclusive_addr = -1;
2069 TCGLabel
*fail_label
= gen_new_label();
2070 TCGLabel
*done_label
= gen_new_label();
2073 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2075 tmp
= tcg_temp_new_i64();
2078 if (s
->be_data
== MO_LE
) {
2079 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2081 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2083 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2084 cpu_exclusive_val
, tmp
,
2086 MO_64
| MO_ALIGN
| s
->be_data
);
2087 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2088 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2089 if (!HAVE_CMPXCHG128
) {
2090 gen_helper_exit_atomic(cpu_env
);
2091 s
->base
.is_jmp
= DISAS_NORETURN
;
2092 } else if (s
->be_data
== MO_LE
) {
2093 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2098 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2103 } else if (s
->be_data
== MO_LE
) {
2104 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2105 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2107 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2108 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2111 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2112 cpu_reg(s
, rt
), get_mem_index(s
),
2113 size
| MO_ALIGN
| s
->be_data
);
2114 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2116 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2117 tcg_temp_free_i64(tmp
);
2118 tcg_gen_br(done_label
);
2120 gen_set_label(fail_label
);
2121 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2122 gen_set_label(done_label
);
2123 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2126 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2129 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2130 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2131 int memidx
= get_mem_index(s
);
2132 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2135 gen_check_sp_alignment(s
);
2137 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, addr
, tcg_rs
, tcg_rt
, memidx
,
2138 size
| MO_ALIGN
| s
->be_data
);
2141 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2144 TCGv_i64 s1
= cpu_reg(s
, rs
);
2145 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2146 TCGv_i64 t1
= cpu_reg(s
, rt
);
2147 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2148 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2149 int memidx
= get_mem_index(s
);
2152 gen_check_sp_alignment(s
);
2156 TCGv_i64 cmp
= tcg_temp_new_i64();
2157 TCGv_i64 val
= tcg_temp_new_i64();
2159 if (s
->be_data
== MO_LE
) {
2160 tcg_gen_concat32_i64(val
, t1
, t2
);
2161 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2163 tcg_gen_concat32_i64(val
, t2
, t1
);
2164 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2167 tcg_gen_atomic_cmpxchg_i64(cmp
, addr
, cmp
, val
, memidx
,
2168 MO_64
| MO_ALIGN
| s
->be_data
);
2169 tcg_temp_free_i64(val
);
2171 if (s
->be_data
== MO_LE
) {
2172 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2174 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2176 tcg_temp_free_i64(cmp
);
2177 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2178 if (HAVE_CMPXCHG128
) {
2179 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2180 if (s
->be_data
== MO_LE
) {
2181 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2183 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2185 tcg_temp_free_i32(tcg_rs
);
2187 gen_helper_exit_atomic(cpu_env
);
2188 s
->base
.is_jmp
= DISAS_NORETURN
;
2191 TCGv_i64 d1
= tcg_temp_new_i64();
2192 TCGv_i64 d2
= tcg_temp_new_i64();
2193 TCGv_i64 a2
= tcg_temp_new_i64();
2194 TCGv_i64 c1
= tcg_temp_new_i64();
2195 TCGv_i64 c2
= tcg_temp_new_i64();
2196 TCGv_i64 zero
= tcg_const_i64(0);
2198 /* Load the two words, in memory order. */
2199 tcg_gen_qemu_ld_i64(d1
, addr
, memidx
,
2200 MO_64
| MO_ALIGN_16
| s
->be_data
);
2201 tcg_gen_addi_i64(a2
, addr
, 8);
2202 tcg_gen_qemu_ld_i64(d2
, addr
, memidx
, MO_64
| s
->be_data
);
2204 /* Compare the two words, also in memory order. */
2205 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2206 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2207 tcg_gen_and_i64(c2
, c2
, c1
);
2209 /* If compare equal, write back new data, else write back old data. */
2210 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2211 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2212 tcg_gen_qemu_st_i64(c1
, addr
, memidx
, MO_64
| s
->be_data
);
2213 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2214 tcg_temp_free_i64(a2
);
2215 tcg_temp_free_i64(c1
);
2216 tcg_temp_free_i64(c2
);
2217 tcg_temp_free_i64(zero
);
2219 /* Write back the data from memory to Rs. */
2220 tcg_gen_mov_i64(s1
, d1
);
2221 tcg_gen_mov_i64(s2
, d2
);
2222 tcg_temp_free_i64(d1
);
2223 tcg_temp_free_i64(d2
);
2227 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2228 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2230 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2232 int opc0
= extract32(opc
, 0, 1);
2236 regsize
= opc0
? 32 : 64;
2238 regsize
= size
== 3 ? 64 : 32;
2240 return regsize
== 64;
2243 /* Load/store exclusive
2245 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2246 * +-----+-------------+----+---+----+------+----+-------+------+------+
2247 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2248 * +-----+-------------+----+---+----+------+----+-------+------+------+
2250 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2251 * L: 0 -> store, 1 -> load
2252 * o2: 0 -> exclusive, 1 -> not
2253 * o1: 0 -> single register, 1 -> register pair
2254 * o0: 1 -> load-acquire/store-release, 0 -> not
2256 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2258 int rt
= extract32(insn
, 0, 5);
2259 int rn
= extract32(insn
, 5, 5);
2260 int rt2
= extract32(insn
, 10, 5);
2261 int rs
= extract32(insn
, 16, 5);
2262 int is_lasr
= extract32(insn
, 15, 1);
2263 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2264 int size
= extract32(insn
, 30, 2);
2267 switch (o2_L_o1_o0
) {
2268 case 0x0: /* STXR */
2269 case 0x1: /* STLXR */
2271 gen_check_sp_alignment(s
);
2274 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2276 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2277 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, false);
2280 case 0x4: /* LDXR */
2281 case 0x5: /* LDAXR */
2283 gen_check_sp_alignment(s
);
2285 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2287 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, false);
2289 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2293 case 0x8: /* STLLR */
2294 if (!dc_isar_feature(aa64_lor
, s
)) {
2297 /* StoreLORelease is the same as Store-Release for QEMU. */
2299 case 0x9: /* STLR */
2300 /* Generate ISS for non-exclusive accesses including LASR. */
2302 gen_check_sp_alignment(s
);
2304 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2305 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2306 do_gpr_st(s
, cpu_reg(s
, rt
), tcg_addr
, size
, true, rt
,
2307 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2310 case 0xc: /* LDLAR */
2311 if (!dc_isar_feature(aa64_lor
, s
)) {
2314 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2316 case 0xd: /* LDAR */
2317 /* Generate ISS for non-exclusive accesses including LASR. */
2319 gen_check_sp_alignment(s
);
2321 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2322 do_gpr_ld(s
, cpu_reg(s
, rt
), tcg_addr
, size
, false, false, true, rt
,
2323 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2324 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2327 case 0x2: case 0x3: /* CASP / STXP */
2328 if (size
& 2) { /* STXP / STLXP */
2330 gen_check_sp_alignment(s
);
2333 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2335 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2336 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, true);
2340 && ((rt
| rs
) & 1) == 0
2341 && dc_isar_feature(aa64_atomics
, s
)) {
2343 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2348 case 0x6: case 0x7: /* CASPA / LDXP */
2349 if (size
& 2) { /* LDXP / LDAXP */
2351 gen_check_sp_alignment(s
);
2353 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2355 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, true);
2357 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2362 && ((rt
| rs
) & 1) == 0
2363 && dc_isar_feature(aa64_atomics
, s
)) {
2364 /* CASPA / CASPAL */
2365 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2371 case 0xb: /* CASL */
2372 case 0xe: /* CASA */
2373 case 0xf: /* CASAL */
2374 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2375 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2380 unallocated_encoding(s
);
2384 * Load register (literal)
2386 * 31 30 29 27 26 25 24 23 5 4 0
2387 * +-----+-------+---+-----+-------------------+-------+
2388 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2389 * +-----+-------+---+-----+-------------------+-------+
2391 * V: 1 -> vector (simd/fp)
2392 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2393 * 10-> 32 bit signed, 11 -> prefetch
2394 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2396 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2398 int rt
= extract32(insn
, 0, 5);
2399 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2400 bool is_vector
= extract32(insn
, 26, 1);
2401 int opc
= extract32(insn
, 30, 2);
2402 bool is_signed
= false;
2404 TCGv_i64 tcg_rt
, tcg_addr
;
2408 unallocated_encoding(s
);
2412 if (!fp_access_check(s
)) {
2417 /* PRFM (literal) : prefetch */
2420 size
= 2 + extract32(opc
, 0, 1);
2421 is_signed
= extract32(opc
, 1, 1);
2424 tcg_rt
= cpu_reg(s
, rt
);
2426 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2428 do_fp_ld(s
, rt
, tcg_addr
, size
);
2430 /* Only unsigned 32bit loads target 32bit registers. */
2431 bool iss_sf
= opc
!= 0;
2433 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2434 true, rt
, iss_sf
, false);
2436 tcg_temp_free_i64(tcg_addr
);
2440 * LDNP (Load Pair - non-temporal hint)
2441 * LDP (Load Pair - non vector)
2442 * LDPSW (Load Pair Signed Word - non vector)
2443 * STNP (Store Pair - non-temporal hint)
2444 * STP (Store Pair - non vector)
2445 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2446 * LDP (Load Pair of SIMD&FP)
2447 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2448 * STP (Store Pair of SIMD&FP)
2450 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2451 * +-----+-------+---+---+-------+---+-----------------------------+
2452 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2453 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2455 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2457 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2458 * V: 0 -> GPR, 1 -> Vector
2459 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2460 * 10 -> signed offset, 11 -> pre-index
2461 * L: 0 -> Store 1 -> Load
2463 * Rt, Rt2 = GPR or SIMD registers to be stored
2464 * Rn = general purpose register containing address
2465 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2467 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2469 int rt
= extract32(insn
, 0, 5);
2470 int rn
= extract32(insn
, 5, 5);
2471 int rt2
= extract32(insn
, 10, 5);
2472 uint64_t offset
= sextract64(insn
, 15, 7);
2473 int index
= extract32(insn
, 23, 2);
2474 bool is_vector
= extract32(insn
, 26, 1);
2475 bool is_load
= extract32(insn
, 22, 1);
2476 int opc
= extract32(insn
, 30, 2);
2478 bool is_signed
= false;
2479 bool postindex
= false;
2482 TCGv_i64 tcg_addr
; /* calculated address */
2486 unallocated_encoding(s
);
2493 size
= 2 + extract32(opc
, 1, 1);
2494 is_signed
= extract32(opc
, 0, 1);
2495 if (!is_load
&& is_signed
) {
2496 unallocated_encoding(s
);
2502 case 1: /* post-index */
2507 /* signed offset with "non-temporal" hint. Since we don't emulate
2508 * caches we don't care about hints to the cache system about
2509 * data access patterns, and handle this identically to plain
2513 /* There is no non-temporal-hint version of LDPSW */
2514 unallocated_encoding(s
);
2519 case 2: /* signed offset, rn not updated */
2522 case 3: /* pre-index */
2528 if (is_vector
&& !fp_access_check(s
)) {
2535 gen_check_sp_alignment(s
);
2538 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2541 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2546 do_fp_ld(s
, rt
, tcg_addr
, size
);
2548 do_fp_st(s
, rt
, tcg_addr
, size
);
2550 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2552 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2554 do_fp_st(s
, rt2
, tcg_addr
, size
);
2557 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2558 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2561 TCGv_i64 tmp
= tcg_temp_new_i64();
2563 /* Do not modify tcg_rt before recognizing any exception
2564 * from the second load.
2566 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2567 false, 0, false, false);
2568 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2569 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2570 false, 0, false, false);
2572 tcg_gen_mov_i64(tcg_rt
, tmp
);
2573 tcg_temp_free_i64(tmp
);
2575 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2576 false, 0, false, false);
2577 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2578 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2579 false, 0, false, false);
2585 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2587 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2589 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2594 * Load/store (immediate post-indexed)
2595 * Load/store (immediate pre-indexed)
2596 * Load/store (unscaled immediate)
2598 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2599 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2600 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2601 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2603 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2605 * V = 0 -> non-vector
2606 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2607 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2609 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2615 int rn
= extract32(insn
, 5, 5);
2616 int imm9
= sextract32(insn
, 12, 9);
2617 int idx
= extract32(insn
, 10, 2);
2618 bool is_signed
= false;
2619 bool is_store
= false;
2620 bool is_extended
= false;
2621 bool is_unpriv
= (idx
== 2);
2622 bool iss_valid
= !is_vector
;
2629 size
|= (opc
& 2) << 1;
2630 if (size
> 4 || is_unpriv
) {
2631 unallocated_encoding(s
);
2634 is_store
= ((opc
& 1) == 0);
2635 if (!fp_access_check(s
)) {
2639 if (size
== 3 && opc
== 2) {
2640 /* PRFM - prefetch */
2642 unallocated_encoding(s
);
2647 if (opc
== 3 && size
> 1) {
2648 unallocated_encoding(s
);
2651 is_store
= (opc
== 0);
2652 is_signed
= extract32(opc
, 1, 1);
2653 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2671 g_assert_not_reached();
2675 gen_check_sp_alignment(s
);
2677 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2680 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2685 do_fp_st(s
, rt
, tcg_addr
, size
);
2687 do_fp_ld(s
, rt
, tcg_addr
, size
);
2690 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2691 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2692 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2695 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2696 iss_valid
, rt
, iss_sf
, false);
2698 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2699 is_signed
, is_extended
, memidx
,
2700 iss_valid
, rt
, iss_sf
, false);
2705 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2707 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2709 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2714 * Load/store (register offset)
2716 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2717 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2718 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2719 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2722 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2723 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2725 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2726 * opc<0>: 0 -> store, 1 -> load
2727 * V: 1 -> vector/simd
2728 * opt: extend encoding (see DecodeRegExtend)
2729 * S: if S=1 then scale (essentially index by sizeof(size))
2730 * Rt: register to transfer into/out of
2731 * Rn: address register or SP for base
2732 * Rm: offset register or ZR for offset
2734 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2740 int rn
= extract32(insn
, 5, 5);
2741 int shift
= extract32(insn
, 12, 1);
2742 int rm
= extract32(insn
, 16, 5);
2743 int opt
= extract32(insn
, 13, 3);
2744 bool is_signed
= false;
2745 bool is_store
= false;
2746 bool is_extended
= false;
2751 if (extract32(opt
, 1, 1) == 0) {
2752 unallocated_encoding(s
);
2757 size
|= (opc
& 2) << 1;
2759 unallocated_encoding(s
);
2762 is_store
= !extract32(opc
, 0, 1);
2763 if (!fp_access_check(s
)) {
2767 if (size
== 3 && opc
== 2) {
2768 /* PRFM - prefetch */
2771 if (opc
== 3 && size
> 1) {
2772 unallocated_encoding(s
);
2775 is_store
= (opc
== 0);
2776 is_signed
= extract32(opc
, 1, 1);
2777 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2781 gen_check_sp_alignment(s
);
2783 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2785 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2786 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2788 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2792 do_fp_st(s
, rt
, tcg_addr
, size
);
2794 do_fp_ld(s
, rt
, tcg_addr
, size
);
2797 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2798 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2800 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2801 true, rt
, iss_sf
, false);
2803 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2804 is_signed
, is_extended
,
2805 true, rt
, iss_sf
, false);
2811 * Load/store (unsigned immediate)
2813 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2814 * +----+-------+---+-----+-----+------------+-------+------+
2815 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2816 * +----+-------+---+-----+-----+------------+-------+------+
2819 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2820 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2822 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2823 * opc<0>: 0 -> store, 1 -> load
2824 * Rn: base address register (inc SP)
2825 * Rt: target register
2827 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2833 int rn
= extract32(insn
, 5, 5);
2834 unsigned int imm12
= extract32(insn
, 10, 12);
2835 unsigned int offset
;
2840 bool is_signed
= false;
2841 bool is_extended
= false;
2844 size
|= (opc
& 2) << 1;
2846 unallocated_encoding(s
);
2849 is_store
= !extract32(opc
, 0, 1);
2850 if (!fp_access_check(s
)) {
2854 if (size
== 3 && opc
== 2) {
2855 /* PRFM - prefetch */
2858 if (opc
== 3 && size
> 1) {
2859 unallocated_encoding(s
);
2862 is_store
= (opc
== 0);
2863 is_signed
= extract32(opc
, 1, 1);
2864 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2868 gen_check_sp_alignment(s
);
2870 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2871 offset
= imm12
<< size
;
2872 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2876 do_fp_st(s
, rt
, tcg_addr
, size
);
2878 do_fp_ld(s
, rt
, tcg_addr
, size
);
2881 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2882 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2884 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2885 true, rt
, iss_sf
, false);
2887 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2888 true, rt
, iss_sf
, false);
2893 /* Atomic memory operations
2895 * 31 30 27 26 24 22 21 16 15 12 10 5 0
2896 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
2897 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
2898 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
2900 * Rt: the result register
2901 * Rn: base address or SP
2902 * Rs: the source register for the operation
2903 * V: vector flag (always 0 as of v8.3)
2907 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
2908 int size
, int rt
, bool is_vector
)
2910 int rs
= extract32(insn
, 16, 5);
2911 int rn
= extract32(insn
, 5, 5);
2912 int o3_opc
= extract32(insn
, 12, 4);
2913 TCGv_i64 tcg_rn
, tcg_rs
;
2914 AtomicThreeOpFn
*fn
;
2916 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
2917 unallocated_encoding(s
);
2921 case 000: /* LDADD */
2922 fn
= tcg_gen_atomic_fetch_add_i64
;
2924 case 001: /* LDCLR */
2925 fn
= tcg_gen_atomic_fetch_and_i64
;
2927 case 002: /* LDEOR */
2928 fn
= tcg_gen_atomic_fetch_xor_i64
;
2930 case 003: /* LDSET */
2931 fn
= tcg_gen_atomic_fetch_or_i64
;
2933 case 004: /* LDSMAX */
2934 fn
= tcg_gen_atomic_fetch_smax_i64
;
2936 case 005: /* LDSMIN */
2937 fn
= tcg_gen_atomic_fetch_smin_i64
;
2939 case 006: /* LDUMAX */
2940 fn
= tcg_gen_atomic_fetch_umax_i64
;
2942 case 007: /* LDUMIN */
2943 fn
= tcg_gen_atomic_fetch_umin_i64
;
2946 fn
= tcg_gen_atomic_xchg_i64
;
2949 unallocated_encoding(s
);
2954 gen_check_sp_alignment(s
);
2956 tcg_rn
= cpu_reg_sp(s
, rn
);
2957 tcg_rs
= read_cpu_reg(s
, rs
, true);
2959 if (o3_opc
== 1) { /* LDCLR */
2960 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
2963 /* The tcg atomic primitives are all full barriers. Therefore we
2964 * can ignore the Acquire and Release bits of this instruction.
2966 fn(cpu_reg(s
, rt
), tcg_rn
, tcg_rs
, get_mem_index(s
),
2967 s
->be_data
| size
| MO_ALIGN
);
2970 /* Load/store register (all forms) */
2971 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2973 int rt
= extract32(insn
, 0, 5);
2974 int opc
= extract32(insn
, 22, 2);
2975 bool is_vector
= extract32(insn
, 26, 1);
2976 int size
= extract32(insn
, 30, 2);
2978 switch (extract32(insn
, 24, 2)) {
2980 if (extract32(insn
, 21, 1) == 0) {
2981 /* Load/store register (unscaled immediate)
2982 * Load/store immediate pre/post-indexed
2983 * Load/store register unprivileged
2985 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2988 switch (extract32(insn
, 10, 2)) {
2990 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
2993 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2998 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3001 unallocated_encoding(s
);
3004 /* AdvSIMD load/store multiple structures
3006 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3007 * +---+---+---------------+---+-------------+--------+------+------+------+
3008 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3009 * +---+---+---------------+---+-------------+--------+------+------+------+
3011 * AdvSIMD load/store multiple structures (post-indexed)
3013 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3014 * +---+---+---------------+---+---+---------+--------+------+------+------+
3015 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3016 * +---+---+---------------+---+---+---------+--------+------+------+------+
3018 * Rt: first (or only) SIMD&FP register to be transferred
3019 * Rn: base address or SP
3020 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3022 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3024 int rt
= extract32(insn
, 0, 5);
3025 int rn
= extract32(insn
, 5, 5);
3026 int size
= extract32(insn
, 10, 2);
3027 int opcode
= extract32(insn
, 12, 4);
3028 bool is_store
= !extract32(insn
, 22, 1);
3029 bool is_postidx
= extract32(insn
, 23, 1);
3030 bool is_q
= extract32(insn
, 30, 1);
3031 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3032 TCGMemOp endian
= s
->be_data
;
3034 int ebytes
; /* bytes per element */
3035 int elements
; /* elements per vector */
3036 int rpt
; /* num iterations */
3037 int selem
; /* structure elements */
3040 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3041 unallocated_encoding(s
);
3045 /* From the shared decode logic */
3076 unallocated_encoding(s
);
3080 if (size
== 3 && !is_q
&& selem
!= 1) {
3082 unallocated_encoding(s
);
3086 if (!fp_access_check(s
)) {
3091 gen_check_sp_alignment(s
);
3094 /* For our purposes, bytes are always little-endian. */
3099 /* Consecutive little-endian elements from a single register
3100 * can be promoted to a larger little-endian operation.
3102 if (selem
== 1 && endian
== MO_LE
) {
3106 elements
= (is_q
? 16 : 8) / ebytes
;
3108 tcg_rn
= cpu_reg_sp(s
, rn
);
3109 tcg_addr
= tcg_temp_new_i64();
3110 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3111 tcg_ebytes
= tcg_const_i64(ebytes
);
3113 for (r
= 0; r
< rpt
; r
++) {
3115 for (e
= 0; e
< elements
; e
++) {
3117 for (xs
= 0; xs
< selem
; xs
++) {
3118 int tt
= (rt
+ r
+ xs
) % 32;
3120 do_vec_st(s
, tt
, e
, tcg_addr
, size
, endian
);
3122 do_vec_ld(s
, tt
, e
, tcg_addr
, size
, endian
);
3124 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3130 /* For non-quad operations, setting a slice of the low
3131 * 64 bits of the register clears the high 64 bits (in
3132 * the ARM ARM pseudocode this is implicit in the fact
3133 * that 'rval' is a 64 bit wide variable).
3134 * For quad operations, we might still need to zero the
3137 for (r
= 0; r
< rpt
* selem
; r
++) {
3138 int tt
= (rt
+ r
) % 32;
3139 clear_vec_high(s
, is_q
, tt
);
3144 int rm
= extract32(insn
, 16, 5);
3146 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3148 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3151 tcg_temp_free_i64(tcg_ebytes
);
3152 tcg_temp_free_i64(tcg_addr
);
3155 /* AdvSIMD load/store single structure
3157 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3158 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3159 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3160 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3162 * AdvSIMD load/store single structure (post-indexed)
3164 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3165 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3166 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3167 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3169 * Rt: first (or only) SIMD&FP register to be transferred
3170 * Rn: base address or SP
3171 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3172 * index = encoded in Q:S:size dependent on size
3174 * lane_size = encoded in R, opc
3175 * transfer width = encoded in opc, S, size
3177 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3179 int rt
= extract32(insn
, 0, 5);
3180 int rn
= extract32(insn
, 5, 5);
3181 int size
= extract32(insn
, 10, 2);
3182 int S
= extract32(insn
, 12, 1);
3183 int opc
= extract32(insn
, 13, 3);
3184 int R
= extract32(insn
, 21, 1);
3185 int is_load
= extract32(insn
, 22, 1);
3186 int is_postidx
= extract32(insn
, 23, 1);
3187 int is_q
= extract32(insn
, 30, 1);
3189 int scale
= extract32(opc
, 1, 2);
3190 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3191 bool replicate
= false;
3192 int index
= is_q
<< 3 | S
<< 2 | size
;
3194 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3198 if (!is_load
|| S
) {
3199 unallocated_encoding(s
);
3208 if (extract32(size
, 0, 1)) {
3209 unallocated_encoding(s
);
3215 if (extract32(size
, 1, 1)) {
3216 unallocated_encoding(s
);
3219 if (!extract32(size
, 0, 1)) {
3223 unallocated_encoding(s
);
3231 g_assert_not_reached();
3234 if (!fp_access_check(s
)) {
3238 ebytes
= 1 << scale
;
3241 gen_check_sp_alignment(s
);
3244 tcg_rn
= cpu_reg_sp(s
, rn
);
3245 tcg_addr
= tcg_temp_new_i64();
3246 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3247 tcg_ebytes
= tcg_const_i64(ebytes
);
3249 for (xs
= 0; xs
< selem
; xs
++) {
3251 /* Load and replicate to all elements */
3252 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3254 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
3255 get_mem_index(s
), s
->be_data
+ scale
);
3256 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3257 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3259 tcg_temp_free_i64(tcg_tmp
);
3261 /* Load/store one element per register */
3263 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
, s
->be_data
);
3265 do_vec_st(s
, rt
, index
, tcg_addr
, scale
, s
->be_data
);
3268 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3273 int rm
= extract32(insn
, 16, 5);
3275 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3277 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3280 tcg_temp_free_i64(tcg_ebytes
);
3281 tcg_temp_free_i64(tcg_addr
);
3284 /* Loads and stores */
3285 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3287 switch (extract32(insn
, 24, 6)) {
3288 case 0x08: /* Load/store exclusive */
3289 disas_ldst_excl(s
, insn
);
3291 case 0x18: case 0x1c: /* Load register (literal) */
3292 disas_ld_lit(s
, insn
);
3294 case 0x28: case 0x29:
3295 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3296 disas_ldst_pair(s
, insn
);
3298 case 0x38: case 0x39:
3299 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3300 disas_ldst_reg(s
, insn
);
3302 case 0x0c: /* AdvSIMD load/store multiple structures */
3303 disas_ldst_multiple_struct(s
, insn
);
3305 case 0x0d: /* AdvSIMD load/store single structure */
3306 disas_ldst_single_struct(s
, insn
);
3309 unallocated_encoding(s
);
3314 /* PC-rel. addressing
3315 * 31 30 29 28 24 23 5 4 0
3316 * +----+-------+-----------+-------------------+------+
3317 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3318 * +----+-------+-----------+-------------------+------+
3320 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3322 unsigned int page
, rd
;
3326 page
= extract32(insn
, 31, 1);
3327 /* SignExtend(immhi:immlo) -> offset */
3328 offset
= sextract64(insn
, 5, 19);
3329 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3330 rd
= extract32(insn
, 0, 5);
3334 /* ADRP (page based) */
3339 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3343 * Add/subtract (immediate)
3345 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3346 * +--+--+--+-----------+-----+-------------+-----+-----+
3347 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3348 * +--+--+--+-----------+-----+-------------+-----+-----+
3350 * sf: 0 -> 32bit, 1 -> 64bit
3351 * op: 0 -> add , 1 -> sub
3353 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3355 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3357 int rd
= extract32(insn
, 0, 5);
3358 int rn
= extract32(insn
, 5, 5);
3359 uint64_t imm
= extract32(insn
, 10, 12);
3360 int shift
= extract32(insn
, 22, 2);
3361 bool setflags
= extract32(insn
, 29, 1);
3362 bool sub_op
= extract32(insn
, 30, 1);
3363 bool is_64bit
= extract32(insn
, 31, 1);
3365 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3366 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3367 TCGv_i64 tcg_result
;
3376 unallocated_encoding(s
);
3380 tcg_result
= tcg_temp_new_i64();
3383 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3385 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3388 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3390 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3392 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3394 tcg_temp_free_i64(tcg_imm
);
3398 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3400 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3403 tcg_temp_free_i64(tcg_result
);
3406 /* The input should be a value in the bottom e bits (with higher
3407 * bits zero); returns that value replicated into every element
3408 * of size e in a 64 bit integer.
3410 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3420 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3421 static inline uint64_t bitmask64(unsigned int length
)
3423 assert(length
> 0 && length
<= 64);
3424 return ~0ULL >> (64 - length
);
3427 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3428 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3429 * value (ie should cause a guest UNDEF exception), and true if they are
3430 * valid, in which case the decoded bit pattern is written to result.
3432 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3433 unsigned int imms
, unsigned int immr
)
3436 unsigned e
, levels
, s
, r
;
3439 assert(immn
< 2 && imms
< 64 && immr
< 64);
3441 /* The bit patterns we create here are 64 bit patterns which
3442 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3443 * 64 bits each. Each element contains the same value: a run
3444 * of between 1 and e-1 non-zero bits, rotated within the
3445 * element by between 0 and e-1 bits.
3447 * The element size and run length are encoded into immn (1 bit)
3448 * and imms (6 bits) as follows:
3449 * 64 bit elements: immn = 1, imms = <length of run - 1>
3450 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3451 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3452 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3453 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3454 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3455 * Notice that immn = 0, imms = 11111x is the only combination
3456 * not covered by one of the above options; this is reserved.
3457 * Further, <length of run - 1> all-ones is a reserved pattern.
3459 * In all cases the rotation is by immr % e (and immr is 6 bits).
3462 /* First determine the element size */
3463 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3465 /* This is the immn == 0, imms == 0x11111x case */
3475 /* <length of run - 1> mustn't be all-ones. */
3479 /* Create the value of one element: s+1 set bits rotated
3480 * by r within the element (which is e bits wide)...
3482 mask
= bitmask64(s
+ 1);
3484 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3485 mask
&= bitmask64(e
);
3487 /* ...then replicate the element over the whole 64 bit value */
3488 mask
= bitfield_replicate(mask
, e
);
3493 /* Logical (immediate)
3494 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3495 * +----+-----+-------------+---+------+------+------+------+
3496 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3497 * +----+-----+-------------+---+------+------+------+------+
3499 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3501 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3502 TCGv_i64 tcg_rd
, tcg_rn
;
3504 bool is_and
= false;
3506 sf
= extract32(insn
, 31, 1);
3507 opc
= extract32(insn
, 29, 2);
3508 is_n
= extract32(insn
, 22, 1);
3509 immr
= extract32(insn
, 16, 6);
3510 imms
= extract32(insn
, 10, 6);
3511 rn
= extract32(insn
, 5, 5);
3512 rd
= extract32(insn
, 0, 5);
3515 unallocated_encoding(s
);
3519 if (opc
== 0x3) { /* ANDS */
3520 tcg_rd
= cpu_reg(s
, rd
);
3522 tcg_rd
= cpu_reg_sp(s
, rd
);
3524 tcg_rn
= cpu_reg(s
, rn
);
3526 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3527 /* some immediate field values are reserved */
3528 unallocated_encoding(s
);
3533 wmask
&= 0xffffffff;
3537 case 0x3: /* ANDS */
3539 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3543 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3546 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3549 assert(FALSE
); /* must handle all above */
3553 if (!sf
&& !is_and
) {
3554 /* zero extend final result; we know we can skip this for AND
3555 * since the immediate had the high 32 bits clear.
3557 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3560 if (opc
== 3) { /* ANDS */
3561 gen_logic_CC(sf
, tcg_rd
);
3566 * Move wide (immediate)
3568 * 31 30 29 28 23 22 21 20 5 4 0
3569 * +--+-----+-------------+-----+----------------+------+
3570 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3571 * +--+-----+-------------+-----+----------------+------+
3573 * sf: 0 -> 32 bit, 1 -> 64 bit
3574 * opc: 00 -> N, 10 -> Z, 11 -> K
3575 * hw: shift/16 (0,16, and sf only 32, 48)
3577 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3579 int rd
= extract32(insn
, 0, 5);
3580 uint64_t imm
= extract32(insn
, 5, 16);
3581 int sf
= extract32(insn
, 31, 1);
3582 int opc
= extract32(insn
, 29, 2);
3583 int pos
= extract32(insn
, 21, 2) << 4;
3584 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3587 if (!sf
&& (pos
>= 32)) {
3588 unallocated_encoding(s
);
3602 tcg_gen_movi_i64(tcg_rd
, imm
);
3605 tcg_imm
= tcg_const_i64(imm
);
3606 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3607 tcg_temp_free_i64(tcg_imm
);
3609 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3613 unallocated_encoding(s
);
3619 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3620 * +----+-----+-------------+---+------+------+------+------+
3621 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3622 * +----+-----+-------------+---+------+------+------+------+
3624 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3626 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3627 TCGv_i64 tcg_rd
, tcg_tmp
;
3629 sf
= extract32(insn
, 31, 1);
3630 opc
= extract32(insn
, 29, 2);
3631 n
= extract32(insn
, 22, 1);
3632 ri
= extract32(insn
, 16, 6);
3633 si
= extract32(insn
, 10, 6);
3634 rn
= extract32(insn
, 5, 5);
3635 rd
= extract32(insn
, 0, 5);
3636 bitsize
= sf
? 64 : 32;
3638 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3639 unallocated_encoding(s
);
3643 tcg_rd
= cpu_reg(s
, rd
);
3645 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3646 to be smaller than bitsize, we'll never reference data outside the
3647 low 32-bits anyway. */
3648 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3650 /* Recognize simple(r) extractions. */
3652 /* Wd<s-r:0> = Wn<s:r> */
3653 len
= (si
- ri
) + 1;
3654 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3655 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3657 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3658 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3661 /* opc == 1, BXFIL fall through to deposit */
3662 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3665 /* Handle the ri > si case with a deposit
3666 * Wd<32+s-r,32-r> = Wn<s:0>
3669 pos
= (bitsize
- ri
) & (bitsize
- 1);
3672 if (opc
== 0 && len
< ri
) {
3673 /* SBFM: sign extend the destination field from len to fill
3674 the balance of the word. Let the deposit below insert all
3675 of those sign bits. */
3676 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3680 if (opc
== 1) { /* BFM, BXFIL */
3681 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3683 /* SBFM or UBFM: We start with zero, and we haven't modified
3684 any bits outside bitsize, therefore the zero-extension
3685 below is unneeded. */
3686 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3691 if (!sf
) { /* zero extend final result */
3692 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3697 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3698 * +----+------+-------------+---+----+------+--------+------+------+
3699 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3700 * +----+------+-------------+---+----+------+--------+------+------+
3702 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3704 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3706 sf
= extract32(insn
, 31, 1);
3707 n
= extract32(insn
, 22, 1);
3708 rm
= extract32(insn
, 16, 5);
3709 imm
= extract32(insn
, 10, 6);
3710 rn
= extract32(insn
, 5, 5);
3711 rd
= extract32(insn
, 0, 5);
3712 op21
= extract32(insn
, 29, 2);
3713 op0
= extract32(insn
, 21, 1);
3714 bitsize
= sf
? 64 : 32;
3716 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3717 unallocated_encoding(s
);
3719 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3721 tcg_rd
= cpu_reg(s
, rd
);
3723 if (unlikely(imm
== 0)) {
3724 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3725 * so an extract from bit 0 is a special case.
3728 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3730 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3732 } else if (rm
== rn
) { /* ROR */
3733 tcg_rm
= cpu_reg(s
, rm
);
3735 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3737 TCGv_i32 tmp
= tcg_temp_new_i32();
3738 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3739 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3740 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3741 tcg_temp_free_i32(tmp
);
3744 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3745 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3746 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3747 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3748 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3750 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3756 /* Data processing - immediate */
3757 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3759 switch (extract32(insn
, 23, 6)) {
3760 case 0x20: case 0x21: /* PC-rel. addressing */
3761 disas_pc_rel_adr(s
, insn
);
3763 case 0x22: case 0x23: /* Add/subtract (immediate) */
3764 disas_add_sub_imm(s
, insn
);
3766 case 0x24: /* Logical (immediate) */
3767 disas_logic_imm(s
, insn
);
3769 case 0x25: /* Move wide (immediate) */
3770 disas_movw_imm(s
, insn
);
3772 case 0x26: /* Bitfield */
3773 disas_bitfield(s
, insn
);
3775 case 0x27: /* Extract */
3776 disas_extract(s
, insn
);
3779 unallocated_encoding(s
);
3784 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3785 * Note that it is the caller's responsibility to ensure that the
3786 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3787 * mandated semantics for out of range shifts.
3789 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3790 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3792 switch (shift_type
) {
3793 case A64_SHIFT_TYPE_LSL
:
3794 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3796 case A64_SHIFT_TYPE_LSR
:
3797 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3799 case A64_SHIFT_TYPE_ASR
:
3801 tcg_gen_ext32s_i64(dst
, src
);
3803 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3805 case A64_SHIFT_TYPE_ROR
:
3807 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3810 t0
= tcg_temp_new_i32();
3811 t1
= tcg_temp_new_i32();
3812 tcg_gen_extrl_i64_i32(t0
, src
);
3813 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3814 tcg_gen_rotr_i32(t0
, t0
, t1
);
3815 tcg_gen_extu_i32_i64(dst
, t0
);
3816 tcg_temp_free_i32(t0
);
3817 tcg_temp_free_i32(t1
);
3821 assert(FALSE
); /* all shift types should be handled */
3825 if (!sf
) { /* zero extend final result */
3826 tcg_gen_ext32u_i64(dst
, dst
);
3830 /* Shift a TCGv src by immediate, put result in dst.
3831 * The shift amount must be in range (this should always be true as the
3832 * relevant instructions will UNDEF on bad shift immediates).
3834 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3835 enum a64_shift_type shift_type
, unsigned int shift_i
)
3837 assert(shift_i
< (sf
? 64 : 32));
3840 tcg_gen_mov_i64(dst
, src
);
3842 TCGv_i64 shift_const
;
3844 shift_const
= tcg_const_i64(shift_i
);
3845 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3846 tcg_temp_free_i64(shift_const
);
3850 /* Logical (shifted register)
3851 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3852 * +----+-----+-----------+-------+---+------+--------+------+------+
3853 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3854 * +----+-----+-----------+-------+---+------+--------+------+------+
3856 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3858 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3859 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3861 sf
= extract32(insn
, 31, 1);
3862 opc
= extract32(insn
, 29, 2);
3863 shift_type
= extract32(insn
, 22, 2);
3864 invert
= extract32(insn
, 21, 1);
3865 rm
= extract32(insn
, 16, 5);
3866 shift_amount
= extract32(insn
, 10, 6);
3867 rn
= extract32(insn
, 5, 5);
3868 rd
= extract32(insn
, 0, 5);
3870 if (!sf
&& (shift_amount
& (1 << 5))) {
3871 unallocated_encoding(s
);
3875 tcg_rd
= cpu_reg(s
, rd
);
3877 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3878 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3879 * register-register MOV and MVN, so it is worth special casing.
3881 tcg_rm
= cpu_reg(s
, rm
);
3883 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3885 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3889 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3891 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3897 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3900 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3903 tcg_rn
= cpu_reg(s
, rn
);
3905 switch (opc
| (invert
<< 2)) {
3908 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3911 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3914 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3918 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3921 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3924 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3932 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3936 gen_logic_CC(sf
, tcg_rd
);
3941 * Add/subtract (extended register)
3943 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3944 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3945 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3946 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3948 * sf: 0 -> 32bit, 1 -> 64bit
3949 * op: 0 -> add , 1 -> sub
3952 * option: extension type (see DecodeRegExtend)
3953 * imm3: optional shift to Rm
3955 * Rd = Rn + LSL(extend(Rm), amount)
3957 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3959 int rd
= extract32(insn
, 0, 5);
3960 int rn
= extract32(insn
, 5, 5);
3961 int imm3
= extract32(insn
, 10, 3);
3962 int option
= extract32(insn
, 13, 3);
3963 int rm
= extract32(insn
, 16, 5);
3964 bool setflags
= extract32(insn
, 29, 1);
3965 bool sub_op
= extract32(insn
, 30, 1);
3966 bool sf
= extract32(insn
, 31, 1);
3968 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3970 TCGv_i64 tcg_result
;
3973 unallocated_encoding(s
);
3977 /* non-flag setting ops may use SP */
3979 tcg_rd
= cpu_reg_sp(s
, rd
);
3981 tcg_rd
= cpu_reg(s
, rd
);
3983 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3985 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3986 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3988 tcg_result
= tcg_temp_new_i64();
3992 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3994 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3998 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4000 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4005 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4007 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4010 tcg_temp_free_i64(tcg_result
);
4014 * Add/subtract (shifted register)
4016 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4017 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4018 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4019 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4021 * sf: 0 -> 32bit, 1 -> 64bit
4022 * op: 0 -> add , 1 -> sub
4024 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4025 * imm6: Shift amount to apply to Rm before the add/sub
4027 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4029 int rd
= extract32(insn
, 0, 5);
4030 int rn
= extract32(insn
, 5, 5);
4031 int imm6
= extract32(insn
, 10, 6);
4032 int rm
= extract32(insn
, 16, 5);
4033 int shift_type
= extract32(insn
, 22, 2);
4034 bool setflags
= extract32(insn
, 29, 1);
4035 bool sub_op
= extract32(insn
, 30, 1);
4036 bool sf
= extract32(insn
, 31, 1);
4038 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4039 TCGv_i64 tcg_rn
, tcg_rm
;
4040 TCGv_i64 tcg_result
;
4042 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4043 unallocated_encoding(s
);
4047 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4048 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4050 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4052 tcg_result
= tcg_temp_new_i64();
4056 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4058 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4062 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4064 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4069 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4071 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4074 tcg_temp_free_i64(tcg_result
);
4077 /* Data-processing (3 source)
4079 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4080 * +--+------+-----------+------+------+----+------+------+------+
4081 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4082 * +--+------+-----------+------+------+----+------+------+------+
4084 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4086 int rd
= extract32(insn
, 0, 5);
4087 int rn
= extract32(insn
, 5, 5);
4088 int ra
= extract32(insn
, 10, 5);
4089 int rm
= extract32(insn
, 16, 5);
4090 int op_id
= (extract32(insn
, 29, 3) << 4) |
4091 (extract32(insn
, 21, 3) << 1) |
4092 extract32(insn
, 15, 1);
4093 bool sf
= extract32(insn
, 31, 1);
4094 bool is_sub
= extract32(op_id
, 0, 1);
4095 bool is_high
= extract32(op_id
, 2, 1);
4096 bool is_signed
= false;
4101 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4103 case 0x42: /* SMADDL */
4104 case 0x43: /* SMSUBL */
4105 case 0x44: /* SMULH */
4108 case 0x0: /* MADD (32bit) */
4109 case 0x1: /* MSUB (32bit) */
4110 case 0x40: /* MADD (64bit) */
4111 case 0x41: /* MSUB (64bit) */
4112 case 0x4a: /* UMADDL */
4113 case 0x4b: /* UMSUBL */
4114 case 0x4c: /* UMULH */
4117 unallocated_encoding(s
);
4122 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4123 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4124 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4125 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4128 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4130 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4133 tcg_temp_free_i64(low_bits
);
4137 tcg_op1
= tcg_temp_new_i64();
4138 tcg_op2
= tcg_temp_new_i64();
4139 tcg_tmp
= tcg_temp_new_i64();
4142 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4143 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4146 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4147 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4149 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4150 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4154 if (ra
== 31 && !is_sub
) {
4155 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4156 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4158 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4160 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4162 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4167 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4170 tcg_temp_free_i64(tcg_op1
);
4171 tcg_temp_free_i64(tcg_op2
);
4172 tcg_temp_free_i64(tcg_tmp
);
4175 /* Add/subtract (with carry)
4176 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4177 * +--+--+--+------------------------+------+---------+------+-----+
4178 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4179 * +--+--+--+------------------------+------+---------+------+-----+
4183 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4185 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4186 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4188 if (extract32(insn
, 10, 6) != 0) {
4189 unallocated_encoding(s
);
4193 sf
= extract32(insn
, 31, 1);
4194 op
= extract32(insn
, 30, 1);
4195 setflags
= extract32(insn
, 29, 1);
4196 rm
= extract32(insn
, 16, 5);
4197 rn
= extract32(insn
, 5, 5);
4198 rd
= extract32(insn
, 0, 5);
4200 tcg_rd
= cpu_reg(s
, rd
);
4201 tcg_rn
= cpu_reg(s
, rn
);
4204 tcg_y
= new_tmp_a64(s
);
4205 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4207 tcg_y
= cpu_reg(s
, rm
);
4211 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4213 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4217 /* Conditional compare (immediate / register)
4218 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4219 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4220 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4221 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4224 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4226 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4227 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4228 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4231 if (!extract32(insn
, 29, 1)) {
4232 unallocated_encoding(s
);
4235 if (insn
& (1 << 10 | 1 << 4)) {
4236 unallocated_encoding(s
);
4239 sf
= extract32(insn
, 31, 1);
4240 op
= extract32(insn
, 30, 1);
4241 is_imm
= extract32(insn
, 11, 1);
4242 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4243 cond
= extract32(insn
, 12, 4);
4244 rn
= extract32(insn
, 5, 5);
4245 nzcv
= extract32(insn
, 0, 4);
4247 /* Set T0 = !COND. */
4248 tcg_t0
= tcg_temp_new_i32();
4249 arm_test_cc(&c
, cond
);
4250 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4253 /* Load the arguments for the new comparison. */
4255 tcg_y
= new_tmp_a64(s
);
4256 tcg_gen_movi_i64(tcg_y
, y
);
4258 tcg_y
= cpu_reg(s
, y
);
4260 tcg_rn
= cpu_reg(s
, rn
);
4262 /* Set the flags for the new comparison. */
4263 tcg_tmp
= tcg_temp_new_i64();
4265 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4267 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4269 tcg_temp_free_i64(tcg_tmp
);
4271 /* If COND was false, force the flags to #nzcv. Compute two masks
4272 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4273 * For tcg hosts that support ANDC, we can make do with just T1.
4274 * In either case, allow the tcg optimizer to delete any unused mask.
4276 tcg_t1
= tcg_temp_new_i32();
4277 tcg_t2
= tcg_temp_new_i32();
4278 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4279 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4281 if (nzcv
& 8) { /* N */
4282 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4284 if (TCG_TARGET_HAS_andc_i32
) {
4285 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4287 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4290 if (nzcv
& 4) { /* Z */
4291 if (TCG_TARGET_HAS_andc_i32
) {
4292 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4294 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4297 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4299 if (nzcv
& 2) { /* C */
4300 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4302 if (TCG_TARGET_HAS_andc_i32
) {
4303 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4305 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4308 if (nzcv
& 1) { /* V */
4309 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4311 if (TCG_TARGET_HAS_andc_i32
) {
4312 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4314 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4317 tcg_temp_free_i32(tcg_t0
);
4318 tcg_temp_free_i32(tcg_t1
);
4319 tcg_temp_free_i32(tcg_t2
);
4322 /* Conditional select
4323 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4324 * +----+----+---+-----------------+------+------+-----+------+------+
4325 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4326 * +----+----+---+-----------------+------+------+-----+------+------+
4328 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4330 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4331 TCGv_i64 tcg_rd
, zero
;
4334 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4335 /* S == 1 or op2<1> == 1 */
4336 unallocated_encoding(s
);
4339 sf
= extract32(insn
, 31, 1);
4340 else_inv
= extract32(insn
, 30, 1);
4341 rm
= extract32(insn
, 16, 5);
4342 cond
= extract32(insn
, 12, 4);
4343 else_inc
= extract32(insn
, 10, 1);
4344 rn
= extract32(insn
, 5, 5);
4345 rd
= extract32(insn
, 0, 5);
4347 tcg_rd
= cpu_reg(s
, rd
);
4349 a64_test_cc(&c
, cond
);
4350 zero
= tcg_const_i64(0);
4352 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4354 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4356 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4359 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4360 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4361 if (else_inv
&& else_inc
) {
4362 tcg_gen_neg_i64(t_false
, t_false
);
4363 } else if (else_inv
) {
4364 tcg_gen_not_i64(t_false
, t_false
);
4365 } else if (else_inc
) {
4366 tcg_gen_addi_i64(t_false
, t_false
, 1);
4368 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4371 tcg_temp_free_i64(zero
);
4375 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4379 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4380 unsigned int rn
, unsigned int rd
)
4382 TCGv_i64 tcg_rd
, tcg_rn
;
4383 tcg_rd
= cpu_reg(s
, rd
);
4384 tcg_rn
= cpu_reg(s
, rn
);
4387 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4389 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4390 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4391 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4392 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4393 tcg_temp_free_i32(tcg_tmp32
);
4397 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4398 unsigned int rn
, unsigned int rd
)
4400 TCGv_i64 tcg_rd
, tcg_rn
;
4401 tcg_rd
= cpu_reg(s
, rd
);
4402 tcg_rn
= cpu_reg(s
, rn
);
4405 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4407 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4408 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4409 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4410 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4411 tcg_temp_free_i32(tcg_tmp32
);
4415 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4416 unsigned int rn
, unsigned int rd
)
4418 TCGv_i64 tcg_rd
, tcg_rn
;
4419 tcg_rd
= cpu_reg(s
, rd
);
4420 tcg_rn
= cpu_reg(s
, rn
);
4423 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4425 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4426 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4427 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4428 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4429 tcg_temp_free_i32(tcg_tmp32
);
4433 /* REV with sf==1, opcode==3 ("REV64") */
4434 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4435 unsigned int rn
, unsigned int rd
)
4438 unallocated_encoding(s
);
4441 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4444 /* REV with sf==0, opcode==2
4445 * REV32 (sf==1, opcode==2)
4447 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4448 unsigned int rn
, unsigned int rd
)
4450 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4453 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4454 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4456 /* bswap32_i64 requires zero high word */
4457 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4458 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4459 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4460 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4461 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4463 tcg_temp_free_i64(tcg_tmp
);
4465 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4466 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4470 /* REV16 (opcode==1) */
4471 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4472 unsigned int rn
, unsigned int rd
)
4474 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4475 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4476 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4477 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4479 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4480 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4481 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4482 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4483 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4485 tcg_temp_free_i64(mask
);
4486 tcg_temp_free_i64(tcg_tmp
);
4489 /* Data-processing (1 source)
4490 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4491 * +----+---+---+-----------------+---------+--------+------+------+
4492 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4493 * +----+---+---+-----------------+---------+--------+------+------+
4495 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4497 unsigned int sf
, opcode
, rn
, rd
;
4499 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4500 unallocated_encoding(s
);
4504 sf
= extract32(insn
, 31, 1);
4505 opcode
= extract32(insn
, 10, 6);
4506 rn
= extract32(insn
, 5, 5);
4507 rd
= extract32(insn
, 0, 5);
4511 handle_rbit(s
, sf
, rn
, rd
);
4514 handle_rev16(s
, sf
, rn
, rd
);
4517 handle_rev32(s
, sf
, rn
, rd
);
4520 handle_rev64(s
, sf
, rn
, rd
);
4523 handle_clz(s
, sf
, rn
, rd
);
4526 handle_cls(s
, sf
, rn
, rd
);
4531 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4532 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4534 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4535 tcg_rd
= cpu_reg(s
, rd
);
4537 if (!sf
&& is_signed
) {
4538 tcg_n
= new_tmp_a64(s
);
4539 tcg_m
= new_tmp_a64(s
);
4540 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4541 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4543 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4544 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4548 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4550 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4553 if (!sf
) { /* zero extend final result */
4554 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4558 /* LSLV, LSRV, ASRV, RORV */
4559 static void handle_shift_reg(DisasContext
*s
,
4560 enum a64_shift_type shift_type
, unsigned int sf
,
4561 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4563 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4564 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4565 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4567 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4568 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4569 tcg_temp_free_i64(tcg_shift
);
4572 /* CRC32[BHWX], CRC32C[BHWX] */
4573 static void handle_crc32(DisasContext
*s
,
4574 unsigned int sf
, unsigned int sz
, bool crc32c
,
4575 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4577 TCGv_i64 tcg_acc
, tcg_val
;
4580 if (!dc_isar_feature(aa64_crc32
, s
)
4581 || (sf
== 1 && sz
!= 3)
4582 || (sf
== 0 && sz
== 3)) {
4583 unallocated_encoding(s
);
4588 tcg_val
= cpu_reg(s
, rm
);
4602 g_assert_not_reached();
4604 tcg_val
= new_tmp_a64(s
);
4605 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4608 tcg_acc
= cpu_reg(s
, rn
);
4609 tcg_bytes
= tcg_const_i32(1 << sz
);
4612 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4614 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4617 tcg_temp_free_i32(tcg_bytes
);
4620 /* Data-processing (2 source)
4621 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4622 * +----+---+---+-----------------+------+--------+------+------+
4623 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4624 * +----+---+---+-----------------+------+--------+------+------+
4626 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4628 unsigned int sf
, rm
, opcode
, rn
, rd
;
4629 sf
= extract32(insn
, 31, 1);
4630 rm
= extract32(insn
, 16, 5);
4631 opcode
= extract32(insn
, 10, 6);
4632 rn
= extract32(insn
, 5, 5);
4633 rd
= extract32(insn
, 0, 5);
4635 if (extract32(insn
, 29, 1)) {
4636 unallocated_encoding(s
);
4642 handle_div(s
, false, sf
, rm
, rn
, rd
);
4645 handle_div(s
, true, sf
, rm
, rn
, rd
);
4648 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4651 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4654 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4657 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4666 case 23: /* CRC32 */
4668 int sz
= extract32(opcode
, 0, 2);
4669 bool crc32c
= extract32(opcode
, 2, 1);
4670 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4674 unallocated_encoding(s
);
4679 /* Data processing - register */
4680 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4682 switch (extract32(insn
, 24, 5)) {
4683 case 0x0a: /* Logical (shifted register) */
4684 disas_logic_reg(s
, insn
);
4686 case 0x0b: /* Add/subtract */
4687 if (insn
& (1 << 21)) { /* (extended register) */
4688 disas_add_sub_ext_reg(s
, insn
);
4690 disas_add_sub_reg(s
, insn
);
4693 case 0x1b: /* Data-processing (3 source) */
4694 disas_data_proc_3src(s
, insn
);
4697 switch (extract32(insn
, 21, 3)) {
4698 case 0x0: /* Add/subtract (with carry) */
4699 disas_adc_sbc(s
, insn
);
4701 case 0x2: /* Conditional compare */
4702 disas_cc(s
, insn
); /* both imm and reg forms */
4704 case 0x4: /* Conditional select */
4705 disas_cond_select(s
, insn
);
4707 case 0x6: /* Data-processing */
4708 if (insn
& (1 << 30)) { /* (1 source) */
4709 disas_data_proc_1src(s
, insn
);
4710 } else { /* (2 source) */
4711 disas_data_proc_2src(s
, insn
);
4715 unallocated_encoding(s
);
4720 unallocated_encoding(s
);
4725 static void handle_fp_compare(DisasContext
*s
, int size
,
4726 unsigned int rn
, unsigned int rm
,
4727 bool cmp_with_zero
, bool signal_all_nans
)
4729 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4730 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
4732 if (size
== MO_64
) {
4733 TCGv_i64 tcg_vn
, tcg_vm
;
4735 tcg_vn
= read_fp_dreg(s
, rn
);
4736 if (cmp_with_zero
) {
4737 tcg_vm
= tcg_const_i64(0);
4739 tcg_vm
= read_fp_dreg(s
, rm
);
4741 if (signal_all_nans
) {
4742 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4744 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4746 tcg_temp_free_i64(tcg_vn
);
4747 tcg_temp_free_i64(tcg_vm
);
4749 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
4750 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
4752 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
4753 if (cmp_with_zero
) {
4754 tcg_gen_movi_i32(tcg_vm
, 0);
4756 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
4761 if (signal_all_nans
) {
4762 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4764 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4768 if (signal_all_nans
) {
4769 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4771 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4775 g_assert_not_reached();
4778 tcg_temp_free_i32(tcg_vn
);
4779 tcg_temp_free_i32(tcg_vm
);
4782 tcg_temp_free_ptr(fpst
);
4784 gen_set_nzcv(tcg_flags
);
4786 tcg_temp_free_i64(tcg_flags
);
4789 /* Floating point compare
4790 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4791 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4792 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4793 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4795 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4797 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4800 mos
= extract32(insn
, 29, 3);
4801 type
= extract32(insn
, 22, 2);
4802 rm
= extract32(insn
, 16, 5);
4803 op
= extract32(insn
, 14, 2);
4804 rn
= extract32(insn
, 5, 5);
4805 opc
= extract32(insn
, 3, 2);
4806 op2r
= extract32(insn
, 0, 3);
4808 if (mos
|| op
|| op2r
) {
4809 unallocated_encoding(s
);
4822 if (dc_isar_feature(aa64_fp16
, s
)) {
4827 unallocated_encoding(s
);
4831 if (!fp_access_check(s
)) {
4835 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
4838 /* Floating point conditional compare
4839 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4840 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4841 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4842 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4844 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4846 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4848 TCGLabel
*label_continue
= NULL
;
4851 mos
= extract32(insn
, 29, 3);
4852 type
= extract32(insn
, 22, 2);
4853 rm
= extract32(insn
, 16, 5);
4854 cond
= extract32(insn
, 12, 4);
4855 rn
= extract32(insn
, 5, 5);
4856 op
= extract32(insn
, 4, 1);
4857 nzcv
= extract32(insn
, 0, 4);
4860 unallocated_encoding(s
);
4873 if (dc_isar_feature(aa64_fp16
, s
)) {
4878 unallocated_encoding(s
);
4882 if (!fp_access_check(s
)) {
4886 if (cond
< 0x0e) { /* not always */
4887 TCGLabel
*label_match
= gen_new_label();
4888 label_continue
= gen_new_label();
4889 arm_gen_test_cc(cond
, label_match
);
4891 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4892 gen_set_nzcv(tcg_flags
);
4893 tcg_temp_free_i64(tcg_flags
);
4894 tcg_gen_br(label_continue
);
4895 gen_set_label(label_match
);
4898 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
4901 gen_set_label(label_continue
);
4905 /* Floating point conditional select
4906 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4907 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4908 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4909 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4911 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4913 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4914 TCGv_i64 t_true
, t_false
, t_zero
;
4918 mos
= extract32(insn
, 29, 3);
4919 type
= extract32(insn
, 22, 2);
4920 rm
= extract32(insn
, 16, 5);
4921 cond
= extract32(insn
, 12, 4);
4922 rn
= extract32(insn
, 5, 5);
4923 rd
= extract32(insn
, 0, 5);
4926 unallocated_encoding(s
);
4939 if (dc_isar_feature(aa64_fp16
, s
)) {
4944 unallocated_encoding(s
);
4948 if (!fp_access_check(s
)) {
4952 /* Zero extend sreg & hreg inputs to 64 bits now. */
4953 t_true
= tcg_temp_new_i64();
4954 t_false
= tcg_temp_new_i64();
4955 read_vec_element(s
, t_true
, rn
, 0, sz
);
4956 read_vec_element(s
, t_false
, rm
, 0, sz
);
4958 a64_test_cc(&c
, cond
);
4959 t_zero
= tcg_const_i64(0);
4960 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4961 tcg_temp_free_i64(t_zero
);
4962 tcg_temp_free_i64(t_false
);
4965 /* Note that sregs & hregs write back zeros to the high bits,
4966 and we've already done the zero-extension. */
4967 write_fp_dreg(s
, rd
, t_true
);
4968 tcg_temp_free_i64(t_true
);
4971 /* Floating-point data-processing (1 source) - half precision */
4972 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
4974 TCGv_ptr fpst
= NULL
;
4975 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
4976 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4979 case 0x0: /* FMOV */
4980 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4982 case 0x1: /* FABS */
4983 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
4985 case 0x2: /* FNEG */
4986 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
4988 case 0x3: /* FSQRT */
4989 fpst
= get_fpstatus_ptr(true);
4990 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
4992 case 0x8: /* FRINTN */
4993 case 0x9: /* FRINTP */
4994 case 0xa: /* FRINTM */
4995 case 0xb: /* FRINTZ */
4996 case 0xc: /* FRINTA */
4998 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4999 fpst
= get_fpstatus_ptr(true);
5001 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5002 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5004 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5005 tcg_temp_free_i32(tcg_rmode
);
5008 case 0xe: /* FRINTX */
5009 fpst
= get_fpstatus_ptr(true);
5010 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5012 case 0xf: /* FRINTI */
5013 fpst
= get_fpstatus_ptr(true);
5014 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5020 write_fp_sreg(s
, rd
, tcg_res
);
5023 tcg_temp_free_ptr(fpst
);
5025 tcg_temp_free_i32(tcg_op
);
5026 tcg_temp_free_i32(tcg_res
);
5029 /* Floating-point data-processing (1 source) - single precision */
5030 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5036 fpst
= get_fpstatus_ptr(false);
5037 tcg_op
= read_fp_sreg(s
, rn
);
5038 tcg_res
= tcg_temp_new_i32();
5041 case 0x0: /* FMOV */
5042 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5044 case 0x1: /* FABS */
5045 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5047 case 0x2: /* FNEG */
5048 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5050 case 0x3: /* FSQRT */
5051 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5053 case 0x8: /* FRINTN */
5054 case 0x9: /* FRINTP */
5055 case 0xa: /* FRINTM */
5056 case 0xb: /* FRINTZ */
5057 case 0xc: /* FRINTA */
5059 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5061 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5062 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5064 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5065 tcg_temp_free_i32(tcg_rmode
);
5068 case 0xe: /* FRINTX */
5069 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5071 case 0xf: /* FRINTI */
5072 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5078 write_fp_sreg(s
, rd
, tcg_res
);
5080 tcg_temp_free_ptr(fpst
);
5081 tcg_temp_free_i32(tcg_op
);
5082 tcg_temp_free_i32(tcg_res
);
5085 /* Floating-point data-processing (1 source) - double precision */
5086 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5093 case 0x0: /* FMOV */
5094 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5098 fpst
= get_fpstatus_ptr(false);
5099 tcg_op
= read_fp_dreg(s
, rn
);
5100 tcg_res
= tcg_temp_new_i64();
5103 case 0x1: /* FABS */
5104 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5106 case 0x2: /* FNEG */
5107 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5109 case 0x3: /* FSQRT */
5110 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5112 case 0x8: /* FRINTN */
5113 case 0x9: /* FRINTP */
5114 case 0xa: /* FRINTM */
5115 case 0xb: /* FRINTZ */
5116 case 0xc: /* FRINTA */
5118 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5120 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5121 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5123 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5124 tcg_temp_free_i32(tcg_rmode
);
5127 case 0xe: /* FRINTX */
5128 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5130 case 0xf: /* FRINTI */
5131 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5137 write_fp_dreg(s
, rd
, tcg_res
);
5139 tcg_temp_free_ptr(fpst
);
5140 tcg_temp_free_i64(tcg_op
);
5141 tcg_temp_free_i64(tcg_res
);
5144 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5145 int rd
, int rn
, int dtype
, int ntype
)
5150 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5152 /* Single to double */
5153 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5154 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5155 write_fp_dreg(s
, rd
, tcg_rd
);
5156 tcg_temp_free_i64(tcg_rd
);
5158 /* Single to half */
5159 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5160 TCGv_i32 ahp
= get_ahp_flag();
5161 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5163 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5164 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5165 write_fp_sreg(s
, rd
, tcg_rd
);
5166 tcg_temp_free_i32(tcg_rd
);
5167 tcg_temp_free_i32(ahp
);
5168 tcg_temp_free_ptr(fpst
);
5170 tcg_temp_free_i32(tcg_rn
);
5175 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5176 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5178 /* Double to single */
5179 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5181 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5182 TCGv_i32 ahp
= get_ahp_flag();
5183 /* Double to half */
5184 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5185 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5186 tcg_temp_free_ptr(fpst
);
5187 tcg_temp_free_i32(ahp
);
5189 write_fp_sreg(s
, rd
, tcg_rd
);
5190 tcg_temp_free_i32(tcg_rd
);
5191 tcg_temp_free_i64(tcg_rn
);
5196 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5197 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5198 TCGv_i32 tcg_ahp
= get_ahp_flag();
5199 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5201 /* Half to single */
5202 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5203 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5204 write_fp_sreg(s
, rd
, tcg_rd
);
5205 tcg_temp_free_ptr(tcg_fpst
);
5206 tcg_temp_free_i32(tcg_ahp
);
5207 tcg_temp_free_i32(tcg_rd
);
5209 /* Half to double */
5210 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5211 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5212 write_fp_dreg(s
, rd
, tcg_rd
);
5213 tcg_temp_free_i64(tcg_rd
);
5215 tcg_temp_free_i32(tcg_rn
);
5223 /* Floating point data-processing (1 source)
5224 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5225 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5226 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5227 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5229 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5231 int type
= extract32(insn
, 22, 2);
5232 int opcode
= extract32(insn
, 15, 6);
5233 int rn
= extract32(insn
, 5, 5);
5234 int rd
= extract32(insn
, 0, 5);
5237 case 0x4: case 0x5: case 0x7:
5239 /* FCVT between half, single and double precision */
5240 int dtype
= extract32(opcode
, 0, 2);
5241 if (type
== 2 || dtype
== type
) {
5242 unallocated_encoding(s
);
5245 if (!fp_access_check(s
)) {
5249 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5255 /* 32-to-32 and 64-to-64 ops */
5258 if (!fp_access_check(s
)) {
5262 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5265 if (!fp_access_check(s
)) {
5269 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5272 if (!dc_isar_feature(aa64_fp16
, s
)) {
5273 unallocated_encoding(s
);
5277 if (!fp_access_check(s
)) {
5281 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5284 unallocated_encoding(s
);
5288 unallocated_encoding(s
);
5293 /* Floating-point data-processing (2 source) - single precision */
5294 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5295 int rd
, int rn
, int rm
)
5302 tcg_res
= tcg_temp_new_i32();
5303 fpst
= get_fpstatus_ptr(false);
5304 tcg_op1
= read_fp_sreg(s
, rn
);
5305 tcg_op2
= read_fp_sreg(s
, rm
);
5308 case 0x0: /* FMUL */
5309 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5311 case 0x1: /* FDIV */
5312 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5314 case 0x2: /* FADD */
5315 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5317 case 0x3: /* FSUB */
5318 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5320 case 0x4: /* FMAX */
5321 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5323 case 0x5: /* FMIN */
5324 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5326 case 0x6: /* FMAXNM */
5327 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5329 case 0x7: /* FMINNM */
5330 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5332 case 0x8: /* FNMUL */
5333 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5334 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5338 write_fp_sreg(s
, rd
, tcg_res
);
5340 tcg_temp_free_ptr(fpst
);
5341 tcg_temp_free_i32(tcg_op1
);
5342 tcg_temp_free_i32(tcg_op2
);
5343 tcg_temp_free_i32(tcg_res
);
5346 /* Floating-point data-processing (2 source) - double precision */
5347 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5348 int rd
, int rn
, int rm
)
5355 tcg_res
= tcg_temp_new_i64();
5356 fpst
= get_fpstatus_ptr(false);
5357 tcg_op1
= read_fp_dreg(s
, rn
);
5358 tcg_op2
= read_fp_dreg(s
, rm
);
5361 case 0x0: /* FMUL */
5362 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5364 case 0x1: /* FDIV */
5365 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5367 case 0x2: /* FADD */
5368 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5370 case 0x3: /* FSUB */
5371 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5373 case 0x4: /* FMAX */
5374 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5376 case 0x5: /* FMIN */
5377 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5379 case 0x6: /* FMAXNM */
5380 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5382 case 0x7: /* FMINNM */
5383 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5385 case 0x8: /* FNMUL */
5386 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5387 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5391 write_fp_dreg(s
, rd
, tcg_res
);
5393 tcg_temp_free_ptr(fpst
);
5394 tcg_temp_free_i64(tcg_op1
);
5395 tcg_temp_free_i64(tcg_op2
);
5396 tcg_temp_free_i64(tcg_res
);
5399 /* Floating-point data-processing (2 source) - half precision */
5400 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5401 int rd
, int rn
, int rm
)
5408 tcg_res
= tcg_temp_new_i32();
5409 fpst
= get_fpstatus_ptr(true);
5410 tcg_op1
= read_fp_hreg(s
, rn
);
5411 tcg_op2
= read_fp_hreg(s
, rm
);
5414 case 0x0: /* FMUL */
5415 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5417 case 0x1: /* FDIV */
5418 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5420 case 0x2: /* FADD */
5421 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5423 case 0x3: /* FSUB */
5424 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5426 case 0x4: /* FMAX */
5427 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5429 case 0x5: /* FMIN */
5430 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5432 case 0x6: /* FMAXNM */
5433 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5435 case 0x7: /* FMINNM */
5436 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5438 case 0x8: /* FNMUL */
5439 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5440 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5443 g_assert_not_reached();
5446 write_fp_sreg(s
, rd
, tcg_res
);
5448 tcg_temp_free_ptr(fpst
);
5449 tcg_temp_free_i32(tcg_op1
);
5450 tcg_temp_free_i32(tcg_op2
);
5451 tcg_temp_free_i32(tcg_res
);
5454 /* Floating point data-processing (2 source)
5455 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5456 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5457 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5458 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5460 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5462 int type
= extract32(insn
, 22, 2);
5463 int rd
= extract32(insn
, 0, 5);
5464 int rn
= extract32(insn
, 5, 5);
5465 int rm
= extract32(insn
, 16, 5);
5466 int opcode
= extract32(insn
, 12, 4);
5469 unallocated_encoding(s
);
5475 if (!fp_access_check(s
)) {
5478 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5481 if (!fp_access_check(s
)) {
5484 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5487 if (!dc_isar_feature(aa64_fp16
, s
)) {
5488 unallocated_encoding(s
);
5491 if (!fp_access_check(s
)) {
5494 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5497 unallocated_encoding(s
);
5501 /* Floating-point data-processing (3 source) - single precision */
5502 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
5503 int rd
, int rn
, int rm
, int ra
)
5505 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5506 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5507 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5509 tcg_op1
= read_fp_sreg(s
, rn
);
5510 tcg_op2
= read_fp_sreg(s
, rm
);
5511 tcg_op3
= read_fp_sreg(s
, ra
);
5513 /* These are fused multiply-add, and must be done as one
5514 * floating point operation with no rounding between the
5515 * multiplication and addition steps.
5516 * NB that doing the negations here as separate steps is
5517 * correct : an input NaN should come out with its sign bit
5518 * flipped if it is a negated-input.
5521 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
5525 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
5528 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5530 write_fp_sreg(s
, rd
, tcg_res
);
5532 tcg_temp_free_ptr(fpst
);
5533 tcg_temp_free_i32(tcg_op1
);
5534 tcg_temp_free_i32(tcg_op2
);
5535 tcg_temp_free_i32(tcg_op3
);
5536 tcg_temp_free_i32(tcg_res
);
5539 /* Floating-point data-processing (3 source) - double precision */
5540 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
5541 int rd
, int rn
, int rm
, int ra
)
5543 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
5544 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5545 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5547 tcg_op1
= read_fp_dreg(s
, rn
);
5548 tcg_op2
= read_fp_dreg(s
, rm
);
5549 tcg_op3
= read_fp_dreg(s
, ra
);
5551 /* These are fused multiply-add, and must be done as one
5552 * floating point operation with no rounding between the
5553 * multiplication and addition steps.
5554 * NB that doing the negations here as separate steps is
5555 * correct : an input NaN should come out with its sign bit
5556 * flipped if it is a negated-input.
5559 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
5563 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
5566 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5568 write_fp_dreg(s
, rd
, tcg_res
);
5570 tcg_temp_free_ptr(fpst
);
5571 tcg_temp_free_i64(tcg_op1
);
5572 tcg_temp_free_i64(tcg_op2
);
5573 tcg_temp_free_i64(tcg_op3
);
5574 tcg_temp_free_i64(tcg_res
);
5577 /* Floating-point data-processing (3 source) - half precision */
5578 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
5579 int rd
, int rn
, int rm
, int ra
)
5581 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5582 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5583 TCGv_ptr fpst
= get_fpstatus_ptr(true);
5585 tcg_op1
= read_fp_hreg(s
, rn
);
5586 tcg_op2
= read_fp_hreg(s
, rm
);
5587 tcg_op3
= read_fp_hreg(s
, ra
);
5589 /* These are fused multiply-add, and must be done as one
5590 * floating point operation with no rounding between the
5591 * multiplication and addition steps.
5592 * NB that doing the negations here as separate steps is
5593 * correct : an input NaN should come out with its sign bit
5594 * flipped if it is a negated-input.
5597 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
5601 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
5604 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5606 write_fp_sreg(s
, rd
, tcg_res
);
5608 tcg_temp_free_ptr(fpst
);
5609 tcg_temp_free_i32(tcg_op1
);
5610 tcg_temp_free_i32(tcg_op2
);
5611 tcg_temp_free_i32(tcg_op3
);
5612 tcg_temp_free_i32(tcg_res
);
5615 /* Floating point data-processing (3 source)
5616 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
5617 * +---+---+---+-----------+------+----+------+----+------+------+------+
5618 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
5619 * +---+---+---+-----------+------+----+------+----+------+------+------+
5621 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
5623 int type
= extract32(insn
, 22, 2);
5624 int rd
= extract32(insn
, 0, 5);
5625 int rn
= extract32(insn
, 5, 5);
5626 int ra
= extract32(insn
, 10, 5);
5627 int rm
= extract32(insn
, 16, 5);
5628 bool o0
= extract32(insn
, 15, 1);
5629 bool o1
= extract32(insn
, 21, 1);
5633 if (!fp_access_check(s
)) {
5636 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5639 if (!fp_access_check(s
)) {
5642 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5645 if (!dc_isar_feature(aa64_fp16
, s
)) {
5646 unallocated_encoding(s
);
5649 if (!fp_access_check(s
)) {
5652 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5655 unallocated_encoding(s
);
5659 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
5660 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
5661 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
5663 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
5669 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5670 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5671 extract32(imm8
, 0, 6);
5675 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5676 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5677 (extract32(imm8
, 0, 6) << 3);
5681 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5682 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
5683 (extract32(imm8
, 0, 6) << 6);
5686 g_assert_not_reached();
5691 /* Floating point immediate
5692 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5693 * +---+---+---+-----------+------+---+------------+-------+------+------+
5694 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5695 * +---+---+---+-----------+------+---+------------+-------+------+------+
5697 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
5699 int rd
= extract32(insn
, 0, 5);
5700 int imm8
= extract32(insn
, 13, 8);
5701 int type
= extract32(insn
, 22, 2);
5715 if (dc_isar_feature(aa64_fp16
, s
)) {
5720 unallocated_encoding(s
);
5724 if (!fp_access_check(s
)) {
5728 imm
= vfp_expand_imm(sz
, imm8
);
5730 tcg_res
= tcg_const_i64(imm
);
5731 write_fp_dreg(s
, rd
, tcg_res
);
5732 tcg_temp_free_i64(tcg_res
);
5735 /* Handle floating point <=> fixed point conversions. Note that we can
5736 * also deal with fp <=> integer conversions as a special case (scale == 64)
5737 * OPTME: consider handling that special case specially or at least skipping
5738 * the call to scalbn in the helpers for zero shifts.
5740 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5741 bool itof
, int rmode
, int scale
, int sf
, int type
)
5743 bool is_signed
= !(opcode
& 1);
5744 TCGv_ptr tcg_fpstatus
;
5745 TCGv_i32 tcg_shift
, tcg_single
;
5746 TCGv_i64 tcg_double
;
5748 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
5750 tcg_shift
= tcg_const_i32(64 - scale
);
5753 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5755 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5758 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5760 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5763 tcg_int
= tcg_extend
;
5767 case 1: /* float64 */
5768 tcg_double
= tcg_temp_new_i64();
5770 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5771 tcg_shift
, tcg_fpstatus
);
5773 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5774 tcg_shift
, tcg_fpstatus
);
5776 write_fp_dreg(s
, rd
, tcg_double
);
5777 tcg_temp_free_i64(tcg_double
);
5780 case 0: /* float32 */
5781 tcg_single
= tcg_temp_new_i32();
5783 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5784 tcg_shift
, tcg_fpstatus
);
5786 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5787 tcg_shift
, tcg_fpstatus
);
5789 write_fp_sreg(s
, rd
, tcg_single
);
5790 tcg_temp_free_i32(tcg_single
);
5793 case 3: /* float16 */
5794 tcg_single
= tcg_temp_new_i32();
5796 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
5797 tcg_shift
, tcg_fpstatus
);
5799 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
5800 tcg_shift
, tcg_fpstatus
);
5802 write_fp_sreg(s
, rd
, tcg_single
);
5803 tcg_temp_free_i32(tcg_single
);
5807 g_assert_not_reached();
5810 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5813 if (extract32(opcode
, 2, 1)) {
5814 /* There are too many rounding modes to all fit into rmode,
5815 * so FCVTA[US] is a special case.
5817 rmode
= FPROUNDING_TIEAWAY
;
5820 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5822 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5825 case 1: /* float64 */
5826 tcg_double
= read_fp_dreg(s
, rn
);
5829 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5830 tcg_shift
, tcg_fpstatus
);
5832 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5833 tcg_shift
, tcg_fpstatus
);
5837 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5838 tcg_shift
, tcg_fpstatus
);
5840 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5841 tcg_shift
, tcg_fpstatus
);
5845 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5847 tcg_temp_free_i64(tcg_double
);
5850 case 0: /* float32 */
5851 tcg_single
= read_fp_sreg(s
, rn
);
5854 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5855 tcg_shift
, tcg_fpstatus
);
5857 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5858 tcg_shift
, tcg_fpstatus
);
5861 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5863 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5864 tcg_shift
, tcg_fpstatus
);
5866 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5867 tcg_shift
, tcg_fpstatus
);
5869 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5870 tcg_temp_free_i32(tcg_dest
);
5872 tcg_temp_free_i32(tcg_single
);
5875 case 3: /* float16 */
5876 tcg_single
= read_fp_sreg(s
, rn
);
5879 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
5880 tcg_shift
, tcg_fpstatus
);
5882 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
5883 tcg_shift
, tcg_fpstatus
);
5886 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5888 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
5889 tcg_shift
, tcg_fpstatus
);
5891 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
5892 tcg_shift
, tcg_fpstatus
);
5894 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5895 tcg_temp_free_i32(tcg_dest
);
5897 tcg_temp_free_i32(tcg_single
);
5901 g_assert_not_reached();
5904 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5905 tcg_temp_free_i32(tcg_rmode
);
5908 tcg_temp_free_ptr(tcg_fpstatus
);
5909 tcg_temp_free_i32(tcg_shift
);
5912 /* Floating point <-> fixed point conversions
5913 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5914 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5915 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5916 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5918 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5920 int rd
= extract32(insn
, 0, 5);
5921 int rn
= extract32(insn
, 5, 5);
5922 int scale
= extract32(insn
, 10, 6);
5923 int opcode
= extract32(insn
, 16, 3);
5924 int rmode
= extract32(insn
, 19, 2);
5925 int type
= extract32(insn
, 22, 2);
5926 bool sbit
= extract32(insn
, 29, 1);
5927 bool sf
= extract32(insn
, 31, 1);
5930 if (sbit
|| (!sf
&& scale
< 32)) {
5931 unallocated_encoding(s
);
5936 case 0: /* float32 */
5937 case 1: /* float64 */
5939 case 3: /* float16 */
5940 if (dc_isar_feature(aa64_fp16
, s
)) {
5945 unallocated_encoding(s
);
5949 switch ((rmode
<< 3) | opcode
) {
5950 case 0x2: /* SCVTF */
5951 case 0x3: /* UCVTF */
5954 case 0x18: /* FCVTZS */
5955 case 0x19: /* FCVTZU */
5959 unallocated_encoding(s
);
5963 if (!fp_access_check(s
)) {
5967 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5970 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5972 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5973 * without conversion.
5977 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5983 tmp
= tcg_temp_new_i64();
5984 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5985 write_fp_dreg(s
, rd
, tmp
);
5986 tcg_temp_free_i64(tmp
);
5990 write_fp_dreg(s
, rd
, tcg_rn
);
5993 /* 64 bit to top half. */
5994 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5995 clear_vec_high(s
, true, rd
);
5999 tmp
= tcg_temp_new_i64();
6000 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6001 write_fp_dreg(s
, rd
, tmp
);
6002 tcg_temp_free_i64(tmp
);
6005 g_assert_not_reached();
6008 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6013 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6017 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6020 /* 64 bits from top half */
6021 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6025 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6028 g_assert_not_reached();
6033 /* Floating point <-> integer conversions
6034 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6035 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6036 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6037 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6039 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6041 int rd
= extract32(insn
, 0, 5);
6042 int rn
= extract32(insn
, 5, 5);
6043 int opcode
= extract32(insn
, 16, 3);
6044 int rmode
= extract32(insn
, 19, 2);
6045 int type
= extract32(insn
, 22, 2);
6046 bool sbit
= extract32(insn
, 29, 1);
6047 bool sf
= extract32(insn
, 31, 1);
6050 unallocated_encoding(s
);
6056 bool itof
= opcode
& 1;
6059 unallocated_encoding(s
);
6063 switch (sf
<< 3 | type
<< 1 | rmode
) {
6064 case 0x0: /* 32 bit */
6065 case 0xa: /* 64 bit */
6066 case 0xd: /* 64 bit to top half of quad */
6068 case 0x6: /* 16-bit float, 32-bit int */
6069 case 0xe: /* 16-bit float, 64-bit int */
6070 if (dc_isar_feature(aa64_fp16
, s
)) {
6075 /* all other sf/type/rmode combinations are invalid */
6076 unallocated_encoding(s
);
6080 if (!fp_access_check(s
)) {
6083 handle_fmov(s
, rd
, rn
, type
, itof
);
6085 /* actual FP conversions */
6086 bool itof
= extract32(opcode
, 1, 1);
6088 if (rmode
!= 0 && opcode
> 1) {
6089 unallocated_encoding(s
);
6093 case 0: /* float32 */
6094 case 1: /* float64 */
6096 case 3: /* float16 */
6097 if (dc_isar_feature(aa64_fp16
, s
)) {
6102 unallocated_encoding(s
);
6106 if (!fp_access_check(s
)) {
6109 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6113 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6114 * 31 30 29 28 25 24 0
6115 * +---+---+---+---------+-----------------------------+
6116 * | | 0 | | 1 1 1 1 | |
6117 * +---+---+---+---------+-----------------------------+
6119 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6121 if (extract32(insn
, 24, 1)) {
6122 /* Floating point data-processing (3 source) */
6123 disas_fp_3src(s
, insn
);
6124 } else if (extract32(insn
, 21, 1) == 0) {
6125 /* Floating point to fixed point conversions */
6126 disas_fp_fixed_conv(s
, insn
);
6128 switch (extract32(insn
, 10, 2)) {
6130 /* Floating point conditional compare */
6131 disas_fp_ccomp(s
, insn
);
6134 /* Floating point data-processing (2 source) */
6135 disas_fp_2src(s
, insn
);
6138 /* Floating point conditional select */
6139 disas_fp_csel(s
, insn
);
6142 switch (ctz32(extract32(insn
, 12, 4))) {
6143 case 0: /* [15:12] == xxx1 */
6144 /* Floating point immediate */
6145 disas_fp_imm(s
, insn
);
6147 case 1: /* [15:12] == xx10 */
6148 /* Floating point compare */
6149 disas_fp_compare(s
, insn
);
6151 case 2: /* [15:12] == x100 */
6152 /* Floating point data-processing (1 source) */
6153 disas_fp_1src(s
, insn
);
6155 case 3: /* [15:12] == 1000 */
6156 unallocated_encoding(s
);
6158 default: /* [15:12] == 0000 */
6159 /* Floating point <-> integer conversions */
6160 disas_fp_int_conv(s
, insn
);
6168 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6171 /* Extract 64 bits from the middle of two concatenated 64 bit
6172 * vector register slices left:right. The extracted bits start
6173 * at 'pos' bits into the right (least significant) side.
6174 * We return the result in tcg_right, and guarantee not to
6177 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6178 assert(pos
> 0 && pos
< 64);
6180 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6181 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6182 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6184 tcg_temp_free_i64(tcg_tmp
);
6188 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6189 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6190 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6191 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6193 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6195 int is_q
= extract32(insn
, 30, 1);
6196 int op2
= extract32(insn
, 22, 2);
6197 int imm4
= extract32(insn
, 11, 4);
6198 int rm
= extract32(insn
, 16, 5);
6199 int rn
= extract32(insn
, 5, 5);
6200 int rd
= extract32(insn
, 0, 5);
6201 int pos
= imm4
<< 3;
6202 TCGv_i64 tcg_resl
, tcg_resh
;
6204 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6205 unallocated_encoding(s
);
6209 if (!fp_access_check(s
)) {
6213 tcg_resh
= tcg_temp_new_i64();
6214 tcg_resl
= tcg_temp_new_i64();
6216 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6217 * either extracting 128 bits from a 128:128 concatenation, or
6218 * extracting 64 bits from a 64:64 concatenation.
6221 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6223 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6224 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6226 tcg_gen_movi_i64(tcg_resh
, 0);
6233 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6234 EltPosns
*elt
= eltposns
;
6241 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6243 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6246 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6247 tcg_hh
= tcg_temp_new_i64();
6248 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6249 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6250 tcg_temp_free_i64(tcg_hh
);
6254 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6255 tcg_temp_free_i64(tcg_resl
);
6256 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6257 tcg_temp_free_i64(tcg_resh
);
6261 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6262 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6263 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6264 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6266 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6268 int op2
= extract32(insn
, 22, 2);
6269 int is_q
= extract32(insn
, 30, 1);
6270 int rm
= extract32(insn
, 16, 5);
6271 int rn
= extract32(insn
, 5, 5);
6272 int rd
= extract32(insn
, 0, 5);
6273 int is_tblx
= extract32(insn
, 12, 1);
6274 int len
= extract32(insn
, 13, 2);
6275 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6276 TCGv_i32 tcg_regno
, tcg_numregs
;
6279 unallocated_encoding(s
);
6283 if (!fp_access_check(s
)) {
6287 /* This does a table lookup: for every byte element in the input
6288 * we index into a table formed from up to four vector registers,
6289 * and then the output is the result of the lookups. Our helper
6290 * function does the lookup operation for a single 64 bit part of
6293 tcg_resl
= tcg_temp_new_i64();
6294 tcg_resh
= tcg_temp_new_i64();
6297 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6299 tcg_gen_movi_i64(tcg_resl
, 0);
6301 if (is_tblx
&& is_q
) {
6302 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6304 tcg_gen_movi_i64(tcg_resh
, 0);
6307 tcg_idx
= tcg_temp_new_i64();
6308 tcg_regno
= tcg_const_i32(rn
);
6309 tcg_numregs
= tcg_const_i32(len
+ 1);
6310 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6311 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6312 tcg_regno
, tcg_numregs
);
6314 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6315 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6316 tcg_regno
, tcg_numregs
);
6318 tcg_temp_free_i64(tcg_idx
);
6319 tcg_temp_free_i32(tcg_regno
);
6320 tcg_temp_free_i32(tcg_numregs
);
6322 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6323 tcg_temp_free_i64(tcg_resl
);
6324 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6325 tcg_temp_free_i64(tcg_resh
);
6329 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6330 * +---+---+-------------+------+---+------+---+------------------+------+
6331 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6332 * +---+---+-------------+------+---+------+---+------------------+------+
6334 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6336 int rd
= extract32(insn
, 0, 5);
6337 int rn
= extract32(insn
, 5, 5);
6338 int rm
= extract32(insn
, 16, 5);
6339 int size
= extract32(insn
, 22, 2);
6340 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6341 * bit 2 indicates 1 vs 2 variant of the insn.
6343 int opcode
= extract32(insn
, 12, 2);
6344 bool part
= extract32(insn
, 14, 1);
6345 bool is_q
= extract32(insn
, 30, 1);
6346 int esize
= 8 << size
;
6348 int datasize
= is_q
? 128 : 64;
6349 int elements
= datasize
/ esize
;
6350 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6352 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6353 unallocated_encoding(s
);
6357 if (!fp_access_check(s
)) {
6361 tcg_resl
= tcg_const_i64(0);
6362 tcg_resh
= tcg_const_i64(0);
6363 tcg_res
= tcg_temp_new_i64();
6365 for (i
= 0; i
< elements
; i
++) {
6367 case 1: /* UZP1/2 */
6369 int midpoint
= elements
/ 2;
6371 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6373 read_vec_element(s
, tcg_res
, rm
,
6374 2 * (i
- midpoint
) + part
, size
);
6378 case 2: /* TRN1/2 */
6380 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6382 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6385 case 3: /* ZIP1/2 */
6387 int base
= part
* elements
/ 2;
6389 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6391 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6396 g_assert_not_reached();
6401 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6402 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6404 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6405 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6409 tcg_temp_free_i64(tcg_res
);
6411 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6412 tcg_temp_free_i64(tcg_resl
);
6413 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6414 tcg_temp_free_i64(tcg_resh
);
6418 * do_reduction_op helper
6420 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6421 * important for correct NaN propagation that we do these
6422 * operations in exactly the order specified by the pseudocode.
6424 * This is a recursive function, TCG temps should be freed by the
6425 * calling function once it is done with the values.
6427 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6428 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6430 if (esize
== size
) {
6432 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6435 /* We should have one register left here */
6436 assert(ctpop8(vmap
) == 1);
6437 element
= ctz32(vmap
);
6438 assert(element
< 8);
6440 tcg_elem
= tcg_temp_new_i32();
6441 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6444 int bits
= size
/ 2;
6445 int shift
= ctpop8(vmap
) / 2;
6446 int vmap_lo
= (vmap
>> shift
) & vmap
;
6447 int vmap_hi
= (vmap
& ~vmap_lo
);
6448 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6450 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6451 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6452 tcg_res
= tcg_temp_new_i32();
6455 case 0x0c: /* fmaxnmv half-precision */
6456 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6458 case 0x0f: /* fmaxv half-precision */
6459 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6461 case 0x1c: /* fminnmv half-precision */
6462 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6464 case 0x1f: /* fminv half-precision */
6465 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6467 case 0x2c: /* fmaxnmv */
6468 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6470 case 0x2f: /* fmaxv */
6471 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6473 case 0x3c: /* fminnmv */
6474 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6476 case 0x3f: /* fminv */
6477 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6480 g_assert_not_reached();
6483 tcg_temp_free_i32(tcg_hi
);
6484 tcg_temp_free_i32(tcg_lo
);
6489 /* AdvSIMD across lanes
6490 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6491 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6492 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6493 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6495 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
6497 int rd
= extract32(insn
, 0, 5);
6498 int rn
= extract32(insn
, 5, 5);
6499 int size
= extract32(insn
, 22, 2);
6500 int opcode
= extract32(insn
, 12, 5);
6501 bool is_q
= extract32(insn
, 30, 1);
6502 bool is_u
= extract32(insn
, 29, 1);
6504 bool is_min
= false;
6508 TCGv_i64 tcg_res
, tcg_elt
;
6511 case 0x1b: /* ADDV */
6513 unallocated_encoding(s
);
6517 case 0x3: /* SADDLV, UADDLV */
6518 case 0xa: /* SMAXV, UMAXV */
6519 case 0x1a: /* SMINV, UMINV */
6520 if (size
== 3 || (size
== 2 && !is_q
)) {
6521 unallocated_encoding(s
);
6525 case 0xc: /* FMAXNMV, FMINNMV */
6526 case 0xf: /* FMAXV, FMINV */
6527 /* Bit 1 of size field encodes min vs max and the actual size
6528 * depends on the encoding of the U bit. If not set (and FP16
6529 * enabled) then we do half-precision float instead of single
6532 is_min
= extract32(size
, 1, 1);
6534 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
6536 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
6537 unallocated_encoding(s
);
6544 unallocated_encoding(s
);
6548 if (!fp_access_check(s
)) {
6553 elements
= (is_q
? 128 : 64) / esize
;
6555 tcg_res
= tcg_temp_new_i64();
6556 tcg_elt
= tcg_temp_new_i64();
6558 /* These instructions operate across all lanes of a vector
6559 * to produce a single result. We can guarantee that a 64
6560 * bit intermediate is sufficient:
6561 * + for [US]ADDLV the maximum element size is 32 bits, and
6562 * the result type is 64 bits
6563 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
6564 * same as the element size, which is 32 bits at most
6565 * For the integer operations we can choose to work at 64
6566 * or 32 bits and truncate at the end; for simplicity
6567 * we use 64 bits always. The floating point
6568 * ops do require 32 bit intermediates, though.
6571 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
6573 for (i
= 1; i
< elements
; i
++) {
6574 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
6577 case 0x03: /* SADDLV / UADDLV */
6578 case 0x1b: /* ADDV */
6579 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
6581 case 0x0a: /* SMAXV / UMAXV */
6583 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
6585 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
6588 case 0x1a: /* SMINV / UMINV */
6590 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
6592 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
6596 g_assert_not_reached();
6601 /* Floating point vector reduction ops which work across 32
6602 * bit (single) or 16 bit (half-precision) intermediates.
6603 * Note that correct NaN propagation requires that we do these
6604 * operations in exactly the order specified by the pseudocode.
6606 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
6607 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
6608 int vmap
= (1 << elements
) - 1;
6609 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
6610 (is_q
? 128 : 64), vmap
, fpst
);
6611 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
6612 tcg_temp_free_i32(tcg_res32
);
6613 tcg_temp_free_ptr(fpst
);
6616 tcg_temp_free_i64(tcg_elt
);
6618 /* Now truncate the result to the width required for the final output */
6619 if (opcode
== 0x03) {
6620 /* SADDLV, UADDLV: result is 2*esize */
6626 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
6629 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
6632 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6637 g_assert_not_reached();
6640 write_fp_dreg(s
, rd
, tcg_res
);
6641 tcg_temp_free_i64(tcg_res
);
6644 /* DUP (Element, Vector)
6646 * 31 30 29 21 20 16 15 10 9 5 4 0
6647 * +---+---+-------------------+--------+-------------+------+------+
6648 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6649 * +---+---+-------------------+--------+-------------+------+------+
6651 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6653 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
6656 int size
= ctz32(imm5
);
6657 int index
= imm5
>> (size
+ 1);
6659 if (size
> 3 || (size
== 3 && !is_q
)) {
6660 unallocated_encoding(s
);
6664 if (!fp_access_check(s
)) {
6668 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
6669 vec_reg_offset(s
, rn
, index
, size
),
6670 is_q
? 16 : 8, vec_full_reg_size(s
));
6673 /* DUP (element, scalar)
6674 * 31 21 20 16 15 10 9 5 4 0
6675 * +-----------------------+--------+-------------+------+------+
6676 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6677 * +-----------------------+--------+-------------+------+------+
6679 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
6682 int size
= ctz32(imm5
);
6687 unallocated_encoding(s
);
6691 if (!fp_access_check(s
)) {
6695 index
= imm5
>> (size
+ 1);
6697 /* This instruction just extracts the specified element and
6698 * zero-extends it into the bottom of the destination register.
6700 tmp
= tcg_temp_new_i64();
6701 read_vec_element(s
, tmp
, rn
, index
, size
);
6702 write_fp_dreg(s
, rd
, tmp
);
6703 tcg_temp_free_i64(tmp
);
6708 * 31 30 29 21 20 16 15 10 9 5 4 0
6709 * +---+---+-------------------+--------+-------------+------+------+
6710 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
6711 * +---+---+-------------------+--------+-------------+------+------+
6713 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6715 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
6718 int size
= ctz32(imm5
);
6719 uint32_t dofs
, oprsz
, maxsz
;
6721 if (size
> 3 || ((size
== 3) && !is_q
)) {
6722 unallocated_encoding(s
);
6726 if (!fp_access_check(s
)) {
6730 dofs
= vec_full_reg_offset(s
, rd
);
6731 oprsz
= is_q
? 16 : 8;
6732 maxsz
= vec_full_reg_size(s
);
6734 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
6739 * 31 21 20 16 15 14 11 10 9 5 4 0
6740 * +-----------------------+--------+------------+---+------+------+
6741 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6742 * +-----------------------+--------+------------+---+------+------+
6744 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6745 * index: encoded in imm5<4:size+1>
6747 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
6750 int size
= ctz32(imm5
);
6751 int src_index
, dst_index
;
6755 unallocated_encoding(s
);
6759 if (!fp_access_check(s
)) {
6763 dst_index
= extract32(imm5
, 1+size
, 5);
6764 src_index
= extract32(imm4
, size
, 4);
6766 tmp
= tcg_temp_new_i64();
6768 read_vec_element(s
, tmp
, rn
, src_index
, size
);
6769 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
6771 tcg_temp_free_i64(tmp
);
6777 * 31 21 20 16 15 10 9 5 4 0
6778 * +-----------------------+--------+-------------+------+------+
6779 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
6780 * +-----------------------+--------+-------------+------+------+
6782 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6783 * index: encoded in imm5<4:size+1>
6785 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
6787 int size
= ctz32(imm5
);
6791 unallocated_encoding(s
);
6795 if (!fp_access_check(s
)) {
6799 idx
= extract32(imm5
, 1 + size
, 4 - size
);
6800 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
6807 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6808 * +---+---+-------------------+--------+-------------+------+------+
6809 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6810 * +---+---+-------------------+--------+-------------+------+------+
6812 * U: unsigned when set
6813 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6815 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6816 int rn
, int rd
, int imm5
)
6818 int size
= ctz32(imm5
);
6822 /* Check for UnallocatedEncodings */
6824 if (size
> 2 || (size
== 2 && !is_q
)) {
6825 unallocated_encoding(s
);
6830 || (size
< 3 && is_q
)
6831 || (size
== 3 && !is_q
)) {
6832 unallocated_encoding(s
);
6837 if (!fp_access_check(s
)) {
6841 element
= extract32(imm5
, 1+size
, 4);
6843 tcg_rd
= cpu_reg(s
, rd
);
6844 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6845 if (is_signed
&& !is_q
) {
6846 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6851 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6852 * +---+---+----+-----------------+------+---+------+---+------+------+
6853 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6854 * +---+---+----+-----------------+------+---+------+---+------+------+
6856 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6858 int rd
= extract32(insn
, 0, 5);
6859 int rn
= extract32(insn
, 5, 5);
6860 int imm4
= extract32(insn
, 11, 4);
6861 int op
= extract32(insn
, 29, 1);
6862 int is_q
= extract32(insn
, 30, 1);
6863 int imm5
= extract32(insn
, 16, 5);
6868 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6870 unallocated_encoding(s
);
6875 /* DUP (element - vector) */
6876 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6880 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6885 handle_simd_insg(s
, rd
, rn
, imm5
);
6887 unallocated_encoding(s
);
6892 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6893 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6896 unallocated_encoding(s
);
6902 /* AdvSIMD modified immediate
6903 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6904 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6905 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6906 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6908 * There are a number of operations that can be carried out here:
6909 * MOVI - move (shifted) imm into register
6910 * MVNI - move inverted (shifted) imm into register
6911 * ORR - bitwise OR of (shifted) imm with register
6912 * BIC - bitwise clear of (shifted) imm with register
6913 * With ARMv8.2 we also have:
6914 * FMOV half-precision
6916 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6918 int rd
= extract32(insn
, 0, 5);
6919 int cmode
= extract32(insn
, 12, 4);
6920 int cmode_3_1
= extract32(cmode
, 1, 3);
6921 int cmode_0
= extract32(cmode
, 0, 1);
6922 int o2
= extract32(insn
, 11, 1);
6923 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6924 bool is_neg
= extract32(insn
, 29, 1);
6925 bool is_q
= extract32(insn
, 30, 1);
6928 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6929 /* Check for FMOV (vector, immediate) - half-precision */
6930 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
6931 unallocated_encoding(s
);
6936 if (!fp_access_check(s
)) {
6940 /* See AdvSIMDExpandImm() in ARM ARM */
6941 switch (cmode_3_1
) {
6942 case 0: /* Replicate(Zeros(24):imm8, 2) */
6943 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6944 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6945 case 3: /* Replicate(imm8:Zeros(24), 2) */
6947 int shift
= cmode_3_1
* 8;
6948 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6951 case 4: /* Replicate(Zeros(8):imm8, 4) */
6952 case 5: /* Replicate(imm8:Zeros(8), 4) */
6954 int shift
= (cmode_3_1
& 0x1) * 8;
6955 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6960 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6961 imm
= (abcdefgh
<< 16) | 0xffff;
6963 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6964 imm
= (abcdefgh
<< 8) | 0xff;
6966 imm
= bitfield_replicate(imm
, 32);
6969 if (!cmode_0
&& !is_neg
) {
6970 imm
= bitfield_replicate(abcdefgh
, 8);
6971 } else if (!cmode_0
&& is_neg
) {
6974 for (i
= 0; i
< 8; i
++) {
6975 if ((abcdefgh
) & (1 << i
)) {
6976 imm
|= 0xffULL
<< (i
* 8);
6979 } else if (cmode_0
) {
6981 imm
= (abcdefgh
& 0x3f) << 48;
6982 if (abcdefgh
& 0x80) {
6983 imm
|= 0x8000000000000000ULL
;
6985 if (abcdefgh
& 0x40) {
6986 imm
|= 0x3fc0000000000000ULL
;
6988 imm
|= 0x4000000000000000ULL
;
6992 /* FMOV (vector, immediate) - half-precision */
6993 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
6994 /* now duplicate across the lanes */
6995 imm
= bitfield_replicate(imm
, 16);
6997 imm
= (abcdefgh
& 0x3f) << 19;
6998 if (abcdefgh
& 0x80) {
7001 if (abcdefgh
& 0x40) {
7012 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7013 g_assert_not_reached();
7016 if (cmode_3_1
!= 7 && is_neg
) {
7020 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7021 /* MOVI or MVNI, with MVNI negation handled above. */
7022 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7023 vec_full_reg_size(s
), imm
);
7025 /* ORR or BIC, with BIC negation to AND handled above. */
7027 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7029 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7034 /* AdvSIMD scalar copy
7035 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7036 * +-----+----+-----------------+------+---+------+---+------+------+
7037 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7038 * +-----+----+-----------------+------+---+------+---+------+------+
7040 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7042 int rd
= extract32(insn
, 0, 5);
7043 int rn
= extract32(insn
, 5, 5);
7044 int imm4
= extract32(insn
, 11, 4);
7045 int imm5
= extract32(insn
, 16, 5);
7046 int op
= extract32(insn
, 29, 1);
7048 if (op
!= 0 || imm4
!= 0) {
7049 unallocated_encoding(s
);
7053 /* DUP (element, scalar) */
7054 handle_simd_dupes(s
, rd
, rn
, imm5
);
7057 /* AdvSIMD scalar pairwise
7058 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7059 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7060 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7061 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7063 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7065 int u
= extract32(insn
, 29, 1);
7066 int size
= extract32(insn
, 22, 2);
7067 int opcode
= extract32(insn
, 12, 5);
7068 int rn
= extract32(insn
, 5, 5);
7069 int rd
= extract32(insn
, 0, 5);
7072 /* For some ops (the FP ones), size[1] is part of the encoding.
7073 * For ADDP strictly it is not but size[1] is always 1 for valid
7076 opcode
|= (extract32(size
, 1, 1) << 5);
7079 case 0x3b: /* ADDP */
7080 if (u
|| size
!= 3) {
7081 unallocated_encoding(s
);
7084 if (!fp_access_check(s
)) {
7090 case 0xc: /* FMAXNMP */
7091 case 0xd: /* FADDP */
7092 case 0xf: /* FMAXP */
7093 case 0x2c: /* FMINNMP */
7094 case 0x2f: /* FMINP */
7095 /* FP op, size[0] is 32 or 64 bit*/
7097 if (!dc_isar_feature(aa64_fp16
, s
)) {
7098 unallocated_encoding(s
);
7104 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7107 if (!fp_access_check(s
)) {
7111 fpst
= get_fpstatus_ptr(size
== MO_16
);
7114 unallocated_encoding(s
);
7118 if (size
== MO_64
) {
7119 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7120 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7121 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7123 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7124 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7127 case 0x3b: /* ADDP */
7128 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7130 case 0xc: /* FMAXNMP */
7131 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7133 case 0xd: /* FADDP */
7134 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7136 case 0xf: /* FMAXP */
7137 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7139 case 0x2c: /* FMINNMP */
7140 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7142 case 0x2f: /* FMINP */
7143 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7146 g_assert_not_reached();
7149 write_fp_dreg(s
, rd
, tcg_res
);
7151 tcg_temp_free_i64(tcg_op1
);
7152 tcg_temp_free_i64(tcg_op2
);
7153 tcg_temp_free_i64(tcg_res
);
7155 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7156 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7157 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7159 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7160 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7162 if (size
== MO_16
) {
7164 case 0xc: /* FMAXNMP */
7165 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7167 case 0xd: /* FADDP */
7168 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7170 case 0xf: /* FMAXP */
7171 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7173 case 0x2c: /* FMINNMP */
7174 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7176 case 0x2f: /* FMINP */
7177 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7180 g_assert_not_reached();
7184 case 0xc: /* FMAXNMP */
7185 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7187 case 0xd: /* FADDP */
7188 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7190 case 0xf: /* FMAXP */
7191 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7193 case 0x2c: /* FMINNMP */
7194 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7196 case 0x2f: /* FMINP */
7197 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7200 g_assert_not_reached();
7204 write_fp_sreg(s
, rd
, tcg_res
);
7206 tcg_temp_free_i32(tcg_op1
);
7207 tcg_temp_free_i32(tcg_op2
);
7208 tcg_temp_free_i32(tcg_res
);
7212 tcg_temp_free_ptr(fpst
);
7217 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7219 * This code is handles the common shifting code and is used by both
7220 * the vector and scalar code.
7222 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7223 TCGv_i64 tcg_rnd
, bool accumulate
,
7224 bool is_u
, int size
, int shift
)
7226 bool extended_result
= false;
7227 bool round
= tcg_rnd
!= NULL
;
7229 TCGv_i64 tcg_src_hi
;
7231 if (round
&& size
== 3) {
7232 extended_result
= true;
7233 ext_lshift
= 64 - shift
;
7234 tcg_src_hi
= tcg_temp_new_i64();
7235 } else if (shift
== 64) {
7236 if (!accumulate
&& is_u
) {
7237 /* result is zero */
7238 tcg_gen_movi_i64(tcg_res
, 0);
7243 /* Deal with the rounding step */
7245 if (extended_result
) {
7246 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7248 /* take care of sign extending tcg_res */
7249 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7250 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7251 tcg_src
, tcg_src_hi
,
7254 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7258 tcg_temp_free_i64(tcg_zero
);
7260 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7264 /* Now do the shift right */
7265 if (round
&& extended_result
) {
7266 /* extended case, >64 bit precision required */
7267 if (ext_lshift
== 0) {
7268 /* special case, only high bits matter */
7269 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7271 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7272 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7273 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7278 /* essentially shifting in 64 zeros */
7279 tcg_gen_movi_i64(tcg_src
, 0);
7281 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7285 /* effectively extending the sign-bit */
7286 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7288 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7294 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7296 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7299 if (extended_result
) {
7300 tcg_temp_free_i64(tcg_src_hi
);
7304 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7305 static void handle_scalar_simd_shri(DisasContext
*s
,
7306 bool is_u
, int immh
, int immb
,
7307 int opcode
, int rn
, int rd
)
7310 int immhb
= immh
<< 3 | immb
;
7311 int shift
= 2 * (8 << size
) - immhb
;
7312 bool accumulate
= false;
7314 bool insert
= false;
7319 if (!extract32(immh
, 3, 1)) {
7320 unallocated_encoding(s
);
7324 if (!fp_access_check(s
)) {
7329 case 0x02: /* SSRA / USRA (accumulate) */
7332 case 0x04: /* SRSHR / URSHR (rounding) */
7335 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7336 accumulate
= round
= true;
7338 case 0x08: /* SRI */
7344 uint64_t round_const
= 1ULL << (shift
- 1);
7345 tcg_round
= tcg_const_i64(round_const
);
7350 tcg_rn
= read_fp_dreg(s
, rn
);
7351 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7354 /* shift count same as element size is valid but does nothing;
7355 * special case to avoid potential shift by 64.
7357 int esize
= 8 << size
;
7358 if (shift
!= esize
) {
7359 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7360 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7363 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7364 accumulate
, is_u
, size
, shift
);
7367 write_fp_dreg(s
, rd
, tcg_rd
);
7369 tcg_temp_free_i64(tcg_rn
);
7370 tcg_temp_free_i64(tcg_rd
);
7372 tcg_temp_free_i64(tcg_round
);
7376 /* SHL/SLI - Scalar shift left */
7377 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7378 int immh
, int immb
, int opcode
,
7381 int size
= 32 - clz32(immh
) - 1;
7382 int immhb
= immh
<< 3 | immb
;
7383 int shift
= immhb
- (8 << size
);
7384 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7385 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7387 if (!extract32(immh
, 3, 1)) {
7388 unallocated_encoding(s
);
7392 if (!fp_access_check(s
)) {
7396 tcg_rn
= read_fp_dreg(s
, rn
);
7397 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7400 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7402 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7405 write_fp_dreg(s
, rd
, tcg_rd
);
7407 tcg_temp_free_i64(tcg_rn
);
7408 tcg_temp_free_i64(tcg_rd
);
7411 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7412 * (signed/unsigned) narrowing */
7413 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7414 bool is_u_shift
, bool is_u_narrow
,
7415 int immh
, int immb
, int opcode
,
7418 int immhb
= immh
<< 3 | immb
;
7419 int size
= 32 - clz32(immh
) - 1;
7420 int esize
= 8 << size
;
7421 int shift
= (2 * esize
) - immhb
;
7422 int elements
= is_scalar
? 1 : (64 / esize
);
7423 bool round
= extract32(opcode
, 0, 1);
7424 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7425 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7426 TCGv_i32 tcg_rd_narrowed
;
7429 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7430 { gen_helper_neon_narrow_sat_s8
,
7431 gen_helper_neon_unarrow_sat8
},
7432 { gen_helper_neon_narrow_sat_s16
,
7433 gen_helper_neon_unarrow_sat16
},
7434 { gen_helper_neon_narrow_sat_s32
,
7435 gen_helper_neon_unarrow_sat32
},
7438 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7439 gen_helper_neon_narrow_sat_u8
,
7440 gen_helper_neon_narrow_sat_u16
,
7441 gen_helper_neon_narrow_sat_u32
,
7444 NeonGenNarrowEnvFn
*narrowfn
;
7450 if (extract32(immh
, 3, 1)) {
7451 unallocated_encoding(s
);
7455 if (!fp_access_check(s
)) {
7460 narrowfn
= unsigned_narrow_fns
[size
];
7462 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
7465 tcg_rn
= tcg_temp_new_i64();
7466 tcg_rd
= tcg_temp_new_i64();
7467 tcg_rd_narrowed
= tcg_temp_new_i32();
7468 tcg_final
= tcg_const_i64(0);
7471 uint64_t round_const
= 1ULL << (shift
- 1);
7472 tcg_round
= tcg_const_i64(round_const
);
7477 for (i
= 0; i
< elements
; i
++) {
7478 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
7479 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7480 false, is_u_shift
, size
+1, shift
);
7481 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
7482 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
7483 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7487 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7489 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7493 tcg_temp_free_i64(tcg_round
);
7495 tcg_temp_free_i64(tcg_rn
);
7496 tcg_temp_free_i64(tcg_rd
);
7497 tcg_temp_free_i32(tcg_rd_narrowed
);
7498 tcg_temp_free_i64(tcg_final
);
7500 clear_vec_high(s
, is_q
, rd
);
7503 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
7504 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
7505 bool src_unsigned
, bool dst_unsigned
,
7506 int immh
, int immb
, int rn
, int rd
)
7508 int immhb
= immh
<< 3 | immb
;
7509 int size
= 32 - clz32(immh
) - 1;
7510 int shift
= immhb
- (8 << size
);
7514 assert(!(scalar
&& is_q
));
7517 if (!is_q
&& extract32(immh
, 3, 1)) {
7518 unallocated_encoding(s
);
7522 /* Since we use the variable-shift helpers we must
7523 * replicate the shift count into each element of
7524 * the tcg_shift value.
7528 shift
|= shift
<< 8;
7531 shift
|= shift
<< 16;
7537 g_assert_not_reached();
7541 if (!fp_access_check(s
)) {
7546 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
7547 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
7548 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
7549 { NULL
, gen_helper_neon_qshl_u64
},
7551 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
7552 int maxpass
= is_q
? 2 : 1;
7554 for (pass
= 0; pass
< maxpass
; pass
++) {
7555 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7557 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7558 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7559 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7561 tcg_temp_free_i64(tcg_op
);
7563 tcg_temp_free_i64(tcg_shift
);
7564 clear_vec_high(s
, is_q
, rd
);
7566 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
7567 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
7569 { gen_helper_neon_qshl_s8
,
7570 gen_helper_neon_qshl_s16
,
7571 gen_helper_neon_qshl_s32
},
7572 { gen_helper_neon_qshlu_s8
,
7573 gen_helper_neon_qshlu_s16
,
7574 gen_helper_neon_qshlu_s32
}
7576 { NULL
, NULL
, NULL
},
7577 { gen_helper_neon_qshl_u8
,
7578 gen_helper_neon_qshl_u16
,
7579 gen_helper_neon_qshl_u32
}
7582 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
7583 TCGMemOp memop
= scalar
? size
: MO_32
;
7584 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
7586 for (pass
= 0; pass
< maxpass
; pass
++) {
7587 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7589 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
7590 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7594 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
7597 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
7602 g_assert_not_reached();
7604 write_fp_sreg(s
, rd
, tcg_op
);
7606 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
7609 tcg_temp_free_i32(tcg_op
);
7611 tcg_temp_free_i32(tcg_shift
);
7614 clear_vec_high(s
, is_q
, rd
);
7619 /* Common vector code for handling integer to FP conversion */
7620 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
7621 int elements
, int is_signed
,
7622 int fracbits
, int size
)
7624 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
7625 TCGv_i32 tcg_shift
= NULL
;
7627 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
7630 if (fracbits
|| size
== MO_64
) {
7631 tcg_shift
= tcg_const_i32(fracbits
);
7634 if (size
== MO_64
) {
7635 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
7636 TCGv_i64 tcg_double
= tcg_temp_new_i64();
7638 for (pass
= 0; pass
< elements
; pass
++) {
7639 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
7642 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
7643 tcg_shift
, tcg_fpst
);
7645 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
7646 tcg_shift
, tcg_fpst
);
7648 if (elements
== 1) {
7649 write_fp_dreg(s
, rd
, tcg_double
);
7651 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
7655 tcg_temp_free_i64(tcg_int64
);
7656 tcg_temp_free_i64(tcg_double
);
7659 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
7660 TCGv_i32 tcg_float
= tcg_temp_new_i32();
7662 for (pass
= 0; pass
< elements
; pass
++) {
7663 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
7669 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
7670 tcg_shift
, tcg_fpst
);
7672 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
7673 tcg_shift
, tcg_fpst
);
7677 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
7679 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
7686 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
7687 tcg_shift
, tcg_fpst
);
7689 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
7690 tcg_shift
, tcg_fpst
);
7694 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7696 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7701 g_assert_not_reached();
7704 if (elements
== 1) {
7705 write_fp_sreg(s
, rd
, tcg_float
);
7707 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
7711 tcg_temp_free_i32(tcg_int32
);
7712 tcg_temp_free_i32(tcg_float
);
7715 tcg_temp_free_ptr(tcg_fpst
);
7717 tcg_temp_free_i32(tcg_shift
);
7720 clear_vec_high(s
, elements
<< size
== 16, rd
);
7723 /* UCVTF/SCVTF - Integer to FP conversion */
7724 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
7725 bool is_q
, bool is_u
,
7726 int immh
, int immb
, int opcode
,
7729 int size
, elements
, fracbits
;
7730 int immhb
= immh
<< 3 | immb
;
7734 if (!is_scalar
&& !is_q
) {
7735 unallocated_encoding(s
);
7738 } else if (immh
& 4) {
7740 } else if (immh
& 2) {
7742 if (!dc_isar_feature(aa64_fp16
, s
)) {
7743 unallocated_encoding(s
);
7747 /* immh == 0 would be a failure of the decode logic */
7748 g_assert(immh
== 1);
7749 unallocated_encoding(s
);
7756 elements
= (8 << is_q
) >> size
;
7758 fracbits
= (16 << size
) - immhb
;
7760 if (!fp_access_check(s
)) {
7764 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
7767 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
7768 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
7769 bool is_q
, bool is_u
,
7770 int immh
, int immb
, int rn
, int rd
)
7772 int immhb
= immh
<< 3 | immb
;
7773 int pass
, size
, fracbits
;
7774 TCGv_ptr tcg_fpstatus
;
7775 TCGv_i32 tcg_rmode
, tcg_shift
;
7779 if (!is_scalar
&& !is_q
) {
7780 unallocated_encoding(s
);
7783 } else if (immh
& 0x4) {
7785 } else if (immh
& 0x2) {
7787 if (!dc_isar_feature(aa64_fp16
, s
)) {
7788 unallocated_encoding(s
);
7792 /* Should have split out AdvSIMD modified immediate earlier. */
7794 unallocated_encoding(s
);
7798 if (!fp_access_check(s
)) {
7802 assert(!(is_scalar
&& is_q
));
7804 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
7805 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
7806 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7807 fracbits
= (16 << size
) - immhb
;
7808 tcg_shift
= tcg_const_i32(fracbits
);
7810 if (size
== MO_64
) {
7811 int maxpass
= is_scalar
? 1 : 2;
7813 for (pass
= 0; pass
< maxpass
; pass
++) {
7814 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7816 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7818 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7820 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7822 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7823 tcg_temp_free_i64(tcg_op
);
7825 clear_vec_high(s
, is_q
, rd
);
7827 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
7828 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
7833 fn
= gen_helper_vfp_touhh
;
7835 fn
= gen_helper_vfp_toshh
;
7840 fn
= gen_helper_vfp_touls
;
7842 fn
= gen_helper_vfp_tosls
;
7846 g_assert_not_reached();
7849 for (pass
= 0; pass
< maxpass
; pass
++) {
7850 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7852 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
7853 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7855 write_fp_sreg(s
, rd
, tcg_op
);
7857 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
7859 tcg_temp_free_i32(tcg_op
);
7862 clear_vec_high(s
, is_q
, rd
);
7866 tcg_temp_free_ptr(tcg_fpstatus
);
7867 tcg_temp_free_i32(tcg_shift
);
7868 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7869 tcg_temp_free_i32(tcg_rmode
);
7872 /* AdvSIMD scalar shift by immediate
7873 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7874 * +-----+---+-------------+------+------+--------+---+------+------+
7875 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7876 * +-----+---+-------------+------+------+--------+---+------+------+
7878 * This is the scalar version so it works on a fixed sized registers
7880 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
7882 int rd
= extract32(insn
, 0, 5);
7883 int rn
= extract32(insn
, 5, 5);
7884 int opcode
= extract32(insn
, 11, 5);
7885 int immb
= extract32(insn
, 16, 3);
7886 int immh
= extract32(insn
, 19, 4);
7887 bool is_u
= extract32(insn
, 29, 1);
7890 unallocated_encoding(s
);
7895 case 0x08: /* SRI */
7897 unallocated_encoding(s
);
7901 case 0x00: /* SSHR / USHR */
7902 case 0x02: /* SSRA / USRA */
7903 case 0x04: /* SRSHR / URSHR */
7904 case 0x06: /* SRSRA / URSRA */
7905 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7907 case 0x0a: /* SHL / SLI */
7908 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7910 case 0x1c: /* SCVTF, UCVTF */
7911 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7914 case 0x10: /* SQSHRUN, SQSHRUN2 */
7915 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7917 unallocated_encoding(s
);
7920 handle_vec_simd_sqshrn(s
, true, false, false, true,
7921 immh
, immb
, opcode
, rn
, rd
);
7923 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7924 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7925 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7926 immh
, immb
, opcode
, rn
, rd
);
7928 case 0xc: /* SQSHLU */
7930 unallocated_encoding(s
);
7933 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7935 case 0xe: /* SQSHL, UQSHL */
7936 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7938 case 0x1f: /* FCVTZS, FCVTZU */
7939 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7942 unallocated_encoding(s
);
7947 /* AdvSIMD scalar three different
7948 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7949 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7950 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7951 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7953 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7955 bool is_u
= extract32(insn
, 29, 1);
7956 int size
= extract32(insn
, 22, 2);
7957 int opcode
= extract32(insn
, 12, 4);
7958 int rm
= extract32(insn
, 16, 5);
7959 int rn
= extract32(insn
, 5, 5);
7960 int rd
= extract32(insn
, 0, 5);
7963 unallocated_encoding(s
);
7968 case 0x9: /* SQDMLAL, SQDMLAL2 */
7969 case 0xb: /* SQDMLSL, SQDMLSL2 */
7970 case 0xd: /* SQDMULL, SQDMULL2 */
7971 if (size
== 0 || size
== 3) {
7972 unallocated_encoding(s
);
7977 unallocated_encoding(s
);
7981 if (!fp_access_check(s
)) {
7986 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7987 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7988 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7990 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7991 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7993 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7994 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7997 case 0xd: /* SQDMULL, SQDMULL2 */
7999 case 0xb: /* SQDMLSL, SQDMLSL2 */
8000 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8002 case 0x9: /* SQDMLAL, SQDMLAL2 */
8003 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8004 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8008 g_assert_not_reached();
8011 write_fp_dreg(s
, rd
, tcg_res
);
8013 tcg_temp_free_i64(tcg_op1
);
8014 tcg_temp_free_i64(tcg_op2
);
8015 tcg_temp_free_i64(tcg_res
);
8017 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8018 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8019 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8021 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8022 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8025 case 0xd: /* SQDMULL, SQDMULL2 */
8027 case 0xb: /* SQDMLSL, SQDMLSL2 */
8028 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8030 case 0x9: /* SQDMLAL, SQDMLAL2 */
8032 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8033 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8034 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8036 tcg_temp_free_i64(tcg_op3
);
8040 g_assert_not_reached();
8043 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8044 write_fp_dreg(s
, rd
, tcg_res
);
8046 tcg_temp_free_i32(tcg_op1
);
8047 tcg_temp_free_i32(tcg_op2
);
8048 tcg_temp_free_i64(tcg_res
);
8052 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8053 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8055 /* Handle 64x64->64 opcodes which are shared between the scalar
8056 * and vector 3-same groups. We cover every opcode where size == 3
8057 * is valid in either the three-reg-same (integer, not pairwise)
8058 * or scalar-three-reg-same groups.
8063 case 0x1: /* SQADD */
8065 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8067 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8070 case 0x5: /* SQSUB */
8072 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8074 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8077 case 0x6: /* CMGT, CMHI */
8078 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8079 * We implement this using setcond (test) and then negating.
8081 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8083 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8084 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8086 case 0x7: /* CMGE, CMHS */
8087 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8089 case 0x11: /* CMTST, CMEQ */
8094 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8096 case 0x8: /* SSHL, USHL */
8098 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8100 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8103 case 0x9: /* SQSHL, UQSHL */
8105 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8107 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8110 case 0xa: /* SRSHL, URSHL */
8112 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8114 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8117 case 0xb: /* SQRSHL, UQRSHL */
8119 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8121 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8124 case 0x10: /* ADD, SUB */
8126 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8128 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8132 g_assert_not_reached();
8136 /* Handle the 3-same-operands float operations; shared by the scalar
8137 * and vector encodings. The caller must filter out any encodings
8138 * not allocated for the encoding it is dealing with.
8140 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8141 int fpopcode
, int rd
, int rn
, int rm
)
8144 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8146 for (pass
= 0; pass
< elements
; pass
++) {
8149 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8150 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8151 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8153 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8154 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8157 case 0x39: /* FMLS */
8158 /* As usual for ARM, separate negation for fused multiply-add */
8159 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8161 case 0x19: /* FMLA */
8162 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8163 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8166 case 0x18: /* FMAXNM */
8167 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8169 case 0x1a: /* FADD */
8170 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8172 case 0x1b: /* FMULX */
8173 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8175 case 0x1c: /* FCMEQ */
8176 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8178 case 0x1e: /* FMAX */
8179 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8181 case 0x1f: /* FRECPS */
8182 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8184 case 0x38: /* FMINNM */
8185 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8187 case 0x3a: /* FSUB */
8188 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8190 case 0x3e: /* FMIN */
8191 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8193 case 0x3f: /* FRSQRTS */
8194 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8196 case 0x5b: /* FMUL */
8197 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8199 case 0x5c: /* FCMGE */
8200 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8202 case 0x5d: /* FACGE */
8203 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8205 case 0x5f: /* FDIV */
8206 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8208 case 0x7a: /* FABD */
8209 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8210 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8212 case 0x7c: /* FCMGT */
8213 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8215 case 0x7d: /* FACGT */
8216 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8219 g_assert_not_reached();
8222 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8224 tcg_temp_free_i64(tcg_res
);
8225 tcg_temp_free_i64(tcg_op1
);
8226 tcg_temp_free_i64(tcg_op2
);
8229 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8230 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8231 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8233 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8234 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8237 case 0x39: /* FMLS */
8238 /* As usual for ARM, separate negation for fused multiply-add */
8239 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8241 case 0x19: /* FMLA */
8242 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8243 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8246 case 0x1a: /* FADD */
8247 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8249 case 0x1b: /* FMULX */
8250 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8252 case 0x1c: /* FCMEQ */
8253 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8255 case 0x1e: /* FMAX */
8256 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8258 case 0x1f: /* FRECPS */
8259 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8261 case 0x18: /* FMAXNM */
8262 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8264 case 0x38: /* FMINNM */
8265 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8267 case 0x3a: /* FSUB */
8268 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8270 case 0x3e: /* FMIN */
8271 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8273 case 0x3f: /* FRSQRTS */
8274 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8276 case 0x5b: /* FMUL */
8277 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8279 case 0x5c: /* FCMGE */
8280 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8282 case 0x5d: /* FACGE */
8283 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8285 case 0x5f: /* FDIV */
8286 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8288 case 0x7a: /* FABD */
8289 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8290 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8292 case 0x7c: /* FCMGT */
8293 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8295 case 0x7d: /* FACGT */
8296 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8299 g_assert_not_reached();
8302 if (elements
== 1) {
8303 /* scalar single so clear high part */
8304 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8306 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8307 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8308 tcg_temp_free_i64(tcg_tmp
);
8310 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8313 tcg_temp_free_i32(tcg_res
);
8314 tcg_temp_free_i32(tcg_op1
);
8315 tcg_temp_free_i32(tcg_op2
);
8319 tcg_temp_free_ptr(fpst
);
8321 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8324 /* AdvSIMD scalar three same
8325 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8326 * +-----+---+-----------+------+---+------+--------+---+------+------+
8327 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8328 * +-----+---+-----------+------+---+------+--------+---+------+------+
8330 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8332 int rd
= extract32(insn
, 0, 5);
8333 int rn
= extract32(insn
, 5, 5);
8334 int opcode
= extract32(insn
, 11, 5);
8335 int rm
= extract32(insn
, 16, 5);
8336 int size
= extract32(insn
, 22, 2);
8337 bool u
= extract32(insn
, 29, 1);
8340 if (opcode
>= 0x18) {
8341 /* Floating point: U, size[1] and opcode indicate operation */
8342 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8344 case 0x1b: /* FMULX */
8345 case 0x1f: /* FRECPS */
8346 case 0x3f: /* FRSQRTS */
8347 case 0x5d: /* FACGE */
8348 case 0x7d: /* FACGT */
8349 case 0x1c: /* FCMEQ */
8350 case 0x5c: /* FCMGE */
8351 case 0x7c: /* FCMGT */
8352 case 0x7a: /* FABD */
8355 unallocated_encoding(s
);
8359 if (!fp_access_check(s
)) {
8363 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8368 case 0x1: /* SQADD, UQADD */
8369 case 0x5: /* SQSUB, UQSUB */
8370 case 0x9: /* SQSHL, UQSHL */
8371 case 0xb: /* SQRSHL, UQRSHL */
8373 case 0x8: /* SSHL, USHL */
8374 case 0xa: /* SRSHL, URSHL */
8375 case 0x6: /* CMGT, CMHI */
8376 case 0x7: /* CMGE, CMHS */
8377 case 0x11: /* CMTST, CMEQ */
8378 case 0x10: /* ADD, SUB (vector) */
8380 unallocated_encoding(s
);
8384 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8385 if (size
!= 1 && size
!= 2) {
8386 unallocated_encoding(s
);
8391 unallocated_encoding(s
);
8395 if (!fp_access_check(s
)) {
8399 tcg_rd
= tcg_temp_new_i64();
8402 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8403 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8405 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8406 tcg_temp_free_i64(tcg_rn
);
8407 tcg_temp_free_i64(tcg_rm
);
8409 /* Do a single operation on the lowest element in the vector.
8410 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8411 * no side effects for all these operations.
8412 * OPTME: special-purpose helpers would avoid doing some
8413 * unnecessary work in the helper for the 8 and 16 bit cases.
8415 NeonGenTwoOpEnvFn
*genenvfn
;
8416 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8417 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8418 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8420 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8421 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8424 case 0x1: /* SQADD, UQADD */
8426 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8427 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8428 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8429 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8431 genenvfn
= fns
[size
][u
];
8434 case 0x5: /* SQSUB, UQSUB */
8436 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8437 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8438 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8439 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8441 genenvfn
= fns
[size
][u
];
8444 case 0x9: /* SQSHL, UQSHL */
8446 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8447 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8448 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8449 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8451 genenvfn
= fns
[size
][u
];
8454 case 0xb: /* SQRSHL, UQRSHL */
8456 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8457 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8458 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8459 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8461 genenvfn
= fns
[size
][u
];
8464 case 0x16: /* SQDMULH, SQRDMULH */
8466 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8467 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8468 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8470 assert(size
== 1 || size
== 2);
8471 genenvfn
= fns
[size
- 1][u
];
8475 g_assert_not_reached();
8478 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
8479 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
8480 tcg_temp_free_i32(tcg_rd32
);
8481 tcg_temp_free_i32(tcg_rn
);
8482 tcg_temp_free_i32(tcg_rm
);
8485 write_fp_dreg(s
, rd
, tcg_rd
);
8487 tcg_temp_free_i64(tcg_rd
);
8490 /* AdvSIMD scalar three same FP16
8491 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8492 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8493 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8494 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8495 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8496 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8498 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
8501 int rd
= extract32(insn
, 0, 5);
8502 int rn
= extract32(insn
, 5, 5);
8503 int opcode
= extract32(insn
, 11, 3);
8504 int rm
= extract32(insn
, 16, 5);
8505 bool u
= extract32(insn
, 29, 1);
8506 bool a
= extract32(insn
, 23, 1);
8507 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
8514 case 0x03: /* FMULX */
8515 case 0x04: /* FCMEQ (reg) */
8516 case 0x07: /* FRECPS */
8517 case 0x0f: /* FRSQRTS */
8518 case 0x14: /* FCMGE (reg) */
8519 case 0x15: /* FACGE */
8520 case 0x1a: /* FABD */
8521 case 0x1c: /* FCMGT (reg) */
8522 case 0x1d: /* FACGT */
8525 unallocated_encoding(s
);
8529 if (!dc_isar_feature(aa64_fp16
, s
)) {
8530 unallocated_encoding(s
);
8533 if (!fp_access_check(s
)) {
8537 fpst
= get_fpstatus_ptr(true);
8539 tcg_op1
= read_fp_hreg(s
, rn
);
8540 tcg_op2
= read_fp_hreg(s
, rm
);
8541 tcg_res
= tcg_temp_new_i32();
8544 case 0x03: /* FMULX */
8545 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8547 case 0x04: /* FCMEQ (reg) */
8548 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8550 case 0x07: /* FRECPS */
8551 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8553 case 0x0f: /* FRSQRTS */
8554 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8556 case 0x14: /* FCMGE (reg) */
8557 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8559 case 0x15: /* FACGE */
8560 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8562 case 0x1a: /* FABD */
8563 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8564 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
8566 case 0x1c: /* FCMGT (reg) */
8567 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8569 case 0x1d: /* FACGT */
8570 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8573 g_assert_not_reached();
8576 write_fp_sreg(s
, rd
, tcg_res
);
8579 tcg_temp_free_i32(tcg_res
);
8580 tcg_temp_free_i32(tcg_op1
);
8581 tcg_temp_free_i32(tcg_op2
);
8582 tcg_temp_free_ptr(fpst
);
8585 /* AdvSIMD scalar three same extra
8586 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
8587 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8588 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
8589 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8591 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
8594 int rd
= extract32(insn
, 0, 5);
8595 int rn
= extract32(insn
, 5, 5);
8596 int opcode
= extract32(insn
, 11, 4);
8597 int rm
= extract32(insn
, 16, 5);
8598 int size
= extract32(insn
, 22, 2);
8599 bool u
= extract32(insn
, 29, 1);
8600 TCGv_i32 ele1
, ele2
, ele3
;
8604 switch (u
* 16 + opcode
) {
8605 case 0x10: /* SQRDMLAH (vector) */
8606 case 0x11: /* SQRDMLSH (vector) */
8607 if (size
!= 1 && size
!= 2) {
8608 unallocated_encoding(s
);
8611 feature
= dc_isar_feature(aa64_rdm
, s
);
8614 unallocated_encoding(s
);
8618 unallocated_encoding(s
);
8621 if (!fp_access_check(s
)) {
8625 /* Do a single operation on the lowest element in the vector.
8626 * We use the standard Neon helpers and rely on 0 OP 0 == 0
8627 * with no side effects for all these operations.
8628 * OPTME: special-purpose helpers would avoid doing some
8629 * unnecessary work in the helper for the 16 bit cases.
8631 ele1
= tcg_temp_new_i32();
8632 ele2
= tcg_temp_new_i32();
8633 ele3
= tcg_temp_new_i32();
8635 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
8636 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
8637 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
8640 case 0x0: /* SQRDMLAH */
8642 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8644 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8647 case 0x1: /* SQRDMLSH */
8649 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8651 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8655 g_assert_not_reached();
8657 tcg_temp_free_i32(ele1
);
8658 tcg_temp_free_i32(ele2
);
8660 res
= tcg_temp_new_i64();
8661 tcg_gen_extu_i32_i64(res
, ele3
);
8662 tcg_temp_free_i32(ele3
);
8664 write_fp_dreg(s
, rd
, res
);
8665 tcg_temp_free_i64(res
);
8668 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
8669 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
8670 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
8672 /* Handle 64->64 opcodes which are shared between the scalar and
8673 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
8674 * is valid in either group and also the double-precision fp ops.
8675 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
8681 case 0x4: /* CLS, CLZ */
8683 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
8685 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
8689 /* This opcode is shared with CNT and RBIT but we have earlier
8690 * enforced that size == 3 if and only if this is the NOT insn.
8692 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
8694 case 0x7: /* SQABS, SQNEG */
8696 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
8698 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
8701 case 0xa: /* CMLT */
8702 /* 64 bit integer comparison against zero, result is
8703 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
8708 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
8709 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8711 case 0x8: /* CMGT, CMGE */
8712 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
8714 case 0x9: /* CMEQ, CMLE */
8715 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
8717 case 0xb: /* ABS, NEG */
8719 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8721 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8722 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8723 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
8725 tcg_temp_free_i64(tcg_zero
);
8728 case 0x2f: /* FABS */
8729 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
8731 case 0x6f: /* FNEG */
8732 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
8734 case 0x7f: /* FSQRT */
8735 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
8737 case 0x1a: /* FCVTNS */
8738 case 0x1b: /* FCVTMS */
8739 case 0x1c: /* FCVTAS */
8740 case 0x3a: /* FCVTPS */
8741 case 0x3b: /* FCVTZS */
8743 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8744 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8745 tcg_temp_free_i32(tcg_shift
);
8748 case 0x5a: /* FCVTNU */
8749 case 0x5b: /* FCVTMU */
8750 case 0x5c: /* FCVTAU */
8751 case 0x7a: /* FCVTPU */
8752 case 0x7b: /* FCVTZU */
8754 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8755 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8756 tcg_temp_free_i32(tcg_shift
);
8759 case 0x18: /* FRINTN */
8760 case 0x19: /* FRINTM */
8761 case 0x38: /* FRINTP */
8762 case 0x39: /* FRINTZ */
8763 case 0x58: /* FRINTA */
8764 case 0x79: /* FRINTI */
8765 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8767 case 0x59: /* FRINTX */
8768 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8771 g_assert_not_reached();
8775 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
8776 bool is_scalar
, bool is_u
, bool is_q
,
8777 int size
, int rn
, int rd
)
8779 bool is_double
= (size
== MO_64
);
8782 if (!fp_access_check(s
)) {
8786 fpst
= get_fpstatus_ptr(size
== MO_16
);
8789 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8790 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8791 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8792 NeonGenTwoDoubleOPFn
*genfn
;
8797 case 0x2e: /* FCMLT (zero) */
8800 case 0x2c: /* FCMGT (zero) */
8801 genfn
= gen_helper_neon_cgt_f64
;
8803 case 0x2d: /* FCMEQ (zero) */
8804 genfn
= gen_helper_neon_ceq_f64
;
8806 case 0x6d: /* FCMLE (zero) */
8809 case 0x6c: /* FCMGE (zero) */
8810 genfn
= gen_helper_neon_cge_f64
;
8813 g_assert_not_reached();
8816 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8817 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8819 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8821 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8823 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8825 tcg_temp_free_i64(tcg_res
);
8826 tcg_temp_free_i64(tcg_zero
);
8827 tcg_temp_free_i64(tcg_op
);
8829 clear_vec_high(s
, !is_scalar
, rd
);
8831 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8832 TCGv_i32 tcg_zero
= tcg_const_i32(0);
8833 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8834 NeonGenTwoSingleOPFn
*genfn
;
8836 int pass
, maxpasses
;
8838 if (size
== MO_16
) {
8840 case 0x2e: /* FCMLT (zero) */
8843 case 0x2c: /* FCMGT (zero) */
8844 genfn
= gen_helper_advsimd_cgt_f16
;
8846 case 0x2d: /* FCMEQ (zero) */
8847 genfn
= gen_helper_advsimd_ceq_f16
;
8849 case 0x6d: /* FCMLE (zero) */
8852 case 0x6c: /* FCMGE (zero) */
8853 genfn
= gen_helper_advsimd_cge_f16
;
8856 g_assert_not_reached();
8860 case 0x2e: /* FCMLT (zero) */
8863 case 0x2c: /* FCMGT (zero) */
8864 genfn
= gen_helper_neon_cgt_f32
;
8866 case 0x2d: /* FCMEQ (zero) */
8867 genfn
= gen_helper_neon_ceq_f32
;
8869 case 0x6d: /* FCMLE (zero) */
8872 case 0x6c: /* FCMGE (zero) */
8873 genfn
= gen_helper_neon_cge_f32
;
8876 g_assert_not_reached();
8883 int vector_size
= 8 << is_q
;
8884 maxpasses
= vector_size
>> size
;
8887 for (pass
= 0; pass
< maxpasses
; pass
++) {
8888 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8890 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8892 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8895 write_fp_sreg(s
, rd
, tcg_res
);
8897 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
8900 tcg_temp_free_i32(tcg_res
);
8901 tcg_temp_free_i32(tcg_zero
);
8902 tcg_temp_free_i32(tcg_op
);
8904 clear_vec_high(s
, is_q
, rd
);
8908 tcg_temp_free_ptr(fpst
);
8911 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
8912 bool is_scalar
, bool is_u
, bool is_q
,
8913 int size
, int rn
, int rd
)
8915 bool is_double
= (size
== 3);
8916 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8919 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8920 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8923 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8924 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8926 case 0x3d: /* FRECPE */
8927 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
8929 case 0x3f: /* FRECPX */
8930 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
8932 case 0x7d: /* FRSQRTE */
8933 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
8936 g_assert_not_reached();
8938 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8940 tcg_temp_free_i64(tcg_res
);
8941 tcg_temp_free_i64(tcg_op
);
8942 clear_vec_high(s
, !is_scalar
, rd
);
8944 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8945 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8946 int pass
, maxpasses
;
8951 maxpasses
= is_q
? 4 : 2;
8954 for (pass
= 0; pass
< maxpasses
; pass
++) {
8955 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
8958 case 0x3c: /* URECPE */
8959 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
8961 case 0x3d: /* FRECPE */
8962 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
8964 case 0x3f: /* FRECPX */
8965 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
8967 case 0x7d: /* FRSQRTE */
8968 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
8971 g_assert_not_reached();
8975 write_fp_sreg(s
, rd
, tcg_res
);
8977 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8980 tcg_temp_free_i32(tcg_res
);
8981 tcg_temp_free_i32(tcg_op
);
8983 clear_vec_high(s
, is_q
, rd
);
8986 tcg_temp_free_ptr(fpst
);
8989 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
8990 int opcode
, bool u
, bool is_q
,
8991 int size
, int rn
, int rd
)
8993 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
8994 * in the source becomes a size element in the destination).
8997 TCGv_i32 tcg_res
[2];
8998 int destelt
= is_q
? 2 : 0;
8999 int passes
= scalar
? 1 : 2;
9002 tcg_res
[1] = tcg_const_i32(0);
9005 for (pass
= 0; pass
< passes
; pass
++) {
9006 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9007 NeonGenNarrowFn
*genfn
= NULL
;
9008 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9011 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9013 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9015 tcg_res
[pass
] = tcg_temp_new_i32();
9018 case 0x12: /* XTN, SQXTUN */
9020 static NeonGenNarrowFn
* const xtnfns
[3] = {
9021 gen_helper_neon_narrow_u8
,
9022 gen_helper_neon_narrow_u16
,
9023 tcg_gen_extrl_i64_i32
,
9025 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9026 gen_helper_neon_unarrow_sat8
,
9027 gen_helper_neon_unarrow_sat16
,
9028 gen_helper_neon_unarrow_sat32
,
9031 genenvfn
= sqxtunfns
[size
];
9033 genfn
= xtnfns
[size
];
9037 case 0x14: /* SQXTN, UQXTN */
9039 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9040 { gen_helper_neon_narrow_sat_s8
,
9041 gen_helper_neon_narrow_sat_u8
},
9042 { gen_helper_neon_narrow_sat_s16
,
9043 gen_helper_neon_narrow_sat_u16
},
9044 { gen_helper_neon_narrow_sat_s32
,
9045 gen_helper_neon_narrow_sat_u32
},
9047 genenvfn
= fns
[size
][u
];
9050 case 0x16: /* FCVTN, FCVTN2 */
9051 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9053 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9055 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9056 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9057 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9058 TCGv_i32 ahp
= get_ahp_flag();
9060 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9061 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9062 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9063 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9064 tcg_temp_free_i32(tcg_lo
);
9065 tcg_temp_free_i32(tcg_hi
);
9066 tcg_temp_free_ptr(fpst
);
9067 tcg_temp_free_i32(ahp
);
9070 case 0x56: /* FCVTXN, FCVTXN2 */
9071 /* 64 bit to 32 bit float conversion
9072 * with von Neumann rounding (round to odd)
9075 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9078 g_assert_not_reached();
9082 genfn(tcg_res
[pass
], tcg_op
);
9083 } else if (genenvfn
) {
9084 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9087 tcg_temp_free_i64(tcg_op
);
9090 for (pass
= 0; pass
< 2; pass
++) {
9091 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9092 tcg_temp_free_i32(tcg_res
[pass
]);
9094 clear_vec_high(s
, is_q
, rd
);
9097 /* Remaining saturating accumulating ops */
9098 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9099 bool is_q
, int size
, int rn
, int rd
)
9101 bool is_double
= (size
== 3);
9104 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9105 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9108 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9109 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9110 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9112 if (is_u
) { /* USQADD */
9113 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9114 } else { /* SUQADD */
9115 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9117 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9119 tcg_temp_free_i64(tcg_rd
);
9120 tcg_temp_free_i64(tcg_rn
);
9121 clear_vec_high(s
, !is_scalar
, rd
);
9123 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9124 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9125 int pass
, maxpasses
;
9130 maxpasses
= is_q
? 4 : 2;
9133 for (pass
= 0; pass
< maxpasses
; pass
++) {
9135 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9136 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9138 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9139 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9142 if (is_u
) { /* USQADD */
9145 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9148 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9151 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9154 g_assert_not_reached();
9156 } else { /* SUQADD */
9159 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9162 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9165 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9168 g_assert_not_reached();
9173 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9174 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9175 tcg_temp_free_i64(tcg_zero
);
9177 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9179 tcg_temp_free_i32(tcg_rd
);
9180 tcg_temp_free_i32(tcg_rn
);
9181 clear_vec_high(s
, is_q
, rd
);
9185 /* AdvSIMD scalar two reg misc
9186 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9187 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9188 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9189 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9191 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9193 int rd
= extract32(insn
, 0, 5);
9194 int rn
= extract32(insn
, 5, 5);
9195 int opcode
= extract32(insn
, 12, 5);
9196 int size
= extract32(insn
, 22, 2);
9197 bool u
= extract32(insn
, 29, 1);
9198 bool is_fcvt
= false;
9201 TCGv_ptr tcg_fpstatus
;
9204 case 0x3: /* USQADD / SUQADD*/
9205 if (!fp_access_check(s
)) {
9208 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9210 case 0x7: /* SQABS / SQNEG */
9212 case 0xa: /* CMLT */
9214 unallocated_encoding(s
);
9218 case 0x8: /* CMGT, CMGE */
9219 case 0x9: /* CMEQ, CMLE */
9220 case 0xb: /* ABS, NEG */
9222 unallocated_encoding(s
);
9226 case 0x12: /* SQXTUN */
9228 unallocated_encoding(s
);
9232 case 0x14: /* SQXTN, UQXTN */
9234 unallocated_encoding(s
);
9237 if (!fp_access_check(s
)) {
9240 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9245 /* Floating point: U, size[1] and opcode indicate operation;
9246 * size[0] indicates single or double precision.
9248 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9249 size
= extract32(size
, 0, 1) ? 3 : 2;
9251 case 0x2c: /* FCMGT (zero) */
9252 case 0x2d: /* FCMEQ (zero) */
9253 case 0x2e: /* FCMLT (zero) */
9254 case 0x6c: /* FCMGE (zero) */
9255 case 0x6d: /* FCMLE (zero) */
9256 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9258 case 0x1d: /* SCVTF */
9259 case 0x5d: /* UCVTF */
9261 bool is_signed
= (opcode
== 0x1d);
9262 if (!fp_access_check(s
)) {
9265 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9268 case 0x3d: /* FRECPE */
9269 case 0x3f: /* FRECPX */
9270 case 0x7d: /* FRSQRTE */
9271 if (!fp_access_check(s
)) {
9274 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9276 case 0x1a: /* FCVTNS */
9277 case 0x1b: /* FCVTMS */
9278 case 0x3a: /* FCVTPS */
9279 case 0x3b: /* FCVTZS */
9280 case 0x5a: /* FCVTNU */
9281 case 0x5b: /* FCVTMU */
9282 case 0x7a: /* FCVTPU */
9283 case 0x7b: /* FCVTZU */
9285 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9287 case 0x1c: /* FCVTAS */
9288 case 0x5c: /* FCVTAU */
9289 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9291 rmode
= FPROUNDING_TIEAWAY
;
9293 case 0x56: /* FCVTXN, FCVTXN2 */
9295 unallocated_encoding(s
);
9298 if (!fp_access_check(s
)) {
9301 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9304 unallocated_encoding(s
);
9309 unallocated_encoding(s
);
9313 if (!fp_access_check(s
)) {
9318 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9319 tcg_fpstatus
= get_fpstatus_ptr(false);
9320 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9323 tcg_fpstatus
= NULL
;
9327 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9328 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9330 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9331 write_fp_dreg(s
, rd
, tcg_rd
);
9332 tcg_temp_free_i64(tcg_rd
);
9333 tcg_temp_free_i64(tcg_rn
);
9335 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9336 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9338 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9341 case 0x7: /* SQABS, SQNEG */
9343 NeonGenOneOpEnvFn
*genfn
;
9344 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9345 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9346 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9347 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9349 genfn
= fns
[size
][u
];
9350 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9353 case 0x1a: /* FCVTNS */
9354 case 0x1b: /* FCVTMS */
9355 case 0x1c: /* FCVTAS */
9356 case 0x3a: /* FCVTPS */
9357 case 0x3b: /* FCVTZS */
9359 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9360 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9361 tcg_temp_free_i32(tcg_shift
);
9364 case 0x5a: /* FCVTNU */
9365 case 0x5b: /* FCVTMU */
9366 case 0x5c: /* FCVTAU */
9367 case 0x7a: /* FCVTPU */
9368 case 0x7b: /* FCVTZU */
9370 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9371 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9372 tcg_temp_free_i32(tcg_shift
);
9376 g_assert_not_reached();
9379 write_fp_sreg(s
, rd
, tcg_rd
);
9380 tcg_temp_free_i32(tcg_rd
);
9381 tcg_temp_free_i32(tcg_rn
);
9385 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9386 tcg_temp_free_i32(tcg_rmode
);
9387 tcg_temp_free_ptr(tcg_fpstatus
);
9391 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9392 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9393 int immh
, int immb
, int opcode
, int rn
, int rd
)
9395 int size
= 32 - clz32(immh
) - 1;
9396 int immhb
= immh
<< 3 | immb
;
9397 int shift
= 2 * (8 << size
) - immhb
;
9398 bool accumulate
= false;
9399 int dsize
= is_q
? 128 : 64;
9400 int esize
= 8 << size
;
9401 int elements
= dsize
/esize
;
9402 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9403 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9404 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9406 uint64_t round_const
;
9409 if (extract32(immh
, 3, 1) && !is_q
) {
9410 unallocated_encoding(s
);
9413 tcg_debug_assert(size
<= 3);
9415 if (!fp_access_check(s
)) {
9420 case 0x02: /* SSRA / USRA (accumulate) */
9422 /* Shift count same as element size produces zero to add. */
9423 if (shift
== 8 << size
) {
9426 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9428 /* Shift count same as element size produces all sign to add. */
9429 if (shift
== 8 << size
) {
9432 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9435 case 0x08: /* SRI */
9436 /* Shift count same as element size is valid but does nothing. */
9437 if (shift
== 8 << size
) {
9440 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9443 case 0x00: /* SSHR / USHR */
9445 if (shift
== 8 << size
) {
9446 /* Shift count the same size as element size produces zero. */
9447 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9448 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9450 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9453 /* Shift count the same size as element size produces all sign. */
9454 if (shift
== 8 << size
) {
9457 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
9461 case 0x04: /* SRSHR / URSHR (rounding) */
9463 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9467 g_assert_not_reached();
9470 round_const
= 1ULL << (shift
- 1);
9471 tcg_round
= tcg_const_i64(round_const
);
9473 for (i
= 0; i
< elements
; i
++) {
9474 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
9476 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
9479 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9480 accumulate
, is_u
, size
, shift
);
9482 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
9484 tcg_temp_free_i64(tcg_round
);
9487 clear_vec_high(s
, is_q
, rd
);
9490 /* SHL/SLI - Vector shift left */
9491 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
9492 int immh
, int immb
, int opcode
, int rn
, int rd
)
9494 int size
= 32 - clz32(immh
) - 1;
9495 int immhb
= immh
<< 3 | immb
;
9496 int shift
= immhb
- (8 << size
);
9498 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
9499 assert(size
>= 0 && size
<= 3);
9501 if (extract32(immh
, 3, 1) && !is_q
) {
9502 unallocated_encoding(s
);
9506 if (!fp_access_check(s
)) {
9511 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
9513 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
9517 /* USHLL/SHLL - Vector shift left with widening */
9518 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
9519 int immh
, int immb
, int opcode
, int rn
, int rd
)
9521 int size
= 32 - clz32(immh
) - 1;
9522 int immhb
= immh
<< 3 | immb
;
9523 int shift
= immhb
- (8 << size
);
9525 int esize
= 8 << size
;
9526 int elements
= dsize
/esize
;
9527 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9528 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9532 unallocated_encoding(s
);
9536 if (!fp_access_check(s
)) {
9540 /* For the LL variants the store is larger than the load,
9541 * so if rd == rn we would overwrite parts of our input.
9542 * So load everything right now and use shifts in the main loop.
9544 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
9546 for (i
= 0; i
< elements
; i
++) {
9547 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
9548 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
9549 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
9550 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
9554 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
9555 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
9556 int immh
, int immb
, int opcode
, int rn
, int rd
)
9558 int immhb
= immh
<< 3 | immb
;
9559 int size
= 32 - clz32(immh
) - 1;
9561 int esize
= 8 << size
;
9562 int elements
= dsize
/esize
;
9563 int shift
= (2 * esize
) - immhb
;
9564 bool round
= extract32(opcode
, 0, 1);
9565 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
9569 if (extract32(immh
, 3, 1)) {
9570 unallocated_encoding(s
);
9574 if (!fp_access_check(s
)) {
9578 tcg_rn
= tcg_temp_new_i64();
9579 tcg_rd
= tcg_temp_new_i64();
9580 tcg_final
= tcg_temp_new_i64();
9581 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
9584 uint64_t round_const
= 1ULL << (shift
- 1);
9585 tcg_round
= tcg_const_i64(round_const
);
9590 for (i
= 0; i
< elements
; i
++) {
9591 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
9592 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9593 false, true, size
+1, shift
);
9595 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
9599 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
9601 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
9604 tcg_temp_free_i64(tcg_round
);
9606 tcg_temp_free_i64(tcg_rn
);
9607 tcg_temp_free_i64(tcg_rd
);
9608 tcg_temp_free_i64(tcg_final
);
9610 clear_vec_high(s
, is_q
, rd
);
9614 /* AdvSIMD shift by immediate
9615 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9616 * +---+---+---+-------------+------+------+--------+---+------+------+
9617 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9618 * +---+---+---+-------------+------+------+--------+---+------+------+
9620 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
9622 int rd
= extract32(insn
, 0, 5);
9623 int rn
= extract32(insn
, 5, 5);
9624 int opcode
= extract32(insn
, 11, 5);
9625 int immb
= extract32(insn
, 16, 3);
9626 int immh
= extract32(insn
, 19, 4);
9627 bool is_u
= extract32(insn
, 29, 1);
9628 bool is_q
= extract32(insn
, 30, 1);
9631 case 0x08: /* SRI */
9633 unallocated_encoding(s
);
9637 case 0x00: /* SSHR / USHR */
9638 case 0x02: /* SSRA / USRA (accumulate) */
9639 case 0x04: /* SRSHR / URSHR (rounding) */
9640 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9641 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9643 case 0x0a: /* SHL / SLI */
9644 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9646 case 0x10: /* SHRN */
9647 case 0x11: /* RSHRN / SQRSHRUN */
9649 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
9652 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
9655 case 0x12: /* SQSHRN / UQSHRN */
9656 case 0x13: /* SQRSHRN / UQRSHRN */
9657 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
9660 case 0x14: /* SSHLL / USHLL */
9661 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9663 case 0x1c: /* SCVTF / UCVTF */
9664 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
9667 case 0xc: /* SQSHLU */
9669 unallocated_encoding(s
);
9672 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
9674 case 0xe: /* SQSHL, UQSHL */
9675 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
9677 case 0x1f: /* FCVTZS/ FCVTZU */
9678 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
9681 unallocated_encoding(s
);
9686 /* Generate code to do a "long" addition or subtraction, ie one done in
9687 * TCGv_i64 on vector lanes twice the width specified by size.
9689 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
9690 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
9692 static NeonGenTwo64OpFn
* const fns
[3][2] = {
9693 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
9694 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
9695 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
9697 NeonGenTwo64OpFn
*genfn
;
9700 genfn
= fns
[size
][is_sub
];
9701 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9704 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
9705 int opcode
, int rd
, int rn
, int rm
)
9707 /* 3-reg-different widening insns: 64 x 64 -> 128 */
9708 TCGv_i64 tcg_res
[2];
9711 tcg_res
[0] = tcg_temp_new_i64();
9712 tcg_res
[1] = tcg_temp_new_i64();
9714 /* Does this op do an adding accumulate, a subtracting accumulate,
9715 * or no accumulate at all?
9733 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9734 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9737 /* size == 2 means two 32x32->64 operations; this is worth special
9738 * casing because we can generally handle it inline.
9741 for (pass
= 0; pass
< 2; pass
++) {
9742 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9743 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9744 TCGv_i64 tcg_passres
;
9745 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
9747 int elt
= pass
+ is_q
* 2;
9749 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
9750 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
9753 tcg_passres
= tcg_res
[pass
];
9755 tcg_passres
= tcg_temp_new_i64();
9759 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9760 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9762 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9763 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9765 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9766 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9768 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
9769 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
9771 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
9772 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
9773 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
9775 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
9776 tcg_temp_free_i64(tcg_tmp1
);
9777 tcg_temp_free_i64(tcg_tmp2
);
9780 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9781 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9782 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
9783 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9785 case 9: /* SQDMLAL, SQDMLAL2 */
9786 case 11: /* SQDMLSL, SQDMLSL2 */
9787 case 13: /* SQDMULL, SQDMULL2 */
9788 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9789 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
9790 tcg_passres
, tcg_passres
);
9793 g_assert_not_reached();
9796 if (opcode
== 9 || opcode
== 11) {
9797 /* saturating accumulate ops */
9799 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
9801 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
9802 tcg_res
[pass
], tcg_passres
);
9803 } else if (accop
> 0) {
9804 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
9805 } else if (accop
< 0) {
9806 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
9810 tcg_temp_free_i64(tcg_passres
);
9813 tcg_temp_free_i64(tcg_op1
);
9814 tcg_temp_free_i64(tcg_op2
);
9817 /* size 0 or 1, generally helper functions */
9818 for (pass
= 0; pass
< 2; pass
++) {
9819 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9820 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9821 TCGv_i64 tcg_passres
;
9822 int elt
= pass
+ is_q
* 2;
9824 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
9825 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
9828 tcg_passres
= tcg_res
[pass
];
9830 tcg_passres
= tcg_temp_new_i64();
9834 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9835 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9837 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
9838 static NeonGenWidenFn
* const widenfns
[2][2] = {
9839 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
9840 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
9842 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
9844 widenfn(tcg_op2_64
, tcg_op2
);
9845 widenfn(tcg_passres
, tcg_op1
);
9846 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
9847 tcg_passres
, tcg_op2_64
);
9848 tcg_temp_free_i64(tcg_op2_64
);
9851 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9852 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9855 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
9857 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
9861 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
9863 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
9867 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9868 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9869 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
9872 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
9874 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
9878 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
9880 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
9884 case 9: /* SQDMLAL, SQDMLAL2 */
9885 case 11: /* SQDMLSL, SQDMLSL2 */
9886 case 13: /* SQDMULL, SQDMULL2 */
9888 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
9889 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
9890 tcg_passres
, tcg_passres
);
9892 case 14: /* PMULL */
9894 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
9897 g_assert_not_reached();
9899 tcg_temp_free_i32(tcg_op1
);
9900 tcg_temp_free_i32(tcg_op2
);
9903 if (opcode
== 9 || opcode
== 11) {
9904 /* saturating accumulate ops */
9906 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
9908 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
9912 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
9913 tcg_res
[pass
], tcg_passres
);
9915 tcg_temp_free_i64(tcg_passres
);
9920 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9921 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9922 tcg_temp_free_i64(tcg_res
[0]);
9923 tcg_temp_free_i64(tcg_res
[1]);
9926 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
9927 int opcode
, int rd
, int rn
, int rm
)
9929 TCGv_i64 tcg_res
[2];
9930 int part
= is_q
? 2 : 0;
9933 for (pass
= 0; pass
< 2; pass
++) {
9934 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9935 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9936 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
9937 static NeonGenWidenFn
* const widenfns
[3][2] = {
9938 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
9939 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
9940 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
9942 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
9944 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9945 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
9946 widenfn(tcg_op2_wide
, tcg_op2
);
9947 tcg_temp_free_i32(tcg_op2
);
9948 tcg_res
[pass
] = tcg_temp_new_i64();
9949 gen_neon_addl(size
, (opcode
== 3),
9950 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
9951 tcg_temp_free_i64(tcg_op1
);
9952 tcg_temp_free_i64(tcg_op2_wide
);
9955 for (pass
= 0; pass
< 2; pass
++) {
9956 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9957 tcg_temp_free_i64(tcg_res
[pass
]);
9961 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
9963 tcg_gen_addi_i64(in
, in
, 1U << 31);
9964 tcg_gen_extrh_i64_i32(res
, in
);
9967 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
9968 int opcode
, int rd
, int rn
, int rm
)
9970 TCGv_i32 tcg_res
[2];
9971 int part
= is_q
? 2 : 0;
9974 for (pass
= 0; pass
< 2; pass
++) {
9975 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9976 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9977 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
9978 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
9979 { gen_helper_neon_narrow_high_u8
,
9980 gen_helper_neon_narrow_round_high_u8
},
9981 { gen_helper_neon_narrow_high_u16
,
9982 gen_helper_neon_narrow_round_high_u16
},
9983 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
9985 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
9987 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9988 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9990 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
9992 tcg_temp_free_i64(tcg_op1
);
9993 tcg_temp_free_i64(tcg_op2
);
9995 tcg_res
[pass
] = tcg_temp_new_i32();
9996 gennarrow(tcg_res
[pass
], tcg_wideres
);
9997 tcg_temp_free_i64(tcg_wideres
);
10000 for (pass
= 0; pass
< 2; pass
++) {
10001 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10002 tcg_temp_free_i32(tcg_res
[pass
]);
10004 clear_vec_high(s
, is_q
, rd
);
10007 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10009 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10010 * is the only three-reg-diff instruction which produces a
10011 * 128-bit wide result from a single operation. However since
10012 * it's possible to calculate the two halves more or less
10013 * separately we just use two helper calls.
10015 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10016 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10017 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10019 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10020 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10021 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10022 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10023 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10024 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10026 tcg_temp_free_i64(tcg_op1
);
10027 tcg_temp_free_i64(tcg_op2
);
10028 tcg_temp_free_i64(tcg_res
);
10031 /* AdvSIMD three different
10032 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10033 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10034 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10035 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10037 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10039 /* Instructions in this group fall into three basic classes
10040 * (in each case with the operation working on each element in
10041 * the input vectors):
10042 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10044 * (2) wide 64 x 128 -> 128
10045 * (3) narrowing 128 x 128 -> 64
10046 * Here we do initial decode, catch unallocated cases and
10047 * dispatch to separate functions for each class.
10049 int is_q
= extract32(insn
, 30, 1);
10050 int is_u
= extract32(insn
, 29, 1);
10051 int size
= extract32(insn
, 22, 2);
10052 int opcode
= extract32(insn
, 12, 4);
10053 int rm
= extract32(insn
, 16, 5);
10054 int rn
= extract32(insn
, 5, 5);
10055 int rd
= extract32(insn
, 0, 5);
10058 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10059 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10060 /* 64 x 128 -> 128 */
10062 unallocated_encoding(s
);
10065 if (!fp_access_check(s
)) {
10068 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10070 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10071 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10072 /* 128 x 128 -> 64 */
10074 unallocated_encoding(s
);
10077 if (!fp_access_check(s
)) {
10080 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10082 case 14: /* PMULL, PMULL2 */
10083 if (is_u
|| size
== 1 || size
== 2) {
10084 unallocated_encoding(s
);
10088 if (!dc_isar_feature(aa64_pmull
, s
)) {
10089 unallocated_encoding(s
);
10092 if (!fp_access_check(s
)) {
10095 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10099 case 9: /* SQDMLAL, SQDMLAL2 */
10100 case 11: /* SQDMLSL, SQDMLSL2 */
10101 case 13: /* SQDMULL, SQDMULL2 */
10102 if (is_u
|| size
== 0) {
10103 unallocated_encoding(s
);
10107 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10108 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10109 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10110 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10111 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10112 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10113 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10114 /* 64 x 64 -> 128 */
10116 unallocated_encoding(s
);
10120 if (!fp_access_check(s
)) {
10124 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10127 /* opcode 15 not allocated */
10128 unallocated_encoding(s
);
10133 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10134 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10136 int rd
= extract32(insn
, 0, 5);
10137 int rn
= extract32(insn
, 5, 5);
10138 int rm
= extract32(insn
, 16, 5);
10139 int size
= extract32(insn
, 22, 2);
10140 bool is_u
= extract32(insn
, 29, 1);
10141 bool is_q
= extract32(insn
, 30, 1);
10143 if (!fp_access_check(s
)) {
10147 switch (size
+ 4 * is_u
) {
10149 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10152 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10155 if (rn
== rm
) { /* MOV */
10156 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_mov
, 0);
10158 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10162 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10165 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10168 case 5: /* BSL bitwise select */
10169 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10171 case 6: /* BIT, bitwise insert if true */
10172 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10174 case 7: /* BIF, bitwise insert if false */
10175 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10179 g_assert_not_reached();
10183 /* Pairwise op subgroup of C3.6.16.
10185 * This is called directly or via the handle_3same_float for float pairwise
10186 * operations where the opcode and size are calculated differently.
10188 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10189 int size
, int rn
, int rm
, int rd
)
10194 /* Floating point operations need fpst */
10195 if (opcode
>= 0x58) {
10196 fpst
= get_fpstatus_ptr(false);
10201 if (!fp_access_check(s
)) {
10205 /* These operations work on the concatenated rm:rn, with each pair of
10206 * adjacent elements being operated on to produce an element in the result.
10209 TCGv_i64 tcg_res
[2];
10211 for (pass
= 0; pass
< 2; pass
++) {
10212 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10213 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10214 int passreg
= (pass
== 0) ? rn
: rm
;
10216 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10217 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10218 tcg_res
[pass
] = tcg_temp_new_i64();
10221 case 0x17: /* ADDP */
10222 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10224 case 0x58: /* FMAXNMP */
10225 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10227 case 0x5a: /* FADDP */
10228 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10230 case 0x5e: /* FMAXP */
10231 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10233 case 0x78: /* FMINNMP */
10234 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10236 case 0x7e: /* FMINP */
10237 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10240 g_assert_not_reached();
10243 tcg_temp_free_i64(tcg_op1
);
10244 tcg_temp_free_i64(tcg_op2
);
10247 for (pass
= 0; pass
< 2; pass
++) {
10248 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10249 tcg_temp_free_i64(tcg_res
[pass
]);
10252 int maxpass
= is_q
? 4 : 2;
10253 TCGv_i32 tcg_res
[4];
10255 for (pass
= 0; pass
< maxpass
; pass
++) {
10256 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10257 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10258 NeonGenTwoOpFn
*genfn
= NULL
;
10259 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10260 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10262 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10263 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10264 tcg_res
[pass
] = tcg_temp_new_i32();
10267 case 0x17: /* ADDP */
10269 static NeonGenTwoOpFn
* const fns
[3] = {
10270 gen_helper_neon_padd_u8
,
10271 gen_helper_neon_padd_u16
,
10277 case 0x14: /* SMAXP, UMAXP */
10279 static NeonGenTwoOpFn
* const fns
[3][2] = {
10280 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10281 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10282 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10284 genfn
= fns
[size
][u
];
10287 case 0x15: /* SMINP, UMINP */
10289 static NeonGenTwoOpFn
* const fns
[3][2] = {
10290 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10291 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10292 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10294 genfn
= fns
[size
][u
];
10297 /* The FP operations are all on single floats (32 bit) */
10298 case 0x58: /* FMAXNMP */
10299 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10301 case 0x5a: /* FADDP */
10302 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10304 case 0x5e: /* FMAXP */
10305 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10307 case 0x78: /* FMINNMP */
10308 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10310 case 0x7e: /* FMINP */
10311 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10314 g_assert_not_reached();
10317 /* FP ops called directly, otherwise call now */
10319 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10322 tcg_temp_free_i32(tcg_op1
);
10323 tcg_temp_free_i32(tcg_op2
);
10326 for (pass
= 0; pass
< maxpass
; pass
++) {
10327 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10328 tcg_temp_free_i32(tcg_res
[pass
]);
10330 clear_vec_high(s
, is_q
, rd
);
10334 tcg_temp_free_ptr(fpst
);
10338 /* Floating point op subgroup of C3.6.16. */
10339 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10341 /* For floating point ops, the U, size[1] and opcode bits
10342 * together indicate the operation. size[0] indicates single
10345 int fpopcode
= extract32(insn
, 11, 5)
10346 | (extract32(insn
, 23, 1) << 5)
10347 | (extract32(insn
, 29, 1) << 6);
10348 int is_q
= extract32(insn
, 30, 1);
10349 int size
= extract32(insn
, 22, 1);
10350 int rm
= extract32(insn
, 16, 5);
10351 int rn
= extract32(insn
, 5, 5);
10352 int rd
= extract32(insn
, 0, 5);
10354 int datasize
= is_q
? 128 : 64;
10355 int esize
= 32 << size
;
10356 int elements
= datasize
/ esize
;
10358 if (size
== 1 && !is_q
) {
10359 unallocated_encoding(s
);
10363 switch (fpopcode
) {
10364 case 0x58: /* FMAXNMP */
10365 case 0x5a: /* FADDP */
10366 case 0x5e: /* FMAXP */
10367 case 0x78: /* FMINNMP */
10368 case 0x7e: /* FMINP */
10369 if (size
&& !is_q
) {
10370 unallocated_encoding(s
);
10373 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10376 case 0x1b: /* FMULX */
10377 case 0x1f: /* FRECPS */
10378 case 0x3f: /* FRSQRTS */
10379 case 0x5d: /* FACGE */
10380 case 0x7d: /* FACGT */
10381 case 0x19: /* FMLA */
10382 case 0x39: /* FMLS */
10383 case 0x18: /* FMAXNM */
10384 case 0x1a: /* FADD */
10385 case 0x1c: /* FCMEQ */
10386 case 0x1e: /* FMAX */
10387 case 0x38: /* FMINNM */
10388 case 0x3a: /* FSUB */
10389 case 0x3e: /* FMIN */
10390 case 0x5b: /* FMUL */
10391 case 0x5c: /* FCMGE */
10392 case 0x5f: /* FDIV */
10393 case 0x7a: /* FABD */
10394 case 0x7c: /* FCMGT */
10395 if (!fp_access_check(s
)) {
10399 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10402 unallocated_encoding(s
);
10407 /* Integer op subgroup of C3.6.16. */
10408 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10410 int is_q
= extract32(insn
, 30, 1);
10411 int u
= extract32(insn
, 29, 1);
10412 int size
= extract32(insn
, 22, 2);
10413 int opcode
= extract32(insn
, 11, 5);
10414 int rm
= extract32(insn
, 16, 5);
10415 int rn
= extract32(insn
, 5, 5);
10416 int rd
= extract32(insn
, 0, 5);
10421 case 0x13: /* MUL, PMUL */
10422 if (u
&& size
!= 0) {
10423 unallocated_encoding(s
);
10427 case 0x0: /* SHADD, UHADD */
10428 case 0x2: /* SRHADD, URHADD */
10429 case 0x4: /* SHSUB, UHSUB */
10430 case 0xc: /* SMAX, UMAX */
10431 case 0xd: /* SMIN, UMIN */
10432 case 0xe: /* SABD, UABD */
10433 case 0xf: /* SABA, UABA */
10434 case 0x12: /* MLA, MLS */
10436 unallocated_encoding(s
);
10440 case 0x16: /* SQDMULH, SQRDMULH */
10441 if (size
== 0 || size
== 3) {
10442 unallocated_encoding(s
);
10447 if (size
== 3 && !is_q
) {
10448 unallocated_encoding(s
);
10454 if (!fp_access_check(s
)) {
10459 case 0x10: /* ADD, SUB */
10461 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
10463 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
10466 case 0x13: /* MUL, PMUL */
10467 if (!u
) { /* MUL */
10468 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
10472 case 0x12: /* MLA, MLS */
10474 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
10476 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
10480 if (!u
) { /* CMTST */
10481 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
10485 cond
= TCG_COND_EQ
;
10487 case 0x06: /* CMGT, CMHI */
10488 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
10490 case 0x07: /* CMGE, CMHS */
10491 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
10493 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
10494 vec_full_reg_offset(s
, rn
),
10495 vec_full_reg_offset(s
, rm
),
10496 is_q
? 16 : 8, vec_full_reg_size(s
));
10502 for (pass
= 0; pass
< 2; pass
++) {
10503 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10504 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10505 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10507 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10508 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10510 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
10512 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10514 tcg_temp_free_i64(tcg_res
);
10515 tcg_temp_free_i64(tcg_op1
);
10516 tcg_temp_free_i64(tcg_op2
);
10519 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10520 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10521 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10522 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10523 NeonGenTwoOpFn
*genfn
= NULL
;
10524 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
10526 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
10527 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
10530 case 0x0: /* SHADD, UHADD */
10532 static NeonGenTwoOpFn
* const fns
[3][2] = {
10533 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
10534 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
10535 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
10537 genfn
= fns
[size
][u
];
10540 case 0x1: /* SQADD, UQADD */
10542 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10543 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
10544 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
10545 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
10547 genenvfn
= fns
[size
][u
];
10550 case 0x2: /* SRHADD, URHADD */
10552 static NeonGenTwoOpFn
* const fns
[3][2] = {
10553 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
10554 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
10555 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
10557 genfn
= fns
[size
][u
];
10560 case 0x4: /* SHSUB, UHSUB */
10562 static NeonGenTwoOpFn
* const fns
[3][2] = {
10563 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
10564 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
10565 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
10567 genfn
= fns
[size
][u
];
10570 case 0x5: /* SQSUB, UQSUB */
10572 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10573 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
10574 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
10575 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
10577 genenvfn
= fns
[size
][u
];
10580 case 0x8: /* SSHL, USHL */
10582 static NeonGenTwoOpFn
* const fns
[3][2] = {
10583 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
10584 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
10585 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
10587 genfn
= fns
[size
][u
];
10590 case 0x9: /* SQSHL, UQSHL */
10592 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10593 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
10594 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
10595 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
10597 genenvfn
= fns
[size
][u
];
10600 case 0xa: /* SRSHL, URSHL */
10602 static NeonGenTwoOpFn
* const fns
[3][2] = {
10603 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
10604 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
10605 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
10607 genfn
= fns
[size
][u
];
10610 case 0xb: /* SQRSHL, UQRSHL */
10612 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10613 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
10614 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
10615 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
10617 genenvfn
= fns
[size
][u
];
10620 case 0xc: /* SMAX, UMAX */
10622 static NeonGenTwoOpFn
* const fns
[3][2] = {
10623 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
10624 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
10625 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10627 genfn
= fns
[size
][u
];
10631 case 0xd: /* SMIN, UMIN */
10633 static NeonGenTwoOpFn
* const fns
[3][2] = {
10634 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
10635 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
10636 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10638 genfn
= fns
[size
][u
];
10641 case 0xe: /* SABD, UABD */
10642 case 0xf: /* SABA, UABA */
10644 static NeonGenTwoOpFn
* const fns
[3][2] = {
10645 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
10646 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
10647 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
10649 genfn
= fns
[size
][u
];
10652 case 0x13: /* MUL, PMUL */
10653 assert(u
); /* PMUL */
10655 genfn
= gen_helper_neon_mul_p8
;
10657 case 0x16: /* SQDMULH, SQRDMULH */
10659 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
10660 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
10661 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
10663 assert(size
== 1 || size
== 2);
10664 genenvfn
= fns
[size
- 1][u
];
10668 g_assert_not_reached();
10672 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
10674 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10677 if (opcode
== 0xf) {
10678 /* SABA, UABA: accumulating ops */
10679 static NeonGenTwoOpFn
* const fns
[3] = {
10680 gen_helper_neon_add_u8
,
10681 gen_helper_neon_add_u16
,
10685 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
10686 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
10689 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10691 tcg_temp_free_i32(tcg_res
);
10692 tcg_temp_free_i32(tcg_op1
);
10693 tcg_temp_free_i32(tcg_op2
);
10696 clear_vec_high(s
, is_q
, rd
);
10699 /* AdvSIMD three same
10700 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
10701 * +---+---+---+-----------+------+---+------+--------+---+------+------+
10702 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
10703 * +---+---+---+-----------+------+---+------+--------+---+------+------+
10705 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
10707 int opcode
= extract32(insn
, 11, 5);
10710 case 0x3: /* logic ops */
10711 disas_simd_3same_logic(s
, insn
);
10713 case 0x17: /* ADDP */
10714 case 0x14: /* SMAXP, UMAXP */
10715 case 0x15: /* SMINP, UMINP */
10717 /* Pairwise operations */
10718 int is_q
= extract32(insn
, 30, 1);
10719 int u
= extract32(insn
, 29, 1);
10720 int size
= extract32(insn
, 22, 2);
10721 int rm
= extract32(insn
, 16, 5);
10722 int rn
= extract32(insn
, 5, 5);
10723 int rd
= extract32(insn
, 0, 5);
10724 if (opcode
== 0x17) {
10725 if (u
|| (size
== 3 && !is_q
)) {
10726 unallocated_encoding(s
);
10731 unallocated_encoding(s
);
10735 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
10738 case 0x18 ... 0x31:
10739 /* floating point ops, sz[1] and U are part of opcode */
10740 disas_simd_3same_float(s
, insn
);
10743 disas_simd_3same_int(s
, insn
);
10749 * Advanced SIMD three same (ARMv8.2 FP16 variants)
10751 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
10752 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
10753 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
10754 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
10756 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
10757 * (register), FACGE, FABD, FCMGT (register) and FACGT.
10760 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
10762 int opcode
, fpopcode
;
10763 int is_q
, u
, a
, rm
, rn
, rd
;
10764 int datasize
, elements
;
10767 bool pairwise
= false;
10769 if (!dc_isar_feature(aa64_fp16
, s
)) {
10770 unallocated_encoding(s
);
10774 if (!fp_access_check(s
)) {
10778 /* For these floating point ops, the U, a and opcode bits
10779 * together indicate the operation.
10781 opcode
= extract32(insn
, 11, 3);
10782 u
= extract32(insn
, 29, 1);
10783 a
= extract32(insn
, 23, 1);
10784 is_q
= extract32(insn
, 30, 1);
10785 rm
= extract32(insn
, 16, 5);
10786 rn
= extract32(insn
, 5, 5);
10787 rd
= extract32(insn
, 0, 5);
10789 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
10790 datasize
= is_q
? 128 : 64;
10791 elements
= datasize
/ 16;
10793 switch (fpopcode
) {
10794 case 0x10: /* FMAXNMP */
10795 case 0x12: /* FADDP */
10796 case 0x16: /* FMAXP */
10797 case 0x18: /* FMINNMP */
10798 case 0x1e: /* FMINP */
10803 fpst
= get_fpstatus_ptr(true);
10806 int maxpass
= is_q
? 8 : 4;
10807 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10808 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10809 TCGv_i32 tcg_res
[8];
10811 for (pass
= 0; pass
< maxpass
; pass
++) {
10812 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10813 int passelt
= (pass
<< 1) & (maxpass
- 1);
10815 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
10816 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
10817 tcg_res
[pass
] = tcg_temp_new_i32();
10819 switch (fpopcode
) {
10820 case 0x10: /* FMAXNMP */
10821 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
10824 case 0x12: /* FADDP */
10825 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10827 case 0x16: /* FMAXP */
10828 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10830 case 0x18: /* FMINNMP */
10831 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
10834 case 0x1e: /* FMINP */
10835 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10838 g_assert_not_reached();
10842 for (pass
= 0; pass
< maxpass
; pass
++) {
10843 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
10844 tcg_temp_free_i32(tcg_res
[pass
]);
10847 tcg_temp_free_i32(tcg_op1
);
10848 tcg_temp_free_i32(tcg_op2
);
10851 for (pass
= 0; pass
< elements
; pass
++) {
10852 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10853 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10854 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10856 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
10857 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
10859 switch (fpopcode
) {
10860 case 0x0: /* FMAXNM */
10861 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10863 case 0x1: /* FMLA */
10864 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
10865 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
10868 case 0x2: /* FADD */
10869 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10871 case 0x3: /* FMULX */
10872 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10874 case 0x4: /* FCMEQ */
10875 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10877 case 0x6: /* FMAX */
10878 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10880 case 0x7: /* FRECPS */
10881 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10883 case 0x8: /* FMINNM */
10884 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10886 case 0x9: /* FMLS */
10887 /* As usual for ARM, separate negation for fused multiply-add */
10888 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
10889 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
10890 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
10893 case 0xa: /* FSUB */
10894 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10896 case 0xe: /* FMIN */
10897 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10899 case 0xf: /* FRSQRTS */
10900 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10902 case 0x13: /* FMUL */
10903 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10905 case 0x14: /* FCMGE */
10906 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10908 case 0x15: /* FACGE */
10909 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10911 case 0x17: /* FDIV */
10912 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10914 case 0x1a: /* FABD */
10915 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10916 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
10918 case 0x1c: /* FCMGT */
10919 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10921 case 0x1d: /* FACGT */
10922 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
10925 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
10926 __func__
, insn
, fpopcode
, s
->pc
);
10927 g_assert_not_reached();
10930 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
10931 tcg_temp_free_i32(tcg_res
);
10932 tcg_temp_free_i32(tcg_op1
);
10933 tcg_temp_free_i32(tcg_op2
);
10937 tcg_temp_free_ptr(fpst
);
10939 clear_vec_high(s
, is_q
, rd
);
10942 /* AdvSIMD three same extra
10943 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
10944 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
10945 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
10946 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
10948 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
10950 int rd
= extract32(insn
, 0, 5);
10951 int rn
= extract32(insn
, 5, 5);
10952 int opcode
= extract32(insn
, 11, 4);
10953 int rm
= extract32(insn
, 16, 5);
10954 int size
= extract32(insn
, 22, 2);
10955 bool u
= extract32(insn
, 29, 1);
10956 bool is_q
= extract32(insn
, 30, 1);
10960 switch (u
* 16 + opcode
) {
10961 case 0x10: /* SQRDMLAH (vector) */
10962 case 0x11: /* SQRDMLSH (vector) */
10963 if (size
!= 1 && size
!= 2) {
10964 unallocated_encoding(s
);
10967 feature
= dc_isar_feature(aa64_rdm
, s
);
10969 case 0x02: /* SDOT (vector) */
10970 case 0x12: /* UDOT (vector) */
10971 if (size
!= MO_32
) {
10972 unallocated_encoding(s
);
10975 feature
= dc_isar_feature(aa64_dp
, s
);
10977 case 0x18: /* FCMLA, #0 */
10978 case 0x19: /* FCMLA, #90 */
10979 case 0x1a: /* FCMLA, #180 */
10980 case 0x1b: /* FCMLA, #270 */
10981 case 0x1c: /* FCADD, #90 */
10982 case 0x1e: /* FCADD, #270 */
10984 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
10985 || (size
== 3 && !is_q
)) {
10986 unallocated_encoding(s
);
10989 feature
= dc_isar_feature(aa64_fcma
, s
);
10992 unallocated_encoding(s
);
10996 unallocated_encoding(s
);
10999 if (!fp_access_check(s
)) {
11004 case 0x0: /* SQRDMLAH (vector) */
11007 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11010 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11013 g_assert_not_reached();
11017 case 0x1: /* SQRDMLSH (vector) */
11020 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11023 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11026 g_assert_not_reached();
11030 case 0x2: /* SDOT / UDOT */
11031 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11032 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11035 case 0x8: /* FCMLA, #0 */
11036 case 0x9: /* FCMLA, #90 */
11037 case 0xa: /* FCMLA, #180 */
11038 case 0xb: /* FCMLA, #270 */
11039 rot
= extract32(opcode
, 0, 2);
11042 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11043 gen_helper_gvec_fcmlah
);
11046 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11047 gen_helper_gvec_fcmlas
);
11050 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11051 gen_helper_gvec_fcmlad
);
11054 g_assert_not_reached();
11058 case 0xc: /* FCADD, #90 */
11059 case 0xe: /* FCADD, #270 */
11060 rot
= extract32(opcode
, 1, 1);
11063 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11064 gen_helper_gvec_fcaddh
);
11067 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11068 gen_helper_gvec_fcadds
);
11071 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11072 gen_helper_gvec_fcaddd
);
11075 g_assert_not_reached();
11080 g_assert_not_reached();
11084 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11085 int size
, int rn
, int rd
)
11087 /* Handle 2-reg-misc ops which are widening (so each size element
11088 * in the source becomes a 2*size element in the destination.
11089 * The only instruction like this is FCVTL.
11094 /* 32 -> 64 bit fp conversion */
11095 TCGv_i64 tcg_res
[2];
11096 int srcelt
= is_q
? 2 : 0;
11098 for (pass
= 0; pass
< 2; pass
++) {
11099 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11100 tcg_res
[pass
] = tcg_temp_new_i64();
11102 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11103 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11104 tcg_temp_free_i32(tcg_op
);
11106 for (pass
= 0; pass
< 2; pass
++) {
11107 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11108 tcg_temp_free_i64(tcg_res
[pass
]);
11111 /* 16 -> 32 bit fp conversion */
11112 int srcelt
= is_q
? 4 : 0;
11113 TCGv_i32 tcg_res
[4];
11114 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11115 TCGv_i32 ahp
= get_ahp_flag();
11117 for (pass
= 0; pass
< 4; pass
++) {
11118 tcg_res
[pass
] = tcg_temp_new_i32();
11120 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11121 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11124 for (pass
= 0; pass
< 4; pass
++) {
11125 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11126 tcg_temp_free_i32(tcg_res
[pass
]);
11129 tcg_temp_free_ptr(fpst
);
11130 tcg_temp_free_i32(ahp
);
11134 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11135 bool is_q
, int size
, int rn
, int rd
)
11137 int op
= (opcode
<< 1) | u
;
11138 int opsz
= op
+ size
;
11139 int grp_size
= 3 - opsz
;
11140 int dsize
= is_q
? 128 : 64;
11144 unallocated_encoding(s
);
11148 if (!fp_access_check(s
)) {
11153 /* Special case bytes, use bswap op on each group of elements */
11154 int groups
= dsize
/ (8 << grp_size
);
11156 for (i
= 0; i
< groups
; i
++) {
11157 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11159 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11160 switch (grp_size
) {
11162 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11165 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11168 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11171 g_assert_not_reached();
11173 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11174 tcg_temp_free_i64(tcg_tmp
);
11176 clear_vec_high(s
, is_q
, rd
);
11178 int revmask
= (1 << grp_size
) - 1;
11179 int esize
= 8 << size
;
11180 int elements
= dsize
/ esize
;
11181 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11182 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11183 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11185 for (i
= 0; i
< elements
; i
++) {
11186 int e_rev
= (i
& 0xf) ^ revmask
;
11187 int off
= e_rev
* esize
;
11188 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11190 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11191 tcg_rn
, off
- 64, esize
);
11193 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11196 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11197 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11199 tcg_temp_free_i64(tcg_rd_hi
);
11200 tcg_temp_free_i64(tcg_rd
);
11201 tcg_temp_free_i64(tcg_rn
);
11205 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11206 bool is_q
, int size
, int rn
, int rd
)
11208 /* Implement the pairwise operations from 2-misc:
11209 * SADDLP, UADDLP, SADALP, UADALP.
11210 * These all add pairs of elements in the input to produce a
11211 * double-width result element in the output (possibly accumulating).
11213 bool accum
= (opcode
== 0x6);
11214 int maxpass
= is_q
? 2 : 1;
11216 TCGv_i64 tcg_res
[2];
11219 /* 32 + 32 -> 64 op */
11220 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11222 for (pass
= 0; pass
< maxpass
; pass
++) {
11223 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11224 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11226 tcg_res
[pass
] = tcg_temp_new_i64();
11228 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11229 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11230 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11232 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11233 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11236 tcg_temp_free_i64(tcg_op1
);
11237 tcg_temp_free_i64(tcg_op2
);
11240 for (pass
= 0; pass
< maxpass
; pass
++) {
11241 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11242 NeonGenOneOpFn
*genfn
;
11243 static NeonGenOneOpFn
* const fns
[2][2] = {
11244 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11245 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11248 genfn
= fns
[size
][u
];
11250 tcg_res
[pass
] = tcg_temp_new_i64();
11252 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11253 genfn(tcg_res
[pass
], tcg_op
);
11256 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11258 gen_helper_neon_addl_u16(tcg_res
[pass
],
11259 tcg_res
[pass
], tcg_op
);
11261 gen_helper_neon_addl_u32(tcg_res
[pass
],
11262 tcg_res
[pass
], tcg_op
);
11265 tcg_temp_free_i64(tcg_op
);
11269 tcg_res
[1] = tcg_const_i64(0);
11271 for (pass
= 0; pass
< 2; pass
++) {
11272 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11273 tcg_temp_free_i64(tcg_res
[pass
]);
11277 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11279 /* Implement SHLL and SHLL2 */
11281 int part
= is_q
? 2 : 0;
11282 TCGv_i64 tcg_res
[2];
11284 for (pass
= 0; pass
< 2; pass
++) {
11285 static NeonGenWidenFn
* const widenfns
[3] = {
11286 gen_helper_neon_widen_u8
,
11287 gen_helper_neon_widen_u16
,
11288 tcg_gen_extu_i32_i64
,
11290 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11291 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11293 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11294 tcg_res
[pass
] = tcg_temp_new_i64();
11295 widenfn(tcg_res
[pass
], tcg_op
);
11296 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11298 tcg_temp_free_i32(tcg_op
);
11301 for (pass
= 0; pass
< 2; pass
++) {
11302 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11303 tcg_temp_free_i64(tcg_res
[pass
]);
11307 /* AdvSIMD two reg misc
11308 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11309 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11310 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11311 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11313 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11315 int size
= extract32(insn
, 22, 2);
11316 int opcode
= extract32(insn
, 12, 5);
11317 bool u
= extract32(insn
, 29, 1);
11318 bool is_q
= extract32(insn
, 30, 1);
11319 int rn
= extract32(insn
, 5, 5);
11320 int rd
= extract32(insn
, 0, 5);
11321 bool need_fpstatus
= false;
11322 bool need_rmode
= false;
11324 TCGv_i32 tcg_rmode
;
11325 TCGv_ptr tcg_fpstatus
;
11328 case 0x0: /* REV64, REV32 */
11329 case 0x1: /* REV16 */
11330 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11332 case 0x5: /* CNT, NOT, RBIT */
11333 if (u
&& size
== 0) {
11336 } else if (u
&& size
== 1) {
11339 } else if (!u
&& size
== 0) {
11343 unallocated_encoding(s
);
11345 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11346 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11348 unallocated_encoding(s
);
11351 if (!fp_access_check(s
)) {
11355 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11357 case 0x4: /* CLS, CLZ */
11359 unallocated_encoding(s
);
11363 case 0x2: /* SADDLP, UADDLP */
11364 case 0x6: /* SADALP, UADALP */
11366 unallocated_encoding(s
);
11369 if (!fp_access_check(s
)) {
11372 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11374 case 0x13: /* SHLL, SHLL2 */
11375 if (u
== 0 || size
== 3) {
11376 unallocated_encoding(s
);
11379 if (!fp_access_check(s
)) {
11382 handle_shll(s
, is_q
, size
, rn
, rd
);
11384 case 0xa: /* CMLT */
11386 unallocated_encoding(s
);
11390 case 0x8: /* CMGT, CMGE */
11391 case 0x9: /* CMEQ, CMLE */
11392 case 0xb: /* ABS, NEG */
11393 if (size
== 3 && !is_q
) {
11394 unallocated_encoding(s
);
11398 case 0x3: /* SUQADD, USQADD */
11399 if (size
== 3 && !is_q
) {
11400 unallocated_encoding(s
);
11403 if (!fp_access_check(s
)) {
11406 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11408 case 0x7: /* SQABS, SQNEG */
11409 if (size
== 3 && !is_q
) {
11410 unallocated_encoding(s
);
11415 case 0x16 ... 0x1d:
11418 /* Floating point: U, size[1] and opcode indicate operation;
11419 * size[0] indicates single or double precision.
11421 int is_double
= extract32(size
, 0, 1);
11422 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11423 size
= is_double
? 3 : 2;
11425 case 0x2f: /* FABS */
11426 case 0x6f: /* FNEG */
11427 if (size
== 3 && !is_q
) {
11428 unallocated_encoding(s
);
11432 case 0x1d: /* SCVTF */
11433 case 0x5d: /* UCVTF */
11435 bool is_signed
= (opcode
== 0x1d) ? true : false;
11436 int elements
= is_double
? 2 : is_q
? 4 : 2;
11437 if (is_double
&& !is_q
) {
11438 unallocated_encoding(s
);
11441 if (!fp_access_check(s
)) {
11444 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11447 case 0x2c: /* FCMGT (zero) */
11448 case 0x2d: /* FCMEQ (zero) */
11449 case 0x2e: /* FCMLT (zero) */
11450 case 0x6c: /* FCMGE (zero) */
11451 case 0x6d: /* FCMLE (zero) */
11452 if (size
== 3 && !is_q
) {
11453 unallocated_encoding(s
);
11456 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11458 case 0x7f: /* FSQRT */
11459 if (size
== 3 && !is_q
) {
11460 unallocated_encoding(s
);
11464 case 0x1a: /* FCVTNS */
11465 case 0x1b: /* FCVTMS */
11466 case 0x3a: /* FCVTPS */
11467 case 0x3b: /* FCVTZS */
11468 case 0x5a: /* FCVTNU */
11469 case 0x5b: /* FCVTMU */
11470 case 0x7a: /* FCVTPU */
11471 case 0x7b: /* FCVTZU */
11472 need_fpstatus
= true;
11474 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11475 if (size
== 3 && !is_q
) {
11476 unallocated_encoding(s
);
11480 case 0x5c: /* FCVTAU */
11481 case 0x1c: /* FCVTAS */
11482 need_fpstatus
= true;
11484 rmode
= FPROUNDING_TIEAWAY
;
11485 if (size
== 3 && !is_q
) {
11486 unallocated_encoding(s
);
11490 case 0x3c: /* URECPE */
11492 unallocated_encoding(s
);
11496 case 0x3d: /* FRECPE */
11497 case 0x7d: /* FRSQRTE */
11498 if (size
== 3 && !is_q
) {
11499 unallocated_encoding(s
);
11502 if (!fp_access_check(s
)) {
11505 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11507 case 0x56: /* FCVTXN, FCVTXN2 */
11509 unallocated_encoding(s
);
11513 case 0x16: /* FCVTN, FCVTN2 */
11514 /* handle_2misc_narrow does a 2*size -> size operation, but these
11515 * instructions encode the source size rather than dest size.
11517 if (!fp_access_check(s
)) {
11520 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
11522 case 0x17: /* FCVTL, FCVTL2 */
11523 if (!fp_access_check(s
)) {
11526 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
11528 case 0x18: /* FRINTN */
11529 case 0x19: /* FRINTM */
11530 case 0x38: /* FRINTP */
11531 case 0x39: /* FRINTZ */
11533 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11535 case 0x59: /* FRINTX */
11536 case 0x79: /* FRINTI */
11537 need_fpstatus
= true;
11538 if (size
== 3 && !is_q
) {
11539 unallocated_encoding(s
);
11543 case 0x58: /* FRINTA */
11545 rmode
= FPROUNDING_TIEAWAY
;
11546 need_fpstatus
= true;
11547 if (size
== 3 && !is_q
) {
11548 unallocated_encoding(s
);
11552 case 0x7c: /* URSQRTE */
11554 unallocated_encoding(s
);
11557 need_fpstatus
= true;
11560 unallocated_encoding(s
);
11566 unallocated_encoding(s
);
11570 if (!fp_access_check(s
)) {
11574 if (need_fpstatus
|| need_rmode
) {
11575 tcg_fpstatus
= get_fpstatus_ptr(false);
11577 tcg_fpstatus
= NULL
;
11580 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
11581 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
11588 if (u
&& size
== 0) { /* NOT */
11589 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
11595 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
11602 /* All 64-bit element operations can be shared with scalar 2misc */
11605 /* Coverity claims (size == 3 && !is_q) has been eliminated
11606 * from all paths leading to here.
11608 tcg_debug_assert(is_q
);
11609 for (pass
= 0; pass
< 2; pass
++) {
11610 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11611 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11613 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11615 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
11616 tcg_rmode
, tcg_fpstatus
);
11618 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11620 tcg_temp_free_i64(tcg_res
);
11621 tcg_temp_free_i64(tcg_op
);
11626 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11627 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11628 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11631 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
11634 /* Special cases for 32 bit elements */
11636 case 0xa: /* CMLT */
11637 /* 32 bit integer comparison against zero, result is
11638 * test ? (2^32 - 1) : 0. We implement via setcond(test)
11641 cond
= TCG_COND_LT
;
11643 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
11644 tcg_gen_neg_i32(tcg_res
, tcg_res
);
11646 case 0x8: /* CMGT, CMGE */
11647 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
11649 case 0x9: /* CMEQ, CMLE */
11650 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
11652 case 0x4: /* CLS */
11654 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
11656 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
11659 case 0x7: /* SQABS, SQNEG */
11661 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
11663 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
11666 case 0xb: /* ABS, NEG */
11668 tcg_gen_neg_i32(tcg_res
, tcg_op
);
11670 TCGv_i32 tcg_zero
= tcg_const_i32(0);
11671 tcg_gen_neg_i32(tcg_res
, tcg_op
);
11672 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
11673 tcg_zero
, tcg_op
, tcg_res
);
11674 tcg_temp_free_i32(tcg_zero
);
11677 case 0x2f: /* FABS */
11678 gen_helper_vfp_abss(tcg_res
, tcg_op
);
11680 case 0x6f: /* FNEG */
11681 gen_helper_vfp_negs(tcg_res
, tcg_op
);
11683 case 0x7f: /* FSQRT */
11684 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
11686 case 0x1a: /* FCVTNS */
11687 case 0x1b: /* FCVTMS */
11688 case 0x1c: /* FCVTAS */
11689 case 0x3a: /* FCVTPS */
11690 case 0x3b: /* FCVTZS */
11692 TCGv_i32 tcg_shift
= tcg_const_i32(0);
11693 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
11694 tcg_shift
, tcg_fpstatus
);
11695 tcg_temp_free_i32(tcg_shift
);
11698 case 0x5a: /* FCVTNU */
11699 case 0x5b: /* FCVTMU */
11700 case 0x5c: /* FCVTAU */
11701 case 0x7a: /* FCVTPU */
11702 case 0x7b: /* FCVTZU */
11704 TCGv_i32 tcg_shift
= tcg_const_i32(0);
11705 gen_helper_vfp_touls(tcg_res
, tcg_op
,
11706 tcg_shift
, tcg_fpstatus
);
11707 tcg_temp_free_i32(tcg_shift
);
11710 case 0x18: /* FRINTN */
11711 case 0x19: /* FRINTM */
11712 case 0x38: /* FRINTP */
11713 case 0x39: /* FRINTZ */
11714 case 0x58: /* FRINTA */
11715 case 0x79: /* FRINTI */
11716 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
11718 case 0x59: /* FRINTX */
11719 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
11721 case 0x7c: /* URSQRTE */
11722 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
11725 g_assert_not_reached();
11728 /* Use helpers for 8 and 16 bit elements */
11730 case 0x5: /* CNT, RBIT */
11731 /* For these two insns size is part of the opcode specifier
11732 * (handled earlier); they always operate on byte elements.
11735 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
11737 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
11740 case 0x7: /* SQABS, SQNEG */
11742 NeonGenOneOpEnvFn
*genfn
;
11743 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
11744 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
11745 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
11747 genfn
= fns
[size
][u
];
11748 genfn(tcg_res
, cpu_env
, tcg_op
);
11751 case 0x8: /* CMGT, CMGE */
11752 case 0x9: /* CMEQ, CMLE */
11753 case 0xa: /* CMLT */
11755 static NeonGenTwoOpFn
* const fns
[3][2] = {
11756 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
11757 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
11758 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
11760 NeonGenTwoOpFn
*genfn
;
11763 TCGv_i32 tcg_zero
= tcg_const_i32(0);
11765 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
11766 comp
= (opcode
- 0x8) * 2 + u
;
11767 /* ...but LE, LT are implemented as reverse GE, GT */
11768 reverse
= (comp
> 2);
11772 genfn
= fns
[comp
][size
];
11774 genfn(tcg_res
, tcg_zero
, tcg_op
);
11776 genfn(tcg_res
, tcg_op
, tcg_zero
);
11778 tcg_temp_free_i32(tcg_zero
);
11781 case 0xb: /* ABS, NEG */
11783 TCGv_i32 tcg_zero
= tcg_const_i32(0);
11785 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
11787 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
11789 tcg_temp_free_i32(tcg_zero
);
11792 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
11794 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
11798 case 0x4: /* CLS, CLZ */
11801 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
11803 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
11807 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
11809 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
11814 g_assert_not_reached();
11818 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11820 tcg_temp_free_i32(tcg_res
);
11821 tcg_temp_free_i32(tcg_op
);
11824 clear_vec_high(s
, is_q
, rd
);
11827 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
11828 tcg_temp_free_i32(tcg_rmode
);
11830 if (need_fpstatus
) {
11831 tcg_temp_free_ptr(tcg_fpstatus
);
11835 /* AdvSIMD [scalar] two register miscellaneous (FP16)
11837 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
11838 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
11839 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
11840 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
11841 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
11842 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
11844 * This actually covers two groups where scalar access is governed by
11845 * bit 28. A bunch of the instructions (float to integral) only exist
11846 * in the vector form and are un-allocated for the scalar decode. Also
11847 * in the scalar decode Q is always 1.
11849 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
11851 int fpop
, opcode
, a
, u
;
11855 bool only_in_vector
= false;
11858 TCGv_i32 tcg_rmode
= NULL
;
11859 TCGv_ptr tcg_fpstatus
= NULL
;
11860 bool need_rmode
= false;
11861 bool need_fpst
= true;
11864 if (!dc_isar_feature(aa64_fp16
, s
)) {
11865 unallocated_encoding(s
);
11869 rd
= extract32(insn
, 0, 5);
11870 rn
= extract32(insn
, 5, 5);
11872 a
= extract32(insn
, 23, 1);
11873 u
= extract32(insn
, 29, 1);
11874 is_scalar
= extract32(insn
, 28, 1);
11875 is_q
= extract32(insn
, 30, 1);
11877 opcode
= extract32(insn
, 12, 5);
11878 fpop
= deposit32(opcode
, 5, 1, a
);
11879 fpop
= deposit32(fpop
, 6, 1, u
);
11881 rd
= extract32(insn
, 0, 5);
11882 rn
= extract32(insn
, 5, 5);
11885 case 0x1d: /* SCVTF */
11886 case 0x5d: /* UCVTF */
11893 elements
= (is_q
? 8 : 4);
11896 if (!fp_access_check(s
)) {
11899 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
11903 case 0x2c: /* FCMGT (zero) */
11904 case 0x2d: /* FCMEQ (zero) */
11905 case 0x2e: /* FCMLT (zero) */
11906 case 0x6c: /* FCMGE (zero) */
11907 case 0x6d: /* FCMLE (zero) */
11908 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
11910 case 0x3d: /* FRECPE */
11911 case 0x3f: /* FRECPX */
11913 case 0x18: /* FRINTN */
11915 only_in_vector
= true;
11916 rmode
= FPROUNDING_TIEEVEN
;
11918 case 0x19: /* FRINTM */
11920 only_in_vector
= true;
11921 rmode
= FPROUNDING_NEGINF
;
11923 case 0x38: /* FRINTP */
11925 only_in_vector
= true;
11926 rmode
= FPROUNDING_POSINF
;
11928 case 0x39: /* FRINTZ */
11930 only_in_vector
= true;
11931 rmode
= FPROUNDING_ZERO
;
11933 case 0x58: /* FRINTA */
11935 only_in_vector
= true;
11936 rmode
= FPROUNDING_TIEAWAY
;
11938 case 0x59: /* FRINTX */
11939 case 0x79: /* FRINTI */
11940 only_in_vector
= true;
11941 /* current rounding mode */
11943 case 0x1a: /* FCVTNS */
11945 rmode
= FPROUNDING_TIEEVEN
;
11947 case 0x1b: /* FCVTMS */
11949 rmode
= FPROUNDING_NEGINF
;
11951 case 0x1c: /* FCVTAS */
11953 rmode
= FPROUNDING_TIEAWAY
;
11955 case 0x3a: /* FCVTPS */
11957 rmode
= FPROUNDING_POSINF
;
11959 case 0x3b: /* FCVTZS */
11961 rmode
= FPROUNDING_ZERO
;
11963 case 0x5a: /* FCVTNU */
11965 rmode
= FPROUNDING_TIEEVEN
;
11967 case 0x5b: /* FCVTMU */
11969 rmode
= FPROUNDING_NEGINF
;
11971 case 0x5c: /* FCVTAU */
11973 rmode
= FPROUNDING_TIEAWAY
;
11975 case 0x7a: /* FCVTPU */
11977 rmode
= FPROUNDING_POSINF
;
11979 case 0x7b: /* FCVTZU */
11981 rmode
= FPROUNDING_ZERO
;
11983 case 0x2f: /* FABS */
11984 case 0x6f: /* FNEG */
11987 case 0x7d: /* FRSQRTE */
11988 case 0x7f: /* FSQRT (vector) */
11991 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
11992 g_assert_not_reached();
11996 /* Check additional constraints for the scalar encoding */
11999 unallocated_encoding(s
);
12002 /* FRINTxx is only in the vector form */
12003 if (only_in_vector
) {
12004 unallocated_encoding(s
);
12009 if (!fp_access_check(s
)) {
12013 if (need_rmode
|| need_fpst
) {
12014 tcg_fpstatus
= get_fpstatus_ptr(true);
12018 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12019 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12023 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12024 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12027 case 0x1a: /* FCVTNS */
12028 case 0x1b: /* FCVTMS */
12029 case 0x1c: /* FCVTAS */
12030 case 0x3a: /* FCVTPS */
12031 case 0x3b: /* FCVTZS */
12032 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12034 case 0x3d: /* FRECPE */
12035 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12037 case 0x3f: /* FRECPX */
12038 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12040 case 0x5a: /* FCVTNU */
12041 case 0x5b: /* FCVTMU */
12042 case 0x5c: /* FCVTAU */
12043 case 0x7a: /* FCVTPU */
12044 case 0x7b: /* FCVTZU */
12045 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12047 case 0x6f: /* FNEG */
12048 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12050 case 0x7d: /* FRSQRTE */
12051 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12054 g_assert_not_reached();
12057 /* limit any sign extension going on */
12058 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12059 write_fp_sreg(s
, rd
, tcg_res
);
12061 tcg_temp_free_i32(tcg_res
);
12062 tcg_temp_free_i32(tcg_op
);
12064 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12065 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12066 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12068 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12071 case 0x1a: /* FCVTNS */
12072 case 0x1b: /* FCVTMS */
12073 case 0x1c: /* FCVTAS */
12074 case 0x3a: /* FCVTPS */
12075 case 0x3b: /* FCVTZS */
12076 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12078 case 0x3d: /* FRECPE */
12079 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12081 case 0x5a: /* FCVTNU */
12082 case 0x5b: /* FCVTMU */
12083 case 0x5c: /* FCVTAU */
12084 case 0x7a: /* FCVTPU */
12085 case 0x7b: /* FCVTZU */
12086 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12088 case 0x18: /* FRINTN */
12089 case 0x19: /* FRINTM */
12090 case 0x38: /* FRINTP */
12091 case 0x39: /* FRINTZ */
12092 case 0x58: /* FRINTA */
12093 case 0x79: /* FRINTI */
12094 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12096 case 0x59: /* FRINTX */
12097 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12099 case 0x2f: /* FABS */
12100 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12102 case 0x6f: /* FNEG */
12103 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12105 case 0x7d: /* FRSQRTE */
12106 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12108 case 0x7f: /* FSQRT */
12109 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12112 g_assert_not_reached();
12115 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12117 tcg_temp_free_i32(tcg_res
);
12118 tcg_temp_free_i32(tcg_op
);
12121 clear_vec_high(s
, is_q
, rd
);
12125 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12126 tcg_temp_free_i32(tcg_rmode
);
12129 if (tcg_fpstatus
) {
12130 tcg_temp_free_ptr(tcg_fpstatus
);
12134 /* AdvSIMD scalar x indexed element
12135 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12136 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12137 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12138 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12139 * AdvSIMD vector x indexed element
12140 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12141 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12142 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12143 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12145 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12147 /* This encoding has two kinds of instruction:
12148 * normal, where we perform elt x idxelt => elt for each
12149 * element in the vector
12150 * long, where we perform elt x idxelt and generate a result of
12151 * double the width of the input element
12152 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12154 bool is_scalar
= extract32(insn
, 28, 1);
12155 bool is_q
= extract32(insn
, 30, 1);
12156 bool u
= extract32(insn
, 29, 1);
12157 int size
= extract32(insn
, 22, 2);
12158 int l
= extract32(insn
, 21, 1);
12159 int m
= extract32(insn
, 20, 1);
12160 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12161 int rm
= extract32(insn
, 16, 4);
12162 int opcode
= extract32(insn
, 12, 4);
12163 int h
= extract32(insn
, 11, 1);
12164 int rn
= extract32(insn
, 5, 5);
12165 int rd
= extract32(insn
, 0, 5);
12166 bool is_long
= false;
12168 bool is_fp16
= false;
12172 switch (16 * u
+ opcode
) {
12173 case 0x08: /* MUL */
12174 case 0x10: /* MLA */
12175 case 0x14: /* MLS */
12177 unallocated_encoding(s
);
12181 case 0x02: /* SMLAL, SMLAL2 */
12182 case 0x12: /* UMLAL, UMLAL2 */
12183 case 0x06: /* SMLSL, SMLSL2 */
12184 case 0x16: /* UMLSL, UMLSL2 */
12185 case 0x0a: /* SMULL, SMULL2 */
12186 case 0x1a: /* UMULL, UMULL2 */
12188 unallocated_encoding(s
);
12193 case 0x03: /* SQDMLAL, SQDMLAL2 */
12194 case 0x07: /* SQDMLSL, SQDMLSL2 */
12195 case 0x0b: /* SQDMULL, SQDMULL2 */
12198 case 0x0c: /* SQDMULH */
12199 case 0x0d: /* SQRDMULH */
12201 case 0x01: /* FMLA */
12202 case 0x05: /* FMLS */
12203 case 0x09: /* FMUL */
12204 case 0x19: /* FMULX */
12207 case 0x1d: /* SQRDMLAH */
12208 case 0x1f: /* SQRDMLSH */
12209 if (!dc_isar_feature(aa64_rdm
, s
)) {
12210 unallocated_encoding(s
);
12214 case 0x0e: /* SDOT */
12215 case 0x1e: /* UDOT */
12216 if (size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12217 unallocated_encoding(s
);
12221 case 0x11: /* FCMLA #0 */
12222 case 0x13: /* FCMLA #90 */
12223 case 0x15: /* FCMLA #180 */
12224 case 0x17: /* FCMLA #270 */
12225 if (!dc_isar_feature(aa64_fcma
, s
)) {
12226 unallocated_encoding(s
);
12232 unallocated_encoding(s
);
12237 case 1: /* normal fp */
12238 /* convert insn encoded size to TCGMemOp size */
12240 case 0: /* half-precision */
12244 case MO_32
: /* single precision */
12245 case MO_64
: /* double precision */
12248 unallocated_encoding(s
);
12253 case 2: /* complex fp */
12254 /* Each indexable element is a complex pair. */
12259 unallocated_encoding(s
);
12267 unallocated_encoding(s
);
12272 default: /* integer */
12276 unallocated_encoding(s
);
12281 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12282 unallocated_encoding(s
);
12286 /* Given TCGMemOp size, adjust register and indexing. */
12289 index
= h
<< 2 | l
<< 1 | m
;
12292 index
= h
<< 1 | l
;
12297 unallocated_encoding(s
);
12304 g_assert_not_reached();
12307 if (!fp_access_check(s
)) {
12312 fpst
= get_fpstatus_ptr(is_fp16
);
12317 switch (16 * u
+ opcode
) {
12318 case 0x0e: /* SDOT */
12319 case 0x1e: /* UDOT */
12320 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12321 u
? gen_helper_gvec_udot_idx_b
12322 : gen_helper_gvec_sdot_idx_b
);
12324 case 0x11: /* FCMLA #0 */
12325 case 0x13: /* FCMLA #90 */
12326 case 0x15: /* FCMLA #180 */
12327 case 0x17: /* FCMLA #270 */
12329 int rot
= extract32(insn
, 13, 2);
12330 int data
= (index
<< 2) | rot
;
12331 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12332 vec_full_reg_offset(s
, rn
),
12333 vec_full_reg_offset(s
, rm
), fpst
,
12334 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12336 ? gen_helper_gvec_fcmlas_idx
12337 : gen_helper_gvec_fcmlah_idx
);
12338 tcg_temp_free_ptr(fpst
);
12344 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12347 assert(is_fp
&& is_q
&& !is_long
);
12349 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12351 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12352 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12353 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12355 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12357 switch (16 * u
+ opcode
) {
12358 case 0x05: /* FMLS */
12359 /* As usual for ARM, separate negation for fused multiply-add */
12360 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12362 case 0x01: /* FMLA */
12363 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12364 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12366 case 0x09: /* FMUL */
12367 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12369 case 0x19: /* FMULX */
12370 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12373 g_assert_not_reached();
12376 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12377 tcg_temp_free_i64(tcg_op
);
12378 tcg_temp_free_i64(tcg_res
);
12381 tcg_temp_free_i64(tcg_idx
);
12382 clear_vec_high(s
, !is_scalar
, rd
);
12383 } else if (!is_long
) {
12384 /* 32 bit floating point, or 16 or 32 bit integer.
12385 * For the 16 bit scalar case we use the usual Neon helpers and
12386 * rely on the fact that 0 op 0 == 0 with no side effects.
12388 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12389 int pass
, maxpasses
;
12394 maxpasses
= is_q
? 4 : 2;
12397 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12399 if (size
== 1 && !is_scalar
) {
12400 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12401 * the index into both halves of the 32 bit tcg_idx and then use
12402 * the usual Neon helpers.
12404 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12407 for (pass
= 0; pass
< maxpasses
; pass
++) {
12408 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12409 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12411 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12413 switch (16 * u
+ opcode
) {
12414 case 0x08: /* MUL */
12415 case 0x10: /* MLA */
12416 case 0x14: /* MLS */
12418 static NeonGenTwoOpFn
* const fns
[2][2] = {
12419 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12420 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12422 NeonGenTwoOpFn
*genfn
;
12423 bool is_sub
= opcode
== 0x4;
12426 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
12428 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
12430 if (opcode
== 0x8) {
12433 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
12434 genfn
= fns
[size
- 1][is_sub
];
12435 genfn(tcg_res
, tcg_op
, tcg_res
);
12438 case 0x05: /* FMLS */
12439 case 0x01: /* FMLA */
12440 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12441 is_scalar
? size
: MO_32
);
12444 if (opcode
== 0x5) {
12445 /* As usual for ARM, separate negation for fused
12447 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
12450 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
12453 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
12458 if (opcode
== 0x5) {
12459 /* As usual for ARM, separate negation for
12460 * fused multiply-add */
12461 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
12463 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
12467 g_assert_not_reached();
12470 case 0x09: /* FMUL */
12474 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
12477 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
12482 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12485 g_assert_not_reached();
12488 case 0x19: /* FMULX */
12492 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
12495 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
12500 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12503 g_assert_not_reached();
12506 case 0x0c: /* SQDMULH */
12508 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
12511 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
12515 case 0x0d: /* SQRDMULH */
12517 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
12520 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
12524 case 0x1d: /* SQRDMLAH */
12525 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12526 is_scalar
? size
: MO_32
);
12528 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
12529 tcg_op
, tcg_idx
, tcg_res
);
12531 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
12532 tcg_op
, tcg_idx
, tcg_res
);
12535 case 0x1f: /* SQRDMLSH */
12536 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12537 is_scalar
? size
: MO_32
);
12539 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
12540 tcg_op
, tcg_idx
, tcg_res
);
12542 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
12543 tcg_op
, tcg_idx
, tcg_res
);
12547 g_assert_not_reached();
12551 write_fp_sreg(s
, rd
, tcg_res
);
12553 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12556 tcg_temp_free_i32(tcg_op
);
12557 tcg_temp_free_i32(tcg_res
);
12560 tcg_temp_free_i32(tcg_idx
);
12561 clear_vec_high(s
, is_q
, rd
);
12563 /* long ops: 16x16->32 or 32x32->64 */
12564 TCGv_i64 tcg_res
[2];
12566 bool satop
= extract32(opcode
, 0, 1);
12567 TCGMemOp memop
= MO_32
;
12574 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12576 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
12578 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12579 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12580 TCGv_i64 tcg_passres
;
12586 passelt
= pass
+ (is_q
* 2);
12589 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
12591 tcg_res
[pass
] = tcg_temp_new_i64();
12593 if (opcode
== 0xa || opcode
== 0xb) {
12594 /* Non-accumulating ops */
12595 tcg_passres
= tcg_res
[pass
];
12597 tcg_passres
= tcg_temp_new_i64();
12600 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
12601 tcg_temp_free_i64(tcg_op
);
12604 /* saturating, doubling */
12605 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
12606 tcg_passres
, tcg_passres
);
12609 if (opcode
== 0xa || opcode
== 0xb) {
12613 /* Accumulating op: handle accumulate step */
12614 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12617 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
12618 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
12620 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
12621 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
12623 case 0x7: /* SQDMLSL, SQDMLSL2 */
12624 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
12626 case 0x3: /* SQDMLAL, SQDMLAL2 */
12627 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
12632 g_assert_not_reached();
12634 tcg_temp_free_i64(tcg_passres
);
12636 tcg_temp_free_i64(tcg_idx
);
12638 clear_vec_high(s
, !is_scalar
, rd
);
12640 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12643 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12646 /* The simplest way to handle the 16x16 indexed ops is to
12647 * duplicate the index into both halves of the 32 bit tcg_idx
12648 * and then use the usual Neon helpers.
12650 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12653 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12654 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12655 TCGv_i64 tcg_passres
;
12658 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
12660 read_vec_element_i32(s
, tcg_op
, rn
,
12661 pass
+ (is_q
* 2), MO_32
);
12664 tcg_res
[pass
] = tcg_temp_new_i64();
12666 if (opcode
== 0xa || opcode
== 0xb) {
12667 /* Non-accumulating ops */
12668 tcg_passres
= tcg_res
[pass
];
12670 tcg_passres
= tcg_temp_new_i64();
12673 if (memop
& MO_SIGN
) {
12674 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
12676 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
12679 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
12680 tcg_passres
, tcg_passres
);
12682 tcg_temp_free_i32(tcg_op
);
12684 if (opcode
== 0xa || opcode
== 0xb) {
12688 /* Accumulating op: handle accumulate step */
12689 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12692 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
12693 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
12696 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
12697 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
12700 case 0x7: /* SQDMLSL, SQDMLSL2 */
12701 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
12703 case 0x3: /* SQDMLAL, SQDMLAL2 */
12704 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
12709 g_assert_not_reached();
12711 tcg_temp_free_i64(tcg_passres
);
12713 tcg_temp_free_i32(tcg_idx
);
12716 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
12721 tcg_res
[1] = tcg_const_i64(0);
12724 for (pass
= 0; pass
< 2; pass
++) {
12725 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12726 tcg_temp_free_i64(tcg_res
[pass
]);
12731 tcg_temp_free_ptr(fpst
);
12736 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
12737 * +-----------------+------+-----------+--------+-----+------+------+
12738 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
12739 * +-----------------+------+-----------+--------+-----+------+------+
12741 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
12743 int size
= extract32(insn
, 22, 2);
12744 int opcode
= extract32(insn
, 12, 5);
12745 int rn
= extract32(insn
, 5, 5);
12746 int rd
= extract32(insn
, 0, 5);
12748 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
12749 TCGv_i32 tcg_decrypt
;
12750 CryptoThreeOpIntFn
*genfn
;
12752 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
12753 unallocated_encoding(s
);
12758 case 0x4: /* AESE */
12760 genfn
= gen_helper_crypto_aese
;
12762 case 0x6: /* AESMC */
12764 genfn
= gen_helper_crypto_aesmc
;
12766 case 0x5: /* AESD */
12768 genfn
= gen_helper_crypto_aese
;
12770 case 0x7: /* AESIMC */
12772 genfn
= gen_helper_crypto_aesmc
;
12775 unallocated_encoding(s
);
12779 if (!fp_access_check(s
)) {
12783 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
12784 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
12785 tcg_decrypt
= tcg_const_i32(decrypt
);
12787 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
12789 tcg_temp_free_ptr(tcg_rd_ptr
);
12790 tcg_temp_free_ptr(tcg_rn_ptr
);
12791 tcg_temp_free_i32(tcg_decrypt
);
12794 /* Crypto three-reg SHA
12795 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
12796 * +-----------------+------+---+------+---+--------+-----+------+------+
12797 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
12798 * +-----------------+------+---+------+---+--------+-----+------+------+
12800 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
12802 int size
= extract32(insn
, 22, 2);
12803 int opcode
= extract32(insn
, 12, 3);
12804 int rm
= extract32(insn
, 16, 5);
12805 int rn
= extract32(insn
, 5, 5);
12806 int rd
= extract32(insn
, 0, 5);
12807 CryptoThreeOpFn
*genfn
;
12808 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
12812 unallocated_encoding(s
);
12817 case 0: /* SHA1C */
12818 case 1: /* SHA1P */
12819 case 2: /* SHA1M */
12820 case 3: /* SHA1SU0 */
12822 feature
= dc_isar_feature(aa64_sha1
, s
);
12824 case 4: /* SHA256H */
12825 genfn
= gen_helper_crypto_sha256h
;
12826 feature
= dc_isar_feature(aa64_sha256
, s
);
12828 case 5: /* SHA256H2 */
12829 genfn
= gen_helper_crypto_sha256h2
;
12830 feature
= dc_isar_feature(aa64_sha256
, s
);
12832 case 6: /* SHA256SU1 */
12833 genfn
= gen_helper_crypto_sha256su1
;
12834 feature
= dc_isar_feature(aa64_sha256
, s
);
12837 unallocated_encoding(s
);
12842 unallocated_encoding(s
);
12846 if (!fp_access_check(s
)) {
12850 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
12851 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
12852 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
12855 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
12857 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
12859 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
12860 tcg_rm_ptr
, tcg_opcode
);
12861 tcg_temp_free_i32(tcg_opcode
);
12864 tcg_temp_free_ptr(tcg_rd_ptr
);
12865 tcg_temp_free_ptr(tcg_rn_ptr
);
12866 tcg_temp_free_ptr(tcg_rm_ptr
);
12869 /* Crypto two-reg SHA
12870 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
12871 * +-----------------+------+-----------+--------+-----+------+------+
12872 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
12873 * +-----------------+------+-----------+--------+-----+------+------+
12875 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
12877 int size
= extract32(insn
, 22, 2);
12878 int opcode
= extract32(insn
, 12, 5);
12879 int rn
= extract32(insn
, 5, 5);
12880 int rd
= extract32(insn
, 0, 5);
12881 CryptoTwoOpFn
*genfn
;
12883 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
12886 unallocated_encoding(s
);
12891 case 0: /* SHA1H */
12892 feature
= dc_isar_feature(aa64_sha1
, s
);
12893 genfn
= gen_helper_crypto_sha1h
;
12895 case 1: /* SHA1SU1 */
12896 feature
= dc_isar_feature(aa64_sha1
, s
);
12897 genfn
= gen_helper_crypto_sha1su1
;
12899 case 2: /* SHA256SU0 */
12900 feature
= dc_isar_feature(aa64_sha256
, s
);
12901 genfn
= gen_helper_crypto_sha256su0
;
12904 unallocated_encoding(s
);
12909 unallocated_encoding(s
);
12913 if (!fp_access_check(s
)) {
12917 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
12918 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
12920 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
12922 tcg_temp_free_ptr(tcg_rd_ptr
);
12923 tcg_temp_free_ptr(tcg_rn_ptr
);
12926 /* Crypto three-reg SHA512
12927 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
12928 * +-----------------------+------+---+---+-----+--------+------+------+
12929 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
12930 * +-----------------------+------+---+---+-----+--------+------+------+
12932 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
12934 int opcode
= extract32(insn
, 10, 2);
12935 int o
= extract32(insn
, 14, 1);
12936 int rm
= extract32(insn
, 16, 5);
12937 int rn
= extract32(insn
, 5, 5);
12938 int rd
= extract32(insn
, 0, 5);
12940 CryptoThreeOpFn
*genfn
;
12944 case 0: /* SHA512H */
12945 feature
= dc_isar_feature(aa64_sha512
, s
);
12946 genfn
= gen_helper_crypto_sha512h
;
12948 case 1: /* SHA512H2 */
12949 feature
= dc_isar_feature(aa64_sha512
, s
);
12950 genfn
= gen_helper_crypto_sha512h2
;
12952 case 2: /* SHA512SU1 */
12953 feature
= dc_isar_feature(aa64_sha512
, s
);
12954 genfn
= gen_helper_crypto_sha512su1
;
12957 feature
= dc_isar_feature(aa64_sha3
, s
);
12963 case 0: /* SM3PARTW1 */
12964 feature
= dc_isar_feature(aa64_sm3
, s
);
12965 genfn
= gen_helper_crypto_sm3partw1
;
12967 case 1: /* SM3PARTW2 */
12968 feature
= dc_isar_feature(aa64_sm3
, s
);
12969 genfn
= gen_helper_crypto_sm3partw2
;
12971 case 2: /* SM4EKEY */
12972 feature
= dc_isar_feature(aa64_sm4
, s
);
12973 genfn
= gen_helper_crypto_sm4ekey
;
12976 unallocated_encoding(s
);
12982 unallocated_encoding(s
);
12986 if (!fp_access_check(s
)) {
12991 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
12993 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
12994 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
12995 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
12997 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
12999 tcg_temp_free_ptr(tcg_rd_ptr
);
13000 tcg_temp_free_ptr(tcg_rn_ptr
);
13001 tcg_temp_free_ptr(tcg_rm_ptr
);
13003 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13006 tcg_op1
= tcg_temp_new_i64();
13007 tcg_op2
= tcg_temp_new_i64();
13008 tcg_res
[0] = tcg_temp_new_i64();
13009 tcg_res
[1] = tcg_temp_new_i64();
13011 for (pass
= 0; pass
< 2; pass
++) {
13012 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13013 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13015 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13016 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13018 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13019 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13021 tcg_temp_free_i64(tcg_op1
);
13022 tcg_temp_free_i64(tcg_op2
);
13023 tcg_temp_free_i64(tcg_res
[0]);
13024 tcg_temp_free_i64(tcg_res
[1]);
13028 /* Crypto two-reg SHA512
13029 * 31 12 11 10 9 5 4 0
13030 * +-----------------------------------------+--------+------+------+
13031 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13032 * +-----------------------------------------+--------+------+------+
13034 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13036 int opcode
= extract32(insn
, 10, 2);
13037 int rn
= extract32(insn
, 5, 5);
13038 int rd
= extract32(insn
, 0, 5);
13039 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13041 CryptoTwoOpFn
*genfn
;
13044 case 0: /* SHA512SU0 */
13045 feature
= dc_isar_feature(aa64_sha512
, s
);
13046 genfn
= gen_helper_crypto_sha512su0
;
13049 feature
= dc_isar_feature(aa64_sm4
, s
);
13050 genfn
= gen_helper_crypto_sm4e
;
13053 unallocated_encoding(s
);
13058 unallocated_encoding(s
);
13062 if (!fp_access_check(s
)) {
13066 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13067 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13069 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13071 tcg_temp_free_ptr(tcg_rd_ptr
);
13072 tcg_temp_free_ptr(tcg_rn_ptr
);
13075 /* Crypto four-register
13076 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13077 * +-------------------+-----+------+---+------+------+------+
13078 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13079 * +-------------------+-----+------+---+------+------+------+
13081 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13083 int op0
= extract32(insn
, 21, 2);
13084 int rm
= extract32(insn
, 16, 5);
13085 int ra
= extract32(insn
, 10, 5);
13086 int rn
= extract32(insn
, 5, 5);
13087 int rd
= extract32(insn
, 0, 5);
13093 feature
= dc_isar_feature(aa64_sha3
, s
);
13095 case 2: /* SM3SS1 */
13096 feature
= dc_isar_feature(aa64_sm3
, s
);
13099 unallocated_encoding(s
);
13104 unallocated_encoding(s
);
13108 if (!fp_access_check(s
)) {
13113 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13116 tcg_op1
= tcg_temp_new_i64();
13117 tcg_op2
= tcg_temp_new_i64();
13118 tcg_op3
= tcg_temp_new_i64();
13119 tcg_res
[0] = tcg_temp_new_i64();
13120 tcg_res
[1] = tcg_temp_new_i64();
13122 for (pass
= 0; pass
< 2; pass
++) {
13123 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13124 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13125 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13129 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13132 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13134 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13136 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13137 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13139 tcg_temp_free_i64(tcg_op1
);
13140 tcg_temp_free_i64(tcg_op2
);
13141 tcg_temp_free_i64(tcg_op3
);
13142 tcg_temp_free_i64(tcg_res
[0]);
13143 tcg_temp_free_i64(tcg_res
[1]);
13145 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13147 tcg_op1
= tcg_temp_new_i32();
13148 tcg_op2
= tcg_temp_new_i32();
13149 tcg_op3
= tcg_temp_new_i32();
13150 tcg_res
= tcg_temp_new_i32();
13151 tcg_zero
= tcg_const_i32(0);
13153 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13154 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13155 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13157 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13158 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13159 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13160 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13162 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13163 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13164 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13165 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13167 tcg_temp_free_i32(tcg_op1
);
13168 tcg_temp_free_i32(tcg_op2
);
13169 tcg_temp_free_i32(tcg_op3
);
13170 tcg_temp_free_i32(tcg_res
);
13171 tcg_temp_free_i32(tcg_zero
);
13176 * 31 21 20 16 15 10 9 5 4 0
13177 * +-----------------------+------+--------+------+------+
13178 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13179 * +-----------------------+------+--------+------+------+
13181 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13183 int rm
= extract32(insn
, 16, 5);
13184 int imm6
= extract32(insn
, 10, 6);
13185 int rn
= extract32(insn
, 5, 5);
13186 int rd
= extract32(insn
, 0, 5);
13187 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13190 if (!dc_isar_feature(aa64_sha3
, s
)) {
13191 unallocated_encoding(s
);
13195 if (!fp_access_check(s
)) {
13199 tcg_op1
= tcg_temp_new_i64();
13200 tcg_op2
= tcg_temp_new_i64();
13201 tcg_res
[0] = tcg_temp_new_i64();
13202 tcg_res
[1] = tcg_temp_new_i64();
13204 for (pass
= 0; pass
< 2; pass
++) {
13205 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13206 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13208 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13209 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13211 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13212 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13214 tcg_temp_free_i64(tcg_op1
);
13215 tcg_temp_free_i64(tcg_op2
);
13216 tcg_temp_free_i64(tcg_res
[0]);
13217 tcg_temp_free_i64(tcg_res
[1]);
13220 /* Crypto three-reg imm2
13221 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13222 * +-----------------------+------+-----+------+--------+------+------+
13223 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13224 * +-----------------------+------+-----+------+--------+------+------+
13226 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13228 int opcode
= extract32(insn
, 10, 2);
13229 int imm2
= extract32(insn
, 12, 2);
13230 int rm
= extract32(insn
, 16, 5);
13231 int rn
= extract32(insn
, 5, 5);
13232 int rd
= extract32(insn
, 0, 5);
13233 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13234 TCGv_i32 tcg_imm2
, tcg_opcode
;
13236 if (!dc_isar_feature(aa64_sm3
, s
)) {
13237 unallocated_encoding(s
);
13241 if (!fp_access_check(s
)) {
13245 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13246 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13247 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13248 tcg_imm2
= tcg_const_i32(imm2
);
13249 tcg_opcode
= tcg_const_i32(opcode
);
13251 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13254 tcg_temp_free_ptr(tcg_rd_ptr
);
13255 tcg_temp_free_ptr(tcg_rn_ptr
);
13256 tcg_temp_free_ptr(tcg_rm_ptr
);
13257 tcg_temp_free_i32(tcg_imm2
);
13258 tcg_temp_free_i32(tcg_opcode
);
13261 /* C3.6 Data processing - SIMD, inc Crypto
13263 * As the decode gets a little complex we are using a table based
13264 * approach for this part of the decode.
13266 static const AArch64DecodeTable data_proc_simd
[] = {
13267 /* pattern , mask , fn */
13268 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13269 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13270 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13271 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13272 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13273 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13274 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13275 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13276 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13277 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13278 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13279 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13280 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13281 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13282 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13283 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13284 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13285 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13286 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13287 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13288 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13289 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13290 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13291 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13292 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13293 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13294 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13295 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13296 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13297 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13298 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13299 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13300 { 0x00000000, 0x00000000, NULL
}
13303 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13305 /* Note that this is called with all non-FP cases from
13306 * table C3-6 so it must UNDEF for entries not specifically
13307 * allocated to instructions in that table.
13309 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13313 unallocated_encoding(s
);
13317 /* C3.6 Data processing - SIMD and floating point */
13318 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13320 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13321 disas_data_proc_fp(s
, insn
);
13323 /* SIMD, including crypto */
13324 disas_data_proc_simd(s
, insn
);
13328 /* C3.1 A64 instruction index by encoding */
13329 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13333 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13337 s
->fp_access_checked
= false;
13339 switch (extract32(insn
, 25, 4)) {
13340 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
13341 unallocated_encoding(s
);
13344 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
13345 unallocated_encoding(s
);
13348 case 0x8: case 0x9: /* Data processing - immediate */
13349 disas_data_proc_imm(s
, insn
);
13351 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13352 disas_b_exc_sys(s
, insn
);
13357 case 0xe: /* Loads and stores */
13358 disas_ldst(s
, insn
);
13361 case 0xd: /* Data processing - register */
13362 disas_data_proc_reg(s
, insn
);
13365 case 0xf: /* Data processing - SIMD and floating point */
13366 disas_data_proc_simd_fp(s
, insn
);
13369 assert(FALSE
); /* all 15 cases should be handled above */
13373 /* if we allocated any temporaries, free them here */
13377 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
13380 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13381 CPUARMState
*env
= cpu
->env_ptr
;
13382 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
13385 dc
->isar
= &arm_cpu
->isar
;
13386 dc
->pc
= dc
->base
.pc_first
;
13390 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
13391 * there is no secure EL1, so we route exceptions to EL3.
13393 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
13394 !arm_el_is_aa64(env
, 3);
13397 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
13398 dc
->condexec_mask
= 0;
13399 dc
->condexec_cond
= 0;
13400 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
13401 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
13402 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
13403 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
13404 #if !defined(CONFIG_USER_ONLY)
13405 dc
->user
= (dc
->current_el
== 0);
13407 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
13408 dc
->sve_excp_el
= ARM_TBFLAG_SVEEXC_EL(dc
->base
.tb
->flags
);
13409 dc
->sve_len
= (ARM_TBFLAG_ZCR_LEN(dc
->base
.tb
->flags
) + 1) * 16;
13411 dc
->vec_stride
= 0;
13412 dc
->cp_regs
= arm_cpu
->cp_regs
;
13413 dc
->features
= env
->features
;
13415 /* Single step state. The code-generation logic here is:
13417 * generate code with no special handling for single-stepping (except
13418 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
13419 * this happens anyway because those changes are all system register or
13421 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
13422 * emit code for one insn
13423 * emit code to clear PSTATE.SS
13424 * emit code to generate software step exception for completed step
13425 * end TB (as usual for having generated an exception)
13426 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
13427 * emit code to generate a software step exception
13430 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
13431 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
13432 dc
->is_ldex
= false;
13433 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
13435 /* Bound the number of insns to execute to those left on the page. */
13436 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
13438 /* If architectural single step active, limit to 1. */
13439 if (dc
->ss_active
) {
13442 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
13444 init_tmp_a64_array(dc
);
13447 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
13451 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
13453 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13455 tcg_gen_insn_start(dc
->pc
, 0, 0);
13456 dc
->insn_start
= tcg_last_op();
13459 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
13460 const CPUBreakpoint
*bp
)
13462 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13464 if (bp
->flags
& BP_CPU
) {
13465 gen_a64_set_pc_im(dc
->pc
);
13466 gen_helper_check_breakpoints(cpu_env
);
13467 /* End the TB early; it likely won't be executed */
13468 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
13470 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
13471 /* The address covered by the breakpoint must be
13472 included in [tb->pc, tb->pc + tb->size) in order
13473 to for it to be properly cleared -- thus we
13474 increment the PC here so that the logic setting
13475 tb->size below does the right thing. */
13477 dc
->base
.is_jmp
= DISAS_NORETURN
;
13483 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
13485 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13486 CPUARMState
*env
= cpu
->env_ptr
;
13488 if (dc
->ss_active
&& !dc
->pstate_ss
) {
13489 /* Singlestep state is Active-pending.
13490 * If we're in this state at the start of a TB then either
13491 * a) we just took an exception to an EL which is being debugged
13492 * and this is the first insn in the exception handler
13493 * b) debug exceptions were masked and we just unmasked them
13494 * without changing EL (eg by clearing PSTATE.D)
13495 * In either case we're going to take a swstep exception in the
13496 * "did not step an insn" case, and so the syndrome ISV and EX
13497 * bits should be zero.
13499 assert(dc
->base
.num_insns
== 1);
13500 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
13501 default_exception_el(dc
));
13502 dc
->base
.is_jmp
= DISAS_NORETURN
;
13504 disas_a64_insn(env
, dc
);
13507 dc
->base
.pc_next
= dc
->pc
;
13508 translator_loop_temp_check(&dc
->base
);
13511 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
13513 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13515 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
13516 /* Note that this means single stepping WFI doesn't halt the CPU.
13517 * For conditional branch insns this is harmless unreachable code as
13518 * gen_goto_tb() has already handled emitting the debug exception
13519 * (and thus a tb-jump is not possible when singlestepping).
13521 switch (dc
->base
.is_jmp
) {
13523 gen_a64_set_pc_im(dc
->pc
);
13527 if (dc
->base
.singlestep_enabled
) {
13528 gen_exception_internal(EXCP_DEBUG
);
13530 gen_step_complete_exception(dc
);
13533 case DISAS_NORETURN
:
13537 switch (dc
->base
.is_jmp
) {
13539 case DISAS_TOO_MANY
:
13540 gen_goto_tb(dc
, 1, dc
->pc
);
13544 gen_a64_set_pc_im(dc
->pc
);
13547 tcg_gen_exit_tb(NULL
, 0);
13550 tcg_gen_lookup_and_goto_ptr();
13552 case DISAS_NORETURN
:
13556 gen_a64_set_pc_im(dc
->pc
);
13557 gen_helper_wfe(cpu_env
);
13560 gen_a64_set_pc_im(dc
->pc
);
13561 gen_helper_yield(cpu_env
);
13565 /* This is a special case because we don't want to just halt the CPU
13566 * if trying to debug across a WFI.
13568 TCGv_i32 tmp
= tcg_const_i32(4);
13570 gen_a64_set_pc_im(dc
->pc
);
13571 gen_helper_wfi(cpu_env
, tmp
);
13572 tcg_temp_free_i32(tmp
);
13573 /* The helper doesn't necessarily throw an exception, but we
13574 * must go back to the main loop to check for interrupts anyway.
13576 tcg_gen_exit_tb(NULL
, 0);
13582 /* Functions above can change dc->pc, so re-align db->pc_next */
13583 dc
->base
.pc_next
= dc
->pc
;
13586 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
13589 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13591 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
13592 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
13595 const TranslatorOps aarch64_translator_ops
= {
13596 .init_disas_context
= aarch64_tr_init_disas_context
,
13597 .tb_start
= aarch64_tr_tb_start
,
13598 .insn_start
= aarch64_tr_insn_start
,
13599 .breakpoint_check
= aarch64_tr_breakpoint_check
,
13600 .translate_insn
= aarch64_tr_translate_insn
,
13601 .tb_stop
= aarch64_tr_tb_stop
,
13602 .disas_log
= aarch64_tr_disas_log
,