target/arm/cpu64.c

   1 /*
   2  * QEMU AArch64 CPU
   3  *
   4  * Copyright (c) 2013 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "qemu/module.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "sysemu/sysemu.h"
  29 #include "sysemu/kvm.h"
  30 #include "kvm_arm.h"
  31 #include "qapi/visitor.h"
  32
  33 static inline void set_feature(CPUARMState *env, int feature)
  34 {
  35     env->features |= 1ULL << feature;
  36 }
  37
  38 static inline void unset_feature(CPUARMState *env, int feature)
  39 {
  40     env->features &= ~(1ULL << feature);
  41 }
  42
  43 #ifndef CONFIG_USER_ONLY
  44 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  45 {
  46     ARMCPU *cpu = env_archcpu(env);
  47
  48     /* Number of cores is in [25:24]; otherwise we RAZ */
  49     return (cpu->core_count - 1) << 24;
  50 }
  51 #endif
  52
  53 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
  54 #ifndef CONFIG_USER_ONLY
  55     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  56       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  57       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  58       .writefn = arm_cp_write_ignore },
  59     { .name = "L2CTLR",
  60       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  61       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  62       .writefn = arm_cp_write_ignore },
  63 #endif
  64     { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  65       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  66       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  67     { .name = "L2ECTLR",
  68       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  69       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  70     { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  71       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  72       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  73     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  74       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  75       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  76     { .name = "CPUACTLR",
  77       .cp = 15, .opc1 = 0, .crm = 15,
  78       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  79     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  80       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  81       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  82     { .name = "CPUECTLR",
  83       .cp = 15, .opc1 = 1, .crm = 15,
  84       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  85     { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  86       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  87       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  88     { .name = "CPUMERRSR",
  89       .cp = 15, .opc1 = 2, .crm = 15,
  90       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  91     { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  92       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  93       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  94     { .name = "L2MERRSR",
  95       .cp = 15, .opc1 = 3, .crm = 15,
  96       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  97     REGINFO_SENTINEL
  98 };
  99
 100 static void aarch64_a57_initfn(Object *obj)
 101 {
 102     ARMCPU *cpu = ARM_CPU(obj);
 103
 104     cpu->dtb_compatible = "arm,cortex-a57";
 105     set_feature(&cpu->env, ARM_FEATURE_V8);
 106     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 107     set_feature(&cpu->env, ARM_FEATURE_NEON);
 108     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 109     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 110     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 111     set_feature(&cpu->env, ARM_FEATURE_EL2);
 112     set_feature(&cpu->env, ARM_FEATURE_EL3);
 113     set_feature(&cpu->env, ARM_FEATURE_PMU);
 114     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 115     cpu->midr = 0x411fd070;
 116     cpu->revidr = 0x00000000;
 117     cpu->reset_fpsid = 0x41034070;
 118     cpu->isar.mvfr0 = 0x10110222;
 119     cpu->isar.mvfr1 = 0x12111111;
 120     cpu->isar.mvfr2 = 0x00000043;
 121     cpu->ctr = 0x8444c004;
 122     cpu->reset_sctlr = 0x00c50838;
 123     cpu->id_pfr0 = 0x00000131;
 124     cpu->id_pfr1 = 0x00011011;
 125     cpu->id_dfr0 = 0x03010066;
 126     cpu->id_afr0 = 0x00000000;
 127     cpu->id_mmfr0 = 0x10101105;
 128     cpu->id_mmfr1 = 0x40000000;
 129     cpu->id_mmfr2 = 0x01260000;
 130     cpu->id_mmfr3 = 0x02102211;
 131     cpu->isar.id_isar0 = 0x02101110;
 132     cpu->isar.id_isar1 = 0x13112111;
 133     cpu->isar.id_isar2 = 0x21232042;
 134     cpu->isar.id_isar3 = 0x01112131;
 135     cpu->isar.id_isar4 = 0x00011142;
 136     cpu->isar.id_isar5 = 0x00011121;
 137     cpu->isar.id_isar6 = 0;
 138     cpu->isar.id_aa64pfr0 = 0x00002222;
 139     cpu->id_aa64dfr0 = 0x10305106;
 140     cpu->isar.id_aa64isar0 = 0x00011120;
 141     cpu->isar.id_aa64mmfr0 = 0x00001124;
 142     cpu->dbgdidr = 0x3516d000;
 143     cpu->clidr = 0x0a200023;
 144     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 145     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 146     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 147     cpu->dcz_blocksize = 4; /* 64 bytes */
 148     cpu->gic_num_lrs = 4;
 149     cpu->gic_vpribits = 5;
 150     cpu->gic_vprebits = 5;
 151     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 152 }
 153
 154 static void aarch64_a53_initfn(Object *obj)
 155 {
 156     ARMCPU *cpu = ARM_CPU(obj);
 157
 158     cpu->dtb_compatible = "arm,cortex-a53";
 159     set_feature(&cpu->env, ARM_FEATURE_V8);
 160     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 161     set_feature(&cpu->env, ARM_FEATURE_NEON);
 162     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 163     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 164     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 165     set_feature(&cpu->env, ARM_FEATURE_EL2);
 166     set_feature(&cpu->env, ARM_FEATURE_EL3);
 167     set_feature(&cpu->env, ARM_FEATURE_PMU);
 168     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 169     cpu->midr = 0x410fd034;
 170     cpu->revidr = 0x00000000;
 171     cpu->reset_fpsid = 0x41034070;
 172     cpu->isar.mvfr0 = 0x10110222;
 173     cpu->isar.mvfr1 = 0x12111111;
 174     cpu->isar.mvfr2 = 0x00000043;
 175     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 176     cpu->reset_sctlr = 0x00c50838;
 177     cpu->id_pfr0 = 0x00000131;
 178     cpu->id_pfr1 = 0x00011011;
 179     cpu->id_dfr0 = 0x03010066;
 180     cpu->id_afr0 = 0x00000000;
 181     cpu->id_mmfr0 = 0x10101105;
 182     cpu->id_mmfr1 = 0x40000000;
 183     cpu->id_mmfr2 = 0x01260000;
 184     cpu->id_mmfr3 = 0x02102211;
 185     cpu->isar.id_isar0 = 0x02101110;
 186     cpu->isar.id_isar1 = 0x13112111;
 187     cpu->isar.id_isar2 = 0x21232042;
 188     cpu->isar.id_isar3 = 0x01112131;
 189     cpu->isar.id_isar4 = 0x00011142;
 190     cpu->isar.id_isar5 = 0x00011121;
 191     cpu->isar.id_isar6 = 0;
 192     cpu->isar.id_aa64pfr0 = 0x00002222;
 193     cpu->id_aa64dfr0 = 0x10305106;
 194     cpu->isar.id_aa64isar0 = 0x00011120;
 195     cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 196     cpu->dbgdidr = 0x3516d000;
 197     cpu->clidr = 0x0a200023;
 198     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 199     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 200     cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 201     cpu->dcz_blocksize = 4; /* 64 bytes */
 202     cpu->gic_num_lrs = 4;
 203     cpu->gic_vpribits = 5;
 204     cpu->gic_vprebits = 5;
 205     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 206 }
 207
 208 static void aarch64_a72_initfn(Object *obj)
 209 {
 210     ARMCPU *cpu = ARM_CPU(obj);
 211
 212     cpu->dtb_compatible = "arm,cortex-a72";
 213     set_feature(&cpu->env, ARM_FEATURE_V8);
 214     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 215     set_feature(&cpu->env, ARM_FEATURE_NEON);
 216     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 217     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 218     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 219     set_feature(&cpu->env, ARM_FEATURE_EL2);
 220     set_feature(&cpu->env, ARM_FEATURE_EL3);
 221     set_feature(&cpu->env, ARM_FEATURE_PMU);
 222     cpu->midr = 0x410fd083;
 223     cpu->revidr = 0x00000000;
 224     cpu->reset_fpsid = 0x41034080;
 225     cpu->isar.mvfr0 = 0x10110222;
 226     cpu->isar.mvfr1 = 0x12111111;
 227     cpu->isar.mvfr2 = 0x00000043;
 228     cpu->ctr = 0x8444c004;
 229     cpu->reset_sctlr = 0x00c50838;
 230     cpu->id_pfr0 = 0x00000131;
 231     cpu->id_pfr1 = 0x00011011;
 232     cpu->id_dfr0 = 0x03010066;
 233     cpu->id_afr0 = 0x00000000;
 234     cpu->id_mmfr0 = 0x10201105;
 235     cpu->id_mmfr1 = 0x40000000;
 236     cpu->id_mmfr2 = 0x01260000;
 237     cpu->id_mmfr3 = 0x02102211;
 238     cpu->isar.id_isar0 = 0x02101110;
 239     cpu->isar.id_isar1 = 0x13112111;
 240     cpu->isar.id_isar2 = 0x21232042;
 241     cpu->isar.id_isar3 = 0x01112131;
 242     cpu->isar.id_isar4 = 0x00011142;
 243     cpu->isar.id_isar5 = 0x00011121;
 244     cpu->isar.id_aa64pfr0 = 0x00002222;
 245     cpu->id_aa64dfr0 = 0x10305106;
 246     cpu->isar.id_aa64isar0 = 0x00011120;
 247     cpu->isar.id_aa64mmfr0 = 0x00001124;
 248     cpu->dbgdidr = 0x3516d000;
 249     cpu->clidr = 0x0a200023;
 250     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 251     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 252     cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
 253     cpu->dcz_blocksize = 4; /* 64 bytes */
 254     cpu->gic_num_lrs = 4;
 255     cpu->gic_vpribits = 5;
 256     cpu->gic_vprebits = 5;
 257     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 258 }
 259
 260 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
 261                                void *opaque, Error **errp)
 262 {
 263     ARMCPU *cpu = ARM_CPU(obj);
 264     visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
 265 }
 266
 267 static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
 268                                void *opaque, Error **errp)
 269 {
 270     ARMCPU *cpu = ARM_CPU(obj);
 271     Error *err = NULL;
 272
 273     visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
 274
 275     if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
 276         error_setg(&err, "unsupported SVE vector length");
 277         error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
 278                           ARM_MAX_VQ);
 279     }
 280     error_propagate(errp, err);
 281 }
 282
 283 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
 284  * otherwise, a CPU with as many features enabled as our emulation supports.
 285  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
 286  * this only needs to handle 64 bits.
 287  */
 288 static void aarch64_max_initfn(Object *obj)
 289 {
 290     ARMCPU *cpu = ARM_CPU(obj);
 291
 292     if (kvm_enabled()) {
 293         kvm_arm_set_cpu_features_from_host(cpu);
 294     } else {
 295         uint64_t t;
 296         uint32_t u;
 297         aarch64_a57_initfn(obj);
 298
 299         /*
 300          * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
 301          * one and try to apply errata workarounds or use impdef features we
 302          * don't provide.
 303          * An IMPLEMENTER field of 0 means "reserved for software use";
 304          * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
 305          * to see which features are present";
 306          * the VARIANT, PARTNUM and REVISION fields are all implementation
 307          * defined and we choose to define PARTNUM just in case guest
 308          * code needs to distinguish this QEMU CPU from other software
 309          * implementations, though this shouldn't be needed.
 310          */
 311         t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
 312         t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
 313         t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
 314         t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
 315         t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
 316         cpu->midr = t;
 317
 318         t = cpu->isar.id_aa64isar0;
 319         t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
 320         t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
 321         t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
 322         t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
 323         t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
 324         t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
 325         t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
 326         t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
 327         t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 328         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 329         t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
 330         t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
 331         t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
 332         cpu->isar.id_aa64isar0 = t;
 333
 334         t = cpu->isar.id_aa64isar1;
 335         t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
 336         t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
 337         t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
 338         t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
 339         t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
 340         t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
 341         t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
 342         t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
 343         t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
 344         cpu->isar.id_aa64isar1 = t;
 345
 346         t = cpu->isar.id_aa64pfr0;
 347         t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 348         t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
 349         t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
 350         cpu->isar.id_aa64pfr0 = t;
 351
 352         t = cpu->isar.id_aa64pfr1;
 353         t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
 354         cpu->isar.id_aa64pfr1 = t;
 355
 356         t = cpu->isar.id_aa64mmfr1;
 357         t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
 358         t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
 359         cpu->isar.id_aa64mmfr1 = t;
 360
 361         /* Replicate the same data to the 32-bit id registers.  */
 362         u = cpu->isar.id_isar5;
 363         u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
 364         u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
 365         u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
 366         u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
 367         u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
 368         u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
 369         cpu->isar.id_isar5 = u;
 370
 371         u = cpu->isar.id_isar6;
 372         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
 373         u = FIELD_DP32(u, ID_ISAR6, DP, 1);
 374         u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
 375         u = FIELD_DP32(u, ID_ISAR6, SB, 1);
 376         u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
 377         cpu->isar.id_isar6 = u;
 378
 379         /*
 380          * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
 381          * so do not set MVFR1.FPHP.  Strictly speaking this is not legal,
 382          * but it is also not legal to enable SVE without support for FP16,
 383          * and enabling SVE in system mode is more useful in the short term.
 384          */
 385
 386 #ifdef CONFIG_USER_ONLY
 387         /* For usermode -cpu max we can use a larger and more efficient DCZ
 388          * blocksize since we don't have to follow what the hardware does.
 389          */
 390         cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 391         cpu->dcz_blocksize = 7; /*  512 bytes */
 392 #endif
 393
 394         cpu->sve_max_vq = ARM_MAX_VQ;
 395         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
 396                             cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
 397     }
 398 }
 399
 400 struct ARMCPUInfo {
 401     const char *name;
 402     void (*initfn)(Object *obj);
 403     void (*class_init)(ObjectClass *oc, void *data);
 404 };
 405
 406 static const ARMCPUInfo aarch64_cpus[] = {
 407     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 408     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 409     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
 410     { .name = "max",                .initfn = aarch64_max_initfn },
 411     { .name = NULL }
 412 };
 413
 414 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 415 {
 416     ARMCPU *cpu = ARM_CPU(obj);
 417
 418     return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 419 }
 420
 421 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 422 {
 423     ARMCPU *cpu = ARM_CPU(obj);
 424
 425     /* At this time, this property is only allowed if KVM is enabled.  This
 426      * restriction allows us to avoid fixing up functionality that assumes a
 427      * uniform execution state like do_interrupt.
 428      */
 429     if (value == false) {
 430         if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
 431             error_setg(errp, "'aarch64' feature cannot be disabled "
 432                              "unless KVM is enabled and 32-bit EL1 "
 433                              "is supported");
 434             return;
 435         }
 436         unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 437     } else {
 438         set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 439     }
 440 }
 441
 442 static void aarch64_cpu_initfn(Object *obj)
 443 {
 444     object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 445                              aarch64_cpu_set_aarch64, NULL);
 446     object_property_set_description(obj, "aarch64",
 447                                     "Set on/off to enable/disable aarch64 "
 448                                     "execution state ",
 449                                     NULL);
 450 }
 451
 452 static void aarch64_cpu_finalizefn(Object *obj)
 453 {
 454 }
 455
 456 static gchar *aarch64_gdb_arch_name(CPUState *cs)
 457 {
 458     return g_strdup("aarch64");
 459 }
 460
 461 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 462 {
 463     CPUClass *cc = CPU_CLASS(oc);
 464
 465     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 466     cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 467     cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 468     cc->gdb_num_core_regs = 34;
 469     cc->gdb_core_xml_file = "aarch64-core.xml";
 470     cc->gdb_arch_name = aarch64_gdb_arch_name;
 471 }
 472
 473 static void aarch64_cpu_instance_init(Object *obj)
 474 {
 475     ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
 476
 477     acc->info->initfn(obj);
 478     arm_cpu_post_init(obj);
 479 }
 480
 481 static void cpu_register_class_init(ObjectClass *oc, void *data)
 482 {
 483     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 484
 485     acc->info = data;
 486 }
 487
 488 static void aarch64_cpu_register(const ARMCPUInfo *info)
 489 {
 490     TypeInfo type_info = {
 491         .parent = TYPE_AARCH64_CPU,
 492         .instance_size = sizeof(ARMCPU),
 493         .instance_init = aarch64_cpu_instance_init,
 494         .class_size = sizeof(ARMCPUClass),
 495         .class_init = info->class_init ?: cpu_register_class_init,
 496         .class_data = (void *)info,
 497     };
 498
 499     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 500     type_register(&type_info);
 501     g_free((void *)type_info.name);
 502 }
 503
 504 static const TypeInfo aarch64_cpu_type_info = {
 505     .name = TYPE_AARCH64_CPU,
 506     .parent = TYPE_ARM_CPU,
 507     .instance_size = sizeof(ARMCPU),
 508     .instance_init = aarch64_cpu_initfn,
 509     .instance_finalize = aarch64_cpu_finalizefn,
 510     .abstract = true,
 511     .class_size = sizeof(AArch64CPUClass),
 512     .class_init = aarch64_cpu_class_init,
 513 };
 514
 515 static void aarch64_cpu_register_types(void)
 516 {
 517     const ARMCPUInfo *info = aarch64_cpus;
 518
 519     type_register_static(&aarch64_cpu_type_info);
 520
 521     while (info->name) {
 522         aarch64_cpu_register(info);
 523         info++;
 524     }
 525 }
 526
 527 type_init(aarch64_cpu_register_types)