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ar7: Update board code for latest QEMU API
[qemu/ar7.git] / target / mips / op_helper.c
blobba5f7355cf0fc5b9343ee3cada51fd41be552f9e
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "sysemu/kvm.h"
28
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
31
32 QEMU_NORETURN
33 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
34 int error_code)
35 {
36 do_raise_exception_err(env, exception, error_code, 0);
37 }
38
39 QEMU_NORETURN
40 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
41 {
42 do_raise_exception(env, exception, GETPC());
43 }
44
45 QEMU_NORETURN void helper_raise_exception_debug(CPUMIPSState *env)
46 {
47 do_raise_exception(env, EXCP_DEBUG, 0);
48 }
49
50 static QEMU_NORETURN
51 void raise_exception(CPUMIPSState *env, uint32_t exception)
52 {
53 do_raise_exception(env, exception, 0);
54 }
55
56 #if defined(CONFIG_USER_ONLY)
57 #define HELPER_LD(name, insn, type) \
58 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
59 int mem_idx, uintptr_t retaddr) \
60 { \
61 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
62 }
63 #else
64 #define HELPER_LD(name, insn, type) \
65 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
66 int mem_idx, uintptr_t retaddr) \
67 { \
68 switch (mem_idx) \
69 { \
70 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
71 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
72 default: \
73 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
74 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
75 } \
76 }
77 #endif
78 HELPER_LD(lw, ldl, int32_t)
79 #if defined(TARGET_MIPS64)
80 HELPER_LD(ld, ldq, int64_t)
81 #endif
82 #undef HELPER_LD
83
84 #if defined(CONFIG_USER_ONLY)
85 #define HELPER_ST(name, insn, type) \
86 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
87 type val, int mem_idx, uintptr_t retaddr) \
88 { \
89 cpu_##insn##_data_ra(env, addr, val, retaddr); \
90 }
91 #else
92 #define HELPER_ST(name, insn, type) \
93 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
94 type val, int mem_idx, uintptr_t retaddr) \
95 { \
96 switch (mem_idx) \
97 { \
98 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
99 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
100 default: \
101 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
102 case 3: \
103 cpu_##insn##_error_ra(env, addr, val, retaddr); \
104 break; \
105 } \
106 }
107 #endif
108 HELPER_ST(sb, stb, uint8_t)
109 HELPER_ST(sw, stl, uint32_t)
110 #if defined(TARGET_MIPS64)
111 HELPER_ST(sd, stq, uint64_t)
112 #endif
113 #undef HELPER_ST
114
115 /* 64 bits arithmetic for 32 bits hosts */
116 static inline uint64_t get_HILO(CPUMIPSState *env)
117 {
118 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
119 }
120
121 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
122 {
123 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
124 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
125 }
126
127 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
128 {
129 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
130 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
131 return tmp;
132 }
133
134 /* Multiplication variants of the vr54xx. */
135 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
136 target_ulong arg2)
137 {
138 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
139 (int64_t)(int32_t)arg2));
140 }
141
142 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
143 target_ulong arg2)
144 {
145 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
146 (uint64_t)(uint32_t)arg2);
147 }
148
149 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
150 target_ulong arg2)
151 {
152 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
153 (int64_t)(int32_t)arg2);
154 }
155
156 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
157 target_ulong arg2)
158 {
159 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
160 (int64_t)(int32_t)arg2);
161 }
162
163 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
164 target_ulong arg2)
165 {
166 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
167 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
168 }
169
170 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
171 target_ulong arg2)
172 {
173 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
174 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
175 }
176
177 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
178 target_ulong arg2)
179 {
180 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
181 (int64_t)(int32_t)arg2);
182 }
183
184 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
185 target_ulong arg2)
186 {
187 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
188 (int64_t)(int32_t)arg2);
189 }
190
191 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
192 target_ulong arg2)
193 {
194 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
195 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
196 }
197
198 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
199 target_ulong arg2)
200 {
201 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
202 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
203 }
204
205 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
206 target_ulong arg2)
207 {
208 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
209 }
210
211 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
212 target_ulong arg2)
213 {
214 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
215 (uint64_t)(uint32_t)arg2);
216 }
217
218 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
219 target_ulong arg2)
220 {
221 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
222 (int64_t)(int32_t)arg2);
223 }
224
225 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
226 target_ulong arg2)
227 {
228 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
229 (uint64_t)(uint32_t)arg2);
230 }
231
232 static inline target_ulong bitswap(target_ulong v)
233 {
234 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
235 ((v & (target_ulong)0x5555555555555555ULL) << 1);
236 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
237 ((v & (target_ulong)0x3333333333333333ULL) << 2);
238 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
239 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
240 return v;
241 }
242
243 #ifdef TARGET_MIPS64
244 target_ulong helper_dbitswap(target_ulong rt)
245 {
246 return bitswap(rt);
247 }
248 #endif
249
250 target_ulong helper_bitswap(target_ulong rt)
251 {
252 return (int32_t)bitswap(rt);
253 }
254
255 target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
256 uint32_t stripe)
257 {
258 int i;
259 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
260 uint64_t tmp1 = tmp0;
261 for (i = 0; i <= 46; i++) {
262 int s;
263 if (i & 0x8) {
264 s = shift;
265 } else {
266 s = shiftx;
267 }
268
269 if (stripe != 0 && !(i & 0x4)) {
270 s = ~s;
271 }
272 if (s & 0x10) {
273 if (tmp0 & (1LL << (i + 16))) {
274 tmp1 |= 1LL << i;
275 } else {
276 tmp1 &= ~(1LL << i);
277 }
278 }
279 }
280
281 uint64_t tmp2 = tmp1;
282 for (i = 0; i <= 38; i++) {
283 int s;
284 if (i & 0x4) {
285 s = shift;
286 } else {
287 s = shiftx;
288 }
289
290 if (s & 0x8) {
291 if (tmp1 & (1LL << (i + 8))) {
292 tmp2 |= 1LL << i;
293 } else {
294 tmp2 &= ~(1LL << i);
295 }
296 }
297 }
298
299 uint64_t tmp3 = tmp2;
300 for (i = 0; i <= 34; i++) {
301 int s;
302 if (i & 0x2) {
303 s = shift;
304 } else {
305 s = shiftx;
306 }
307 if (s & 0x4) {
308 if (tmp2 & (1LL << (i + 4))) {
309 tmp3 |= 1LL << i;
310 } else {
311 tmp3 &= ~(1LL << i);
312 }
313 }
314 }
315
316 uint64_t tmp4 = tmp3;
317 for (i = 0; i <= 32; i++) {
318 int s;
319 if (i & 0x1) {
320 s = shift;
321 } else {
322 s = shiftx;
323 }
324 if (s & 0x2) {
325 if (tmp3 & (1LL << (i + 2))) {
326 tmp4 |= 1LL << i;
327 } else {
328 tmp4 &= ~(1LL << i);
329 }
330 }
331 }
332
333 uint64_t tmp5 = tmp4;
334 for (i = 0; i <= 31; i++) {
335 int s;
336 s = shift;
337 if (s & 0x1) {
338 if (tmp4 & (1LL << (i + 1))) {
339 tmp5 |= 1LL << i;
340 } else {
341 tmp5 &= ~(1LL << i);
342 }
343 }
344 }
345
346 return (int64_t)(int32_t)(uint32_t)tmp5;
347 }
348
349 #ifndef CONFIG_USER_ONLY
350
351 static inline hwaddr do_translate_address(CPUMIPSState *env,
352 target_ulong address,
353 int rw, uintptr_t retaddr)
354 {
355 hwaddr paddr;
356 CPUState *cs = CPU(mips_env_get_cpu(env));
357
358 paddr = cpu_mips_translate_address(env, address, rw);
359
360 if (paddr == -1LL) {
361 cpu_loop_exit_restore(cs, retaddr);
362 } else {
363 return paddr;
364 }
365 }
366
367 #define HELPER_LD_ATOMIC(name, insn, almask) \
368 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
369 { \
370 if (arg & almask) { \
371 if (!(env->hflags & MIPS_HFLAG_DM)) { \
372 env->CP0_BadVAddr = arg; \
373 } \
374 do_raise_exception(env, EXCP_AdEL, GETPC()); \
375 } \
376 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
377 env->lladdr = arg; \
378 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
379 return env->llval; \
380 }
381 HELPER_LD_ATOMIC(ll, lw, 0x3)
382 #ifdef TARGET_MIPS64
383 HELPER_LD_ATOMIC(lld, ld, 0x7)
384 #endif
385 #undef HELPER_LD_ATOMIC
386 #endif
387
388 #ifdef TARGET_WORDS_BIGENDIAN
389 #define GET_LMASK(v) ((v) & 3)
390 #define GET_OFFSET(addr, offset) (addr + (offset))
391 #else
392 #define GET_LMASK(v) (((v) & 3) ^ 3)
393 #define GET_OFFSET(addr, offset) (addr - (offset))
394 #endif
395
396 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
397 int mem_idx)
398 {
399 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
400
401 if (GET_LMASK(arg2) <= 2) {
402 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
403 GETPC());
404 }
405
406 if (GET_LMASK(arg2) <= 1) {
407 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
408 GETPC());
409 }
410
411 if (GET_LMASK(arg2) == 0) {
412 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
413 GETPC());
414 }
415 }
416
417 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
418 int mem_idx)
419 {
420 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
421
422 if (GET_LMASK(arg2) >= 1) {
423 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
424 GETPC());
425 }
426
427 if (GET_LMASK(arg2) >= 2) {
428 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
429 GETPC());
430 }
431
432 if (GET_LMASK(arg2) == 3) {
433 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
434 GETPC());
435 }
436 }
437
438 #if defined(TARGET_MIPS64)
439 /* "half" load and stores. We must do the memory access inline,
440 or fault handling won't work. */
441
442 #ifdef TARGET_WORDS_BIGENDIAN
443 #define GET_LMASK64(v) ((v) & 7)
444 #else
445 #define GET_LMASK64(v) (((v) & 7) ^ 7)
446 #endif
447
448 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
449 int mem_idx)
450 {
451 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
452
453 if (GET_LMASK64(arg2) <= 6) {
454 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
455 GETPC());
456 }
457
458 if (GET_LMASK64(arg2) <= 5) {
459 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
460 GETPC());
461 }
462
463 if (GET_LMASK64(arg2) <= 4) {
464 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
465 GETPC());
466 }
467
468 if (GET_LMASK64(arg2) <= 3) {
469 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
470 GETPC());
471 }
472
473 if (GET_LMASK64(arg2) <= 2) {
474 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
475 GETPC());
476 }
477
478 if (GET_LMASK64(arg2) <= 1) {
479 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
480 GETPC());
481 }
482
483 if (GET_LMASK64(arg2) <= 0) {
484 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
485 GETPC());
486 }
487 }
488
489 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
490 int mem_idx)
491 {
492 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
493
494 if (GET_LMASK64(arg2) >= 1) {
495 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
496 GETPC());
497 }
498
499 if (GET_LMASK64(arg2) >= 2) {
500 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
501 GETPC());
502 }
503
504 if (GET_LMASK64(arg2) >= 3) {
505 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
506 GETPC());
507 }
508
509 if (GET_LMASK64(arg2) >= 4) {
510 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
511 GETPC());
512 }
513
514 if (GET_LMASK64(arg2) >= 5) {
515 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
516 GETPC());
517 }
518
519 if (GET_LMASK64(arg2) >= 6) {
520 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
521 GETPC());
522 }
523
524 if (GET_LMASK64(arg2) == 7) {
525 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
526 GETPC());
527 }
528 }
529 #endif /* TARGET_MIPS64 */
530
531 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
532
533 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
534 uint32_t mem_idx)
535 {
536 target_ulong base_reglist = reglist & 0xf;
537 target_ulong do_r31 = reglist & 0x10;
538
539 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
540 target_ulong i;
541
542 for (i = 0; i < base_reglist; i++) {
543 env->active_tc.gpr[multiple_regs[i]] =
544 (target_long)do_lw(env, addr, mem_idx, GETPC());
545 addr += 4;
546 }
547 }
548
549 if (do_r31) {
550 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
551 GETPC());
552 }
553 }
554
555 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
556 uint32_t mem_idx)
557 {
558 target_ulong base_reglist = reglist & 0xf;
559 target_ulong do_r31 = reglist & 0x10;
560
561 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
562 target_ulong i;
563
564 for (i = 0; i < base_reglist; i++) {
565 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
566 GETPC());
567 addr += 4;
568 }
569 }
570
571 if (do_r31) {
572 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
573 }
574 }
575
576 #if defined(TARGET_MIPS64)
577 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
578 uint32_t mem_idx)
579 {
580 target_ulong base_reglist = reglist & 0xf;
581 target_ulong do_r31 = reglist & 0x10;
582
583 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
584 target_ulong i;
585
586 for (i = 0; i < base_reglist; i++) {
587 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
588 GETPC());
589 addr += 8;
590 }
591 }
592
593 if (do_r31) {
594 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
595 }
596 }
597
598 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
599 uint32_t mem_idx)
600 {
601 target_ulong base_reglist = reglist & 0xf;
602 target_ulong do_r31 = reglist & 0x10;
603
604 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
605 target_ulong i;
606
607 for (i = 0; i < base_reglist; i++) {
608 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
609 GETPC());
610 addr += 8;
611 }
612 }
613
614 if (do_r31) {
615 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
616 }
617 }
618 #endif
619
620 #ifndef CONFIG_USER_ONLY
621 /* SMP helpers. */
622 static bool mips_vpe_is_wfi(MIPSCPU *c)
623 {
624 CPUState *cpu = CPU(c);
625 CPUMIPSState *env = &c->env;
626
627 /* If the VPE is halted but otherwise active, it means it's waiting for
628 an interrupt. */
629 return cpu->halted && mips_vpe_active(env);
630 }
631
632 static bool mips_vp_is_wfi(MIPSCPU *c)
633 {
634 CPUState *cpu = CPU(c);
635 CPUMIPSState *env = &c->env;
636
637 return cpu->halted && mips_vp_active(env);
638 }
639
640 static inline void mips_vpe_wake(MIPSCPU *c)
641 {
642 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
643 because there might be other conditions that state that c should
644 be sleeping. */
645 qemu_mutex_lock_iothread();
646 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
647 qemu_mutex_unlock_iothread();
648 }
649
650 static inline void mips_vpe_sleep(MIPSCPU *cpu)
651 {
652 CPUState *cs = CPU(cpu);
653
654 /* The VPE was shut off, really go to bed.
655 Reset any old _WAKE requests. */
656 cs->halted = 1;
657 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
658 }
659
660 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
661 {
662 CPUMIPSState *c = &cpu->env;
663
664 /* FIXME: TC reschedule. */
665 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
666 mips_vpe_wake(cpu);
667 }
668 }
669
670 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
671 {
672 CPUMIPSState *c = &cpu->env;
673
674 /* FIXME: TC reschedule. */
675 if (!mips_vpe_active(c)) {
676 mips_vpe_sleep(cpu);
677 }
678 }
679
680 /**
681 * mips_cpu_map_tc:
682 * @env: CPU from which mapping is performed.
683 * @tc: Should point to an int with the value of the global TC index.
684 *
685 * This function will transform @tc into a local index within the
686 * returned #CPUMIPSState.
687 */
688 /* FIXME: This code assumes that all VPEs have the same number of TCs,
689 which depends on runtime setup. Can probably be fixed by
690 walking the list of CPUMIPSStates. */
691 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
692 {
693 MIPSCPU *cpu;
694 CPUState *cs;
695 CPUState *other_cs;
696 int vpe_idx;
697 int tc_idx = *tc;
698
699 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
700 /* Not allowed to address other CPUs. */
701 *tc = env->current_tc;
702 return env;
703 }
704
705 cs = CPU(mips_env_get_cpu(env));
706 vpe_idx = tc_idx / cs->nr_threads;
707 *tc = tc_idx % cs->nr_threads;
708 other_cs = qemu_get_cpu(vpe_idx);
709 if (other_cs == NULL) {
710 return env;
711 }
712 cpu = MIPS_CPU(other_cs);
713 return &cpu->env;
714 }
715
716 /* The per VPE CP0_Status register shares some fields with the per TC
717 CP0_TCStatus registers. These fields are wired to the same registers,
718 so changes to either of them should be reflected on both registers.
719
720 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
721
722 These helper call synchronizes the regs for a given cpu. */
723
724 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
725 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
726 int tc); */
727
728 /* Called for updates to CP0_TCStatus. */
729 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
730 target_ulong v)
731 {
732 uint32_t status;
733 uint32_t tcu, tmx, tasid, tksu;
734 uint32_t mask = ((1U << CP0St_CU3)
735 | (1 << CP0St_CU2)
736 | (1 << CP0St_CU1)
737 | (1 << CP0St_CU0)
738 | (1 << CP0St_MX)
739 | (3 << CP0St_KSU));
740
741 tcu = (v >> CP0TCSt_TCU0) & 0xf;
742 tmx = (v >> CP0TCSt_TMX) & 0x1;
743 tasid = v & cpu->CP0_EntryHi_ASID_mask;
744 tksu = (v >> CP0TCSt_TKSU) & 0x3;
745
746 status = tcu << CP0St_CU0;
747 status |= tmx << CP0St_MX;
748 status |= tksu << CP0St_KSU;
749
750 cpu->CP0_Status &= ~mask;
751 cpu->CP0_Status |= status;
752
753 /* Sync the TASID with EntryHi. */
754 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
755 cpu->CP0_EntryHi |= tasid;
756
757 compute_hflags(cpu);
758 }
759
760 /* Called for updates to CP0_EntryHi. */
761 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
762 {
763 int32_t *tcst;
764 uint32_t asid, v = cpu->CP0_EntryHi;
765
766 asid = v & cpu->CP0_EntryHi_ASID_mask;
767
768 if (tc == cpu->current_tc) {
769 tcst = &cpu->active_tc.CP0_TCStatus;
770 } else {
771 tcst = &cpu->tcs[tc].CP0_TCStatus;
772 }
773
774 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
775 *tcst |= asid;
776 }
777
778 /* CP0 helpers */
779 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
780 {
781 return env->mvp->CP0_MVPControl;
782 }
783
784 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
785 {
786 return env->mvp->CP0_MVPConf0;
787 }
788
789 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
790 {
791 return env->mvp->CP0_MVPConf1;
792 }
793
794 target_ulong helper_mfc0_random(CPUMIPSState *env)
795 {
796 return (int32_t)cpu_mips_get_random(env);
797 }
798
799 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
800 {
801 return env->active_tc.CP0_TCStatus;
802 }
803
804 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
805 {
806 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
807 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
808
809 if (other_tc == other->current_tc)
810 return other->active_tc.CP0_TCStatus;
811 else
812 return other->tcs[other_tc].CP0_TCStatus;
813 }
814
815 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
816 {
817 return env->active_tc.CP0_TCBind;
818 }
819
820 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
821 {
822 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
823 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
824
825 if (other_tc == other->current_tc)
826 return other->active_tc.CP0_TCBind;
827 else
828 return other->tcs[other_tc].CP0_TCBind;
829 }
830
831 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
832 {
833 return env->active_tc.PC;
834 }
835
836 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
837 {
838 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
839 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
840
841 if (other_tc == other->current_tc)
842 return other->active_tc.PC;
843 else
844 return other->tcs[other_tc].PC;
845 }
846
847 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
848 {
849 return env->active_tc.CP0_TCHalt;
850 }
851
852 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
853 {
854 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
855 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
856
857 if (other_tc == other->current_tc)
858 return other->active_tc.CP0_TCHalt;
859 else
860 return other->tcs[other_tc].CP0_TCHalt;
861 }
862
863 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
864 {
865 return env->active_tc.CP0_TCContext;
866 }
867
868 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
869 {
870 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
871 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
872
873 if (other_tc == other->current_tc)
874 return other->active_tc.CP0_TCContext;
875 else
876 return other->tcs[other_tc].CP0_TCContext;
877 }
878
879 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
880 {
881 return env->active_tc.CP0_TCSchedule;
882 }
883
884 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
885 {
886 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
887 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
888
889 if (other_tc == other->current_tc)
890 return other->active_tc.CP0_TCSchedule;
891 else
892 return other->tcs[other_tc].CP0_TCSchedule;
893 }
894
895 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
896 {
897 return env->active_tc.CP0_TCScheFBack;
898 }
899
900 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
901 {
902 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
903 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
904
905 if (other_tc == other->current_tc)
906 return other->active_tc.CP0_TCScheFBack;
907 else
908 return other->tcs[other_tc].CP0_TCScheFBack;
909 }
910
911 target_ulong helper_mfc0_count(CPUMIPSState *env)
912 {
913 return (int32_t)cpu_mips_get_count(env);
914 }
915
916 target_ulong helper_mfc0_saar(CPUMIPSState *env)
917 {
918 if ((env->CP0_SAARI & 0x3f) < 2) {
919 return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
920 }
921 return 0;
922 }
923
924 target_ulong helper_mfhc0_saar(CPUMIPSState *env)
925 {
926 if ((env->CP0_SAARI & 0x3f) < 2) {
927 return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
928 }
929 return 0;
930 }
931
932 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
933 {
934 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
935 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
936
937 return other->CP0_EntryHi;
938 }
939
940 target_ulong helper_mftc0_cause(CPUMIPSState *env)
941 {
942 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
943 int32_t tccause;
944 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
945
946 if (other_tc == other->current_tc) {
947 tccause = other->CP0_Cause;
948 } else {
949 tccause = other->CP0_Cause;
950 }
951
952 return tccause;
953 }
954
955 target_ulong helper_mftc0_status(CPUMIPSState *env)
956 {
957 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
958 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
959
960 return other->CP0_Status;
961 }
962
963 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
964 {
965 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
966 }
967
968 target_ulong helper_mfc0_maar(CPUMIPSState *env)
969 {
970 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
971 }
972
973 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
974 {
975 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
976 }
977
978 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
979 {
980 return (int32_t)env->CP0_WatchLo[sel];
981 }
982
983 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
984 {
985 return env->CP0_WatchHi[sel];
986 }
987
988 target_ulong helper_mfc0_debug(CPUMIPSState *env)
989 {
990 target_ulong t0 = env->CP0_Debug;
991 if (env->hflags & MIPS_HFLAG_DM)
992 t0 |= 1 << CP0DB_DM;
993
994 return t0;
995 }
996
997 target_ulong helper_mftc0_debug(CPUMIPSState *env)
998 {
999 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1000 int32_t tcstatus;
1001 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1002
1003 if (other_tc == other->current_tc)
1004 tcstatus = other->active_tc.CP0_Debug_tcstatus;
1005 else
1006 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
1007
1008 /* XXX: Might be wrong, check with EJTAG spec. */
1009 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1010 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1011 }
1012
1013 #if defined(TARGET_MIPS64)
1014 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
1015 {
1016 return env->active_tc.PC;
1017 }
1018
1019 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
1020 {
1021 return env->active_tc.CP0_TCHalt;
1022 }
1023
1024 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
1025 {
1026 return env->active_tc.CP0_TCContext;
1027 }
1028
1029 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
1030 {
1031 return env->active_tc.CP0_TCSchedule;
1032 }
1033
1034 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1035 {
1036 return env->active_tc.CP0_TCScheFBack;
1037 }
1038
1039 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1040 {
1041 return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
1042 }
1043
1044 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
1045 {
1046 return env->CP0_MAAR[env->CP0_MAARI];
1047 }
1048
1049 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1050 {
1051 return env->CP0_WatchLo[sel];
1052 }
1053
1054 target_ulong helper_dmfc0_saar(CPUMIPSState *env)
1055 {
1056 if ((env->CP0_SAARI & 0x3f) < 2) {
1057 return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
1058 }
1059 return 0;
1060 }
1061 #endif /* TARGET_MIPS64 */
1062
1063 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1064 {
1065 uint32_t index_p = env->CP0_Index & 0x80000000;
1066 uint32_t tlb_index = arg1 & 0x7fffffff;
1067 if (tlb_index < env->tlb->nb_tlb) {
1068 if (env->insn_flags & ISA_MIPS32R6) {
1069 index_p |= arg1 & 0x80000000;
1070 }
1071 env->CP0_Index = index_p | tlb_index;
1072 }
1073 }
1074
1075 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1076 {
1077 uint32_t mask = 0;
1078 uint32_t newval;
1079
1080 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1081 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1082 (1 << CP0MVPCo_EVP);
1083 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1084 mask |= (1 << CP0MVPCo_STLB);
1085 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1086
1087 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1088
1089 env->mvp->CP0_MVPControl = newval;
1090 }
1091
1092 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1093 {
1094 uint32_t mask;
1095 uint32_t newval;
1096
1097 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1098 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1099 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1100
1101 /* Yield scheduler intercept not implemented. */
1102 /* Gating storage scheduler intercept not implemented. */
1103
1104 // TODO: Enable/disable TCs.
1105
1106 env->CP0_VPEControl = newval;
1107 }
1108
1109 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1110 {
1111 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1112 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1113 uint32_t mask;
1114 uint32_t newval;
1115
1116 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1117 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1118 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1119
1120 /* TODO: Enable/disable TCs. */
1121
1122 other->CP0_VPEControl = newval;
1123 }
1124
1125 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1126 {
1127 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1128 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1129 /* FIXME: Mask away return zero on read bits. */
1130 return other->CP0_VPEControl;
1131 }
1132
1133 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1134 {
1135 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1136 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1137
1138 return other->CP0_VPEConf0;
1139 }
1140
1141 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1142 {
1143 uint32_t mask = 0;
1144 uint32_t newval;
1145
1146 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1147 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1148 mask |= (0xff << CP0VPEC0_XTC);
1149 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1150 }
1151 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1152
1153 // TODO: TC exclusive handling due to ERL/EXL.
1154
1155 env->CP0_VPEConf0 = newval;
1156 }
1157
1158 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1159 {
1160 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1161 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1162 uint32_t mask = 0;
1163 uint32_t newval;
1164
1165 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1166 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1167
1168 /* TODO: TC exclusive handling due to ERL/EXL. */
1169 other->CP0_VPEConf0 = newval;
1170 }
1171
1172 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1173 {
1174 uint32_t mask = 0;
1175 uint32_t newval;
1176
1177 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1178 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1179 (0xff << CP0VPEC1_NCP1);
1180 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1181
1182 /* UDI not implemented. */
1183 /* CP2 not implemented. */
1184
1185 // TODO: Handle FPU (CP1) binding.
1186
1187 env->CP0_VPEConf1 = newval;
1188 }
1189
1190 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1191 {
1192 /* Yield qualifier inputs not implemented. */
1193 env->CP0_YQMask = 0x00000000;
1194 }
1195
1196 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1197 {
1198 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1199 }
1200
1201 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1202
1203 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1204 {
1205 /* 1k pages not implemented */
1206 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1207 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1208 | (rxi << (CP0EnLo_XI - 30));
1209 }
1210
1211 #if defined(TARGET_MIPS64)
1212 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1213
1214 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1215 {
1216 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1217 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1218 }
1219 #endif
1220
1221 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1222 {
1223 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1224 uint32_t newval;
1225
1226 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1227
1228 env->active_tc.CP0_TCStatus = newval;
1229 sync_c0_tcstatus(env, env->current_tc, newval);
1230 }
1231
1232 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1233 {
1234 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1235 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1236
1237 if (other_tc == other->current_tc)
1238 other->active_tc.CP0_TCStatus = arg1;
1239 else
1240 other->tcs[other_tc].CP0_TCStatus = arg1;
1241 sync_c0_tcstatus(other, other_tc, arg1);
1242 }
1243
1244 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1245 {
1246 uint32_t mask = (1 << CP0TCBd_TBE);
1247 uint32_t newval;
1248
1249 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1250 mask |= (1 << CP0TCBd_CurVPE);
1251 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1252 env->active_tc.CP0_TCBind = newval;
1253 }
1254
1255 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1256 {
1257 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1258 uint32_t mask = (1 << CP0TCBd_TBE);
1259 uint32_t newval;
1260 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1261
1262 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1263 mask |= (1 << CP0TCBd_CurVPE);
1264 if (other_tc == other->current_tc) {
1265 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1266 other->active_tc.CP0_TCBind = newval;
1267 } else {
1268 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1269 other->tcs[other_tc].CP0_TCBind = newval;
1270 }
1271 }
1272
1273 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1274 {
1275 env->active_tc.PC = arg1;
1276 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1277 env->CP0_LLAddr = 0;
1278 env->lladdr = 0;
1279 /* MIPS16 not implemented. */
1280 }
1281
1282 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1283 {
1284 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1285 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1286
1287 if (other_tc == other->current_tc) {
1288 other->active_tc.PC = arg1;
1289 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1290 other->CP0_LLAddr = 0;
1291 other->lladdr = 0;
1292 /* MIPS16 not implemented. */
1293 } else {
1294 other->tcs[other_tc].PC = arg1;
1295 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1296 other->CP0_LLAddr = 0;
1297 other->lladdr = 0;
1298 /* MIPS16 not implemented. */
1299 }
1300 }
1301
1302 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1303 {
1304 MIPSCPU *cpu = mips_env_get_cpu(env);
1305
1306 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1307
1308 // TODO: Halt TC / Restart (if allocated+active) TC.
1309 if (env->active_tc.CP0_TCHalt & 1) {
1310 mips_tc_sleep(cpu, env->current_tc);
1311 } else {
1312 mips_tc_wake(cpu, env->current_tc);
1313 }
1314 }
1315
1316 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1317 {
1318 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1319 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1320 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1321
1322 // TODO: Halt TC / Restart (if allocated+active) TC.
1323
1324 if (other_tc == other->current_tc)
1325 other->active_tc.CP0_TCHalt = arg1;
1326 else
1327 other->tcs[other_tc].CP0_TCHalt = arg1;
1328
1329 if (arg1 & 1) {
1330 mips_tc_sleep(other_cpu, other_tc);
1331 } else {
1332 mips_tc_wake(other_cpu, other_tc);
1333 }
1334 }
1335
1336 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1337 {
1338 env->active_tc.CP0_TCContext = arg1;
1339 }
1340
1341 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1342 {
1343 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1344 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1345
1346 if (other_tc == other->current_tc)
1347 other->active_tc.CP0_TCContext = arg1;
1348 else
1349 other->tcs[other_tc].CP0_TCContext = arg1;
1350 }
1351
1352 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1353 {
1354 env->active_tc.CP0_TCSchedule = arg1;
1355 }
1356
1357 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1358 {
1359 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1360 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1361
1362 if (other_tc == other->current_tc)
1363 other->active_tc.CP0_TCSchedule = arg1;
1364 else
1365 other->tcs[other_tc].CP0_TCSchedule = arg1;
1366 }
1367
1368 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1369 {
1370 env->active_tc.CP0_TCScheFBack = arg1;
1371 }
1372
1373 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1374 {
1375 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1376 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1377
1378 if (other_tc == other->current_tc)
1379 other->active_tc.CP0_TCScheFBack = arg1;
1380 else
1381 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1382 }
1383
1384 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1385 {
1386 /* 1k pages not implemented */
1387 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1388 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1389 | (rxi << (CP0EnLo_XI - 30));
1390 }
1391
1392 #if defined(TARGET_MIPS64)
1393 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1394 {
1395 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1396 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1397 }
1398 #endif
1399
1400 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1401 {
1402 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1403 }
1404
1405 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
1406 {
1407 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1408 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1409 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1410 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1411 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1412 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1413 }
1414 }
1415
1416 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1417 {
1418 update_pagemask(env, arg1, &env->CP0_PageMask);
1419 }
1420
1421 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1422 {
1423 /* SmartMIPS not implemented */
1424 /* 1k pages not implemented */
1425 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1426 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1427 compute_hflags(env);
1428 restore_pamask(env);
1429 }
1430
1431 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
1432 {
1433 CPUState *cs = CPU(mips_env_get_cpu(env));
1434
1435 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
1436 tlb_flush(cs);
1437 }
1438
1439 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
1440 {
1441 CPUState *cs = CPU(mips_env_get_cpu(env));
1442
1443 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
1444 tlb_flush(cs);
1445 }
1446
1447 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
1448 {
1449 CPUState *cs = CPU(mips_env_get_cpu(env));
1450
1451 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
1452 tlb_flush(cs);
1453 }
1454
1455 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
1456 {
1457 #if defined(TARGET_MIPS64)
1458 uint64_t mask = 0x3F3FFFFFFFULL;
1459 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
1460 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
1461
1462 if ((env->insn_flags & ISA_MIPS32R6)) {
1463 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
1464 mask &= ~(0x3FULL << CP0PF_BDI);
1465 }
1466 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
1467 mask &= ~(0x3FULL << CP0PF_GDI);
1468 }
1469 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
1470 mask &= ~(0x3FULL << CP0PF_UDI);
1471 }
1472 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
1473 mask &= ~(0x3FULL << CP0PF_MDI);
1474 }
1475 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
1476 mask &= ~(0x3FULL << CP0PF_PTI);
1477 }
1478 }
1479 env->CP0_PWField = arg1 & mask;
1480
1481 if ((new_ptei >= 32) ||
1482 ((env->insn_flags & ISA_MIPS32R6) &&
1483 (new_ptei == 0 || new_ptei == 1))) {
1484 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
1485 (old_ptei << CP0PF_PTEI);
1486 }
1487 #else
1488 uint32_t mask = 0x3FFFFFFF;
1489 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
1490 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
1491
1492 if ((env->insn_flags & ISA_MIPS32R6)) {
1493 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
1494 mask &= ~(0x3F << CP0PF_GDW);
1495 }
1496 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
1497 mask &= ~(0x3F << CP0PF_UDW);
1498 }
1499 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
1500 mask &= ~(0x3F << CP0PF_MDW);
1501 }
1502 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
1503 mask &= ~(0x3F << CP0PF_PTW);
1504 }
1505 }
1506 env->CP0_PWField = arg1 & mask;
1507
1508 if ((new_ptew >= 32) ||
1509 ((env->insn_flags & ISA_MIPS32R6) &&
1510 (new_ptew == 0 || new_ptew == 1))) {
1511 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1512 (old_ptew << CP0PF_PTEW);
1513 }
1514 #endif
1515 }
1516
1517 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1518 {
1519 #if defined(TARGET_MIPS64)
1520 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1521 #else
1522 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1523 #endif
1524 }
1525
1526 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1527 {
1528 if (env->insn_flags & ISA_MIPS32R6) {
1529 if (arg1 < env->tlb->nb_tlb) {
1530 env->CP0_Wired = arg1;
1531 }
1532 } else {
1533 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1534 }
1535 }
1536
1537 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1538 {
1539 #if defined(TARGET_MIPS64)
1540 /* PWEn = 0. Hardware page table walking is not implemented. */
1541 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1542 #else
1543 env->CP0_PWCtl = (arg1 & 0x800000FF);
1544 #endif
1545 }
1546
1547 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1548 {
1549 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1550 }
1551
1552 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1553 {
1554 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1555 }
1556
1557 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1558 {
1559 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1560 }
1561
1562 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1563 {
1564 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1565 }
1566
1567 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1568 {
1569 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1570 }
1571
1572 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1573 {
1574 uint32_t mask = 0x0000000F;
1575
1576 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1577 (env->insn_flags & ISA_MIPS32R6)) {
1578 mask |= (1 << 4);
1579 }
1580 if (env->insn_flags & ISA_MIPS32R6) {
1581 mask |= (1 << 5);
1582 }
1583 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1584 mask |= (1 << 29);
1585
1586 if (arg1 & (1 << 29)) {
1587 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1588 } else {
1589 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1590 }
1591 }
1592
1593 env->CP0_HWREna = arg1 & mask;
1594 }
1595
1596 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1597 {
1598 cpu_mips_store_count(env, arg1);
1599 }
1600
1601 void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
1602 {
1603 uint32_t target = arg1 & 0x3f;
1604 if (target <= 1) {
1605 env->CP0_SAARI = target;
1606 }
1607 }
1608
1609 void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1610 {
1611 uint32_t target = env->CP0_SAARI & 0x3f;
1612 if (target < 2) {
1613 env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1614 switch (target) {
1615 case 0:
1616 if (env->itu) {
1617 itc_reconfigure(env->itu);
1618 }
1619 break;
1620 }
1621 }
1622 }
1623
1624 void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1625 {
1626 uint32_t target = env->CP0_SAARI & 0x3f;
1627 if (target < 2) {
1628 env->CP0_SAAR[target] =
1629 (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1630 (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1631 switch (target) {
1632 case 0:
1633 if (env->itu) {
1634 itc_reconfigure(env->itu);
1635 }
1636 break;
1637 }
1638 }
1639 }
1640
1641 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1642 {
1643 target_ulong old, val, mask;
1644 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1645 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1646 mask |= 1 << CP0EnHi_EHINV;
1647 }
1648
1649 /* 1k pages not implemented */
1650 #if defined(TARGET_MIPS64)
1651 if (env->insn_flags & ISA_MIPS32R6) {
1652 int entryhi_r = extract64(arg1, 62, 2);
1653 int config0_at = extract32(env->CP0_Config0, 13, 2);
1654 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1655 if ((entryhi_r == 2) ||
1656 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1657 /* skip EntryHi.R field if new value is reserved */
1658 mask &= ~(0x3ull << 62);
1659 }
1660 }
1661 mask &= env->SEGMask;
1662 #endif
1663 old = env->CP0_EntryHi;
1664 val = (arg1 & mask) | (old & ~mask);
1665 env->CP0_EntryHi = val;
1666 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1667 sync_c0_entryhi(env, env->current_tc);
1668 }
1669 /* If the ASID changes, flush qemu's TLB. */
1670 if ((old & env->CP0_EntryHi_ASID_mask) !=
1671 (val & env->CP0_EntryHi_ASID_mask)) {
1672 tlb_flush(CPU(mips_env_get_cpu(env)));
1673 }
1674 }
1675
1676 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1677 {
1678 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1679 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1680
1681 other->CP0_EntryHi = arg1;
1682 sync_c0_entryhi(other, other_tc);
1683 }
1684
1685 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1686 {
1687 cpu_mips_store_compare(env, arg1);
1688 }
1689
1690 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1691 {
1692 MIPSCPU *cpu = mips_env_get_cpu(env);
1693 uint32_t val, old;
1694
1695 old = env->CP0_Status;
1696 cpu_mips_store_status(env, arg1);
1697 val = env->CP0_Status;
1698
1699 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1700 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1701 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1702 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1703 env->CP0_Cause);
1704 switch (cpu_mmu_index(env, false)) {
1705 case 3:
1706 qemu_log(", ERL\n");
1707 break;
1708 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1709 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1710 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1711 default:
1712 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1713 break;
1714 }
1715 }
1716 }
1717
1718 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1719 {
1720 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1721 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1722 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1723
1724 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1725 sync_c0_status(env, other, other_tc);
1726 }
1727
1728 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1729 {
1730 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1731 }
1732
1733 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1734 {
1735 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1736 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1737 }
1738
1739 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1740 {
1741 cpu_mips_store_cause(env, arg1);
1742 }
1743
1744 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1745 {
1746 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1747 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1748
1749 cpu_mips_store_cause(other, arg1);
1750 }
1751
1752 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1753 {
1754 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1755 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1756
1757 return other->CP0_EPC;
1758 }
1759
1760 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1761 {
1762 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1763 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1764
1765 return other->CP0_EBase;
1766 }
1767
1768 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1769 {
1770 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1771 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1772 mask |= ~0x3FFFFFFF;
1773 }
1774 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1775 }
1776
1777 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1778 {
1779 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1780 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1781 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1782 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1783 mask |= ~0x3FFFFFFF;
1784 }
1785 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1786 }
1787
1788 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1789 {
1790 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1791 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1792
1793 switch (idx) {
1794 case 0: return other->CP0_Config0;
1795 case 1: return other->CP0_Config1;
1796 case 2: return other->CP0_Config2;
1797 case 3: return other->CP0_Config3;
1798 /* 4 and 5 are reserved. */
1799 case 6: return other->CP0_Config6;
1800 case 7: return other->CP0_Config7;
1801 default:
1802 break;
1803 }
1804 return 0;
1805 }
1806
1807 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1808 {
1809 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1810 }
1811
1812 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1813 {
1814 /* tertiary/secondary caches not implemented */
1815 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1816 }
1817
1818 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1819 {
1820 if (env->insn_flags & ASE_MICROMIPS) {
1821 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1822 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1823 }
1824 }
1825
1826 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1827 {
1828 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1829 (arg1 & env->CP0_Config4_rw_bitmask);
1830 }
1831
1832 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1833 {
1834 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1835 (arg1 & env->CP0_Config5_rw_bitmask);
1836 compute_hflags(env);
1837 }
1838
1839 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1840 {
1841 target_long mask = env->CP0_LLAddr_rw_bitmask;
1842 arg1 = arg1 << env->CP0_LLAddr_shift;
1843 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1844 }
1845
1846 #define MTC0_MAAR_MASK(env) \
1847 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1848
1849 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1850 {
1851 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1852 }
1853
1854 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1855 {
1856 env->CP0_MAAR[env->CP0_MAARI] =
1857 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1858 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1859 }
1860
1861 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1862 {
1863 int index = arg1 & 0x3f;
1864 if (index == 0x3f) {
1865 /* Software may write all ones to INDEX to determine the
1866 maximum value supported. */
1867 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1868 } else if (index < MIPS_MAAR_MAX) {
1869 env->CP0_MAARI = index;
1870 }
1871 /* Other than the all ones, if the
1872 value written is not supported, then INDEX is unchanged
1873 from its previous value. */
1874 }
1875
1876 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1877 {
1878 /* Watch exceptions for instructions, data loads, data stores
1879 not implemented. */
1880 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1881 }
1882
1883 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1884 {
1885 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1886 env->CP0_WatchHi[sel] = arg1 & mask;
1887 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1888 }
1889
1890 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1891 {
1892 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1893 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1894 }
1895
1896 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1897 {
1898 env->CP0_Framemask = arg1; /* XXX */
1899 }
1900
1901 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1902 {
1903 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1904 if (arg1 & (1 << CP0DB_DM))
1905 env->hflags |= MIPS_HFLAG_DM;
1906 else
1907 env->hflags &= ~MIPS_HFLAG_DM;
1908 }
1909
1910 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1911 {
1912 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1913 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1914 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1915
1916 /* XXX: Might be wrong, check with EJTAG spec. */
1917 if (other_tc == other->current_tc)
1918 other->active_tc.CP0_Debug_tcstatus = val;
1919 else
1920 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1921 other->CP0_Debug = (other->CP0_Debug &
1922 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1923 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1924 }
1925
1926 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1927 {
1928 env->CP0_Performance0 = arg1 & 0x000007ff;
1929 }
1930
1931 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1932 {
1933 int32_t wst = arg1 & (1 << CP0EC_WST);
1934 int32_t spr = arg1 & (1 << CP0EC_SPR);
1935 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1936
1937 env->CP0_ErrCtl = wst | spr | itc;
1938
1939 if (itc && !wst && !spr) {
1940 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1941 } else {
1942 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1943 }
1944 }
1945
1946 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1947 {
1948 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1949 /* If CACHE instruction is configured for ITC tags then make all
1950 CP0.TagLo bits writable. The actual write to ITC Configuration
1951 Tag will take care of the read-only bits. */
1952 env->CP0_TagLo = arg1;
1953 } else {
1954 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1955 }
1956 }
1957
1958 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1959 {
1960 env->CP0_DataLo = arg1; /* XXX */
1961 }
1962
1963 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1964 {
1965 env->CP0_TagHi = arg1; /* XXX */
1966 }
1967
1968 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1969 {
1970 env->CP0_DataHi = arg1; /* XXX */
1971 }
1972
1973 /* MIPS MT functions */
1974 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1975 {
1976 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1977 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1978
1979 if (other_tc == other->current_tc)
1980 return other->active_tc.gpr[sel];
1981 else
1982 return other->tcs[other_tc].gpr[sel];
1983 }
1984
1985 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1986 {
1987 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1988 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1989
1990 if (other_tc == other->current_tc)
1991 return other->active_tc.LO[sel];
1992 else
1993 return other->tcs[other_tc].LO[sel];
1994 }
1995
1996 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1997 {
1998 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1999 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2000
2001 if (other_tc == other->current_tc)
2002 return other->active_tc.HI[sel];
2003 else
2004 return other->tcs[other_tc].HI[sel];
2005 }
2006
2007 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
2008 {
2009 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2010 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2011
2012 if (other_tc == other->current_tc)
2013 return other->active_tc.ACX[sel];
2014 else
2015 return other->tcs[other_tc].ACX[sel];
2016 }
2017
2018 target_ulong helper_mftdsp(CPUMIPSState *env)
2019 {
2020 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2021 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2022
2023 if (other_tc == other->current_tc)
2024 return other->active_tc.DSPControl;
2025 else
2026 return other->tcs[other_tc].DSPControl;
2027 }
2028
2029 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2030 {
2031 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2032 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2033
2034 if (other_tc == other->current_tc)
2035 other->active_tc.gpr[sel] = arg1;
2036 else
2037 other->tcs[other_tc].gpr[sel] = arg1;
2038 }
2039
2040 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2041 {
2042 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2043 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2044
2045 if (other_tc == other->current_tc)
2046 other->active_tc.LO[sel] = arg1;
2047 else
2048 other->tcs[other_tc].LO[sel] = arg1;
2049 }
2050
2051 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2052 {
2053 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2054 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2055
2056 if (other_tc == other->current_tc)
2057 other->active_tc.HI[sel] = arg1;
2058 else
2059 other->tcs[other_tc].HI[sel] = arg1;
2060 }
2061
2062 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2063 {
2064 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2065 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2066
2067 if (other_tc == other->current_tc)
2068 other->active_tc.ACX[sel] = arg1;
2069 else
2070 other->tcs[other_tc].ACX[sel] = arg1;
2071 }
2072
2073 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
2074 {
2075 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2076 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2077
2078 if (other_tc == other->current_tc)
2079 other->active_tc.DSPControl = arg1;
2080 else
2081 other->tcs[other_tc].DSPControl = arg1;
2082 }
2083
2084 /* MIPS MT functions */
2085 target_ulong helper_dmt(void)
2086 {
2087 // TODO
2088 return 0;
2089 }
2090
2091 target_ulong helper_emt(void)
2092 {
2093 // TODO
2094 return 0;
2095 }
2096
2097 target_ulong helper_dvpe(CPUMIPSState *env)
2098 {
2099 CPUState *other_cs = first_cpu;
2100 target_ulong prev = env->mvp->CP0_MVPControl;
2101
2102 CPU_FOREACH(other_cs) {
2103 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2104 /* Turn off all VPEs except the one executing the dvpe. */
2105 if (&other_cpu->env != env) {
2106 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
2107 mips_vpe_sleep(other_cpu);
2108 }
2109 }
2110 return prev;
2111 }
2112
2113 target_ulong helper_evpe(CPUMIPSState *env)
2114 {
2115 CPUState *other_cs = first_cpu;
2116 target_ulong prev = env->mvp->CP0_MVPControl;
2117
2118 CPU_FOREACH(other_cs) {
2119 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2120
2121 if (&other_cpu->env != env
2122 /* If the VPE is WFI, don't disturb its sleep. */
2123 && !mips_vpe_is_wfi(other_cpu)) {
2124 /* Enable the VPE. */
2125 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
2126 mips_vpe_wake(other_cpu); /* And wake it up. */
2127 }
2128 }
2129 return prev;
2130 }
2131 #endif /* !CONFIG_USER_ONLY */
2132
2133 void helper_fork(target_ulong arg1, target_ulong arg2)
2134 {
2135 fprintf(stderr, "%s:%u - %s\n", __FILE__, __LINE__, __func__);
2136 // arg1 = rt, arg2 = rs
2137 // TODO: store to TC register, assert to detect test cases.
2138 g_assert_not_reached();
2139 }
2140
2141 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
2142 {
2143 target_long arg1 = arg;
2144
2145 if (arg1 < 0) {
2146 /* No scheduling policy implemented. */
2147 if (arg1 != -2) {
2148 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2149 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
2150 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2151 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2152 do_raise_exception(env, EXCP_THREAD, GETPC());
2153 }
2154 }
2155 } else if (arg1 == 0) {
2156 if (0 /* TODO: TC underflow */) {
2157 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2158 do_raise_exception(env, EXCP_THREAD, GETPC());
2159 } else {
2160 // TODO: Deallocate TC
2161 }
2162 } else if (arg1 > 0) {
2163 /* Yield qualifier inputs not implemented. */
2164 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2165 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2166 do_raise_exception(env, EXCP_THREAD, GETPC());
2167 }
2168 return env->CP0_YQMask;
2169 }
2170
2171 /* R6 Multi-threading */
2172 #ifndef CONFIG_USER_ONLY
2173 target_ulong helper_dvp(CPUMIPSState *env)
2174 {
2175 CPUState *other_cs = first_cpu;
2176 target_ulong prev = env->CP0_VPControl;
2177
2178 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
2179 CPU_FOREACH(other_cs) {
2180 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2181 /* Turn off all VPs except the one executing the dvp. */
2182 if (&other_cpu->env != env) {
2183 mips_vpe_sleep(other_cpu);
2184 }
2185 }
2186 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
2187 }
2188 return prev;
2189 }
2190
2191 target_ulong helper_evp(CPUMIPSState *env)
2192 {
2193 CPUState *other_cs = first_cpu;
2194 target_ulong prev = env->CP0_VPControl;
2195
2196 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
2197 CPU_FOREACH(other_cs) {
2198 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2199 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
2200 /* If the VP is WFI, don't disturb its sleep.
2201 * Otherwise, wake it up. */
2202 mips_vpe_wake(other_cpu);
2203 }
2204 }
2205 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
2206 }
2207 return prev;
2208 }
2209 #endif /* !CONFIG_USER_ONLY */
2210
2211 #ifndef CONFIG_USER_ONLY
2212 /* TLB management */
2213 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
2214 {
2215 /* Discard entries from env->tlb[first] onwards. */
2216 while (env->tlb->tlb_in_use > first) {
2217 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
2218 }
2219 }
2220
2221 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
2222 {
2223 #if defined(TARGET_MIPS64)
2224 return extract64(entrylo, 6, 54);
2225 #else
2226 return extract64(entrylo, 6, 24) | /* PFN */
2227 (extract64(entrylo, 32, 32) << 24); /* PFNX */
2228 #endif
2229 }
2230
2231 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
2232 {
2233 r4k_tlb_t *tlb;
2234 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
2235
2236 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2237 tlb = &env->tlb->mmu.r4k.tlb[idx];
2238 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
2239 tlb->EHINV = 1;
2240 return;
2241 }
2242 tlb->EHINV = 0;
2243 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2244 #if defined(TARGET_MIPS64)
2245 tlb->VPN &= env->SEGMask;
2246 #endif
2247 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2248 tlb->PageMask = env->CP0_PageMask;
2249 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2250 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
2251 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2252 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2253 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2254 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2255 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
2256 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2257 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2258 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2259 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2260 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2261 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
2262 }
2263
2264 void r4k_helper_tlbinv(CPUMIPSState *env)
2265 {
2266 int idx;
2267 r4k_tlb_t *tlb;
2268 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2269
2270 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2271 tlb = &env->tlb->mmu.r4k.tlb[idx];
2272 if (!tlb->G && tlb->ASID == ASID) {
2273 tlb->EHINV = 1;
2274 }
2275 }
2276 cpu_mips_tlb_flush(env);
2277 }
2278
2279 void r4k_helper_tlbinvf(CPUMIPSState *env)
2280 {
2281 int idx;
2282
2283 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2284 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2285 }
2286 cpu_mips_tlb_flush(env);
2287 }
2288
2289 void r4k_helper_tlbwi(CPUMIPSState *env)
2290 {
2291 r4k_tlb_t *tlb;
2292 int idx;
2293 target_ulong VPN;
2294 uint16_t ASID;
2295 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
2296
2297 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2298 tlb = &env->tlb->mmu.r4k.tlb[idx];
2299 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2300 #if defined(TARGET_MIPS64)
2301 VPN &= env->SEGMask;
2302 #endif
2303 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2304 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
2305 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2306 V0 = (env->CP0_EntryLo0 & 2) != 0;
2307 D0 = (env->CP0_EntryLo0 & 4) != 0;
2308 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
2309 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
2310 V1 = (env->CP0_EntryLo1 & 2) != 0;
2311 D1 = (env->CP0_EntryLo1 & 4) != 0;
2312 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
2313 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
2314
2315 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2316 permissions on the current entry. */
2317 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2318 (!tlb->EHINV && EHINV) ||
2319 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2320 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
2321 (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
2322 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
2323 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2324 }
2325
2326 r4k_invalidate_tlb(env, idx, 0);
2327 r4k_fill_tlb(env, idx);
2328 }
2329
2330 void r4k_helper_tlbwr(CPUMIPSState *env)
2331 {
2332 int r = cpu_mips_get_random(env);
2333
2334 r4k_invalidate_tlb(env, r, 1);
2335 r4k_fill_tlb(env, r);
2336 }
2337
2338 void r4k_helper_tlbp(CPUMIPSState *env)
2339 {
2340 r4k_tlb_t *tlb;
2341 target_ulong mask;
2342 target_ulong tag;
2343 target_ulong VPN;
2344 uint16_t ASID;
2345 int i;
2346
2347 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2348 for (i = 0; i < env->tlb->nb_tlb; i++) {
2349 tlb = &env->tlb->mmu.r4k.tlb[i];
2350 /* 1k pages are not supported. */
2351 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2352 tag = env->CP0_EntryHi & ~mask;
2353 VPN = tlb->VPN & ~mask;
2354 #if defined(TARGET_MIPS64)
2355 tag &= env->SEGMask;
2356 #endif
2357 /* Check ASID, virtual page number & size */
2358 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2359 /* TLB match */
2360 env->CP0_Index = i;
2361 break;
2362 }
2363 }
2364 if (i == env->tlb->nb_tlb) {
2365 /* No match. Discard any shadow entries, if any of them match. */
2366 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2367 tlb = &env->tlb->mmu.r4k.tlb[i];
2368 /* 1k pages are not supported. */
2369 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2370 tag = env->CP0_EntryHi & ~mask;
2371 VPN = tlb->VPN & ~mask;
2372 #if defined(TARGET_MIPS64)
2373 tag &= env->SEGMask;
2374 #endif
2375 /* Check ASID, virtual page number & size */
2376 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2377 r4k_mips_tlb_flush_extra (env, i);
2378 break;
2379 }
2380 }
2381
2382 env->CP0_Index |= 0x80000000;
2383 }
2384 }
2385
2386 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2387 {
2388 #if defined(TARGET_MIPS64)
2389 return tlb_pfn << 6;
2390 #else
2391 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2392 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2393 #endif
2394 }
2395
2396 void r4k_helper_tlbr(CPUMIPSState *env)
2397 {
2398 r4k_tlb_t *tlb;
2399 uint16_t ASID;
2400 int idx;
2401
2402 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2403 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2404 tlb = &env->tlb->mmu.r4k.tlb[idx];
2405
2406 /* If this will change the current ASID, flush qemu's TLB. */
2407 if (ASID != tlb->ASID)
2408 cpu_mips_tlb_flush(env);
2409
2410 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2411
2412 if (tlb->EHINV) {
2413 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2414 env->CP0_PageMask = 0;
2415 env->CP0_EntryLo0 = 0;
2416 env->CP0_EntryLo1 = 0;
2417 } else {
2418 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2419 env->CP0_PageMask = tlb->PageMask;
2420 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2421 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2422 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2423 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2424 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2425 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2426 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2427 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2428 }
2429 }
2430
2431 void helper_tlbwi(CPUMIPSState *env)
2432 {
2433 env->tlb->helper_tlbwi(env);
2434 }
2435
2436 void helper_tlbwr(CPUMIPSState *env)
2437 {
2438 env->tlb->helper_tlbwr(env);
2439 }
2440
2441 void helper_tlbp(CPUMIPSState *env)
2442 {
2443 env->tlb->helper_tlbp(env);
2444 }
2445
2446 void helper_tlbr(CPUMIPSState *env)
2447 {
2448 env->tlb->helper_tlbr(env);
2449 }
2450
2451 void helper_tlbinv(CPUMIPSState *env)
2452 {
2453 env->tlb->helper_tlbinv(env);
2454 }
2455
2456 void helper_tlbinvf(CPUMIPSState *env)
2457 {
2458 env->tlb->helper_tlbinvf(env);
2459 }
2460
2461 /* Specials */
2462 target_ulong helper_di(CPUMIPSState *env)
2463 {
2464 target_ulong t0 = env->CP0_Status;
2465
2466 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2467 return t0;
2468 }
2469
2470 target_ulong helper_ei(CPUMIPSState *env)
2471 {
2472 target_ulong t0 = env->CP0_Status;
2473
2474 env->CP0_Status = t0 | (1 << CP0St_IE);
2475 return t0;
2476 }
2477
2478 static void debug_pre_eret(CPUMIPSState *env)
2479 {
2480 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2481 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2482 env->active_tc.PC, env->CP0_EPC);
2483 if (env->CP0_Status & (1 << CP0St_ERL))
2484 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2485 if (env->hflags & MIPS_HFLAG_DM)
2486 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2487 qemu_log("\n");
2488 }
2489 }
2490
2491 static void debug_post_eret(CPUMIPSState *env)
2492 {
2493 MIPSCPU *cpu = mips_env_get_cpu(env);
2494
2495 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2496 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2497 env->active_tc.PC, env->CP0_EPC);
2498 if (env->CP0_Status & (1 << CP0St_ERL))
2499 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2500 if (env->hflags & MIPS_HFLAG_DM)
2501 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2502 switch (cpu_mmu_index(env, false)) {
2503 case 3:
2504 qemu_log(", ERL\n");
2505 break;
2506 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2507 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2508 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2509 default:
2510 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2511 break;
2512 }
2513 }
2514 }
2515
2516 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2517 {
2518 env->active_tc.PC = error_pc & ~(target_ulong)1;
2519 if (error_pc & 1) {
2520 env->hflags |= MIPS_HFLAG_M16;
2521 } else {
2522 env->hflags &= ~(MIPS_HFLAG_M16);
2523 }
2524 }
2525
2526 static inline void exception_return(CPUMIPSState *env)
2527 {
2528 debug_pre_eret(env);
2529 if (env->CP0_Status & (1 << CP0St_ERL)) {
2530 set_pc(env, env->CP0_ErrorEPC);
2531 env->CP0_Status &= ~(1 << CP0St_ERL);
2532 } else {
2533 set_pc(env, env->CP0_EPC);
2534 env->CP0_Status &= ~(1 << CP0St_EXL);
2535 }
2536 compute_hflags(env);
2537 debug_post_eret(env);
2538 }
2539
2540 void helper_eret(CPUMIPSState *env)
2541 {
2542 exception_return(env);
2543 env->CP0_LLAddr = 1;
2544 env->lladdr = 1;
2545 }
2546
2547 void helper_eretnc(CPUMIPSState *env)
2548 {
2549 exception_return(env);
2550 }
2551
2552 void helper_deret(CPUMIPSState *env)
2553 {
2554 debug_pre_eret(env);
2555
2556 env->hflags &= ~MIPS_HFLAG_DM;
2557 compute_hflags(env);
2558
2559 set_pc(env, env->CP0_DEPC);
2560
2561 debug_post_eret(env);
2562 }
2563 #endif /* !CONFIG_USER_ONLY */
2564
2565 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2566 {
2567 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2568 return;
2569 }
2570 do_raise_exception(env, EXCP_RI, pc);
2571 }
2572
2573 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2574 {
2575 check_hwrena(env, 0, GETPC());
2576 return env->CP0_EBase & 0x3ff;
2577 }
2578
2579 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2580 {
2581 check_hwrena(env, 1, GETPC());
2582 return env->SYNCI_Step;
2583 }
2584
2585 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2586 {
2587 check_hwrena(env, 2, GETPC());
2588 #ifdef CONFIG_USER_ONLY
2589 return env->CP0_Count;
2590 #else
2591 return (int32_t)cpu_mips_get_count(env);
2592 #endif
2593 }
2594
2595 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2596 {
2597 check_hwrena(env, 3, GETPC());
2598 return env->CCRes;
2599 }
2600
2601 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2602 {
2603 check_hwrena(env, 4, GETPC());
2604 return env->CP0_Performance0;
2605 }
2606
2607 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2608 {
2609 check_hwrena(env, 5, GETPC());
2610 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2611 }
2612
2613 void helper_pmon(CPUMIPSState *env, int function)
2614 {
2615 function /= 2;
2616 switch (function) {
2617 case 2: /* TODO: char inbyte(int waitflag); */
2618 if (env->active_tc.gpr[4] == 0)
2619 env->active_tc.gpr[2] = -1;
2620 /* Fall through */
2621 case 11: /* TODO: char inbyte (void); */
2622 env->active_tc.gpr[2] = -1;
2623 break;
2624 case 3:
2625 case 12:
2626 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2627 break;
2628 case 17:
2629 break;
2630 #ifndef CONFIG_USER_ONLY
2631 case 158:
2632 {
2633 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2634 printf("%s", fmt);
2635 }
2636 break;
2637 #endif
2638 }
2639 }
2640
2641 void QEMU_NORETURN helper_wait(CPUMIPSState *env)
2642 {
2643 CPUState *cs = CPU(mips_env_get_cpu(env));
2644
2645 cs->halted = 1;
2646 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2647 /* Last instruction in the block, PC was updated before
2648 - no need to recover PC and icount */
2649 raise_exception(env, EXCP_HLT);
2650 }
2651
2652 #if !defined(CONFIG_USER_ONLY)
2653
2654 void QEMU_NORETURN mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2655 MMUAccessType access_type,
2656 int mmu_idx, uintptr_t retaddr)
2657 {
2658 MIPSCPU *cpu = MIPS_CPU(cs);
2659 CPUMIPSState *env = &cpu->env;
2660 int error_code = 0;
2661 int excp;
2662
2663 if (!(env->hflags & MIPS_HFLAG_DM)) {
2664 env->CP0_BadVAddr = addr;
2665 }
2666
2667 if (access_type == MMU_DATA_STORE) {
2668 excp = EXCP_AdES;
2669 } else {
2670 excp = EXCP_AdEL;
2671 if (access_type == MMU_INST_FETCH) {
2672 error_code |= EXCP_INST_NOTAVAIL;
2673 }
2674 }
2675
2676 do_raise_exception_err(env, excp, error_code, retaddr);
2677 }
2678
2679 void tlb_fill(CPUState *cs, target_ulong addr, int size,
2680 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
2681 {
2682 int ret;
2683
2684 ret = mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
2685 if (ret) {
2686 MIPSCPU *cpu = MIPS_CPU(cs);
2687 CPUMIPSState *env = &cpu->env;
2688
2689 do_raise_exception_err(env, cs->exception_index,
2690 env->error_code, retaddr);
2691 }
2692 }
2693
2694 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2695 bool is_write, bool is_exec, int unused,
2696 unsigned size)
2697 {
2698 MIPSCPU *cpu = MIPS_CPU(cs);
2699 CPUMIPSState *env = &cpu->env;
2700
2701 /*
2702 * Raising an exception with KVM enabled will crash because it won't be from
2703 * the main execution loop so the longjmp won't have a matching setjmp.
2704 * Until we can trigger a bus error exception through KVM lets just ignore
2705 * the access.
2706 */
2707 if (kvm_enabled()) {
2708 /* TODO: here a return was replaced by an assertion. */
2709 g_assert_not_reached();
2710 }
2711
2712 if (is_exec) {
2713 raise_exception(env, EXCP_IBE);
2714 } else {
2715 raise_exception(env, EXCP_DBE);
2716 }
2717 }
2718 #endif /* !CONFIG_USER_ONLY */
2719
2720 /* Complex FPU operations which may need stack space. */
2721
2722 #define FLOAT_TWO32 make_float32(1 << 30)
2723 #define FLOAT_TWO64 make_float64(1ULL << 62)
2724
2725 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2726 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2727
2728 /* convert MIPS rounding mode in FCR31 to IEEE library */
2729 unsigned int ieee_rm[] = {
2730 float_round_nearest_even,
2731 float_round_to_zero,
2732 float_round_up,
2733 float_round_down
2734 };
2735
2736 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2737 {
2738 target_ulong arg1 = 0;
2739
2740 switch (reg) {
2741 case 0:
2742 arg1 = (int32_t)env->active_fpu.fcr0;
2743 break;
2744 case 1:
2745 /* UFR Support - Read Status FR */
2746 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2747 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2748 arg1 = (int32_t)
2749 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2750 } else {
2751 do_raise_exception(env, EXCP_RI, GETPC());
2752 }
2753 }
2754 break;
2755 case 5:
2756 /* FRE Support - read Config5.FRE bit */
2757 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2758 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2759 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2760 } else {
2761 helper_raise_exception(env, EXCP_RI);
2762 }
2763 }
2764 break;
2765 case 25:
2766 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2767 break;
2768 case 26:
2769 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2770 break;
2771 case 28:
2772 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2773 break;
2774 default:
2775 arg1 = (int32_t)env->active_fpu.fcr31;
2776 break;
2777 }
2778
2779 return arg1;
2780 }
2781
2782 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2783 {
2784 switch (fs) {
2785 case 1:
2786 /* UFR Alias - Reset Status FR */
2787 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2788 return;
2789 }
2790 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2791 env->CP0_Status &= ~(1 << CP0St_FR);
2792 compute_hflags(env);
2793 } else {
2794 do_raise_exception(env, EXCP_RI, GETPC());
2795 }
2796 break;
2797 case 4:
2798 /* UNFR Alias - Set Status FR */
2799 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2800 return;
2801 }
2802 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2803 env->CP0_Status |= (1 << CP0St_FR);
2804 compute_hflags(env);
2805 } else {
2806 do_raise_exception(env, EXCP_RI, GETPC());
2807 }
2808 break;
2809 case 5:
2810 /* FRE Support - clear Config5.FRE bit */
2811 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2812 return;
2813 }
2814 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2815 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2816 compute_hflags(env);
2817 } else {
2818 helper_raise_exception(env, EXCP_RI);
2819 }
2820 break;
2821 case 6:
2822 /* FRE Support - set Config5.FRE bit */
2823 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2824 return;
2825 }
2826 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2827 env->CP0_Config5 |= (1 << CP0C5_FRE);
2828 compute_hflags(env);
2829 } else {
2830 helper_raise_exception(env, EXCP_RI);
2831 }
2832 break;
2833 case 25:
2834 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2835 return;
2836 }
2837 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2838 ((arg1 & 0x1) << 23);
2839 break;
2840 case 26:
2841 if (arg1 & 0x007c0000)
2842 return;
2843 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2844 break;
2845 case 28:
2846 if (arg1 & 0x007c0000)
2847 return;
2848 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2849 ((arg1 & 0x4) << 22);
2850 break;
2851 case 31:
2852 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2853 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2854 break;
2855 default:
2856 if (env->insn_flags & ISA_MIPS32R6) {
2857 do_raise_exception(env, EXCP_RI, GETPC());
2858 }
2859 return;
2860 }
2861 restore_fp_status(env);
2862 set_float_exception_flags(0, &env->active_fpu.fp_status);
2863 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) {
2864 do_raise_exception(env, EXCP_FPE, GETPC());
2865 }
2866 }
2867
2868 int ieee_ex_to_mips(int xcpt)
2869 {
2870 int ret = 0;
2871 if (xcpt) {
2872 if (xcpt & float_flag_invalid) {
2873 ret |= FP_INVALID;
2874 }
2875 if (xcpt & float_flag_overflow) {
2876 ret |= FP_OVERFLOW;
2877 }
2878 if (xcpt & float_flag_underflow) {
2879 ret |= FP_UNDERFLOW;
2880 }
2881 if (xcpt & float_flag_divbyzero) {
2882 ret |= FP_DIV0;
2883 }
2884 if (xcpt & float_flag_inexact) {
2885 ret |= FP_INEXACT;
2886 }
2887 }
2888 return ret;
2889 }
2890
2891 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2892 {
2893 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2894
2895 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2896
2897 if (tmp) {
2898 set_float_exception_flags(0, &env->active_fpu.fp_status);
2899
2900 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2901 do_raise_exception(env, EXCP_FPE, pc);
2902 } else {
2903 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2904 }
2905 }
2906 }
2907
2908 /* Float support.
2909 Single precition routines have a "s" suffix, double precision a
2910 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2911 paired single lower "pl", paired single upper "pu". */
2912
2913 /* unary operations, modifying fp status */
2914 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2915 {
2916 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2917 update_fcr31(env, GETPC());
2918 return fdt0;
2919 }
2920
2921 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2922 {
2923 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2924 update_fcr31(env, GETPC());
2925 return fst0;
2926 }
2927
2928 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2929 {
2930 uint64_t fdt2;
2931
2932 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2933 update_fcr31(env, GETPC());
2934 return fdt2;
2935 }
2936
2937 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2938 {
2939 uint64_t fdt2;
2940
2941 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2942 update_fcr31(env, GETPC());
2943 return fdt2;
2944 }
2945
2946 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2947 {
2948 uint64_t fdt2;
2949
2950 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2951 update_fcr31(env, GETPC());
2952 return fdt2;
2953 }
2954
2955 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2956 {
2957 uint64_t dt2;
2958
2959 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2960 if (get_float_exception_flags(&env->active_fpu.fp_status)
2961 & (float_flag_invalid | float_flag_overflow)) {
2962 dt2 = FP_TO_INT64_OVERFLOW;
2963 }
2964 update_fcr31(env, GETPC());
2965 return dt2;
2966 }
2967
2968 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2969 {
2970 uint64_t dt2;
2971
2972 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2973 if (get_float_exception_flags(&env->active_fpu.fp_status)
2974 & (float_flag_invalid | float_flag_overflow)) {
2975 dt2 = FP_TO_INT64_OVERFLOW;
2976 }
2977 update_fcr31(env, GETPC());
2978 return dt2;
2979 }
2980
2981 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2982 {
2983 uint32_t fst2;
2984 uint32_t fsth2;
2985
2986 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2987 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2988 update_fcr31(env, GETPC());
2989 return ((uint64_t)fsth2 << 32) | fst2;
2990 }
2991
2992 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2993 {
2994 uint32_t wt2;
2995 uint32_t wth2;
2996 int excp, excph;
2997
2998 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2999 excp = get_float_exception_flags(&env->active_fpu.fp_status);
3000 if (excp & (float_flag_overflow | float_flag_invalid)) {
3001 wt2 = FP_TO_INT32_OVERFLOW;
3002 }
3003
3004 set_float_exception_flags(0, &env->active_fpu.fp_status);
3005 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
3006 excph = get_float_exception_flags(&env->active_fpu.fp_status);
3007 if (excph & (float_flag_overflow | float_flag_invalid)) {
3008 wth2 = FP_TO_INT32_OVERFLOW;
3009 }
3010
3011 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
3012 update_fcr31(env, GETPC());
3013
3014 return ((uint64_t)wth2 << 32) | wt2;
3015 }
3016
3017 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
3018 {
3019 uint32_t fst2;
3020
3021 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
3022 update_fcr31(env, GETPC());
3023 return fst2;
3024 }
3025
3026 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
3027 {
3028 uint32_t fst2;
3029
3030 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
3031 update_fcr31(env, GETPC());
3032 return fst2;
3033 }
3034
3035 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
3036 {
3037 uint32_t fst2;
3038
3039 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
3040 update_fcr31(env, GETPC());
3041 return fst2;
3042 }
3043
3044 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
3045 {
3046 uint32_t wt2;
3047
3048 wt2 = wt0;
3049 update_fcr31(env, GETPC());
3050 return wt2;
3051 }
3052
3053 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
3054 {
3055 uint32_t wt2;
3056
3057 wt2 = wth0;
3058 update_fcr31(env, GETPC());
3059 return wt2;
3060 }
3061
3062 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
3063 {
3064 uint32_t wt2;
3065
3066 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3067 if (get_float_exception_flags(&env->active_fpu.fp_status)
3068 & (float_flag_invalid | float_flag_overflow)) {
3069 wt2 = FP_TO_INT32_OVERFLOW;
3070 }
3071 update_fcr31(env, GETPC());
3072 return wt2;
3073 }
3074
3075 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
3076 {
3077 uint32_t wt2;
3078
3079 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3080 if (get_float_exception_flags(&env->active_fpu.fp_status)
3081 & (float_flag_invalid | float_flag_overflow)) {
3082 wt2 = FP_TO_INT32_OVERFLOW;
3083 }
3084 update_fcr31(env, GETPC());
3085 return wt2;
3086 }
3087
3088 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
3089 {
3090 uint64_t dt2;
3091
3092 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3093 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3094 restore_rounding_mode(env);
3095 if (get_float_exception_flags(&env->active_fpu.fp_status)
3096 & (float_flag_invalid | float_flag_overflow)) {
3097 dt2 = FP_TO_INT64_OVERFLOW;
3098 }
3099 update_fcr31(env, GETPC());
3100 return dt2;
3101 }
3102
3103 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
3104 {
3105 uint64_t dt2;
3106
3107 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3108 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3109 restore_rounding_mode(env);
3110 if (get_float_exception_flags(&env->active_fpu.fp_status)
3111 & (float_flag_invalid | float_flag_overflow)) {
3112 dt2 = FP_TO_INT64_OVERFLOW;
3113 }
3114 update_fcr31(env, GETPC());
3115 return dt2;
3116 }
3117
3118 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
3119 {
3120 uint32_t wt2;
3121
3122 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3123 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3124 restore_rounding_mode(env);
3125 if (get_float_exception_flags(&env->active_fpu.fp_status)
3126 & (float_flag_invalid | float_flag_overflow)) {
3127 wt2 = FP_TO_INT32_OVERFLOW;
3128 }
3129 update_fcr31(env, GETPC());
3130 return wt2;
3131 }
3132
3133 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
3134 {
3135 uint32_t wt2;
3136
3137 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3138 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3139 restore_rounding_mode(env);
3140 if (get_float_exception_flags(&env->active_fpu.fp_status)
3141 & (float_flag_invalid | float_flag_overflow)) {
3142 wt2 = FP_TO_INT32_OVERFLOW;
3143 }
3144 update_fcr31(env, GETPC());
3145 return wt2;
3146 }
3147
3148 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
3149 {
3150 uint64_t dt2;
3151
3152 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3153 if (get_float_exception_flags(&env->active_fpu.fp_status)
3154 & (float_flag_invalid | float_flag_overflow)) {
3155 dt2 = FP_TO_INT64_OVERFLOW;
3156 }
3157 update_fcr31(env, GETPC());
3158 return dt2;
3159 }
3160
3161 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
3162 {
3163 uint64_t dt2;
3164
3165 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3166 if (get_float_exception_flags(&env->active_fpu.fp_status)
3167 & (float_flag_invalid | float_flag_overflow)) {
3168 dt2 = FP_TO_INT64_OVERFLOW;
3169 }
3170 update_fcr31(env, GETPC());
3171 return dt2;
3172 }
3173
3174 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
3175 {
3176 uint32_t wt2;
3177
3178 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3179 if (get_float_exception_flags(&env->active_fpu.fp_status)
3180 & (float_flag_invalid | float_flag_overflow)) {
3181 wt2 = FP_TO_INT32_OVERFLOW;
3182 }
3183 update_fcr31(env, GETPC());
3184 return wt2;
3185 }
3186
3187 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
3188 {
3189 uint32_t wt2;
3190
3191 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3192 if (get_float_exception_flags(&env->active_fpu.fp_status)
3193 & (float_flag_invalid | float_flag_overflow)) {
3194 wt2 = FP_TO_INT32_OVERFLOW;
3195 }
3196 update_fcr31(env, GETPC());
3197 return wt2;
3198 }
3199
3200 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
3201 {
3202 uint64_t dt2;
3203
3204 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3205 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3206 restore_rounding_mode(env);
3207 if (get_float_exception_flags(&env->active_fpu.fp_status)
3208 & (float_flag_invalid | float_flag_overflow)) {
3209 dt2 = FP_TO_INT64_OVERFLOW;
3210 }
3211 update_fcr31(env, GETPC());
3212 return dt2;
3213 }
3214
3215 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
3216 {
3217 uint64_t dt2;
3218
3219 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3220 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3221 restore_rounding_mode(env);
3222 if (get_float_exception_flags(&env->active_fpu.fp_status)
3223 & (float_flag_invalid | float_flag_overflow)) {
3224 dt2 = FP_TO_INT64_OVERFLOW;
3225 }
3226 update_fcr31(env, GETPC());
3227 return dt2;
3228 }
3229
3230 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
3231 {
3232 uint32_t wt2;
3233
3234 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3235 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3236 restore_rounding_mode(env);
3237 if (get_float_exception_flags(&env->active_fpu.fp_status)
3238 & (float_flag_invalid | float_flag_overflow)) {
3239 wt2 = FP_TO_INT32_OVERFLOW;
3240 }
3241 update_fcr31(env, GETPC());
3242 return wt2;
3243 }
3244
3245 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
3246 {
3247 uint32_t wt2;
3248
3249 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3250 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3251 restore_rounding_mode(env);
3252 if (get_float_exception_flags(&env->active_fpu.fp_status)
3253 & (float_flag_invalid | float_flag_overflow)) {
3254 wt2 = FP_TO_INT32_OVERFLOW;
3255 }
3256 update_fcr31(env, GETPC());
3257 return wt2;
3258 }
3259
3260 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
3261 {
3262 uint64_t dt2;
3263
3264 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3265 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3266 restore_rounding_mode(env);
3267 if (get_float_exception_flags(&env->active_fpu.fp_status)
3268 & (float_flag_invalid | float_flag_overflow)) {
3269 dt2 = FP_TO_INT64_OVERFLOW;
3270 }
3271 update_fcr31(env, GETPC());
3272 return dt2;
3273 }
3274
3275 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3276 {
3277 uint64_t dt2;
3278
3279 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3280 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3281 restore_rounding_mode(env);
3282 if (get_float_exception_flags(&env->active_fpu.fp_status)
3283 & (float_flag_invalid | float_flag_overflow)) {
3284 dt2 = FP_TO_INT64_OVERFLOW;
3285 }
3286 update_fcr31(env, GETPC());
3287 return dt2;
3288 }
3289
3290 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3291 {
3292 uint32_t wt2;
3293
3294 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3295 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3296 restore_rounding_mode(env);
3297 if (get_float_exception_flags(&env->active_fpu.fp_status)
3298 & (float_flag_invalid | float_flag_overflow)) {
3299 wt2 = FP_TO_INT32_OVERFLOW;
3300 }
3301 update_fcr31(env, GETPC());
3302 return wt2;
3303 }
3304
3305 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3306 {
3307 uint32_t wt2;
3308
3309 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3310 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3311 restore_rounding_mode(env);
3312 if (get_float_exception_flags(&env->active_fpu.fp_status)
3313 & (float_flag_invalid | float_flag_overflow)) {
3314 wt2 = FP_TO_INT32_OVERFLOW;
3315 }
3316 update_fcr31(env, GETPC());
3317 return wt2;
3318 }
3319
3320 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3321 {
3322 uint64_t dt2;
3323
3324 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3325 if (get_float_exception_flags(&env->active_fpu.fp_status)
3326 & float_flag_invalid) {
3327 if (float64_is_any_nan(fdt0)) {
3328 dt2 = 0;
3329 }
3330 }
3331 update_fcr31(env, GETPC());
3332 return dt2;
3333 }
3334
3335 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3336 {
3337 uint64_t dt2;
3338
3339 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3340 if (get_float_exception_flags(&env->active_fpu.fp_status)
3341 & float_flag_invalid) {
3342 if (float32_is_any_nan(fst0)) {
3343 dt2 = 0;
3344 }
3345 }
3346 update_fcr31(env, GETPC());
3347 return dt2;
3348 }
3349
3350 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3351 {
3352 uint32_t wt2;
3353
3354 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3355 if (get_float_exception_flags(&env->active_fpu.fp_status)
3356 & float_flag_invalid) {
3357 if (float64_is_any_nan(fdt0)) {
3358 wt2 = 0;
3359 }
3360 }
3361 update_fcr31(env, GETPC());
3362 return wt2;
3363 }
3364
3365 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3366 {
3367 uint32_t wt2;
3368
3369 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3370 if (get_float_exception_flags(&env->active_fpu.fp_status)
3371 & float_flag_invalid) {
3372 if (float32_is_any_nan(fst0)) {
3373 wt2 = 0;
3374 }
3375 }
3376 update_fcr31(env, GETPC());
3377 return wt2;
3378 }
3379
3380 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3381 {
3382 uint64_t dt2;
3383
3384 set_float_rounding_mode(float_round_nearest_even,
3385 &env->active_fpu.fp_status);
3386 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3387 restore_rounding_mode(env);
3388 if (get_float_exception_flags(&env->active_fpu.fp_status)
3389 & float_flag_invalid) {
3390 if (float64_is_any_nan(fdt0)) {
3391 dt2 = 0;
3392 }
3393 }
3394 update_fcr31(env, GETPC());
3395 return dt2;
3396 }
3397
3398 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3399 {
3400 uint64_t dt2;
3401
3402 set_float_rounding_mode(float_round_nearest_even,
3403 &env->active_fpu.fp_status);
3404 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3405 restore_rounding_mode(env);
3406 if (get_float_exception_flags(&env->active_fpu.fp_status)
3407 & float_flag_invalid) {
3408 if (float32_is_any_nan(fst0)) {
3409 dt2 = 0;
3410 }
3411 }
3412 update_fcr31(env, GETPC());
3413 return dt2;
3414 }
3415
3416 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3417 {
3418 uint32_t wt2;
3419
3420 set_float_rounding_mode(float_round_nearest_even,
3421 &env->active_fpu.fp_status);
3422 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3423 restore_rounding_mode(env);
3424 if (get_float_exception_flags(&env->active_fpu.fp_status)
3425 & float_flag_invalid) {
3426 if (float64_is_any_nan(fdt0)) {
3427 wt2 = 0;
3428 }
3429 }
3430 update_fcr31(env, GETPC());
3431 return wt2;
3432 }
3433
3434 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3435 {
3436 uint32_t wt2;
3437
3438 set_float_rounding_mode(float_round_nearest_even,
3439 &env->active_fpu.fp_status);
3440 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3441 restore_rounding_mode(env);
3442 if (get_float_exception_flags(&env->active_fpu.fp_status)
3443 & float_flag_invalid) {
3444 if (float32_is_any_nan(fst0)) {
3445 wt2 = 0;
3446 }
3447 }
3448 update_fcr31(env, GETPC());
3449 return wt2;
3450 }
3451
3452 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3453 {
3454 uint64_t dt2;
3455
3456 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3457 if (get_float_exception_flags(&env->active_fpu.fp_status)
3458 & float_flag_invalid) {
3459 if (float64_is_any_nan(fdt0)) {
3460 dt2 = 0;
3461 }
3462 }
3463 update_fcr31(env, GETPC());
3464 return dt2;
3465 }
3466
3467 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3468 {
3469 uint64_t dt2;
3470
3471 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3472 if (get_float_exception_flags(&env->active_fpu.fp_status)
3473 & float_flag_invalid) {
3474 if (float32_is_any_nan(fst0)) {
3475 dt2 = 0;
3476 }
3477 }
3478 update_fcr31(env, GETPC());
3479 return dt2;
3480 }
3481
3482 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3483 {
3484 uint32_t wt2;
3485
3486 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3487 if (get_float_exception_flags(&env->active_fpu.fp_status)
3488 & float_flag_invalid) {
3489 if (float64_is_any_nan(fdt0)) {
3490 wt2 = 0;
3491 }
3492 }
3493 update_fcr31(env, GETPC());
3494 return wt2;
3495 }
3496
3497 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3498 {
3499 uint32_t wt2;
3500
3501 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3502 if (get_float_exception_flags(&env->active_fpu.fp_status)
3503 & float_flag_invalid) {
3504 if (float32_is_any_nan(fst0)) {
3505 wt2 = 0;
3506 }
3507 }
3508 update_fcr31(env, GETPC());
3509 return wt2;
3510 }
3511
3512 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3513 {
3514 uint64_t dt2;
3515
3516 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3517 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3518 restore_rounding_mode(env);
3519 if (get_float_exception_flags(&env->active_fpu.fp_status)
3520 & float_flag_invalid) {
3521 if (float64_is_any_nan(fdt0)) {
3522 dt2 = 0;
3523 }
3524 }
3525 update_fcr31(env, GETPC());
3526 return dt2;
3527 }
3528
3529 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3530 {
3531 uint64_t dt2;
3532
3533 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3534 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3535 restore_rounding_mode(env);
3536 if (get_float_exception_flags(&env->active_fpu.fp_status)
3537 & float_flag_invalid) {
3538 if (float32_is_any_nan(fst0)) {
3539 dt2 = 0;
3540 }
3541 }
3542 update_fcr31(env, GETPC());
3543 return dt2;
3544 }
3545
3546 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3547 {
3548 uint32_t wt2;
3549
3550 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3551 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3552 restore_rounding_mode(env);
3553 if (get_float_exception_flags(&env->active_fpu.fp_status)
3554 & float_flag_invalid) {
3555 if (float64_is_any_nan(fdt0)) {
3556 wt2 = 0;
3557 }
3558 }
3559 update_fcr31(env, GETPC());
3560 return wt2;
3561 }
3562
3563 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3564 {
3565 uint32_t wt2;
3566
3567 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3568 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3569 restore_rounding_mode(env);
3570 if (get_float_exception_flags(&env->active_fpu.fp_status)
3571 & float_flag_invalid) {
3572 if (float32_is_any_nan(fst0)) {
3573 wt2 = 0;
3574 }
3575 }
3576 update_fcr31(env, GETPC());
3577 return wt2;
3578 }
3579
3580 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3581 {
3582 uint64_t dt2;
3583
3584 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3585 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3586 restore_rounding_mode(env);
3587 if (get_float_exception_flags(&env->active_fpu.fp_status)
3588 & float_flag_invalid) {
3589 if (float64_is_any_nan(fdt0)) {
3590 dt2 = 0;
3591 }
3592 }
3593 update_fcr31(env, GETPC());
3594 return dt2;
3595 }
3596
3597 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3598 {
3599 uint64_t dt2;
3600
3601 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3602 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3603 restore_rounding_mode(env);
3604 if (get_float_exception_flags(&env->active_fpu.fp_status)
3605 & float_flag_invalid) {
3606 if (float32_is_any_nan(fst0)) {
3607 dt2 = 0;
3608 }
3609 }
3610 update_fcr31(env, GETPC());
3611 return dt2;
3612 }
3613
3614 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3615 {
3616 uint32_t wt2;
3617
3618 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3619 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3620 restore_rounding_mode(env);
3621 if (get_float_exception_flags(&env->active_fpu.fp_status)
3622 & float_flag_invalid) {
3623 if (float64_is_any_nan(fdt0)) {
3624 wt2 = 0;
3625 }
3626 }
3627 update_fcr31(env, GETPC());
3628 return wt2;
3629 }
3630
3631 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3632 {
3633 uint32_t wt2;
3634
3635 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3636 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3637 restore_rounding_mode(env);
3638 if (get_float_exception_flags(&env->active_fpu.fp_status)
3639 & float_flag_invalid) {
3640 if (float32_is_any_nan(fst0)) {
3641 wt2 = 0;
3642 }
3643 }
3644 update_fcr31(env, GETPC());
3645 return wt2;
3646 }
3647
3648 /* unary operations, not modifying fp status */
3649 #define FLOAT_UNOP(name) \
3650 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3651 { \
3652 return float64_ ## name(fdt0); \
3653 } \
3654 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3655 { \
3656 return float32_ ## name(fst0); \
3657 } \
3658 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3659 { \
3660 uint32_t wt0; \
3661 uint32_t wth0; \
3662 \
3663 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3664 wth0 = float32_ ## name(fdt0 >> 32); \
3665 return ((uint64_t)wth0 << 32) | wt0; \
3666 }
3667 FLOAT_UNOP(abs)
3668 FLOAT_UNOP(chs)
3669 #undef FLOAT_UNOP
3670
3671 /* MIPS specific unary operations */
3672 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3673 {
3674 uint64_t fdt2;
3675
3676 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3677 update_fcr31(env, GETPC());
3678 return fdt2;
3679 }
3680
3681 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3682 {
3683 uint32_t fst2;
3684
3685 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3686 update_fcr31(env, GETPC());
3687 return fst2;
3688 }
3689
3690 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3691 {
3692 uint64_t fdt2;
3693
3694 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3695 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3696 update_fcr31(env, GETPC());
3697 return fdt2;
3698 }
3699
3700 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3701 {
3702 uint32_t fst2;
3703
3704 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3705 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3706 update_fcr31(env, GETPC());
3707 return fst2;
3708 }
3709
3710 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3711 {
3712 uint64_t fdt2;
3713
3714 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3715 update_fcr31(env, GETPC());
3716 return fdt2;
3717 }
3718
3719 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3720 {
3721 uint32_t fst2;
3722
3723 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3724 update_fcr31(env, GETPC());
3725 return fst2;
3726 }
3727
3728 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3729 {
3730 uint32_t fst2;
3731 uint32_t fsth2;
3732
3733 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3734 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3735 update_fcr31(env, GETPC());
3736 return ((uint64_t)fsth2 << 32) | fst2;
3737 }
3738
3739 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3740 {
3741 uint64_t fdt2;
3742
3743 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3744 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3745 update_fcr31(env, GETPC());
3746 return fdt2;
3747 }
3748
3749 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3750 {
3751 uint32_t fst2;
3752
3753 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3754 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3755 update_fcr31(env, GETPC());
3756 return fst2;
3757 }
3758
3759 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3760 {
3761 uint32_t fst2;
3762 uint32_t fsth2;
3763
3764 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3765 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3766 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3767 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3768 update_fcr31(env, GETPC());
3769 return ((uint64_t)fsth2 << 32) | fst2;
3770 }
3771
3772 #define FLOAT_RINT(name, bits) \
3773 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3774 uint ## bits ## _t fs) \
3775 { \
3776 uint ## bits ## _t fdret; \
3777 \
3778 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3779 update_fcr31(env, GETPC()); \
3780 return fdret; \
3781 }
3782
3783 FLOAT_RINT(rint_s, 32)
3784 FLOAT_RINT(rint_d, 64)
3785 #undef FLOAT_RINT
3786
3787 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3788 #define FLOAT_CLASS_QUIET_NAN 0x002
3789 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3790 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3791 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3792 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3793 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3794 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3795 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3796 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3797
3798 #define FLOAT_CLASS(name, bits) \
3799 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3800 float_status *status) \
3801 { \
3802 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3803 return FLOAT_CLASS_SIGNALING_NAN; \
3804 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3805 return FLOAT_CLASS_QUIET_NAN; \
3806 } else if (float ## bits ## _is_neg(arg)) { \
3807 if (float ## bits ## _is_infinity(arg)) { \
3808 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3809 } else if (float ## bits ## _is_zero(arg)) { \
3810 return FLOAT_CLASS_NEGATIVE_ZERO; \
3811 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3812 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3813 } else { \
3814 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3815 } \
3816 } else { \
3817 if (float ## bits ## _is_infinity(arg)) { \
3818 return FLOAT_CLASS_POSITIVE_INFINITY; \
3819 } else if (float ## bits ## _is_zero(arg)) { \
3820 return FLOAT_CLASS_POSITIVE_ZERO; \
3821 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3822 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3823 } else { \
3824 return FLOAT_CLASS_POSITIVE_NORMAL; \
3825 } \
3826 } \
3827 } \
3828 \
3829 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3830 uint ## bits ## _t arg) \
3831 { \
3832 return float_ ## name(arg, &env->active_fpu.fp_status); \
3833 }
3834
3835 FLOAT_CLASS(class_s, 32)
3836 FLOAT_CLASS(class_d, 64)
3837 #undef FLOAT_CLASS
3838
3839 /* binary operations */
3840 #define FLOAT_BINOP(name) \
3841 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3842 uint64_t fdt0, uint64_t fdt1) \
3843 { \
3844 uint64_t dt2; \
3845 \
3846 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3847 update_fcr31(env, GETPC()); \
3848 return dt2; \
3849 } \
3850 \
3851 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3852 uint32_t fst0, uint32_t fst1) \
3853 { \
3854 uint32_t wt2; \
3855 \
3856 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3857 update_fcr31(env, GETPC()); \
3858 return wt2; \
3859 } \
3860 \
3861 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3862 uint64_t fdt0, \
3863 uint64_t fdt1) \
3864 { \
3865 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3866 uint32_t fsth0 = fdt0 >> 32; \
3867 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3868 uint32_t fsth1 = fdt1 >> 32; \
3869 uint32_t wt2; \
3870 uint32_t wth2; \
3871 \
3872 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3873 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3874 update_fcr31(env, GETPC()); \
3875 return ((uint64_t)wth2 << 32) | wt2; \
3876 }
3877
3878 FLOAT_BINOP(add)
3879 FLOAT_BINOP(sub)
3880 FLOAT_BINOP(mul)
3881 FLOAT_BINOP(div)
3882 #undef FLOAT_BINOP
3883
3884 /* MIPS specific binary operations */
3885 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3886 {
3887 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3888 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3889 update_fcr31(env, GETPC());
3890 return fdt2;
3891 }
3892
3893 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3894 {
3895 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3896 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3897 update_fcr31(env, GETPC());
3898 return fst2;
3899 }
3900
3901 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3902 {
3903 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3904 uint32_t fsth0 = fdt0 >> 32;
3905 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3906 uint32_t fsth2 = fdt2 >> 32;
3907
3908 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3909 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3910 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3911 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3912 update_fcr31(env, GETPC());
3913 return ((uint64_t)fsth2 << 32) | fst2;
3914 }
3915
3916 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3917 {
3918 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3919 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3920 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3921 update_fcr31(env, GETPC());
3922 return fdt2;
3923 }
3924
3925 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3926 {
3927 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3928 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3929 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3930 update_fcr31(env, GETPC());
3931 return fst2;
3932 }
3933
3934 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3935 {
3936 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3937 uint32_t fsth0 = fdt0 >> 32;
3938 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3939 uint32_t fsth2 = fdt2 >> 32;
3940
3941 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3942 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3943 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3944 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3945 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3946 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3947 update_fcr31(env, GETPC());
3948 return ((uint64_t)fsth2 << 32) | fst2;
3949 }
3950
3951 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3952 {
3953 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3954 uint32_t fsth0 = fdt0 >> 32;
3955 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3956 uint32_t fsth1 = fdt1 >> 32;
3957 uint32_t fst2;
3958 uint32_t fsth2;
3959
3960 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3961 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3962 update_fcr31(env, GETPC());
3963 return ((uint64_t)fsth2 << 32) | fst2;
3964 }
3965
3966 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3967 {
3968 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3969 uint32_t fsth0 = fdt0 >> 32;
3970 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3971 uint32_t fsth1 = fdt1 >> 32;
3972 uint32_t fst2;
3973 uint32_t fsth2;
3974
3975 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3976 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3977 update_fcr31(env, GETPC());
3978 return ((uint64_t)fsth2 << 32) | fst2;
3979 }
3980
3981 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3982 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3983 uint ## bits ## _t fs, \
3984 uint ## bits ## _t ft) \
3985 { \
3986 uint ## bits ## _t fdret; \
3987 \
3988 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3989 &env->active_fpu.fp_status); \
3990 update_fcr31(env, GETPC()); \
3991 return fdret; \
3992 }
3993
3994 FLOAT_MINMAX(max_s, 32, maxnum)
3995 FLOAT_MINMAX(max_d, 64, maxnum)
3996 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3997 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3998
3999 FLOAT_MINMAX(min_s, 32, minnum)
4000 FLOAT_MINMAX(min_d, 64, minnum)
4001 FLOAT_MINMAX(mina_s, 32, minnummag)
4002 FLOAT_MINMAX(mina_d, 64, minnummag)
4003 #undef FLOAT_MINMAX
4004
4005 /* ternary operations */
4006 #define UNFUSED_FMA(prefix, a, b, c, flags) \
4007 { \
4008 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
4009 if ((flags) & float_muladd_negate_c) { \
4010 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
4011 } else { \
4012 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
4013 } \
4014 if ((flags) & float_muladd_negate_result) { \
4015 a = prefix##_chs(a); \
4016 } \
4017 }
4018
4019 /* FMA based operations */
4020 #define FLOAT_FMA(name, type) \
4021 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
4022 uint64_t fdt0, uint64_t fdt1, \
4023 uint64_t fdt2) \
4024 { \
4025 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
4026 update_fcr31(env, GETPC()); \
4027 return fdt0; \
4028 } \
4029 \
4030 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
4031 uint32_t fst0, uint32_t fst1, \
4032 uint32_t fst2) \
4033 { \
4034 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4035 update_fcr31(env, GETPC()); \
4036 return fst0; \
4037 } \
4038 \
4039 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
4040 uint64_t fdt0, uint64_t fdt1, \
4041 uint64_t fdt2) \
4042 { \
4043 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4044 uint32_t fsth0 = fdt0 >> 32; \
4045 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4046 uint32_t fsth1 = fdt1 >> 32; \
4047 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4048 uint32_t fsth2 = fdt2 >> 32; \
4049 \
4050 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4051 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4052 update_fcr31(env, GETPC()); \
4053 return ((uint64_t)fsth0 << 32) | fst0; \
4054 }
4055 FLOAT_FMA(madd, 0)
4056 FLOAT_FMA(msub, float_muladd_negate_c)
4057 FLOAT_FMA(nmadd, float_muladd_negate_result)
4058 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
4059 #undef FLOAT_FMA
4060
4061 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4062 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4063 uint ## bits ## _t fs, \
4064 uint ## bits ## _t ft, \
4065 uint ## bits ## _t fd) \
4066 { \
4067 uint ## bits ## _t fdret; \
4068 \
4069 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4070 &env->active_fpu.fp_status); \
4071 update_fcr31(env, GETPC()); \
4072 return fdret; \
4073 }
4074
4075 FLOAT_FMADDSUB(maddf_s, 32, 0)
4076 FLOAT_FMADDSUB(maddf_d, 64, 0)
4077 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
4078 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
4079 #undef FLOAT_FMADDSUB
4080
4081 /* compare operations */
4082 #define FOP_COND_D(op, cond) \
4083 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4084 uint64_t fdt1, int cc) \
4085 { \
4086 int c; \
4087 c = cond; \
4088 update_fcr31(env, GETPC()); \
4089 if (c) \
4090 SET_FP_COND(cc, env->active_fpu); \
4091 else \
4092 CLEAR_FP_COND(cc, env->active_fpu); \
4093 } \
4094 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4095 uint64_t fdt1, int cc) \
4096 { \
4097 int c; \
4098 fdt0 = float64_abs(fdt0); \
4099 fdt1 = float64_abs(fdt1); \
4100 c = cond; \
4101 update_fcr31(env, GETPC()); \
4102 if (c) \
4103 SET_FP_COND(cc, env->active_fpu); \
4104 else \
4105 CLEAR_FP_COND(cc, env->active_fpu); \
4106 }
4107
4108 /* NOTE: the comma operator will make "cond" to eval to false,
4109 * but float64_unordered_quiet() is still called. */
4110 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4111 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
4112 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4113 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4114 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4115 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4116 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4117 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4118 /* NOTE: the comma operator will make "cond" to eval to false,
4119 * but float64_unordered() is still called. */
4120 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4121 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
4122 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4123 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4124 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4125 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4126 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4127 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4128
4129 #define FOP_COND_S(op, cond) \
4130 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4131 uint32_t fst1, int cc) \
4132 { \
4133 int c; \
4134 c = cond; \
4135 update_fcr31(env, GETPC()); \
4136 if (c) \
4137 SET_FP_COND(cc, env->active_fpu); \
4138 else \
4139 CLEAR_FP_COND(cc, env->active_fpu); \
4140 } \
4141 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4142 uint32_t fst1, int cc) \
4143 { \
4144 int c; \
4145 fst0 = float32_abs(fst0); \
4146 fst1 = float32_abs(fst1); \
4147 c = cond; \
4148 update_fcr31(env, GETPC()); \
4149 if (c) \
4150 SET_FP_COND(cc, env->active_fpu); \
4151 else \
4152 CLEAR_FP_COND(cc, env->active_fpu); \
4153 }
4154
4155 /* NOTE: the comma operator will make "cond" to eval to false,
4156 * but float32_unordered_quiet() is still called. */
4157 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4158 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
4159 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4160 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4161 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4162 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4163 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4164 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4165 /* NOTE: the comma operator will make "cond" to eval to false,
4166 * but float32_unordered() is still called. */
4167 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4168 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
4169 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4170 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4171 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4172 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4173 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
4174 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
4175
4176 #define FOP_COND_PS(op, condl, condh) \
4177 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4178 uint64_t fdt1, int cc) \
4179 { \
4180 uint32_t fst0, fsth0, fst1, fsth1; \
4181 int ch, cl; \
4182 fst0 = fdt0 & 0XFFFFFFFF; \
4183 fsth0 = fdt0 >> 32; \
4184 fst1 = fdt1 & 0XFFFFFFFF; \
4185 fsth1 = fdt1 >> 32; \
4186 cl = condl; \
4187 ch = condh; \
4188 update_fcr31(env, GETPC()); \
4189 if (cl) \
4190 SET_FP_COND(cc, env->active_fpu); \
4191 else \
4192 CLEAR_FP_COND(cc, env->active_fpu); \
4193 if (ch) \
4194 SET_FP_COND(cc + 1, env->active_fpu); \
4195 else \
4196 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4197 } \
4198 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4199 uint64_t fdt1, int cc) \
4200 { \
4201 uint32_t fst0, fsth0, fst1, fsth1; \
4202 int ch, cl; \
4203 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4204 fsth0 = float32_abs(fdt0 >> 32); \
4205 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4206 fsth1 = float32_abs(fdt1 >> 32); \
4207 cl = condl; \
4208 ch = condh; \
4209 update_fcr31(env, GETPC()); \
4210 if (cl) \
4211 SET_FP_COND(cc, env->active_fpu); \
4212 else \
4213 CLEAR_FP_COND(cc, env->active_fpu); \
4214 if (ch) \
4215 SET_FP_COND(cc + 1, env->active_fpu); \
4216 else \
4217 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4218 }
4219
4220 /* NOTE: the comma operator will make "cond" to eval to false,
4221 * but float32_unordered_quiet() is still called. */
4222 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
4223 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4224 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
4225 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
4226 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4227 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4228 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4229 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4230 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4231 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4232 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4233 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4234 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4235 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4236 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4237 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4238 /* NOTE: the comma operator will make "cond" to eval to false,
4239 * but float32_unordered() is still called. */
4240 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
4241 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4242 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
4243 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
4244 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4245 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4246 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4247 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4248 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4249 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4250 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4251 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4252 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
4253 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4254 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
4255 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4256
4257 /* R6 compare operations */
4258 #define FOP_CONDN_D(op, cond) \
4259 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4260 uint64_t fdt1) \
4261 { \
4262 uint64_t c; \
4263 c = cond; \
4264 update_fcr31(env, GETPC()); \
4265 if (c) { \
4266 return -1; \
4267 } else { \
4268 return 0; \
4269 } \
4270 }
4271
4272 /* NOTE: the comma operator will make "cond" to eval to false,
4273 * but float64_unordered_quiet() is still called. */
4274 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4275 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
4276 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4277 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4278 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4279 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4280 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4281 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4282 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4283 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4284 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4285 /* NOTE: the comma operator will make "cond" to eval to false,
4286 * but float64_unordered() is still called. */
4287 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4288 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4289 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4290 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4291 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4292 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4293 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4294 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4295 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4296 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4297 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4298 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4299 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4300 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4301 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4302 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4303 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4304 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4305 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4306 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4307 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4308 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4309 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4310 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4311 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4312
4313 #define FOP_CONDN_S(op, cond) \
4314 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4315 uint32_t fst1) \
4316 { \
4317 uint64_t c; \
4318 c = cond; \
4319 update_fcr31(env, GETPC()); \
4320 if (c) { \
4321 return -1; \
4322 } else { \
4323 return 0; \
4324 } \
4325 }
4326
4327 /* NOTE: the comma operator will make "cond" to eval to false,
4328 * but float32_unordered_quiet() is still called. */
4329 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4330 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4331 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4332 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4333 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4334 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4335 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4336 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4337 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4338 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4339 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4340 /* NOTE: the comma operator will make "cond" to eval to false,
4341 * but float32_unordered() is still called. */
4342 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4343 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4344 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4345 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4346 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4347 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4348 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4349 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4350 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4351 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4352 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4353 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4354 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4355 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4356 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4357 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4358 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4359 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4360 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4361 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4362 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4363 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4364 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4365 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4366 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4367
4368 /* MSA */
4369 /* Data format min and max values */
4370 #define DF_BITS(df) (1 << ((df) + 3))
4371
4372 /* Element-by-element access macros */
4373 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4374
4375 #if !defined(CONFIG_USER_ONLY)
4376 #define MEMOP_IDX(DF) \
4377 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4378 cpu_mmu_index(env, false));
4379 #else
4380 #define MEMOP_IDX(DF)
4381 #endif
4382
4383 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4384 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4385 target_ulong addr) \
4386 { \
4387 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4388 wr_t wx; \
4389 int i; \
4390 MEMOP_IDX(DF) \
4391 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4392 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4393 } \
4394 memcpy(pwd, &wx, sizeof(wr_t)); \
4395 }
4396
4397 #if !defined(CONFIG_USER_ONLY)
4398 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC())
4399 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC())
4400 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC())
4401 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC())
4402 #else
4403 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
4404 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
4405 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
4406 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
4407 #endif
4408
4409 #define MSA_PAGESPAN(x) \
4410 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4411
4412 static inline void ensure_writable_pages(CPUMIPSState *env,
4413 target_ulong addr,
4414 int mmu_idx,
4415 uintptr_t retaddr)
4416 {
4417 #if !defined(CONFIG_USER_ONLY)
4418 target_ulong page_addr;
4419 if (unlikely(MSA_PAGESPAN(addr))) {
4420 /* first page */
4421 probe_write(env, addr, 0, mmu_idx, retaddr);
4422 /* second page */
4423 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4424 probe_write(env, page_addr, 0, mmu_idx, retaddr);
4425 }
4426 #endif
4427 }
4428
4429 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4430 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4431 target_ulong addr) \
4432 { \
4433 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4434 int mmu_idx = cpu_mmu_index(env, false); \
4435 int i; \
4436 MEMOP_IDX(DF) \
4437 ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
4438 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4439 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4440 } \
4441 }
4442
4443 #if !defined(CONFIG_USER_ONLY)
4444 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC())
4445 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC())
4446 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC())
4447 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC())
4448 #else
4449 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
4450 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
4451 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
4452 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
4453 #endif
4454
4455 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4456 {
4457 #ifndef CONFIG_USER_ONLY
4458 target_ulong index = addr & 0x1fffffff;
4459 if (op == 9) {
4460 /* Index Store Tag */
4461 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4462 8, MEMTXATTRS_UNSPECIFIED);
4463 } else if (op == 5) {
4464 /* Index Load Tag */
4465 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4466 8, MEMTXATTRS_UNSPECIFIED);
4467 }
4468 #endif
4469 }
AR7 emulation for QEMU