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ar7: Update board code for latest QEMU API
[qemu/ar7.git] / target / mips / helper.c
blob990d7fc3fe54e6b01ed7515b3cad764fa49913ab
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26 #include "hw/mips/cpudevs.h"
27 #include "qapi/qapi-commands-target.h"
28
29 enum {
30 TLBRET_XI = -6,
31 TLBRET_RI = -5,
32 TLBRET_DIRTY = -4,
33 TLBRET_INVALID = -3,
34 TLBRET_NOMATCH = -2,
35 TLBRET_BADADDR = -1,
36 TLBRET_MATCH = 0
37 };
38
39 #if !defined(CONFIG_USER_ONLY)
40
41 /* no MMU emulation */
42 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
43 target_ulong address, int rw, int access_type)
44 {
45 *physical = address;
46 *prot = PAGE_READ;
47 if (rw) {
48 *prot |= PAGE_WRITE;
49 }
50 return TLBRET_MATCH;
51 }
52
53 /* fixed mapping MMU emulation */
54 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
55 target_ulong address, int rw, int access_type)
56 {
57 if (address <= (int32_t)0x7FFFFFFFUL) {
58 if (!(env->CP0_Status & (1 << CP0St_ERL)))
59 *physical = address + 0x40000000UL;
60 else
61 *physical = address;
62 } else if (address <= (int32_t)0xBFFFFFFFUL)
63 *physical = address & 0x1FFFFFFF;
64 else
65 *physical = address;
66
67 *prot = PAGE_READ;
68 if (rw) {
69 *prot |= PAGE_WRITE;
70 }
71 return TLBRET_MATCH;
72 }
73
74 /* MIPS32/MIPS64 R4000-style MMU emulation */
75 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
76 target_ulong address, int rw, int access_type)
77 {
78 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
79 int i;
80
81 for (i = 0; i < env->tlb->tlb_in_use; i++) {
82 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
83 /* 1k pages are not supported. */
84 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
85 target_ulong tag = address & ~mask;
86 target_ulong VPN = tlb->VPN & ~mask;
87 #if defined(TARGET_MIPS64)
88 tag &= env->SEGMask;
89 #endif
90
91 /* Check ASID, virtual page number & size */
92 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
93 /* TLB match */
94 int n = !!(address & mask & ~(mask >> 1));
95 /* Check access rights */
96 if (!(n ? tlb->V1 : tlb->V0)) {
97 return TLBRET_INVALID;
98 }
99 if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
100 return TLBRET_XI;
101 }
102 if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
103 return TLBRET_RI;
104 }
105 if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
106 *physical = tlb->PFN[n] | (address & (mask >> 1));
107 *prot = PAGE_READ;
108 if (n ? tlb->D1 : tlb->D0)
109 *prot |= PAGE_WRITE;
110 return TLBRET_MATCH;
111 }
112 return TLBRET_DIRTY;
113 }
114 }
115 return TLBRET_NOMATCH;
116 }
117
118 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
119 {
120 /*
121 * Interpret access control mode and mmu_idx.
122 * AdE? TLB?
123 * AM K S U E K S U E
124 * UK 0 0 1 1 0 0 - - 0
125 * MK 1 0 1 1 0 1 - - !eu
126 * MSK 2 0 0 1 0 1 1 - !eu
127 * MUSK 3 0 0 0 0 1 1 1 !eu
128 * MUSUK 4 0 0 0 0 0 1 1 0
129 * USK 5 0 0 1 0 0 0 - 0
130 * - 6 - - - - - - - -
131 * UUSK 7 0 0 0 0 0 0 0 0
132 */
133 int32_t adetlb_mask;
134
135 switch (mmu_idx) {
136 case 3 /* ERL */:
137 /* If EU is set, always unmapped */
138 if (eu) {
139 return 0;
140 }
141 /* fall through */
142 case MIPS_HFLAG_KM:
143 /* Never AdE, TLB mapped if AM={1,2,3} */
144 adetlb_mask = 0x70000000;
145 goto check_tlb;
146
147 case MIPS_HFLAG_SM:
148 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
149 adetlb_mask = 0xc0380000;
150 goto check_ade;
151
152 case MIPS_HFLAG_UM:
153 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
154 adetlb_mask = 0xe4180000;
155 /* fall through */
156 check_ade:
157 /* does this AM cause AdE in current execution mode */
158 if ((adetlb_mask << am) < 0) {
159 return TLBRET_BADADDR;
160 }
161 adetlb_mask <<= 8;
162 /* fall through */
163 check_tlb:
164 /* is this AM mapped in current execution mode */
165 return ((adetlb_mask << am) < 0);
166 default:
167 assert(0);
168 return TLBRET_BADADDR;
169 };
170 }
171
172 static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
173 int *prot, target_ulong real_address,
174 int rw, int access_type, int mmu_idx,
175 unsigned int am, bool eu,
176 target_ulong segmask,
177 hwaddr physical_base)
178 {
179 int mapped = is_seg_am_mapped(am, eu, mmu_idx);
180
181 if (mapped < 0) {
182 /* is_seg_am_mapped can report TLBRET_BADADDR */
183 return mapped;
184 } else if (mapped) {
185 /* The segment is TLB mapped */
186 return env->tlb->map_address(env, physical, prot, real_address, rw,
187 access_type);
188 } else {
189 /* The segment is unmapped */
190 *physical = physical_base | (real_address & segmask);
191 *prot = PAGE_READ | PAGE_WRITE;
192 return TLBRET_MATCH;
193 }
194 }
195
196 static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
197 int *prot, target_ulong real_address,
198 int rw, int access_type, int mmu_idx,
199 uint16_t segctl, target_ulong segmask)
200 {
201 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
202 bool eu = (segctl >> CP0SC_EU) & 1;
203 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
204
205 return get_seg_physical_address(env, physical, prot, real_address, rw,
206 access_type, mmu_idx, am, eu, segmask,
207 pa & ~(hwaddr)segmask);
208 }
209
210 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
211 int *prot, target_ulong real_address,
212 int rw, int access_type, int mmu_idx)
213 {
214 /* User mode can only access useg/xuseg */
215 #if defined(TARGET_MIPS64)
216 int user_mode = mmu_idx == MIPS_HFLAG_UM;
217 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
218 int kernel_mode = !user_mode && !supervisor_mode;
219 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
220 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
221 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
222 #endif
223 int ret = TLBRET_MATCH;
224 /* effective address (modified for KVM T&E kernel segments) */
225 target_ulong address = real_address;
226
227 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
228 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
229 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
230 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
231 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
232
233 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
234 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
235
236 if (mips_um_ksegs_enabled()) {
237 /* KVM T&E adds guest kernel segments in useg */
238 if (real_address >= KVM_KSEG0_BASE) {
239 if (real_address < KVM_KSEG2_BASE) {
240 /* kseg0 */
241 address += KSEG0_BASE - KVM_KSEG0_BASE;
242 } else if (real_address <= USEG_LIMIT) {
243 /* kseg2/3 */
244 address += KSEG2_BASE - KVM_KSEG2_BASE;
245 }
246 }
247 }
248
249 if (address <= USEG_LIMIT) {
250 /* useg */
251 uint16_t segctl;
252
253 if (address >= 0x40000000UL) {
254 segctl = env->CP0_SegCtl2;
255 } else {
256 segctl = env->CP0_SegCtl2 >> 16;
257 }
258 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
259 access_type, mmu_idx, segctl,
260 0x3FFFFFFF);
261 #if defined(TARGET_MIPS64)
262 } else if (address < 0x4000000000000000ULL) {
263 /* xuseg */
264 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
265 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
266 } else {
267 ret = TLBRET_BADADDR;
268 }
269 } else if (address < 0x8000000000000000ULL) {
270 /* xsseg */
271 if ((supervisor_mode || kernel_mode) &&
272 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
273 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
274 } else {
275 ret = TLBRET_BADADDR;
276 }
277 } else if (address < 0xC000000000000000ULL) {
278 /* xkphys */
279 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
280 /* KX/SX/UX bit to check for each xkphys EVA access mode */
281 static const uint8_t am_ksux[8] = {
282 [CP0SC_AM_UK] = (1u << CP0St_KX),
283 [CP0SC_AM_MK] = (1u << CP0St_KX),
284 [CP0SC_AM_MSK] = (1u << CP0St_SX),
285 [CP0SC_AM_MUSK] = (1u << CP0St_UX),
286 [CP0SC_AM_MUSUK] = (1u << CP0St_UX),
287 [CP0SC_AM_USK] = (1u << CP0St_SX),
288 [6] = (1u << CP0St_KX),
289 [CP0SC_AM_UUSK] = (1u << CP0St_UX),
290 };
291 unsigned int am = CP0SC_AM_UK;
292 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
293
294 if (xr & (1 << ((address >> 59) & 0x7))) {
295 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
296 }
297 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
298 if (env->CP0_Status & am_ksux[am]) {
299 ret = get_seg_physical_address(env, physical, prot,
300 real_address, rw, access_type,
301 mmu_idx, am, false, env->PAMask,
302 0);
303 } else {
304 ret = TLBRET_BADADDR;
305 }
306 } else {
307 ret = TLBRET_BADADDR;
308 }
309 } else if (address < 0xFFFFFFFF80000000ULL) {
310 /* xkseg */
311 if (kernel_mode && KX &&
312 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
313 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
314 } else {
315 ret = TLBRET_BADADDR;
316 }
317 #endif
318 } else if (address < KSEG1_BASE) {
319 /* kseg0 */
320 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
321 access_type, mmu_idx,
322 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
323 } else if (address < KSEG2_BASE) {
324 /* kseg1 */
325 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
326 access_type, mmu_idx,
327 env->CP0_SegCtl1, 0x1FFFFFFF);
328 } else if (address < KSEG3_BASE) {
329 /* sseg (kseg2) */
330 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
331 access_type, mmu_idx,
332 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
333 } else {
334 /* kseg3 */
335 /* XXX: debug segment is not emulated */
336 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
337 access_type, mmu_idx,
338 env->CP0_SegCtl0, 0x1FFFFFFF);
339 }
340 return ret;
341 }
342
343 void cpu_mips_tlb_flush(CPUMIPSState *env)
344 {
345 MIPSCPU *cpu = mips_env_get_cpu(env);
346
347 /* Flush qemu's TLB and discard all shadowed entries. */
348 tlb_flush(CPU(cpu));
349 env->tlb->tlb_in_use = env->tlb->nb_tlb;
350 }
351
352 /* Called for updates to CP0_Status. */
353 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
354 {
355 int32_t tcstatus, *tcst;
356 uint32_t v = cpu->CP0_Status;
357 uint32_t cu, mx, asid, ksu;
358 uint32_t mask = ((1 << CP0TCSt_TCU3)
359 | (1 << CP0TCSt_TCU2)
360 | (1 << CP0TCSt_TCU1)
361 | (1 << CP0TCSt_TCU0)
362 | (1 << CP0TCSt_TMX)
363 | (3 << CP0TCSt_TKSU)
364 | (0xff << CP0TCSt_TASID));
365
366 cu = (v >> CP0St_CU0) & 0xf;
367 mx = (v >> CP0St_MX) & 0x1;
368 ksu = (v >> CP0St_KSU) & 0x3;
369 asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
370
371 tcstatus = cu << CP0TCSt_TCU0;
372 tcstatus |= mx << CP0TCSt_TMX;
373 tcstatus |= ksu << CP0TCSt_TKSU;
374 tcstatus |= asid;
375
376 if (tc == cpu->current_tc) {
377 tcst = &cpu->active_tc.CP0_TCStatus;
378 } else {
379 tcst = &cpu->tcs[tc].CP0_TCStatus;
380 }
381
382 *tcst &= ~mask;
383 *tcst |= tcstatus;
384 compute_hflags(cpu);
385 }
386
387 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
388 {
389 uint32_t mask = env->CP0_Status_rw_bitmask;
390 target_ulong old = env->CP0_Status;
391
392 if (env->insn_flags & ISA_MIPS32R6) {
393 bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
394 #if defined(TARGET_MIPS64)
395 uint32_t ksux = (1 << CP0St_KX) & val;
396 ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
397 ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
398 val = (val & ~(7 << CP0St_UX)) | ksux;
399 #endif
400 if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
401 mask &= ~(3 << CP0St_KSU);
402 }
403 mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
404 }
405
406 env->CP0_Status = (old & ~mask) | (val & mask);
407 #if defined(TARGET_MIPS64)
408 if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
409 /* Access to at least one of the 64-bit segments has been disabled */
410 tlb_flush(CPU(mips_env_get_cpu(env)));
411 }
412 #endif
413 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
414 sync_c0_status(env, env, env->current_tc);
415 } else {
416 compute_hflags(env);
417 }
418 }
419
420 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
421 {
422 uint32_t mask = 0x00C00300;
423 uint32_t old = env->CP0_Cause;
424 int i;
425
426 if (env->insn_flags & ISA_MIPS32R2) {
427 mask |= 1 << CP0Ca_DC;
428 }
429 if (env->insn_flags & ISA_MIPS32R6) {
430 mask &= ~((1 << CP0Ca_WP) & val);
431 }
432
433 env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
434
435 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
436 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
437 cpu_mips_stop_count(env);
438 } else {
439 cpu_mips_start_count(env);
440 }
441 }
442
443 /* Set/reset software interrupts */
444 for (i = 0 ; i < 2 ; i++) {
445 if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
446 cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
447 }
448 }
449 }
450 #endif
451
452 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
453 int rw, int tlb_error)
454 {
455 CPUState *cs = CPU(mips_env_get_cpu(env));
456 int exception = 0, error_code = 0;
457
458 if (rw == MMU_INST_FETCH) {
459 error_code |= EXCP_INST_NOTAVAIL;
460 }
461
462 switch (tlb_error) {
463 default:
464 case TLBRET_BADADDR:
465 /* Reference to kernel address from user mode or supervisor mode */
466 /* Reference to supervisor address from user mode */
467 if (rw == MMU_DATA_STORE) {
468 exception = EXCP_AdES;
469 } else {
470 exception = EXCP_AdEL;
471 }
472 break;
473 case TLBRET_NOMATCH:
474 /* No TLB match for a mapped address */
475 if (rw == MMU_DATA_STORE) {
476 exception = EXCP_TLBS;
477 } else {
478 exception = EXCP_TLBL;
479 }
480 error_code |= EXCP_TLB_NOMATCH;
481 break;
482 case TLBRET_INVALID:
483 /* TLB match with no valid bit */
484 if (rw == MMU_DATA_STORE) {
485 exception = EXCP_TLBS;
486 } else {
487 exception = EXCP_TLBL;
488 }
489 break;
490 case TLBRET_DIRTY:
491 /* TLB match but 'D' bit is cleared */
492 exception = EXCP_LTLBL;
493 break;
494 case TLBRET_XI:
495 /* Execute-Inhibit Exception */
496 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
497 exception = EXCP_TLBXI;
498 } else {
499 exception = EXCP_TLBL;
500 }
501 break;
502 case TLBRET_RI:
503 /* Read-Inhibit Exception */
504 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
505 exception = EXCP_TLBRI;
506 } else {
507 exception = EXCP_TLBL;
508 }
509 break;
510 }
511 /* Raise exception */
512 if (!(env->hflags & MIPS_HFLAG_DM)) {
513 env->CP0_BadVAddr = address;
514 }
515 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
516 ((address >> 9) & 0x007ffff0);
517 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
518 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
519 (address & (TARGET_PAGE_MASK << 1));
520 #if defined(TARGET_MIPS64)
521 env->CP0_EntryHi &= env->SEGMask;
522 env->CP0_XContext =
523 /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
524 /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
525 /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
526 #endif
527 cs->exception_index = exception;
528 env->error_code = error_code;
529 }
530
531 #if !defined(CONFIG_USER_ONLY)
532 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
533 {
534 MIPSCPU *cpu = MIPS_CPU(cs);
535 CPUMIPSState *env = &cpu->env;
536 hwaddr phys_addr;
537 int prot;
538
539 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT,
540 cpu_mmu_index(env, false)) != 0) {
541 return -1;
542 }
543 return phys_addr;
544 }
545 #endif
546
547 #if !defined(CONFIG_USER_ONLY)
548 #if !defined(TARGET_MIPS64)
549
550 /*
551 * Perform hardware page table walk
552 *
553 * Memory accesses are performed using the KERNEL privilege level.
554 * Synchronous exceptions detected on memory accesses cause a silent exit
555 * from page table walking, resulting in a TLB or XTLB Refill exception.
556 *
557 * Implementations are not required to support page table walk memory
558 * accesses from mapped memory regions. When an unsupported access is
559 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
560 * exception.
561 *
562 * Note that if an exception is caused by AddressTranslation or LoadMemory
563 * functions, the exception is not taken, a silent exit is taken,
564 * resulting in a TLB or XTLB Refill exception.
565 */
566
567 static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,
568 uint64_t *pte)
569 {
570 if ((vaddr & ((entry_size >> 3) - 1)) != 0) {
571 return false;
572 }
573 if (entry_size == 64) {
574 *pte = cpu_ldq_code(env, vaddr);
575 } else {
576 *pte = cpu_ldl_code(env, vaddr);
577 }
578 return true;
579 }
580
581 static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
582 int entry_size, int ptei)
583 {
584 uint64_t result = entry;
585 uint64_t rixi;
586 if (ptei > entry_size) {
587 ptei -= 32;
588 }
589 result >>= (ptei - 2);
590 rixi = result & 3;
591 result >>= 2;
592 result |= rixi << CP0EnLo_XI;
593 return result;
594 }
595
596 static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
597 int directory_index, bool *huge_page, bool *hgpg_directory_hit,
598 uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
599 {
600 int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
601 int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
602 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
603 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
604 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
605 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
606 int directory_shift = (ptew > 1) ? -1 :
607 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
608 int leaf_shift = (ptew > 1) ? -1 :
609 (ptew == 1) ? native_shift + 1 : native_shift;
610 uint32_t direntry_size = 1 << (directory_shift + 3);
611 uint32_t leafentry_size = 1 << (leaf_shift + 3);
612 uint64_t entry;
613 uint64_t paddr;
614 int prot;
615 uint64_t lsb = 0;
616 uint64_t w = 0;
617
618 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
619 ACCESS_INT, cpu_mmu_index(env, false)) !=
620 TLBRET_MATCH) {
621 /* wrong base address */
622 return 0;
623 }
624 if (!get_pte(env, *vaddr, direntry_size, &entry)) {
625 return 0;
626 }
627
628 if ((entry & (1 << psn)) && hugepg) {
629 *huge_page = true;
630 *hgpg_directory_hit = true;
631 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
632 w = directory_index - 1;
633 if (directory_index & 0x1) {
634 /* Generate adjacent page from same PTE for odd TLB page */
635 lsb = (1 << w) >> 6;
636 *pw_entrylo0 = entry & ~lsb; /* even page */
637 *pw_entrylo1 = entry | lsb; /* odd page */
638 } else if (dph) {
639 int oddpagebit = 1 << leaf_shift;
640 uint64_t vaddr2 = *vaddr ^ oddpagebit;
641 if (*vaddr & oddpagebit) {
642 *pw_entrylo1 = entry;
643 } else {
644 *pw_entrylo0 = entry;
645 }
646 if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD,
647 ACCESS_INT, cpu_mmu_index(env, false)) !=
648 TLBRET_MATCH) {
649 return 0;
650 }
651 if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
652 return 0;
653 }
654 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
655 if (*vaddr & oddpagebit) {
656 *pw_entrylo0 = entry;
657 } else {
658 *pw_entrylo1 = entry;
659 }
660 } else {
661 return 0;
662 }
663 return 1;
664 } else {
665 *vaddr = entry;
666 return 2;
667 }
668 }
669
670 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw,
671 int mmu_idx)
672 {
673 int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
674 int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
675 int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F;
676 int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F;
677 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
678
679 /* Initial values */
680 bool huge_page = false;
681 bool hgpg_bdhit = false;
682 bool hgpg_gdhit = false;
683 bool hgpg_udhit = false;
684 bool hgpg_mdhit = false;
685
686 int32_t pw_pagemask = 0;
687 target_ulong pw_entryhi = 0;
688 uint64_t pw_entrylo0 = 0;
689 uint64_t pw_entrylo1 = 0;
690
691 /* Native pointer size */
692 /*For the 32-bit architectures, this bit is fixed to 0.*/
693 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
694
695 /* Indices from PWField */
696 int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F;
697 int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F;
698 int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F;
699 int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F;
700 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
701
702 /* Indices computed from faulting address */
703 int gindex = (address >> pf_gdw) & ((1 << gdw) - 1);
704 int uindex = (address >> pf_udw) & ((1 << udw) - 1);
705 int mindex = (address >> pf_mdw) & ((1 << mdw) - 1);
706 int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1);
707
708 /* Other HTW configs */
709 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
710
711 /* HTW Shift values (depend on entry size) */
712 int directory_shift = (ptew > 1) ? -1 :
713 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
714 int leaf_shift = (ptew > 1) ? -1 :
715 (ptew == 1) ? native_shift + 1 : native_shift;
716
717 /* Offsets into tables */
718 int goffset = gindex << directory_shift;
719 int uoffset = uindex << directory_shift;
720 int moffset = mindex << directory_shift;
721 int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
722 int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
723
724 uint32_t leafentry_size = 1 << (leaf_shift + 3);
725
726 /* Starting address - Page Table Base */
727 uint64_t vaddr = env->CP0_PWBase;
728
729 uint64_t dir_entry;
730 uint64_t paddr;
731 int prot;
732 int m;
733
734 if (!(env->CP0_Config3 & (1 << CP0C3_PW))) {
735 /* walker is unimplemented */
736 return false;
737 }
738 if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) {
739 /* walker is disabled */
740 return false;
741 }
742 if (!(gdw > 0 || udw > 0 || mdw > 0)) {
743 /* no structure to walk */
744 return false;
745 }
746 if ((directory_shift == -1) || (leaf_shift == -1)) {
747 return false;
748 }
749
750 /* Global Directory */
751 if (gdw > 0) {
752 vaddr |= goffset;
753 switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
754 &pw_entrylo0, &pw_entrylo1))
755 {
756 case 0:
757 return false;
758 case 1:
759 goto refill;
760 case 2:
761 default:
762 break;
763 }
764 }
765
766 /* Upper directory */
767 if (udw > 0) {
768 vaddr |= uoffset;
769 switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
770 &pw_entrylo0, &pw_entrylo1))
771 {
772 case 0:
773 return false;
774 case 1:
775 goto refill;
776 case 2:
777 default:
778 break;
779 }
780 }
781
782 /* Middle directory */
783 if (mdw > 0) {
784 vaddr |= moffset;
785 switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
786 &pw_entrylo0, &pw_entrylo1))
787 {
788 case 0:
789 return false;
790 case 1:
791 goto refill;
792 case 2:
793 default:
794 break;
795 }
796 }
797
798 /* Leaf Level Page Table - First half of PTE pair */
799 vaddr |= ptoffset0;
800 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
801 ACCESS_INT, cpu_mmu_index(env, false)) !=
802 TLBRET_MATCH) {
803 return false;
804 }
805 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
806 return false;
807 }
808 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
809 pw_entrylo0 = dir_entry;
810
811 /* Leaf Level Page Table - Second half of PTE pair */
812 vaddr |= ptoffset1;
813 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
814 ACCESS_INT, cpu_mmu_index(env, false)) !=
815 TLBRET_MATCH) {
816 return false;
817 }
818 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
819 return false;
820 }
821 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
822 pw_entrylo1 = dir_entry;
823
824 refill:
825
826 m = (1 << pf_ptw) - 1;
827
828 if (huge_page) {
829 switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 |
830 hgpg_mdhit)
831 {
832 case 4:
833 m = (1 << pf_gdw) - 1;
834 if (pf_gdw & 1) {
835 m >>= 1;
836 }
837 break;
838 case 2:
839 m = (1 << pf_udw) - 1;
840 if (pf_udw & 1) {
841 m >>= 1;
842 }
843 break;
844 case 1:
845 m = (1 << pf_mdw) - 1;
846 if (pf_mdw & 1) {
847 m >>= 1;
848 }
849 break;
850 }
851 }
852 pw_pagemask = m >> 12;
853 update_pagemask(env, pw_pagemask << 13, &pw_pagemask);
854 pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
855 {
856 target_ulong tmp_entryhi = env->CP0_EntryHi;
857 int32_t tmp_pagemask = env->CP0_PageMask;
858 uint64_t tmp_entrylo0 = env->CP0_EntryLo0;
859 uint64_t tmp_entrylo1 = env->CP0_EntryLo1;
860
861 env->CP0_EntryHi = pw_entryhi;
862 env->CP0_PageMask = pw_pagemask;
863 env->CP0_EntryLo0 = pw_entrylo0;
864 env->CP0_EntryLo1 = pw_entrylo1;
865
866 /*
867 * The hardware page walker inserts a page into the TLB in a manner
868 * identical to a TLBWR instruction as executed by the software refill
869 * handler.
870 */
871 r4k_helper_tlbwr(env);
872
873 env->CP0_EntryHi = tmp_entryhi;
874 env->CP0_PageMask = tmp_pagemask;
875 env->CP0_EntryLo0 = tmp_entrylo0;
876 env->CP0_EntryLo1 = tmp_entrylo1;
877 }
878 return true;
879 }
880 #endif
881 #endif
882
883 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
884 int mmu_idx)
885 {
886 MIPSCPU *cpu = MIPS_CPU(cs);
887 CPUMIPSState *env = &cpu->env;
888 #if !defined(CONFIG_USER_ONLY)
889 hwaddr physical;
890 int prot;
891 int access_type;
892 #endif
893 int ret = 0;
894
895 #if 0
896 log_cpu_state(cs, 0);
897 #endif
898 qemu_log_mask(CPU_LOG_MMU,
899 "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
900 __func__, env->active_tc.PC, address, rw, mmu_idx);
901
902 /* data access */
903 #if !defined(CONFIG_USER_ONLY)
904 /* XXX: put correct access by using cpu_restore_state() correctly */
905 access_type = ACCESS_INT;
906 ret = get_physical_address(env, &physical, &prot,
907 address, rw, access_type, mmu_idx);
908 switch (ret) {
909 case TLBRET_MATCH:
910 qemu_log_mask(CPU_LOG_MMU,
911 "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
912 " prot %d\n", __func__, address, physical, prot);
913 break;
914 default:
915 qemu_log_mask(CPU_LOG_MMU,
916 "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
917 ret);
918 break;
919 }
920 if (ret == TLBRET_MATCH) {
921 tlb_set_page(cs, address & TARGET_PAGE_MASK,
922 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
923 mmu_idx, TARGET_PAGE_SIZE);
924 ret = 0;
925 } else if (ret < 0)
926 #endif
927 {
928 #if !defined(CONFIG_USER_ONLY)
929 #if !defined(TARGET_MIPS64)
930 if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
931 /*
932 * Memory reads during hardware page table walking are performed
933 * as if they were kernel-mode load instructions.
934 */
935 int mode = (env->hflags & MIPS_HFLAG_KSU);
936 bool ret_walker;
937 env->hflags &= ~MIPS_HFLAG_KSU;
938 ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
939 env->hflags |= mode;
940 if (ret_walker) {
941 ret = get_physical_address(env, &physical, &prot,
942 address, rw, access_type, mmu_idx);
943 if (ret == TLBRET_MATCH) {
944 tlb_set_page(cs, address & TARGET_PAGE_MASK,
945 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
946 mmu_idx, TARGET_PAGE_SIZE);
947 ret = 0;
948 return ret;
949 }
950 }
951 }
952 #endif
953 #endif
954 raise_mmu_exception(env, address, rw, ret);
955 ret = 1;
956 }
957
958 return ret;
959 }
960
961 #if !defined(CONFIG_USER_ONLY)
962 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
963 {
964 hwaddr physical;
965 int prot;
966 int access_type;
967 int ret = 0;
968
969 /* data access */
970 access_type = ACCESS_INT;
971 ret = get_physical_address(env, &physical, &prot, address, rw, access_type,
972 cpu_mmu_index(env, false));
973 if (ret != TLBRET_MATCH) {
974 raise_mmu_exception(env, address, rw, ret);
975 return -1LL;
976 } else {
977 return physical;
978 }
979 }
980
981 static const char * const excp_names[EXCP_LAST + 1] = {
982 [EXCP_RESET] = "reset",
983 [EXCP_SRESET] = "soft reset",
984 [EXCP_DSS] = "debug single step",
985 [EXCP_DINT] = "debug interrupt",
986 [EXCP_NMI] = "non-maskable interrupt",
987 [EXCP_MCHECK] = "machine check",
988 [EXCP_EXT_INTERRUPT] = "interrupt",
989 [EXCP_DFWATCH] = "deferred watchpoint",
990 [EXCP_DIB] = "debug instruction breakpoint",
991 [EXCP_IWATCH] = "instruction fetch watchpoint",
992 [EXCP_AdEL] = "address error load",
993 [EXCP_AdES] = "address error store",
994 [EXCP_TLBF] = "TLB refill",
995 [EXCP_IBE] = "instruction bus error",
996 [EXCP_DBp] = "debug breakpoint",
997 [EXCP_SYSCALL] = "syscall",
998 [EXCP_BREAK] = "break",
999 [EXCP_CpU] = "coprocessor unusable",
1000 [EXCP_RI] = "reserved instruction",
1001 [EXCP_OVERFLOW] = "arithmetic overflow",
1002 [EXCP_TRAP] = "trap",
1003 [EXCP_FPE] = "floating point",
1004 [EXCP_DDBS] = "debug data break store",
1005 [EXCP_DWATCH] = "data watchpoint",
1006 [EXCP_LTLBL] = "TLB modify",
1007 [EXCP_TLBL] = "TLB load",
1008 [EXCP_TLBS] = "TLB store",
1009 [EXCP_DBE] = "data bus error",
1010 [EXCP_DDBL] = "debug data break load",
1011 [EXCP_THREAD] = "thread",
1012 [EXCP_MDMX] = "MDMX",
1013 [EXCP_C2E] = "precise coprocessor 2",
1014 [EXCP_CACHE] = "cache error",
1015 [EXCP_TLBXI] = "TLB execute-inhibit",
1016 [EXCP_TLBRI] = "TLB read-inhibit",
1017 [EXCP_MSADIS] = "MSA disabled",
1018 [EXCP_MSAFPE] = "MSA floating point",
1019 };
1020 #endif
1021
1022 target_ulong exception_resume_pc (CPUMIPSState *env)
1023 {
1024 target_ulong bad_pc;
1025 target_ulong isa_mode;
1026
1027 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
1028 bad_pc = env->active_tc.PC | isa_mode;
1029 if (env->hflags & MIPS_HFLAG_BMASK) {
1030 /* If the exception was raised from a delay slot, come back to
1031 the jump. */
1032 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
1033 }
1034
1035 return bad_pc;
1036 }
1037
1038 #if !defined(CONFIG_USER_ONLY)
1039 static void set_hflags_for_handler (CPUMIPSState *env)
1040 {
1041 /* Exception handlers are entered in 32-bit mode. */
1042 env->hflags &= ~(MIPS_HFLAG_M16);
1043 /* ...except that microMIPS lets you choose. */
1044 if (env->insn_flags & ASE_MICROMIPS) {
1045 env->hflags |= (!!(env->CP0_Config3
1046 & (1 << CP0C3_ISA_ON_EXC))
1047 << MIPS_HFLAG_M16_SHIFT);
1048 }
1049 }
1050
1051 static inline void set_badinstr_registers(CPUMIPSState *env)
1052 {
1053 if (env->insn_flags & ISA_NANOMIPS32) {
1054 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
1055 uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
1056 if ((instr & 0x10000000) == 0) {
1057 instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
1058 }
1059 env->CP0_BadInstr = instr;
1060
1061 if ((instr & 0xFC000000) == 0x60000000) {
1062 instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
1063 env->CP0_BadInstrX = instr;
1064 }
1065 }
1066 return;
1067 }
1068
1069 if (env->hflags & MIPS_HFLAG_M16) {
1070 /* TODO: add BadInstr support for microMIPS */
1071 return;
1072 }
1073 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
1074 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
1075 }
1076 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
1077 (env->hflags & MIPS_HFLAG_BMASK)) {
1078 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
1079 }
1080 }
1081 #endif
1082
1083 void mips_cpu_do_interrupt(CPUState *cs)
1084 {
1085 #if !defined(CONFIG_USER_ONLY)
1086 MIPSCPU *cpu = MIPS_CPU(cs);
1087 CPUMIPSState *env = &cpu->env;
1088 bool update_badinstr = 0;
1089 target_ulong offset;
1090 int cause = -1;
1091 const char *name;
1092
1093 if (qemu_loglevel_mask(CPU_LOG_INT)
1094 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1095 if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
1096 name = "unknown";
1097 } else {
1098 name = excp_names[cs->exception_index];
1099 }
1100
1101 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
1102 " %s exception\n",
1103 __func__, env->active_tc.PC, env->CP0_EPC, name);
1104 }
1105 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
1106 (env->hflags & MIPS_HFLAG_DM)) {
1107 cs->exception_index = EXCP_DINT;
1108 }
1109 offset = 0x180;
1110 switch (cs->exception_index) {
1111 case EXCP_DSS:
1112 env->CP0_Debug |= 1 << CP0DB_DSS;
1113 /* Debug single step cannot be raised inside a delay slot and
1114 resume will always occur on the next instruction
1115 (but we assume the pc has always been updated during
1116 code translation). */
1117 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
1118 goto enter_debug_mode;
1119 case EXCP_DINT:
1120 env->CP0_Debug |= 1 << CP0DB_DINT;
1121 goto set_DEPC;
1122 case EXCP_DIB:
1123 env->CP0_Debug |= 1 << CP0DB_DIB;
1124 goto set_DEPC;
1125 case EXCP_DBp:
1126 env->CP0_Debug |= 1 << CP0DB_DBp;
1127 /* Setup DExcCode - SDBBP instruction */
1128 env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
1129 goto set_DEPC;
1130 case EXCP_DDBS:
1131 env->CP0_Debug |= 1 << CP0DB_DDBS;
1132 goto set_DEPC;
1133 case EXCP_DDBL:
1134 env->CP0_Debug |= 1 << CP0DB_DDBL;
1135 set_DEPC:
1136 env->CP0_DEPC = exception_resume_pc(env);
1137 env->hflags &= ~MIPS_HFLAG_BMASK;
1138 enter_debug_mode:
1139 if (env->insn_flags & ISA_MIPS3) {
1140 env->hflags |= MIPS_HFLAG_64;
1141 if (!(env->insn_flags & ISA_MIPS64R6) ||
1142 env->CP0_Status & (1 << CP0St_KX)) {
1143 env->hflags &= ~MIPS_HFLAG_AWRAP;
1144 }
1145 }
1146 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
1147 env->hflags &= ~(MIPS_HFLAG_KSU);
1148 /* EJTAG probe trap enable is not implemented... */
1149 if (!(env->CP0_Status & (1 << CP0St_EXL)))
1150 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1151 env->active_tc.PC = env->exception_base + 0x480;
1152 set_hflags_for_handler(env);
1153 break;
1154 case EXCP_RESET:
1155 cpu_reset(CPU(cpu));
1156 break;
1157 case EXCP_SRESET:
1158 env->CP0_Status |= (1 << CP0St_SR);
1159 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
1160 goto set_error_EPC;
1161 case EXCP_NMI:
1162 env->CP0_Status |= (1 << CP0St_NMI);
1163 set_error_EPC:
1164 env->CP0_ErrorEPC = exception_resume_pc(env);
1165 env->hflags &= ~MIPS_HFLAG_BMASK;
1166 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
1167 if (env->insn_flags & ISA_MIPS3) {
1168 env->hflags |= MIPS_HFLAG_64;
1169 if (!(env->insn_flags & ISA_MIPS64R6) ||
1170 env->CP0_Status & (1 << CP0St_KX)) {
1171 env->hflags &= ~MIPS_HFLAG_AWRAP;
1172 }
1173 }
1174 env->hflags |= MIPS_HFLAG_CP0;
1175 env->hflags &= ~(MIPS_HFLAG_KSU);
1176 if (!(env->CP0_Status & (1 << CP0St_EXL)))
1177 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1178 env->active_tc.PC = env->exception_base;
1179 set_hflags_for_handler(env);
1180 break;
1181 case EXCP_EXT_INTERRUPT:
1182 cause = 0;
1183 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
1184 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
1185
1186 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
1187 offset = 0x200;
1188 } else {
1189 uint32_t vector = 0;
1190 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
1191
1192 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
1193 /* For VEIC mode, the external interrupt controller feeds
1194 * the vector through the CP0Cause IP lines. */
1195 vector = pending;
1196 } else {
1197 /* Vectored Interrupts
1198 * Mask with Status.IM7-IM0 to get enabled interrupts. */
1199 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
1200 /* Find the highest-priority interrupt. */
1201 while (pending >>= 1) {
1202 vector++;
1203 }
1204 }
1205 offset = 0x200 + (vector * (spacing << 5));
1206 }
1207 }
1208 goto set_EPC;
1209 case EXCP_LTLBL:
1210 cause = 1;
1211 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1212 goto set_EPC;
1213 case EXCP_TLBL:
1214 cause = 2;
1215 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1216 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1217 !(env->CP0_Status & (1 << CP0St_EXL))) {
1218 #if defined(TARGET_MIPS64)
1219 int R = env->CP0_BadVAddr >> 62;
1220 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1221 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1222
1223 if ((R != 0 || UX) && (R != 3 || KX) &&
1224 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1225 offset = 0x080;
1226 } else {
1227 #endif
1228 offset = 0x000;
1229 #if defined(TARGET_MIPS64)
1230 }
1231 #endif
1232 }
1233 goto set_EPC;
1234 case EXCP_TLBS:
1235 cause = 3;
1236 update_badinstr = 1;
1237 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1238 !(env->CP0_Status & (1 << CP0St_EXL))) {
1239 #if defined(TARGET_MIPS64)
1240 int R = env->CP0_BadVAddr >> 62;
1241 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1242 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1243
1244 if ((R != 0 || UX) && (R != 3 || KX) &&
1245 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1246 offset = 0x080;
1247 } else {
1248 #endif
1249 offset = 0x000;
1250 #if defined(TARGET_MIPS64)
1251 }
1252 #endif
1253 }
1254 goto set_EPC;
1255 case EXCP_AdEL:
1256 cause = 4;
1257 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1258 goto set_EPC;
1259 case EXCP_AdES:
1260 cause = 5;
1261 update_badinstr = 1;
1262 goto set_EPC;
1263 case EXCP_IBE:
1264 cause = 6;
1265 goto set_EPC;
1266 case EXCP_DBE:
1267 cause = 7;
1268 goto set_EPC;
1269 case EXCP_SYSCALL:
1270 cause = 8;
1271 update_badinstr = 1;
1272 goto set_EPC;
1273 case EXCP_BREAK:
1274 cause = 9;
1275 update_badinstr = 1;
1276 goto set_EPC;
1277 case EXCP_RI:
1278 cause = 10;
1279 update_badinstr = 1;
1280 goto set_EPC;
1281 case EXCP_CpU:
1282 cause = 11;
1283 update_badinstr = 1;
1284 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
1285 (env->error_code << CP0Ca_CE);
1286 goto set_EPC;
1287 case EXCP_OVERFLOW:
1288 cause = 12;
1289 update_badinstr = 1;
1290 goto set_EPC;
1291 case EXCP_TRAP:
1292 cause = 13;
1293 update_badinstr = 1;
1294 goto set_EPC;
1295 case EXCP_MSAFPE:
1296 cause = 14;
1297 update_badinstr = 1;
1298 goto set_EPC;
1299 case EXCP_FPE:
1300 cause = 15;
1301 update_badinstr = 1;
1302 goto set_EPC;
1303 case EXCP_C2E:
1304 cause = 18;
1305 goto set_EPC;
1306 case EXCP_TLBRI:
1307 cause = 19;
1308 update_badinstr = 1;
1309 goto set_EPC;
1310 case EXCP_TLBXI:
1311 cause = 20;
1312 goto set_EPC;
1313 case EXCP_MSADIS:
1314 cause = 21;
1315 update_badinstr = 1;
1316 goto set_EPC;
1317 case EXCP_MDMX:
1318 cause = 22;
1319 goto set_EPC;
1320 case EXCP_DWATCH:
1321 cause = 23;
1322 /* XXX: TODO: manage deferred watch exceptions */
1323 goto set_EPC;
1324 case EXCP_MCHECK:
1325 cause = 24;
1326 goto set_EPC;
1327 case EXCP_THREAD:
1328 cause = 25;
1329 goto set_EPC;
1330 case EXCP_DSPDIS:
1331 cause = 26;
1332 goto set_EPC;
1333 case EXCP_CACHE:
1334 cause = 30;
1335 offset = 0x100;
1336 set_EPC:
1337 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1338 env->CP0_EPC = exception_resume_pc(env);
1339 if (update_badinstr) {
1340 set_badinstr_registers(env);
1341 }
1342 if (env->hflags & MIPS_HFLAG_BMASK) {
1343 env->CP0_Cause |= (1U << CP0Ca_BD);
1344 } else {
1345 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1346 }
1347 env->CP0_Status |= (1 << CP0St_EXL);
1348 if (env->insn_flags & ISA_MIPS3) {
1349 env->hflags |= MIPS_HFLAG_64;
1350 if (!(env->insn_flags & ISA_MIPS64R6) ||
1351 env->CP0_Status & (1 << CP0St_KX)) {
1352 env->hflags &= ~MIPS_HFLAG_AWRAP;
1353 }
1354 }
1355 env->hflags |= MIPS_HFLAG_CP0;
1356 env->hflags &= ~(MIPS_HFLAG_KSU);
1357 }
1358 env->hflags &= ~MIPS_HFLAG_BMASK;
1359 if (env->CP0_Status & (1 << CP0St_BEV)) {
1360 env->active_tc.PC = env->exception_base + 0x200;
1361 } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
1362 env->CP0_Config5 & (1 << CP0C5_CV))) {
1363 /* Force KSeg1 for cache errors */
1364 env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
1365 } else {
1366 env->active_tc.PC = env->CP0_EBase & ~0xfff;
1367 }
1368
1369 env->active_tc.PC += offset;
1370 set_hflags_for_handler(env);
1371 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
1372 break;
1373 default:
1374 abort();
1375 }
1376 if (qemu_loglevel_mask(CPU_LOG_INT)
1377 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1378 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
1379 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
1380 __func__, env->active_tc.PC, env->CP0_EPC, cause,
1381 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
1382 env->CP0_DEPC);
1383 }
1384 #endif
1385 cs->exception_index = EXCP_NONE;
1386 }
1387
1388 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
1389 {
1390 if (interrupt_request & CPU_INTERRUPT_HARD) {
1391 MIPSCPU *cpu = MIPS_CPU(cs);
1392 CPUMIPSState *env = &cpu->env;
1393
1394 if (cpu_mips_hw_interrupts_enabled(env) &&
1395 cpu_mips_hw_interrupts_pending(env)) {
1396 /* Raise it */
1397 cs->exception_index = EXCP_EXT_INTERRUPT;
1398 env->error_code = 0;
1399 mips_cpu_do_interrupt(cs);
1400 return true;
1401 }
1402 }
1403 return false;
1404 }
1405
1406 #if !defined(CONFIG_USER_ONLY)
1407 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
1408 {
1409 MIPSCPU *cpu = mips_env_get_cpu(env);
1410 CPUState *cs;
1411 r4k_tlb_t *tlb;
1412 target_ulong addr;
1413 target_ulong end;
1414 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1415 target_ulong mask;
1416
1417 tlb = &env->tlb->mmu.r4k.tlb[idx];
1418 /* The qemu TLB is flushed when the ASID changes, so no need to
1419 flush these entries again. */
1420 if (tlb->G == 0 && tlb->ASID != ASID) {
1421 return;
1422 }
1423
1424 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
1425 /* For tlbwr, we can shadow the discarded entry into
1426 a new (fake) TLB entry, as long as the guest can not
1427 tell that it's there. */
1428 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
1429 env->tlb->tlb_in_use++;
1430 return;
1431 }
1432
1433 /* 1k pages are not supported. */
1434 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1435 if (tlb->V0) {
1436 cs = CPU(cpu);
1437 addr = tlb->VPN & ~mask;
1438 #if defined(TARGET_MIPS64)
1439 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1440 addr |= 0x3FFFFF0000000000ULL;
1441 }
1442 #endif
1443 end = addr | (mask >> 1);
1444 while (addr < end) {
1445 // optimize memset in tlb_flush_page!!!
1446 tlb_flush_page(cs, addr);
1447 addr += TARGET_PAGE_SIZE;
1448 }
1449 }
1450 if (tlb->V1) {
1451 cs = CPU(cpu);
1452 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
1453 #if defined(TARGET_MIPS64)
1454 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1455 addr |= 0x3FFFFF0000000000ULL;
1456 }
1457 #endif
1458 end = addr | mask;
1459 while (addr - 1 < end) {
1460 // optimize memset in tlb_flush_page!!!
1461 tlb_flush_page(cs, addr);
1462 addr += TARGET_PAGE_SIZE;
1463 }
1464 }
1465 }
1466 #endif
1467
1468 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
1469 uint32_t exception,
1470 int error_code,
1471 uintptr_t pc)
1472 {
1473 CPUState *cs = CPU(mips_env_get_cpu(env));
1474
1475 qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
1476 __func__, exception, error_code);
1477 cs->exception_index = exception;
1478 env->error_code = error_code;
1479
1480 cpu_loop_exit_restore(cs, pc);
1481 }
1482
1483 static void mips_cpu_add_definition(gpointer data, gpointer user_data)
1484 {
1485 ObjectClass *oc = data;
1486 CpuDefinitionInfoList **cpu_list = user_data;
1487 CpuDefinitionInfoList *entry;
1488 CpuDefinitionInfo *info;
1489 const char *typename;
1490
1491 typename = object_class_get_name(oc);
1492 info = g_malloc0(sizeof(*info));
1493 info->name = g_strndup(typename,
1494 strlen(typename) - strlen("-" TYPE_MIPS_CPU));
1495 info->q_typename = g_strdup(typename);
1496
1497 entry = g_malloc0(sizeof(*entry));
1498 entry->value = info;
1499 entry->next = *cpu_list;
1500 *cpu_list = entry;
1501 }
1502
1503 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
1504 {
1505 CpuDefinitionInfoList *cpu_list = NULL;
1506 GSList *list;
1507
1508 list = object_class_get_list(TYPE_MIPS_CPU, false);
1509 g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
1510 g_slist_free(list);
1511
1512 return cpu_list;
1513 }
AR7 emulation for QEMU