2 * MIPS internal definitions and helpers
4 * This work is licensed under the terms of the GNU GPL, version 2 or later.
5 * See the COPYING file in the top-level directory.
8 #ifndef MIPS_INTERNAL_H
9 #define MIPS_INTERNAL_H
11 #include "exec/memattrs.h"
13 #include "tcg/tcg-internal.h"
18 * MMU types, the first four entries have the same layout as the
23 MMU_TYPE_R4000
= 1, /* Standard TLB */
24 MMU_TYPE_BAT
= 2, /* Block Address Translation */
25 MMU_TYPE_FMT
= 3, /* Fixed Mapping */
26 MMU_TYPE_DVF
= 4, /* Dual VTLB and FTLB */
40 int32_t CP0_Config4_rw_bitmask
;
42 int32_t CP0_Config5_rw_bitmask
;
44 int32_t CP0_Config6_rw_bitmask
;
46 int32_t CP0_Config7_rw_bitmask
;
47 target_ulong CP0_LLAddr_rw_bitmask
;
51 * @CCRes: rate at which the coprocessor 0 counter increments
53 * The Count register acts as a timer, incrementing at a constant rate,
54 * whether or not an instruction is executed, retired, or any forward
55 * progress is made through the pipeline. The rate at which the counter
56 * increments is implementation dependent, and is a function of the
57 * pipeline clock of the processor, not the issue width of the processor.
60 int32_t CP0_Status_rw_bitmask
;
61 int32_t CP0_TCStatus_rw_bitmask
;
64 int32_t CP1_fcr31_rw_bitmask
;
69 int32_t CP0_SRSConf0_rw_bitmask
;
71 int32_t CP0_SRSConf1_rw_bitmask
;
73 int32_t CP0_SRSConf2_rw_bitmask
;
75 int32_t CP0_SRSConf3_rw_bitmask
;
77 int32_t CP0_SRSConf4_rw_bitmask
;
79 int32_t CP0_PageGrain_rw_bitmask
;
80 int32_t CP0_PageGrain
;
81 target_ulong CP0_EBaseWG_rw_bitmask
;
82 uint32_t lcsr_cpucfg1
;
83 uint32_t lcsr_cpucfg2
;
85 enum mips_mmu_types mmu_type
;
88 extern const char regnames
[32][3];
89 extern const char fregnames
[32][4];
91 extern const struct mips_def_t mips_defs
[];
92 extern const int mips_defs_number
;
94 int mips_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
95 int mips_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
97 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
98 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
99 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
100 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
101 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
103 #if !defined(CONFIG_USER_ONLY)
115 int get_physical_address(CPUMIPSState
*env
, hwaddr
*physical
,
116 int *prot
, target_ulong real_address
,
117 MMUAccessType access_type
, int mmu_idx
);
118 hwaddr
mips_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
120 typedef struct r4k_tlb_t r4k_tlb_t
;
137 unsigned int EHINV
:1;
141 struct CPUMIPSTLBContext
{
144 int (*map_address
)(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
145 target_ulong address
, MMUAccessType access_type
);
146 void (*helper_tlbwi
)(CPUMIPSState
*env
);
147 void (*helper_tlbwr
)(CPUMIPSState
*env
);
148 void (*helper_tlbp
)(CPUMIPSState
*env
);
149 void (*helper_tlbr
)(CPUMIPSState
*env
);
150 void (*helper_tlbinv
)(CPUMIPSState
*env
);
151 void (*helper_tlbinvf
)(CPUMIPSState
*env
);
154 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
159 void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
);
160 void cpu_mips_store_status(CPUMIPSState
*env
, target_ulong val
);
161 void cpu_mips_store_cause(CPUMIPSState
*env
, target_ulong val
);
163 extern const VMStateDescription vmstate_mips_cpu
;
165 #endif /* !CONFIG_USER_ONLY */
167 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState
*env
)
169 return (env
->CP0_Status
& (1 << CP0St_IE
)) &&
170 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
171 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
172 !(env
->hflags
& MIPS_HFLAG_DM
) &&
174 * Note that the TCStatus IXMT field is initialized to zero,
175 * and only MT capable cores can set it to one. So we don't
176 * need to check for MT capabilities here.
178 !(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_IXMT
));
181 /* Check if there is pending and not masked out interrupt */
182 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState
*env
)
188 pending
= env
->CP0_Cause
& CP0Ca_IP_mask
;
189 status
= env
->CP0_Status
& CP0Ca_IP_mask
;
191 if (env
->CP0_Config3
& (1 << CP0C3_VEIC
)) {
193 * A MIPS configured with a vectorizing external interrupt controller
194 * will feed a vector into the Cause pending lines. The core treats
195 * the status lines as a vector level, not as individual masks.
197 r
= pending
> status
;
200 * A MIPS configured with compatibility or VInt (Vectored Interrupts)
201 * treats the pending lines as individual interrupt lines, the status
202 * lines are individual masks.
204 r
= (pending
& status
) != 0;
209 void msa_reset(CPUMIPSState
*env
);
212 uint32_t cpu_mips_get_count(CPUMIPSState
*env
);
213 void cpu_mips_store_count(CPUMIPSState
*env
, uint32_t value
);
214 void cpu_mips_store_compare(CPUMIPSState
*env
, uint32_t value
);
215 void cpu_mips_start_count(CPUMIPSState
*env
);
216 void cpu_mips_stop_count(CPUMIPSState
*env
);
218 static inline void mips_env_set_pc(CPUMIPSState
*env
, target_ulong value
)
220 env
->active_tc
.PC
= value
& ~(target_ulong
)1;
222 env
->hflags
|= MIPS_HFLAG_M16
;
224 env
->hflags
&= ~(MIPS_HFLAG_M16
);
228 static inline void restore_pamask(CPUMIPSState
*env
)
230 if (env
->hflags
& MIPS_HFLAG_ELPA
) {
231 env
->PAMask
= (1ULL << env
->PABITS
) - 1;
233 env
->PAMask
= PAMASK_BASE
;
237 static inline int mips_vpe_active(CPUMIPSState
*env
)
241 /* Check that the VPE is enabled. */
242 if (!(env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_EVP
))) {
245 /* Check that the VPE is activated. */
246 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))) {
251 * Now verify that there are active thread contexts in the VPE.
253 * This assumes the CPU model will internally reschedule threads
254 * if the active one goes to sleep. If there are no threads available
255 * the active one will be in a sleeping state, and we can turn off
258 if (!(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_A
))) {
259 /* TC is not activated. */
262 if (env
->active_tc
.CP0_TCHalt
& 1) {
263 /* TC is in halt state. */
270 static inline int mips_vp_active(CPUMIPSState
*env
)
272 CPUState
*other_cs
= first_cpu
;
274 /* Check if the VP disabled other VPs (which means the VP is enabled) */
275 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
279 /* Check if the virtual processor is disabled due to a DVP */
280 CPU_FOREACH(other_cs
) {
281 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
282 if ((&other_cpu
->env
!= env
) &&
283 ((other_cpu
->env
.CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
290 static inline void compute_hflags(CPUMIPSState
*env
)
292 env
->hflags
&= ~(MIPS_HFLAG_COP1X
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
|
293 MIPS_HFLAG_F64
| MIPS_HFLAG_FPU
| MIPS_HFLAG_KSU
|
294 MIPS_HFLAG_AWRAP
| MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
295 MIPS_HFLAG_DSP_R3
| MIPS_HFLAG_SBRI
| MIPS_HFLAG_MSA
|
296 MIPS_HFLAG_FRE
| MIPS_HFLAG_ELPA
| MIPS_HFLAG_ERL
);
297 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
298 env
->hflags
|= MIPS_HFLAG_ERL
;
300 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
301 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
302 !(env
->hflags
& MIPS_HFLAG_DM
)) {
303 env
->hflags
|= (env
->CP0_Status
>> CP0St_KSU
) &
306 #if defined(TARGET_MIPS64)
307 if ((env
->insn_flags
& ISA_MIPS3
) &&
308 (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_UM
) ||
309 (env
->CP0_Status
& (1 << CP0St_PX
)) ||
310 (env
->CP0_Status
& (1 << CP0St_UX
)))) {
311 env
->hflags
|= MIPS_HFLAG_64
;
314 if (!(env
->insn_flags
& ISA_MIPS3
)) {
315 env
->hflags
|= MIPS_HFLAG_AWRAP
;
316 } else if (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
317 !(env
->CP0_Status
& (1 << CP0St_UX
))) {
318 env
->hflags
|= MIPS_HFLAG_AWRAP
;
319 } else if (env
->insn_flags
& ISA_MIPS_R6
) {
320 /* Address wrapping for Supervisor and Kernel is specified in R6 */
321 if ((((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_SM
) &&
322 !(env
->CP0_Status
& (1 << CP0St_SX
))) ||
323 (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_KM
) &&
324 !(env
->CP0_Status
& (1 << CP0St_KX
)))) {
325 env
->hflags
|= MIPS_HFLAG_AWRAP
;
329 if (((env
->CP0_Status
& (1 << CP0St_CU0
)) &&
330 !(env
->insn_flags
& ISA_MIPS_R6
)) ||
331 !(env
->hflags
& MIPS_HFLAG_KSU
)) {
332 env
->hflags
|= MIPS_HFLAG_CP0
;
334 if (env
->CP0_Status
& (1 << CP0St_CU1
)) {
335 env
->hflags
|= MIPS_HFLAG_FPU
;
337 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
338 env
->hflags
|= MIPS_HFLAG_F64
;
340 if (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_KM
) &&
341 (env
->CP0_Config5
& (1 << CP0C5_SBRI
))) {
342 env
->hflags
|= MIPS_HFLAG_SBRI
;
344 if (env
->insn_flags
& ASE_DSP_R3
) {
346 * Our cpu supports DSP R3 ASE, so enable
347 * access to DSP R3 resources.
349 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
350 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
353 } else if (env
->insn_flags
& ASE_DSP_R2
) {
355 * Our cpu supports DSP R2 ASE, so enable
356 * access to DSP R2 resources.
358 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
359 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
;
362 } else if (env
->insn_flags
& ASE_DSP
) {
364 * Our cpu supports DSP ASE, so enable
365 * access to DSP resources.
367 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
368 env
->hflags
|= MIPS_HFLAG_DSP
;
372 if (env
->insn_flags
& ISA_MIPS_R2
) {
373 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
374 env
->hflags
|= MIPS_HFLAG_COP1X
;
376 } else if (env
->insn_flags
& ISA_MIPS_R1
) {
377 if (env
->hflags
& MIPS_HFLAG_64
) {
378 env
->hflags
|= MIPS_HFLAG_COP1X
;
380 } else if (env
->insn_flags
& ISA_MIPS4
) {
382 * All supported MIPS IV CPUs use the XX (CU3) to enable
383 * and disable the MIPS IV extensions to the MIPS III ISA.
384 * Some other MIPS IV CPUs ignore the bit, so the check here
385 * would be too restrictive for them.
387 if (env
->CP0_Status
& (1U << CP0St_CU3
)) {
388 env
->hflags
|= MIPS_HFLAG_COP1X
;
391 if (ase_msa_available(env
)) {
392 if (env
->CP0_Config5
& (1 << CP0C5_MSAEn
)) {
393 env
->hflags
|= MIPS_HFLAG_MSA
;
396 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
397 if (env
->CP0_Config5
& (1 << CP0C5_FRE
)) {
398 env
->hflags
|= MIPS_HFLAG_FRE
;
401 if (env
->CP0_Config3
& (1 << CP0C3_LPA
)) {
402 if (env
->CP0_PageGrain
& (1 << CP0PG_ELPA
)) {
403 env
->hflags
|= MIPS_HFLAG_ELPA
;