hw/lm32/lm32_boards.c

   1 /*
   2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/units.h"
  22 #include "qemu/error-report.h"
  23 #include "cpu.h"
  24 #include "hw/sysbus.h"
  25 #include "hw/irq.h"
  26 #include "hw/block/flash.h"
  27 #include "hw/boards.h"
  28 #include "hw/loader.h"
  29 #include "elf.h"
  30 #include "lm32_hwsetup.h"
  31 #include "lm32.h"
  32 #include "exec/address-spaces.h"
  33 #include "sysemu/reset.h"
  34 #include "sysemu/sysemu.h"
  35
  36 typedef struct {
  37     LM32CPU *cpu;
  38     hwaddr bootstrap_pc;
  39     hwaddr flash_base;
  40     hwaddr hwsetup_base;
  41     hwaddr initrd_base;
  42     size_t initrd_size;
  43     hwaddr cmdline_base;
  44 } ResetInfo;
  45
  46 static void cpu_irq_handler(void *opaque, int irq, int level)
  47 {
  48     LM32CPU *cpu = opaque;
  49     CPUState *cs = CPU(cpu);
  50
  51     if (level) {
  52         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  53     } else {
  54         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  55     }
  56 }
  57
  58 static void main_cpu_reset(void *opaque)
  59 {
  60     ResetInfo *reset_info = opaque;
  61     CPULM32State *env = &reset_info->cpu->env;
  62
  63     cpu_reset(CPU(reset_info->cpu));
  64
  65     /* init defaults */
  66     env->pc = (uint32_t)reset_info->bootstrap_pc;
  67     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
  68     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
  69     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
  70     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
  71         reset_info->initrd_size);
  72     env->eba = reset_info->flash_base;
  73     env->deba = reset_info->flash_base;
  74 }
  75
  76 static void lm32_evr_init(MachineState *machine)
  77 {
  78     const char *kernel_filename = machine->kernel_filename;
  79     LM32CPU *cpu;
  80     CPULM32State *env;
  81     DriveInfo *dinfo;
  82     MemoryRegion *address_space_mem =  get_system_memory();
  83     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
  84     qemu_irq irq[32];
  85     ResetInfo *reset_info;
  86     int i;
  87
  88     /* memory map */
  89     hwaddr flash_base  = 0x04000000;
  90     size_t flash_sector_size       = 256 * KiB;
  91     size_t flash_size              = 32 * MiB;
  92     hwaddr ram_base    = 0x08000000;
  93     size_t ram_size                = 64 * MiB;
  94     hwaddr timer0_base = 0x80002000;
  95     hwaddr uart0_base  = 0x80006000;
  96     hwaddr timer1_base = 0x8000a000;
  97     int uart0_irq                  = 0;
  98     int timer0_irq                 = 1;
  99     int timer1_irq                 = 3;
 100
 101     reset_info = g_malloc0(sizeof(ResetInfo));
 102
 103     cpu = LM32_CPU(cpu_create(machine->cpu_type));
 104
 105     env = &cpu->env;
 106     reset_info->cpu = cpu;
 107
 108     reset_info->flash_base = flash_base;
 109
 110     memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
 111                                          ram_size);
 112     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 113
 114     dinfo = drive_get(IF_PFLASH, 0, 0);
 115     /* Spansion S29NS128P */
 116     pflash_cfi02_register(flash_base, "lm32_evr.flash", flash_size,
 117                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 118                           flash_sector_size,
 119                           1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 120
 121     /* create irq lines */
 122     env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
 123     for (i = 0; i < 32; i++) {
 124         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 125     }
 126
 127     lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
 128     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 129     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 130
 131     /* make sure juart isn't the first chardev */
 132     env->juart_state = lm32_juart_init(serial_hd(1));
 133
 134     reset_info->bootstrap_pc = flash_base;
 135
 136     if (kernel_filename) {
 137         uint64_t entry;
 138         int kernel_size;
 139
 140         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 141                                &entry, NULL, NULL,
 142                                1, EM_LATTICEMICO32, 0, 0);
 143         reset_info->bootstrap_pc = entry;
 144
 145         if (kernel_size < 0) {
 146             kernel_size = load_image_targphys(kernel_filename, ram_base,
 147                                               ram_size);
 148             reset_info->bootstrap_pc = ram_base;
 149         }
 150
 151         if (kernel_size < 0) {
 152             error_report("could not load kernel '%s'", kernel_filename);
 153             exit(1);
 154         }
 155     }
 156
 157     qemu_register_reset(main_cpu_reset, reset_info);
 158 }
 159
 160 static void lm32_uclinux_init(MachineState *machine)
 161 {
 162     const char *kernel_filename = machine->kernel_filename;
 163     const char *kernel_cmdline = machine->kernel_cmdline;
 164     const char *initrd_filename = machine->initrd_filename;
 165     LM32CPU *cpu;
 166     CPULM32State *env;
 167     DriveInfo *dinfo;
 168     MemoryRegion *address_space_mem =  get_system_memory();
 169     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
 170     qemu_irq irq[32];
 171     HWSetup *hw;
 172     ResetInfo *reset_info;
 173     int i;
 174
 175     /* memory map */
 176     hwaddr flash_base   = 0x04000000;
 177     size_t flash_sector_size        = 256 * KiB;
 178     size_t flash_size               = 32 * MiB;
 179     hwaddr ram_base     = 0x08000000;
 180     size_t ram_size                 = 64 * MiB;
 181     hwaddr uart0_base   = 0x80000000;
 182     hwaddr timer0_base  = 0x80002000;
 183     hwaddr timer1_base  = 0x80010000;
 184     hwaddr timer2_base  = 0x80012000;
 185     int uart0_irq                   = 0;
 186     int timer0_irq                  = 1;
 187     int timer1_irq                  = 20;
 188     int timer2_irq                  = 21;
 189     hwaddr hwsetup_base = 0x0bffe000;
 190     hwaddr cmdline_base = 0x0bfff000;
 191     hwaddr initrd_base  = 0x08400000;
 192     size_t initrd_max               = 0x01000000;
 193
 194     reset_info = g_malloc0(sizeof(ResetInfo));
 195
 196     cpu = LM32_CPU(cpu_create(machine->cpu_type));
 197
 198     env = &cpu->env;
 199     reset_info->cpu = cpu;
 200
 201     reset_info->flash_base = flash_base;
 202
 203     memory_region_allocate_system_memory(phys_ram, NULL,
 204                                          "lm32_uclinux.sdram", ram_size);
 205     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 206
 207     dinfo = drive_get(IF_PFLASH, 0, 0);
 208     /* Spansion S29NS128P */
 209     pflash_cfi02_register(flash_base, "lm32_uclinux.flash", flash_size,
 210                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 211                           flash_sector_size,
 212                           1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 213
 214     /* create irq lines */
 215     env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
 216     for (i = 0; i < 32; i++) {
 217         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 218     }
 219
 220     lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
 221     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 222     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 223     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
 224
 225     /* make sure juart isn't the first chardev */
 226     env->juart_state = lm32_juart_init(serial_hd(1));
 227
 228     reset_info->bootstrap_pc = flash_base;
 229
 230     if (kernel_filename) {
 231         uint64_t entry;
 232         int kernel_size;
 233
 234         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 235                                &entry, NULL, NULL,
 236                                1, EM_LATTICEMICO32, 0, 0);
 237         reset_info->bootstrap_pc = entry;
 238
 239         if (kernel_size < 0) {
 240             kernel_size = load_image_targphys(kernel_filename, ram_base,
 241                                               ram_size);
 242             reset_info->bootstrap_pc = ram_base;
 243         }
 244
 245         if (kernel_size < 0) {
 246             error_report("could not load kernel '%s'", kernel_filename);
 247             exit(1);
 248         }
 249     }
 250
 251     /* generate a rom with the hardware description */
 252     hw = hwsetup_init();
 253     hwsetup_add_cpu(hw, "LM32", 75000000);
 254     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
 255     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
 256     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
 257     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
 258     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
 259     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
 260     hwsetup_add_trailer(hw);
 261     hwsetup_create_rom(hw, hwsetup_base);
 262     hwsetup_free(hw);
 263
 264     reset_info->hwsetup_base = hwsetup_base;
 265
 266     if (kernel_cmdline && strlen(kernel_cmdline)) {
 267         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 268                 kernel_cmdline);
 269         reset_info->cmdline_base = cmdline_base;
 270     }
 271
 272     if (initrd_filename) {
 273         size_t initrd_size;
 274         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 275                 initrd_max);
 276         reset_info->initrd_base = initrd_base;
 277         reset_info->initrd_size = initrd_size;
 278     }
 279
 280     qemu_register_reset(main_cpu_reset, reset_info);
 281 }
 282
 283 static void lm32_evr_class_init(ObjectClass *oc, void *data)
 284 {
 285     MachineClass *mc = MACHINE_CLASS(oc);
 286
 287     mc->desc = "LatticeMico32 EVR32 eval system";
 288     mc->init = lm32_evr_init;
 289     mc->is_default = 1;
 290     mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
 291 }
 292
 293 static const TypeInfo lm32_evr_type = {
 294     .name = MACHINE_TYPE_NAME("lm32-evr"),
 295     .parent = TYPE_MACHINE,
 296     .class_init = lm32_evr_class_init,
 297 };
 298
 299 static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
 300 {
 301     MachineClass *mc = MACHINE_CLASS(oc);
 302
 303     mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
 304     mc->init = lm32_uclinux_init;
 305     mc->is_default = 0;
 306     mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
 307 }
 308
 309 static const TypeInfo lm32_uclinux_type = {
 310     .name = MACHINE_TYPE_NAME("lm32-uclinux"),
 311     .parent = TYPE_MACHINE,
 312     .class_init = lm32_uclinux_class_init,
 313 };
 314
 315 static void lm32_machine_init(void)
 316 {
 317     type_register_static(&lm32_evr_type);
 318     type_register_static(&lm32_uclinux_type);
 319 }
 320
 321 type_init(lm32_machine_init)