1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "hw/core/cpu.h"
31 #include "target/i386/cpu.h"
32 #include "hw/misc/pvpanic.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/isa/isa.h"
40 #include "hw/block/fdc.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "hw/acpi/vmgenid.h"
45 #include "hw/boards.h"
46 #include "sysemu/tpm_backend.h"
47 #include "hw/rtc/mc146818rtc_regs.h"
48 #include "migration/vmstate.h"
49 #include "hw/mem/memory-device.h"
50 #include "sysemu/numa.h"
51 #include "sysemu/reset.h"
53 /* Supported chipsets: */
54 #include "hw/southbridge/piix.h"
55 #include "hw/acpi/pcihp.h"
56 #include "hw/i386/fw_cfg.h"
57 #include "hw/i386/ich9.h"
58 #include "hw/pci/pci_bus.h"
59 #include "hw/pci-host/q35.h"
60 #include "hw/i386/x86-iommu.h"
62 #include "hw/acpi/aml-build.h"
63 #include "hw/acpi/utils.h"
64 #include "hw/acpi/pci.h"
66 #include "qom/qom-qobject.h"
67 #include "hw/i386/amd_iommu.h"
68 #include "hw/i386/intel_iommu.h"
70 #include "hw/acpi/ipmi.h"
72 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
73 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
74 * a little bit, there should be plenty of free space since the DSDT
75 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
77 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
78 #define ACPI_BUILD_ALIGN_SIZE 0x1000
80 #define ACPI_BUILD_TABLE_SIZE 0x20000
82 /* #define DEBUG_ACPI_BUILD */
83 #ifdef DEBUG_ACPI_BUILD
84 #define ACPI_BUILD_DPRINTF(fmt, ...) \
85 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
87 #define ACPI_BUILD_DPRINTF(fmt, ...)
90 /* Default IOAPIC ID */
91 #define ACPI_BUILD_IOAPIC_ID 0x0
93 typedef struct AcpiPmInfo
{
99 uint16_t cpu_hp_io_base
;
100 uint16_t pcihp_io_base
;
101 uint16_t pcihp_io_len
;
104 typedef struct AcpiMiscInfo
{
107 TPMVersion tpm_version
;
108 const unsigned char *dsdt_code
;
110 uint16_t pvpanic_port
;
111 uint16_t applesmc_io_base
;
114 typedef struct AcpiBuildPciBusHotplugState
{
115 GArray
*device_table
;
116 GArray
*notify_table
;
117 struct AcpiBuildPciBusHotplugState
*parent
;
118 bool pcihp_bridge_en
;
119 } AcpiBuildPciBusHotplugState
;
121 typedef struct FwCfgTPMConfig
{
122 uint32_t tpmppi_address
;
124 uint8_t tpmppi_version
;
125 } QEMU_PACKED FwCfgTPMConfig
;
127 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
);
129 static void init_common_fadt_data(MachineState
*ms
, Object
*o
,
132 uint32_t io
= object_property_get_uint(o
, ACPI_PM_PROP_PM_IO_BASE
, NULL
);
133 AmlAddressSpace as
= AML_AS_SYSTEM_IO
;
134 AcpiFadtData fadt
= {
137 (1 << ACPI_FADT_F_WBINVD
) |
138 (1 << ACPI_FADT_F_PROC_C1
) |
139 (1 << ACPI_FADT_F_SLP_BUTTON
) |
140 (1 << ACPI_FADT_F_RTC_S4
) |
141 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
) |
142 /* APIC destination mode ("Flat Logical") has an upper limit of 8
143 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
146 ((ms
->smp
.max_cpus
> 8) ?
147 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
) : 0),
148 .int_model
= 1 /* Multiple APIC */,
149 .rtc_century
= RTC_CENTURY
,
150 .plvl2_lat
= 0xfff /* C2 state not supported */,
151 .plvl3_lat
= 0xfff /* C3 state not supported */,
152 .smi_cmd
= ACPI_PORT_SMI_CMD
,
153 .sci_int
= object_property_get_uint(o
, ACPI_PM_PROP_SCI_INT
, NULL
),
155 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_ENABLE_CMD
, NULL
),
157 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_DISABLE_CMD
, NULL
),
158 .pm1a_evt
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
},
159 .pm1a_cnt
= { .space_id
= as
, .bit_width
= 2 * 8,
160 .address
= io
+ 0x04 },
161 .pm_tmr
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
+ 0x08 },
162 .gpe0_blk
= { .space_id
= as
, .bit_width
=
163 object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK_LEN
, NULL
) * 8,
164 .address
= object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK
, NULL
)
170 static Object
*object_resolve_type_unambiguous(const char *typename
)
173 Object
*o
= object_resolve_path_type("", typename
, &ambig
);
181 static void acpi_get_pm_info(MachineState
*machine
, AcpiPmInfo
*pm
)
183 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
184 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
185 Object
*obj
= piix
? piix
: lpc
;
187 pm
->cpu_hp_io_base
= 0;
188 pm
->pcihp_io_base
= 0;
189 pm
->pcihp_io_len
= 0;
192 init_common_fadt_data(machine
, obj
, &pm
->fadt
);
194 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
196 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
198 object_property_get_uint(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
200 object_property_get_uint(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
203 struct AcpiGenericAddress r
= { .space_id
= AML_AS_SYSTEM_IO
,
204 .bit_width
= 8, .address
= ICH9_RST_CNT_IOPORT
};
205 pm
->fadt
.reset_reg
= r
;
206 pm
->fadt
.reset_val
= 0xf;
207 pm
->fadt
.flags
|= 1 << ACPI_FADT_F_RESET_REG_SUP
;
208 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
211 /* The above need not be conditional on machine type because the reset port
212 * happens to be the same on PIIX (pc) and ICH9 (q35). */
213 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT
!= PIIX_RCR_IOPORT
);
215 /* Fill in optional s3/s4 related properties */
216 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
218 pm
->s3_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
220 pm
->s3_disabled
= false;
223 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
225 pm
->s4_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
227 pm
->s4_disabled
= false;
230 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
232 pm
->s4_val
= qnum_get_uint(qobject_to(QNum
, o
));
238 pm
->pcihp_bridge_en
=
239 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
243 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
245 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
246 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
247 assert(!!piix
!= !!lpc
);
250 info
->is_piix4
= true;
253 info
->is_piix4
= false;
256 info
->has_hpet
= hpet_find();
257 info
->tpm_version
= tpm_get_version(tpm_find());
258 info
->pvpanic_port
= pvpanic_port();
259 info
->applesmc_io_base
= applesmc_port();
263 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
264 * On i386 arch we only have two pci hosts, so we can look only for them.
266 static Object
*acpi_get_i386_pci_host(void)
270 host
= OBJECT_CHECK(PCIHostState
,
271 object_resolve_path("/machine/i440fx", NULL
),
272 TYPE_PCI_HOST_BRIDGE
);
274 host
= OBJECT_CHECK(PCIHostState
,
275 object_resolve_path("/machine/q35", NULL
),
276 TYPE_PCI_HOST_BRIDGE
);
282 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
286 pci_host
= acpi_get_i386_pci_host();
289 range_set_bounds1(hole
,
290 object_property_get_uint(pci_host
,
291 PCI_HOST_PROP_PCI_HOLE_START
,
293 object_property_get_uint(pci_host
,
294 PCI_HOST_PROP_PCI_HOLE_END
,
296 range_set_bounds1(hole64
,
297 object_property_get_uint(pci_host
,
298 PCI_HOST_PROP_PCI_HOLE64_START
,
300 object_property_get_uint(pci_host
,
301 PCI_HOST_PROP_PCI_HOLE64_END
,
305 static void acpi_align_size(GArray
*blob
, unsigned align
)
307 /* Align size to multiple of given size. This reduces the chance
308 * we need to change size in the future (breaking cross version migration).
310 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
315 build_facs(GArray
*table_data
)
317 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
318 memcpy(&facs
->signature
, "FACS", 4);
319 facs
->length
= cpu_to_le32(sizeof(*facs
));
322 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
323 const CPUArchIdList
*apic_ids
, GArray
*entry
)
325 uint32_t apic_id
= apic_ids
->cpus
[uid
].arch_id
;
327 /* ACPI spec says that LAPIC entry for non present
328 * CPU may be omitted from MADT or it must be marked
329 * as disabled. However omitting non present CPU from
330 * MADT breaks hotplug on linux. So possible CPUs
331 * should be put in MADT but kept disabled.
334 AcpiMadtProcessorApic
*apic
= acpi_data_push(entry
, sizeof *apic
);
336 apic
->type
= ACPI_APIC_PROCESSOR
;
337 apic
->length
= sizeof(*apic
);
338 apic
->processor_id
= uid
;
339 apic
->local_apic_id
= apic_id
;
340 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
341 apic
->flags
= cpu_to_le32(1);
343 apic
->flags
= cpu_to_le32(0);
346 AcpiMadtProcessorX2Apic
*apic
= acpi_data_push(entry
, sizeof *apic
);
348 apic
->type
= ACPI_APIC_LOCAL_X2APIC
;
349 apic
->length
= sizeof(*apic
);
350 apic
->uid
= cpu_to_le32(uid
);
351 apic
->x2apic_id
= cpu_to_le32(apic_id
);
352 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
353 apic
->flags
= cpu_to_le32(1);
355 apic
->flags
= cpu_to_le32(0);
361 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
363 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
364 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
365 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
366 int madt_start
= table_data
->len
;
367 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_GET_CLASS(pcms
->acpi_dev
);
368 AcpiDeviceIf
*adev
= ACPI_DEVICE_IF(pcms
->acpi_dev
);
369 bool x2apic_mode
= false;
371 AcpiMultipleApicTable
*madt
;
372 AcpiMadtIoApic
*io_apic
;
373 AcpiMadtIntsrcovr
*intsrcovr
;
376 madt
= acpi_data_push(table_data
, sizeof *madt
);
377 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
378 madt
->flags
= cpu_to_le32(1);
380 for (i
= 0; i
< apic_ids
->len
; i
++) {
381 adevc
->madt_cpu(adev
, i
, apic_ids
, table_data
);
382 if (apic_ids
->cpus
[i
].arch_id
> 254) {
387 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
388 io_apic
->type
= ACPI_APIC_IO
;
389 io_apic
->length
= sizeof(*io_apic
);
390 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
391 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
392 io_apic
->interrupt
= cpu_to_le32(0);
394 if (x86ms
->apic_xrupt_override
) {
395 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
396 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
397 intsrcovr
->length
= sizeof(*intsrcovr
);
398 intsrcovr
->source
= 0;
399 intsrcovr
->gsi
= cpu_to_le32(2);
400 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
402 for (i
= 1; i
< 16; i
++) {
403 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
404 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
405 /* No need for a INT source override structure. */
408 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
409 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
410 intsrcovr
->length
= sizeof(*intsrcovr
);
411 intsrcovr
->source
= i
;
412 intsrcovr
->gsi
= cpu_to_le32(i
);
413 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
417 AcpiMadtLocalX2ApicNmi
*local_nmi
;
419 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
420 local_nmi
->type
= ACPI_APIC_LOCAL_X2APIC_NMI
;
421 local_nmi
->length
= sizeof(*local_nmi
);
422 local_nmi
->uid
= 0xFFFFFFFF; /* all processors */
423 local_nmi
->flags
= cpu_to_le16(0);
424 local_nmi
->lint
= 1; /* ACPI_LINT1 */
426 AcpiMadtLocalNmi
*local_nmi
;
428 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
429 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
430 local_nmi
->length
= sizeof(*local_nmi
);
431 local_nmi
->processor_id
= 0xff; /* all processors */
432 local_nmi
->flags
= cpu_to_le16(0);
433 local_nmi
->lint
= 1; /* ACPI_LINT1 */
436 build_header(linker
, table_data
,
437 (void *)(table_data
->data
+ madt_start
), "APIC",
438 table_data
->len
- madt_start
, 1, NULL
, NULL
);
441 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
444 int32_t devfn
= PCI_DEVFN(slot
, 0);
446 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
447 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
448 aml_append(method
, if_ctx
);
451 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
452 bool pcihp_bridge_en
)
454 Aml
*dev
, *notify_method
= NULL
, *method
;
459 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
461 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
463 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
464 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
467 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
470 PCIDevice
*pdev
= bus
->devices
[i
];
471 int slot
= PCI_SLOT(i
);
472 bool hotplug_enabled_dev
;
476 if (bsel
) { /* add hotplug slots for non present devices */
477 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
478 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
479 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
480 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
482 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
484 aml_append(dev
, method
);
485 aml_append(parent_scope
, dev
);
487 build_append_pcihp_notify_entry(notify_method
, slot
);
492 pc
= PCI_DEVICE_GET_CLASS(pdev
);
493 dc
= DEVICE_GET_CLASS(pdev
);
495 /* When hotplug for bridges is enabled, bridges are
496 * described in ACPI separately (see build_pci_bus_end).
497 * In this case they aren't themselves hot-pluggable.
498 * Hotplugged bridges *are* hot-pluggable.
500 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
501 !DEVICE(pdev
)->hotplugged
;
503 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
505 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
509 /* start to compose PCI slot descriptor */
510 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
511 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
513 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
514 /* add VGA specific AML methods */
517 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
523 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
524 aml_append(method
, aml_return(aml_int(0)));
525 aml_append(dev
, method
);
527 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
528 aml_append(method
, aml_return(aml_int(0)));
529 aml_append(dev
, method
);
531 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
532 aml_append(method
, aml_return(aml_int(s3d
)));
533 aml_append(dev
, method
);
534 } else if (hotplug_enabled_dev
) {
535 /* add _SUN/_EJ0 to make slot hotpluggable */
536 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
538 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
540 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
542 aml_append(dev
, method
);
545 build_append_pcihp_notify_entry(notify_method
, slot
);
547 } else if (bridge_in_acpi
) {
549 * device is coldplugged bridge,
550 * add child device descriptions into its scope
552 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
554 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
556 /* slot descriptor has been composed, add it into parent context */
557 aml_append(parent_scope
, dev
);
561 aml_append(parent_scope
, notify_method
);
564 /* Append PCNT method to notify about events on local and child buses.
565 * Add unconditionally for root since DSDT expects it.
567 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
569 /* If bus supports hotplug select it and notify about local events */
571 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
573 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
575 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
578 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
582 /* Notify about child bus events in any case */
583 if (pcihp_bridge_en
) {
584 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
585 int32_t devfn
= sec
->parent_dev
->devfn
;
587 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
591 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
594 aml_append(parent_scope
, method
);
600 * @link_name: link name for PCI route entry
602 * build AML package containing a PCI route entry for @link_name
604 static Aml
*build_prt_entry(const char *link_name
)
606 Aml
*a_zero
= aml_int(0);
607 Aml
*pkg
= aml_package(4);
608 aml_append(pkg
, a_zero
);
609 aml_append(pkg
, a_zero
);
610 aml_append(pkg
, aml_name("%s", link_name
));
611 aml_append(pkg
, a_zero
);
616 * initialize_route - Initialize the interrupt routing rule
617 * through a specific LINK:
618 * if (lnk_idx == idx)
619 * route using link 'link_name'
621 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
622 Aml
*lnk_idx
, int idx
)
624 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
625 Aml
*pkg
= build_prt_entry(link_name
);
627 aml_append(if_ctx
, aml_store(pkg
, route
));
633 * build_prt - Define interrupt rounting rules
635 * Returns an array of 128 routes, one for each device,
636 * based on device location.
637 * The main goal is to equaly distribute the interrupts
638 * over the 4 existing ACPI links (works only for i440fx).
639 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
642 static Aml
*build_prt(bool is_pci0_prt
)
644 Aml
*method
, *while_ctx
, *pin
, *res
;
646 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
649 aml_append(method
, aml_store(aml_package(128), res
));
650 aml_append(method
, aml_store(aml_int(0), pin
));
652 /* while (pin < 128) */
653 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
655 Aml
*slot
= aml_local(2);
656 Aml
*lnk_idx
= aml_local(3);
657 Aml
*route
= aml_local(4);
659 /* slot = pin >> 2 */
660 aml_append(while_ctx
,
661 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
662 /* lnk_idx = (slot + pin) & 3 */
663 aml_append(while_ctx
,
664 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
667 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
668 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
670 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
672 /* device 1 is the power-management device, needs SCI */
673 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
675 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
678 aml_store(build_prt_entry("LNKS"), route
));
680 aml_append(if_device_1
, if_pin_4
);
681 else_pin_4
= aml_else();
683 aml_append(else_pin_4
,
684 aml_store(build_prt_entry("LNKA"), route
));
686 aml_append(if_device_1
, else_pin_4
);
688 aml_append(while_ctx
, if_device_1
);
690 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
692 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
693 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
695 /* route[0] = 0x[slot]FFFF */
696 aml_append(while_ctx
,
697 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
699 aml_index(route
, aml_int(0))));
700 /* route[1] = pin & 3 */
701 aml_append(while_ctx
,
702 aml_store(aml_and(pin
, aml_int(3), NULL
),
703 aml_index(route
, aml_int(1))));
704 /* res[pin] = route */
705 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
707 aml_append(while_ctx
, aml_increment(pin
));
709 aml_append(method
, while_ctx
);
711 aml_append(method
, aml_return(res
));
716 typedef struct CrsRangeEntry
{
721 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
723 CrsRangeEntry
*entry
;
725 entry
= g_malloc(sizeof(*entry
));
727 entry
->limit
= limit
;
729 g_ptr_array_add(ranges
, entry
);
732 static void crs_range_free(gpointer data
)
734 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
738 typedef struct CrsRangeSet
{
739 GPtrArray
*io_ranges
;
740 GPtrArray
*mem_ranges
;
741 GPtrArray
*mem_64bit_ranges
;
744 static void crs_range_set_init(CrsRangeSet
*range_set
)
746 range_set
->io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
747 range_set
->mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
748 range_set
->mem_64bit_ranges
=
749 g_ptr_array_new_with_free_func(crs_range_free
);
752 static void crs_range_set_free(CrsRangeSet
*range_set
)
754 g_ptr_array_free(range_set
->io_ranges
, true);
755 g_ptr_array_free(range_set
->mem_ranges
, true);
756 g_ptr_array_free(range_set
->mem_64bit_ranges
, true);
759 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
761 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
762 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
764 if (entry_a
->base
< entry_b
->base
) {
766 } else if (entry_a
->base
> entry_b
->base
) {
774 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
775 * interval, computes the 'free' ranges from the same interval.
776 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
777 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
779 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
780 uint64_t start
, uint64_t end
)
782 GPtrArray
*free_ranges
= g_ptr_array_new();
783 uint64_t free_base
= start
;
786 g_ptr_array_sort(ranges
, crs_range_compare
);
787 for (i
= 0; i
< ranges
->len
; i
++) {
788 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
790 if (free_base
< used
->base
) {
791 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
794 free_base
= used
->limit
+ 1;
797 if (free_base
< end
) {
798 crs_range_insert(free_ranges
, free_base
, end
);
801 g_ptr_array_set_size(ranges
, 0);
802 for (i
= 0; i
< free_ranges
->len
; i
++) {
803 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
806 g_ptr_array_free(free_ranges
, true);
810 * crs_range_merge - merges adjacent ranges in the given array.
811 * Array elements are deleted and replaced with the merged ranges.
813 static void crs_range_merge(GPtrArray
*range
)
815 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
816 CrsRangeEntry
*entry
;
817 uint64_t range_base
, range_limit
;
824 g_ptr_array_sort(range
, crs_range_compare
);
826 entry
= g_ptr_array_index(range
, 0);
827 range_base
= entry
->base
;
828 range_limit
= entry
->limit
;
829 for (i
= 1; i
< range
->len
; i
++) {
830 entry
= g_ptr_array_index(range
, i
);
831 if (entry
->base
- 1 == range_limit
) {
832 range_limit
= entry
->limit
;
834 crs_range_insert(tmp
, range_base
, range_limit
);
835 range_base
= entry
->base
;
836 range_limit
= entry
->limit
;
839 crs_range_insert(tmp
, range_base
, range_limit
);
841 g_ptr_array_set_size(range
, 0);
842 for (i
= 0; i
< tmp
->len
; i
++) {
843 entry
= g_ptr_array_index(tmp
, i
);
844 crs_range_insert(range
, entry
->base
, entry
->limit
);
846 g_ptr_array_free(tmp
, true);
849 static Aml
*build_crs(PCIHostState
*host
, CrsRangeSet
*range_set
)
851 Aml
*crs
= aml_resource_template();
852 CrsRangeSet temp_range_set
;
853 CrsRangeEntry
*entry
;
854 uint8_t max_bus
= pci_bus_num(host
->bus
);
859 crs_range_set_init(&temp_range_set
);
860 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
861 uint64_t range_base
, range_limit
;
862 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
868 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
869 PCIIORegion
*r
= &dev
->io_regions
[i
];
871 range_base
= r
->addr
;
872 range_limit
= r
->addr
+ r
->size
- 1;
875 * Work-around for old bioses
876 * that do not support multiple root buses
878 if (!range_base
|| range_base
> range_limit
) {
882 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
883 crs_range_insert(temp_range_set
.io_ranges
,
884 range_base
, range_limit
);
885 } else { /* "memory" */
886 crs_range_insert(temp_range_set
.mem_ranges
,
887 range_base
, range_limit
);
891 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
892 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
893 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
894 if (subordinate
> max_bus
) {
895 max_bus
= subordinate
;
898 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
899 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
902 * Work-around for old bioses
903 * that do not support multiple root buses
905 if (range_base
&& range_base
<= range_limit
) {
906 crs_range_insert(temp_range_set
.io_ranges
,
907 range_base
, range_limit
);
911 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
913 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
916 * Work-around for old bioses
917 * that do not support multiple root buses
919 if (range_base
&& range_base
<= range_limit
) {
920 uint64_t length
= range_limit
- range_base
+ 1;
921 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
922 crs_range_insert(temp_range_set
.mem_ranges
,
923 range_base
, range_limit
);
925 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
926 range_base
, range_limit
);
931 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
933 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
936 * Work-around for old bioses
937 * that do not support multiple root buses
939 if (range_base
&& range_base
<= range_limit
) {
940 uint64_t length
= range_limit
- range_base
+ 1;
941 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
942 crs_range_insert(temp_range_set
.mem_ranges
,
943 range_base
, range_limit
);
945 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
946 range_base
, range_limit
);
952 crs_range_merge(temp_range_set
.io_ranges
);
953 for (i
= 0; i
< temp_range_set
.io_ranges
->len
; i
++) {
954 entry
= g_ptr_array_index(temp_range_set
.io_ranges
, i
);
956 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
957 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
958 0, entry
->base
, entry
->limit
, 0,
959 entry
->limit
- entry
->base
+ 1));
960 crs_range_insert(range_set
->io_ranges
, entry
->base
, entry
->limit
);
963 crs_range_merge(temp_range_set
.mem_ranges
);
964 for (i
= 0; i
< temp_range_set
.mem_ranges
->len
; i
++) {
965 entry
= g_ptr_array_index(temp_range_set
.mem_ranges
, i
);
967 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
968 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
970 0, entry
->base
, entry
->limit
, 0,
971 entry
->limit
- entry
->base
+ 1));
972 crs_range_insert(range_set
->mem_ranges
, entry
->base
, entry
->limit
);
975 crs_range_merge(temp_range_set
.mem_64bit_ranges
);
976 for (i
= 0; i
< temp_range_set
.mem_64bit_ranges
->len
; i
++) {
977 entry
= g_ptr_array_index(temp_range_set
.mem_64bit_ranges
, i
);
979 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
980 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
982 0, entry
->base
, entry
->limit
, 0,
983 entry
->limit
- entry
->base
+ 1));
984 crs_range_insert(range_set
->mem_64bit_ranges
,
985 entry
->base
, entry
->limit
);
988 crs_range_set_free(&temp_range_set
);
991 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
993 pci_bus_num(host
->bus
),
996 max_bus
- pci_bus_num(host
->bus
) + 1));
1001 static void build_hpet_aml(Aml
*table
)
1007 Aml
*scope
= aml_scope("_SB");
1008 Aml
*dev
= aml_device("HPET");
1009 Aml
*zero
= aml_int(0);
1010 Aml
*id
= aml_local(0);
1011 Aml
*period
= aml_local(1);
1013 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1014 aml_append(dev
, aml_name_decl("_UID", zero
));
1017 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1019 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1020 aml_append(field
, aml_named_field("VEND", 32));
1021 aml_append(field
, aml_named_field("PRD", 32));
1022 aml_append(dev
, field
);
1024 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1025 aml_append(method
, aml_store(aml_name("VEND"), id
));
1026 aml_append(method
, aml_store(aml_name("PRD"), period
));
1027 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1028 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1029 aml_equal(id
, aml_int(0xffff))));
1031 aml_append(if_ctx
, aml_return(zero
));
1033 aml_append(method
, if_ctx
);
1035 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1036 aml_lgreater(period
, aml_int(100000000))));
1038 aml_append(if_ctx
, aml_return(zero
));
1040 aml_append(method
, if_ctx
);
1042 aml_append(method
, aml_return(aml_int(0x0F)));
1043 aml_append(dev
, method
);
1045 crs
= aml_resource_template();
1046 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1047 aml_append(dev
, aml_name_decl("_CRS", crs
));
1049 aml_append(scope
, dev
);
1050 aml_append(table
, scope
);
1053 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1056 uint8_t maxc
, maxh
, maxs
;
1058 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1060 dev
= aml_device("FLP%c", 'A' + idx
);
1062 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1064 fdi
= aml_package(16);
1065 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1067 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1069 * the values below are the limits of the drive, and are thus independent
1070 * of the inserted media
1072 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1073 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1074 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1076 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1077 * the drive type, so shall we
1079 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1080 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1081 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1082 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1083 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1084 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1085 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1086 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1087 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1088 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1089 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1091 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1095 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1101 #define ACPI_FDE_MAX_FD 4
1102 uint32_t fde_buf
[5] = {
1103 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1104 cpu_to_le32(2) /* tape presence (2 == never present) */
1107 dev
= aml_device("FDC0");
1108 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1110 crs
= aml_resource_template();
1111 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1112 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1113 aml_append(crs
, aml_irq_no_flags(6));
1115 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1116 aml_append(dev
, aml_name_decl("_CRS", crs
));
1118 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1119 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1121 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1122 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1123 aml_append(dev
, build_fdinfo_aml(i
, type
));
1126 aml_append(dev
, aml_name_decl("_FDE",
1127 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1132 static Aml
*build_rtc_device_aml(void)
1137 dev
= aml_device("RTC");
1138 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1139 crs
= aml_resource_template();
1140 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1141 aml_append(crs
, aml_irq_no_flags(8));
1142 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1143 aml_append(dev
, aml_name_decl("_CRS", crs
));
1148 static Aml
*build_kbd_device_aml(void)
1154 dev
= aml_device("KBD");
1155 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1157 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1158 aml_append(method
, aml_return(aml_int(0x0f)));
1159 aml_append(dev
, method
);
1161 crs
= aml_resource_template();
1162 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1163 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1164 aml_append(crs
, aml_irq_no_flags(1));
1165 aml_append(dev
, aml_name_decl("_CRS", crs
));
1170 static Aml
*build_mouse_device_aml(void)
1176 dev
= aml_device("MOU");
1177 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1179 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1180 aml_append(method
, aml_return(aml_int(0x0f)));
1181 aml_append(dev
, method
);
1183 crs
= aml_resource_template();
1184 aml_append(crs
, aml_irq_no_flags(12));
1185 aml_append(dev
, aml_name_decl("_CRS", crs
));
1190 static Aml
*build_lpt_device_aml(void)
1197 Aml
*zero
= aml_int(0);
1198 Aml
*is_present
= aml_local(0);
1200 dev
= aml_device("LPT");
1201 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1203 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1204 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1205 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1207 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1209 aml_append(method
, if_ctx
);
1210 else_ctx
= aml_else();
1212 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1214 aml_append(method
, else_ctx
);
1215 aml_append(dev
, method
);
1217 crs
= aml_resource_template();
1218 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1219 aml_append(crs
, aml_irq_no_flags(7));
1220 aml_append(dev
, aml_name_decl("_CRS", crs
));
1225 static Aml
*build_com_device_aml(uint8_t uid
)
1232 Aml
*zero
= aml_int(0);
1233 Aml
*is_present
= aml_local(0);
1234 const char *enabled_field
= "CAEN";
1236 uint16_t io_port
= 0x03F8;
1238 assert(uid
== 1 || uid
== 2);
1240 enabled_field
= "CBEN";
1245 dev
= aml_device("COM%d", uid
);
1246 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1247 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1249 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1250 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1251 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1253 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1255 aml_append(method
, if_ctx
);
1256 else_ctx
= aml_else();
1258 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1260 aml_append(method
, else_ctx
);
1261 aml_append(dev
, method
);
1263 crs
= aml_resource_template();
1264 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1265 aml_append(crs
, aml_irq_no_flags(irq
));
1266 aml_append(dev
, aml_name_decl("_CRS", crs
));
1271 static void build_isa_devices_aml(Aml
*table
)
1273 ISADevice
*fdc
= pc_find_fdc0();
1276 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1277 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
1279 aml_append(scope
, build_rtc_device_aml());
1280 aml_append(scope
, build_kbd_device_aml());
1281 aml_append(scope
, build_mouse_device_aml());
1283 aml_append(scope
, build_fdc_device_aml(fdc
));
1285 aml_append(scope
, build_lpt_device_aml());
1286 aml_append(scope
, build_com_device_aml(1));
1287 aml_append(scope
, build_com_device_aml(2));
1290 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1292 error_report("No ISA bus, unable to define IPMI ACPI data");
1294 build_acpi_ipmi_devices(scope
, BUS(obj
), "\\_SB.PCI0.ISA");
1297 aml_append(table
, scope
);
1300 static void build_dbg_aml(Aml
*table
)
1305 Aml
*scope
= aml_scope("\\");
1306 Aml
*buf
= aml_local(0);
1307 Aml
*len
= aml_local(1);
1308 Aml
*idx
= aml_local(2);
1311 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1312 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1313 aml_append(field
, aml_named_field("DBGB", 8));
1314 aml_append(scope
, field
);
1316 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1318 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1319 aml_append(method
, aml_to_buffer(buf
, buf
));
1320 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1321 aml_append(method
, aml_store(aml_int(0), idx
));
1323 while_ctx
= aml_while(aml_lless(idx
, len
));
1324 aml_append(while_ctx
,
1325 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1326 aml_append(while_ctx
, aml_increment(idx
));
1327 aml_append(method
, while_ctx
);
1329 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1330 aml_append(scope
, method
);
1332 aml_append(table
, scope
);
1335 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1340 uint32_t irqs
[] = {5, 10, 11};
1342 dev
= aml_device("%s", name
);
1343 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1344 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1346 crs
= aml_resource_template();
1347 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1348 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1349 aml_append(dev
, aml_name_decl("_PRS", crs
));
1351 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1352 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1353 aml_append(dev
, method
);
1355 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1356 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1357 aml_append(dev
, method
);
1359 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1360 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1361 aml_append(dev
, method
);
1363 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1364 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1365 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1366 aml_append(dev
, method
);
1371 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1378 dev
= aml_device("%s", name
);
1379 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1380 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1382 crs
= aml_resource_template();
1384 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1385 AML_SHARED
, &irqs
, 1));
1386 aml_append(dev
, aml_name_decl("_PRS", crs
));
1388 aml_append(dev
, aml_name_decl("_CRS", crs
));
1391 * _DIS can be no-op because the interrupt cannot be disabled.
1393 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1394 aml_append(dev
, method
);
1396 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1397 aml_append(dev
, method
);
1402 /* _CRS method - get current settings */
1403 static Aml
*build_iqcr_method(bool is_piix4
)
1407 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1408 Aml
*crs
= aml_resource_template();
1411 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1412 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1413 aml_append(method
, aml_name_decl("PRR0", crs
));
1416 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1419 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1420 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1421 aml_append(method
, if_ctx
);
1424 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1428 aml_append(method
, aml_return(aml_name("PRR0")));
1432 /* _STA method - get status */
1433 static Aml
*build_irq_status_method(void)
1436 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1438 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1439 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1440 aml_append(method
, if_ctx
);
1441 aml_append(method
, aml_return(aml_int(0x0B)));
1445 static void build_piix4_pci0_int(Aml
*table
)
1452 Aml
*sb_scope
= aml_scope("_SB");
1453 Aml
*pci0_scope
= aml_scope("PCI0");
1455 aml_append(pci0_scope
, build_prt(true));
1456 aml_append(sb_scope
, pci0_scope
);
1458 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1459 aml_append(field
, aml_named_field("PRQ0", 8));
1460 aml_append(field
, aml_named_field("PRQ1", 8));
1461 aml_append(field
, aml_named_field("PRQ2", 8));
1462 aml_append(field
, aml_named_field("PRQ3", 8));
1463 aml_append(sb_scope
, field
);
1465 aml_append(sb_scope
, build_irq_status_method());
1466 aml_append(sb_scope
, build_iqcr_method(true));
1468 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1469 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1470 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1471 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1473 dev
= aml_device("LNKS");
1475 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1476 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1478 crs
= aml_resource_template();
1480 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1481 AML_ACTIVE_HIGH
, AML_SHARED
,
1483 aml_append(dev
, aml_name_decl("_PRS", crs
));
1485 /* The SCI cannot be disabled and is always attached to GSI 9,
1486 * so these are no-ops. We only need this link to override the
1487 * polarity to active high and match the content of the MADT.
1489 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1490 aml_append(method
, aml_return(aml_int(0x0b)));
1491 aml_append(dev
, method
);
1493 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1494 aml_append(dev
, method
);
1496 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1497 aml_append(method
, aml_return(aml_name("_PRS")));
1498 aml_append(dev
, method
);
1500 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1501 aml_append(dev
, method
);
1503 aml_append(sb_scope
, dev
);
1505 aml_append(table
, sb_scope
);
1508 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1513 char base
= name
[3] < 'E' ? 'A' : 'E';
1514 char *s
= g_strdup(name
);
1515 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1517 assert(strlen(s
) == 4);
1519 head
= name
[3] - base
;
1520 for (i
= 0; i
< 4; i
++) {
1524 s
[3] = base
+ head
+ i
;
1525 pkg
= aml_package(4);
1526 aml_append(pkg
, a_nr
);
1527 aml_append(pkg
, aml_int(i
));
1528 aml_append(pkg
, aml_name("%s", s
));
1529 aml_append(pkg
, aml_int(0));
1530 aml_append(ctx
, pkg
);
1535 static Aml
*build_q35_routing_table(const char *str
)
1539 char *name
= g_strdup_printf("%s ", str
);
1541 pkg
= aml_package(128);
1542 for (i
= 0; i
< 0x18; i
++) {
1543 name
[3] = 'E' + (i
& 0x3);
1544 append_q35_prt_entry(pkg
, i
, name
);
1548 append_q35_prt_entry(pkg
, 0x18, name
);
1550 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1551 for (i
= 0x0019; i
< 0x1e; i
++) {
1553 append_q35_prt_entry(pkg
, i
, name
);
1556 /* PCIe->PCI bridge. use PIRQ[E-H] */
1558 append_q35_prt_entry(pkg
, 0x1e, name
);
1560 append_q35_prt_entry(pkg
, 0x1f, name
);
1566 static void build_q35_pci0_int(Aml
*table
)
1570 Aml
*sb_scope
= aml_scope("_SB");
1571 Aml
*pci0_scope
= aml_scope("PCI0");
1573 /* Zero => PIC mode, One => APIC Mode */
1574 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1575 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1577 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1579 aml_append(table
, method
);
1581 aml_append(pci0_scope
,
1582 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1583 aml_append(pci0_scope
,
1584 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1586 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1591 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1593 /* Note: we provide the same info as the PCI routing
1594 table of the Bochs BIOS */
1595 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1596 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1597 aml_append(method
, if_ctx
);
1598 else_ctx
= aml_else();
1599 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1600 aml_append(method
, else_ctx
);
1602 aml_append(pci0_scope
, method
);
1603 aml_append(sb_scope
, pci0_scope
);
1605 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1606 aml_append(field
, aml_named_field("PRQA", 8));
1607 aml_append(field
, aml_named_field("PRQB", 8));
1608 aml_append(field
, aml_named_field("PRQC", 8));
1609 aml_append(field
, aml_named_field("PRQD", 8));
1610 aml_append(field
, aml_reserved_field(0x20));
1611 aml_append(field
, aml_named_field("PRQE", 8));
1612 aml_append(field
, aml_named_field("PRQF", 8));
1613 aml_append(field
, aml_named_field("PRQG", 8));
1614 aml_append(field
, aml_named_field("PRQH", 8));
1615 aml_append(sb_scope
, field
);
1617 aml_append(sb_scope
, build_irq_status_method());
1618 aml_append(sb_scope
, build_iqcr_method(false));
1620 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1621 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1622 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1623 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1624 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1625 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1626 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1627 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1629 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1630 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1631 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1632 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1633 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1634 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1635 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1636 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1638 aml_append(table
, sb_scope
);
1641 static void build_q35_isa_bridge(Aml
*table
)
1647 scope
= aml_scope("_SB.PCI0");
1648 dev
= aml_device("ISA");
1649 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1651 /* ICH9 PCI to ISA irq remapping */
1652 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1653 aml_int(0x60), 0x0C));
1655 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1656 aml_int(0x80), 0x02));
1657 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1658 aml_append(field
, aml_named_field("COMA", 3));
1659 aml_append(field
, aml_reserved_field(1));
1660 aml_append(field
, aml_named_field("COMB", 3));
1661 aml_append(field
, aml_reserved_field(1));
1662 aml_append(field
, aml_named_field("LPTD", 2));
1663 aml_append(dev
, field
);
1665 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1666 aml_int(0x82), 0x02));
1668 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1669 aml_append(field
, aml_named_field("CAEN", 1));
1670 aml_append(field
, aml_named_field("CBEN", 1));
1671 aml_append(field
, aml_named_field("LPEN", 1));
1672 aml_append(dev
, field
);
1674 aml_append(scope
, dev
);
1675 aml_append(table
, scope
);
1678 static void build_piix4_pm(Aml
*table
)
1683 scope
= aml_scope("_SB.PCI0");
1684 dev
= aml_device("PX13");
1685 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1687 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1688 aml_int(0x00), 0xff));
1689 aml_append(scope
, dev
);
1690 aml_append(table
, scope
);
1693 static void build_piix4_isa_bridge(Aml
*table
)
1699 scope
= aml_scope("_SB.PCI0");
1700 dev
= aml_device("ISA");
1701 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1703 /* PIIX PCI to ISA irq remapping */
1704 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1705 aml_int(0x60), 0x04));
1707 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1708 /* Offset(0x5f),, 7, */
1709 aml_append(field
, aml_reserved_field(0x2f8));
1710 aml_append(field
, aml_reserved_field(7));
1711 aml_append(field
, aml_named_field("LPEN", 1));
1712 /* Offset(0x67),, 3, */
1713 aml_append(field
, aml_reserved_field(0x38));
1714 aml_append(field
, aml_reserved_field(3));
1715 aml_append(field
, aml_named_field("CAEN", 1));
1716 aml_append(field
, aml_reserved_field(3));
1717 aml_append(field
, aml_named_field("CBEN", 1));
1718 aml_append(dev
, field
);
1720 aml_append(scope
, dev
);
1721 aml_append(table
, scope
);
1724 static void build_piix4_pci_hotplug(Aml
*table
)
1730 scope
= aml_scope("_SB.PCI0");
1733 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1734 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1735 aml_append(field
, aml_named_field("PCIU", 32));
1736 aml_append(field
, aml_named_field("PCID", 32));
1737 aml_append(scope
, field
);
1740 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1741 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1742 aml_append(field
, aml_named_field("B0EJ", 32));
1743 aml_append(scope
, field
);
1746 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1747 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1748 aml_append(field
, aml_named_field("BNUM", 32));
1749 aml_append(scope
, field
);
1751 aml_append(scope
, aml_mutex("BLCK", 0));
1753 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1754 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1755 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1757 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1758 aml_append(method
, aml_release(aml_name("BLCK")));
1759 aml_append(method
, aml_return(aml_int(0)));
1760 aml_append(scope
, method
);
1762 aml_append(table
, scope
);
1765 static Aml
*build_q35_osc_method(void)
1771 Aml
*a_cwd1
= aml_name("CDW1");
1772 Aml
*a_ctrl
= aml_local(0);
1774 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1775 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1777 if_ctx
= aml_if(aml_equal(
1778 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1779 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1780 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1782 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1785 * Always allow native PME, AER (no dependencies)
1786 * Allow SHPC (PCI bridges can have SHPC controller)
1788 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1F), a_ctrl
));
1790 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1791 /* Unknown revision */
1792 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1793 aml_append(if_ctx
, if_ctx2
);
1795 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1796 /* Capabilities bits were masked */
1797 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1798 aml_append(if_ctx
, if_ctx2
);
1800 /* Update DWORD3 in the buffer */
1801 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1802 aml_append(method
, if_ctx
);
1804 else_ctx
= aml_else();
1805 /* Unrecognized UUID */
1806 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1807 aml_append(method
, else_ctx
);
1809 aml_append(method
, aml_return(aml_arg(3)));
1813 static void build_smb0(Aml
*table
, I2CBus
*smbus
, int devnr
, int func
)
1815 Aml
*scope
= aml_scope("_SB.PCI0");
1816 Aml
*dev
= aml_device("SMB0");
1818 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0005")));
1819 aml_append(dev
, aml_name_decl("_ADR", aml_int(devnr
<< 16 | func
)));
1820 build_acpi_ipmi_devices(dev
, BUS(smbus
), "\\_SB.PCI0.SMB0");
1821 aml_append(scope
, dev
);
1822 aml_append(table
, scope
);
1826 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1827 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1828 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1830 CrsRangeEntry
*entry
;
1831 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1832 CrsRangeSet crs_range_set
;
1833 PCMachineState
*pcms
= PC_MACHINE(machine
);
1834 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1835 X86MachineState
*x86ms
= X86_MACHINE(machine
);
1837 uint32_t nr_mem
= machine
->ram_slots
;
1838 int root_bus_limit
= 0xFF;
1840 TPMIf
*tpm
= tpm_find();
1843 dsdt
= init_aml_allocator();
1845 /* Reserve space for header */
1846 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1848 build_dbg_aml(dsdt
);
1849 if (misc
->is_piix4
) {
1850 sb_scope
= aml_scope("_SB");
1851 dev
= aml_device("PCI0");
1852 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1853 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1854 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1855 aml_append(sb_scope
, dev
);
1856 aml_append(dsdt
, sb_scope
);
1858 build_hpet_aml(dsdt
);
1859 build_piix4_pm(dsdt
);
1860 build_piix4_isa_bridge(dsdt
);
1861 build_isa_devices_aml(dsdt
);
1862 build_piix4_pci_hotplug(dsdt
);
1863 build_piix4_pci0_int(dsdt
);
1865 sb_scope
= aml_scope("_SB");
1866 dev
= aml_device("PCI0");
1867 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1868 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1869 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1870 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1871 aml_append(dev
, build_q35_osc_method());
1872 aml_append(sb_scope
, dev
);
1873 aml_append(dsdt
, sb_scope
);
1875 build_hpet_aml(dsdt
);
1876 build_q35_isa_bridge(dsdt
);
1877 build_isa_devices_aml(dsdt
);
1878 build_q35_pci0_int(dsdt
);
1879 if (pcms
->smbus
&& !pcmc
->do_not_add_smb_acpi
) {
1880 build_smb0(dsdt
, pcms
->smbus
, ICH9_SMB_DEV
, ICH9_SMB_FUNC
);
1884 if (pcmc
->legacy_cpu_hotplug
) {
1885 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1887 CPUHotplugFeatures opts
= {
1888 .acpi_1_compatible
= true, .has_legacy_cphp
= true
1890 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
1891 "\\_SB.PCI0", "\\_GPE._E02");
1894 if (pcms
->memhp_io_base
&& nr_mem
) {
1895 build_memory_hotplug_aml(dsdt
, nr_mem
, "\\_SB.PCI0",
1896 "\\_GPE._E03", AML_SYSTEM_IO
,
1897 pcms
->memhp_io_base
);
1900 scope
= aml_scope("_GPE");
1902 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1904 if (misc
->is_piix4
) {
1905 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1907 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1908 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1909 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1910 aml_append(scope
, method
);
1913 if (machine
->nvdimms_state
->is_enabled
) {
1914 method
= aml_method("_E04", 0, AML_NOTSERIALIZED
);
1915 aml_append(method
, aml_notify(aml_name("\\_SB.NVDR"),
1917 aml_append(scope
, method
);
1920 aml_append(dsdt
, scope
);
1922 crs_range_set_init(&crs_range_set
);
1923 bus
= PC_MACHINE(machine
)->bus
;
1925 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1926 uint8_t bus_num
= pci_bus_num(bus
);
1927 uint8_t numa_node
= pci_bus_numa_node(bus
);
1929 /* look only for expander root buses */
1930 if (!pci_bus_is_root(bus
)) {
1934 if (bus_num
< root_bus_limit
) {
1935 root_bus_limit
= bus_num
- 1;
1938 scope
= aml_scope("\\_SB");
1939 dev
= aml_device("PC%.02X", bus_num
);
1940 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1941 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1942 if (pci_bus_is_express(bus
)) {
1943 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1944 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1945 aml_append(dev
, build_q35_osc_method());
1947 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1950 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1951 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
1954 aml_append(dev
, build_prt(false));
1955 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
);
1956 aml_append(dev
, aml_name_decl("_CRS", crs
));
1957 aml_append(scope
, dev
);
1958 aml_append(dsdt
, scope
);
1963 * At this point crs_range_set has all the ranges used by pci
1964 * busses *other* than PCI0. These ranges will be excluded from
1965 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1968 if (acpi_get_mcfg(&mcfg
)) {
1969 crs_range_insert(crs_range_set
.mem_ranges
,
1970 mcfg
.base
, mcfg
.base
+ mcfg
.size
- 1);
1973 scope
= aml_scope("\\_SB.PCI0");
1974 /* build PCI0._CRS */
1975 crs
= aml_resource_template();
1977 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1978 0x0000, 0x0, root_bus_limit
,
1979 0x0000, root_bus_limit
+ 1));
1980 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
1983 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1984 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1985 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1987 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
1988 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
1989 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
1991 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1992 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1993 0x0000, entry
->base
, entry
->limit
,
1994 0x0000, entry
->limit
- entry
->base
+ 1));
1998 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1999 AML_CACHEABLE
, AML_READ_WRITE
,
2000 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2002 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
2003 range_lob(pci_hole
),
2004 range_upb(pci_hole
));
2005 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
2006 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
2008 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2009 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2010 0, entry
->base
, entry
->limit
,
2011 0, entry
->limit
- entry
->base
+ 1));
2014 if (!range_is_empty(pci_hole64
)) {
2015 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
2016 range_lob(pci_hole64
),
2017 range_upb(pci_hole64
));
2018 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
2019 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
2021 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
2023 AML_CACHEABLE
, AML_READ_WRITE
,
2024 0, entry
->base
, entry
->limit
,
2025 0, entry
->limit
- entry
->base
+ 1));
2029 if (TPM_IS_TIS(tpm_find())) {
2030 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2031 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2033 aml_append(scope
, aml_name_decl("_CRS", crs
));
2035 /* reserve GPE0 block resources */
2036 dev
= aml_device("GPE0");
2037 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2038 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2039 /* device present, functioning, decoding, not shown in UI */
2040 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2041 crs
= aml_resource_template();
2045 pm
->fadt
.gpe0_blk
.address
,
2046 pm
->fadt
.gpe0_blk
.address
,
2048 pm
->fadt
.gpe0_blk
.bit_width
/ 8)
2050 aml_append(dev
, aml_name_decl("_CRS", crs
));
2051 aml_append(scope
, dev
);
2053 crs_range_set_free(&crs_range_set
);
2055 /* reserve PCIHP resources */
2056 if (pm
->pcihp_io_len
) {
2057 dev
= aml_device("PHPR");
2058 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2060 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2061 /* device present, functioning, decoding, not shown in UI */
2062 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2063 crs
= aml_resource_template();
2065 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2068 aml_append(dev
, aml_name_decl("_CRS", crs
));
2069 aml_append(scope
, dev
);
2071 aml_append(dsdt
, scope
);
2073 /* create S3_ / S4_ / S5_ packages if necessary */
2074 scope
= aml_scope("\\");
2075 if (!pm
->s3_disabled
) {
2076 pkg
= aml_package(4);
2077 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2078 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2079 aml_append(pkg
, aml_int(0)); /* reserved */
2080 aml_append(pkg
, aml_int(0)); /* reserved */
2081 aml_append(scope
, aml_name_decl("_S3", pkg
));
2084 if (!pm
->s4_disabled
) {
2085 pkg
= aml_package(4);
2086 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2087 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2088 aml_append(pkg
, aml_int(pm
->s4_val
));
2089 aml_append(pkg
, aml_int(0)); /* reserved */
2090 aml_append(pkg
, aml_int(0)); /* reserved */
2091 aml_append(scope
, aml_name_decl("_S4", pkg
));
2094 pkg
= aml_package(4);
2095 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2096 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2097 aml_append(pkg
, aml_int(0)); /* reserved */
2098 aml_append(pkg
, aml_int(0)); /* reserved */
2099 aml_append(scope
, aml_name_decl("_S5", pkg
));
2100 aml_append(dsdt
, scope
);
2102 /* create fw_cfg node, unconditionally */
2104 /* when using port i/o, the 8-bit data register *always* overlaps
2105 * with half of the 16-bit control register. Hence, the total size
2106 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2107 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2108 uint8_t io_size
= object_property_get_bool(OBJECT(x86ms
->fw_cfg
),
2109 "dma_enabled", NULL
) ?
2110 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2113 scope
= aml_scope("\\_SB.PCI0");
2114 dev
= aml_device("FWCF");
2116 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2118 /* device present, functioning, decoding, not shown in UI */
2119 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2121 crs
= aml_resource_template();
2123 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2125 aml_append(dev
, aml_name_decl("_CRS", crs
));
2127 aml_append(scope
, dev
);
2128 aml_append(dsdt
, scope
);
2131 if (misc
->applesmc_io_base
) {
2132 scope
= aml_scope("\\_SB.PCI0.ISA");
2133 dev
= aml_device("SMC");
2135 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2136 /* device present, functioning, decoding, not shown in UI */
2137 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2139 crs
= aml_resource_template();
2141 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2142 0x01, APPLESMC_MAX_DATA_LENGTH
)
2144 aml_append(crs
, aml_irq_no_flags(6));
2145 aml_append(dev
, aml_name_decl("_CRS", crs
));
2147 aml_append(scope
, dev
);
2148 aml_append(dsdt
, scope
);
2151 if (misc
->pvpanic_port
) {
2152 scope
= aml_scope("\\_SB.PCI0.ISA");
2154 dev
= aml_device("PEVT");
2155 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2157 crs
= aml_resource_template();
2159 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2161 aml_append(dev
, aml_name_decl("_CRS", crs
));
2163 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2164 aml_int(misc
->pvpanic_port
), 1));
2165 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2166 aml_append(field
, aml_named_field("PEPT", 8));
2167 aml_append(dev
, field
);
2169 /* device present, functioning, decoding, shown in UI */
2170 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2172 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2173 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2174 aml_append(method
, aml_return(aml_local(0)));
2175 aml_append(dev
, method
);
2177 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2178 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2179 aml_append(dev
, method
);
2181 aml_append(scope
, dev
);
2182 aml_append(dsdt
, scope
);
2185 sb_scope
= aml_scope("\\_SB");
2190 pci_host
= acpi_get_i386_pci_host();
2192 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2196 Aml
*scope
= aml_scope("PCI0");
2197 /* Scan all PCI buses. Generate tables to support hotplug. */
2198 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2200 if (TPM_IS_TIS(tpm
)) {
2201 if (misc
->tpm_version
== TPM_VERSION_2_0
) {
2202 dev
= aml_device("TPM");
2203 aml_append(dev
, aml_name_decl("_HID",
2204 aml_string("MSFT0101")));
2206 dev
= aml_device("ISA.TPM");
2207 aml_append(dev
, aml_name_decl("_HID",
2208 aml_eisaid("PNP0C31")));
2211 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2212 crs
= aml_resource_template();
2213 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2214 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2216 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2217 Rewrite to take IRQ from TPM device model and
2218 fix default IRQ value there to use some unused IRQ
2220 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2221 aml_append(dev
, aml_name_decl("_CRS", crs
));
2223 tpm_build_ppi_acpi(tpm
, dev
);
2225 aml_append(scope
, dev
);
2228 aml_append(sb_scope
, scope
);
2232 if (TPM_IS_CRB(tpm
)) {
2233 dev
= aml_device("TPM");
2234 aml_append(dev
, aml_name_decl("_HID", aml_string("MSFT0101")));
2235 crs
= aml_resource_template();
2236 aml_append(crs
, aml_memory32_fixed(TPM_CRB_ADDR_BASE
,
2237 TPM_CRB_ADDR_SIZE
, AML_READ_WRITE
));
2238 aml_append(dev
, aml_name_decl("_CRS", crs
));
2240 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
2241 aml_append(method
, aml_return(aml_int(0x0f)));
2242 aml_append(dev
, method
);
2244 tpm_build_ppi_acpi(tpm
, dev
);
2246 aml_append(sb_scope
, dev
);
2249 aml_append(dsdt
, sb_scope
);
2251 /* copy AML table into ACPI tables blob and patch header there */
2252 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2253 build_header(linker
, table_data
,
2254 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2255 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2256 free_aml_allocator();
2260 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2264 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2265 /* Note timer_block_id value must be kept in sync with value advertised by
2268 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2269 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2270 build_header(linker
, table_data
,
2271 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2275 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2277 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2278 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2279 unsigned log_addr_offset
=
2280 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2282 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2283 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2284 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2286 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2287 false /* high memory */);
2289 /* log area start address to be filled by Guest linker */
2290 bios_linker_loader_add_pointer(linker
,
2291 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2292 ACPI_BUILD_TPMLOG_FILE
, 0);
2294 build_header(linker
, table_data
,
2295 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2299 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2301 Acpi20TPM2
*tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2302 unsigned log_addr_size
= sizeof(tpm2_ptr
->log_area_start_address
);
2303 unsigned log_addr_offset
=
2304 (char *)&tpm2_ptr
->log_area_start_address
- table_data
->data
;
2306 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2307 if (TPM_IS_TIS(tpm_find())) {
2308 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2309 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2310 } else if (TPM_IS_CRB(tpm_find())) {
2311 tpm2_ptr
->control_area_address
= cpu_to_le64(TPM_CRB_ADDR_CTRL
);
2312 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_CRB
);
2314 g_warn_if_reached();
2317 tpm2_ptr
->log_area_minimum_length
=
2318 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2320 /* log area start address to be filled by Guest linker */
2321 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
2322 log_addr_offset
, log_addr_size
,
2323 ACPI_BUILD_TPMLOG_FILE
, 0);
2324 build_header(linker
, table_data
,
2325 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2328 #define HOLE_640K_START (640 * KiB)
2329 #define HOLE_640K_END (1 * MiB)
2332 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2334 AcpiSystemResourceAffinityTable
*srat
;
2335 AcpiSratMemoryAffinity
*numamem
;
2338 int srat_start
, numa_start
, slots
;
2339 uint64_t mem_len
, mem_base
, next_base
;
2340 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2341 X86MachineState
*x86ms
= X86_MACHINE(machine
);
2342 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2343 PCMachineState
*pcms
= PC_MACHINE(machine
);
2344 ram_addr_t hotplugabble_address_space_size
=
2345 object_property_get_int(OBJECT(pcms
), PC_MACHINE_DEVMEM_REGION_SIZE
,
2348 srat_start
= table_data
->len
;
2350 srat
= acpi_data_push(table_data
, sizeof *srat
);
2351 srat
->reserved1
= cpu_to_le32(1);
2353 for (i
= 0; i
< apic_ids
->len
; i
++) {
2354 int node_id
= apic_ids
->cpus
[i
].props
.node_id
;
2355 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
2357 if (apic_id
< 255) {
2358 AcpiSratProcessorAffinity
*core
;
2360 core
= acpi_data_push(table_data
, sizeof *core
);
2361 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2362 core
->length
= sizeof(*core
);
2363 core
->local_apic_id
= apic_id
;
2364 core
->proximity_lo
= node_id
;
2365 memset(core
->proximity_hi
, 0, 3);
2366 core
->local_sapic_eid
= 0;
2367 core
->flags
= cpu_to_le32(1);
2369 AcpiSratProcessorX2ApicAffinity
*core
;
2371 core
= acpi_data_push(table_data
, sizeof *core
);
2372 core
->type
= ACPI_SRAT_PROCESSOR_x2APIC
;
2373 core
->length
= sizeof(*core
);
2374 core
->x2apic_id
= cpu_to_le32(apic_id
);
2375 core
->proximity_domain
= cpu_to_le32(node_id
);
2376 core
->flags
= cpu_to_le32(1);
2381 /* the memory map is a bit tricky, it contains at least one hole
2382 * from 640k-1M and possibly another one from 3.5G-4G.
2385 numa_start
= table_data
->len
;
2387 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2388 mem_base
= next_base
;
2389 mem_len
= pcms
->node_mem
[i
- 1];
2390 next_base
= mem_base
+ mem_len
;
2392 /* Cut out the 640K hole */
2393 if (mem_base
<= HOLE_640K_START
&&
2394 next_base
> HOLE_640K_START
) {
2395 mem_len
-= next_base
- HOLE_640K_START
;
2397 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2398 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2399 MEM_AFFINITY_ENABLED
);
2402 /* Check for the rare case: 640K < RAM < 1M */
2403 if (next_base
<= HOLE_640K_END
) {
2404 next_base
= HOLE_640K_END
;
2407 mem_base
= HOLE_640K_END
;
2408 mem_len
= next_base
- HOLE_640K_END
;
2411 /* Cut out the ACPI_PCI hole */
2412 if (mem_base
<= x86ms
->below_4g_mem_size
&&
2413 next_base
> x86ms
->below_4g_mem_size
) {
2414 mem_len
-= next_base
- x86ms
->below_4g_mem_size
;
2416 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2417 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2418 MEM_AFFINITY_ENABLED
);
2420 mem_base
= 1ULL << 32;
2421 mem_len
= next_base
- x86ms
->below_4g_mem_size
;
2422 next_base
= mem_base
+ mem_len
;
2426 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2427 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2428 MEM_AFFINITY_ENABLED
);
2431 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2432 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2433 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2434 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2438 * Entry is required for Windows to enable memory hotplug in OS
2439 * and for Linux to enable SWIOTLB when booted with less than
2440 * 4G of RAM. Windows works better if the entry sets proximity
2441 * to the highest NUMA node in the machine.
2442 * Memory devices may override proximity set by this entry,
2443 * providing _PXM method if necessary.
2445 if (hotplugabble_address_space_size
) {
2446 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2447 build_srat_memory(numamem
, machine
->device_memory
->base
,
2448 hotplugabble_address_space_size
, pcms
->numa_nodes
- 1,
2449 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2452 build_header(linker
, table_data
,
2453 (void *)(table_data
->data
+ srat_start
),
2455 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2459 * VT-d spec 8.1 DMA Remapping Reporting Structure
2460 * (version Oct. 2014 or later)
2463 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2465 int dmar_start
= table_data
->len
;
2467 AcpiTableDmar
*dmar
;
2468 AcpiDmarHardwareUnit
*drhd
;
2469 AcpiDmarRootPortATS
*atsr
;
2470 uint8_t dmar_flags
= 0;
2471 X86IOMMUState
*iommu
= x86_iommu_get_default();
2472 AcpiDmarDeviceScope
*scope
= NULL
;
2473 /* Root complex IOAPIC use one path[0] only */
2474 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
2475 IntelIOMMUState
*intel_iommu
= INTEL_IOMMU_DEVICE(iommu
);
2478 if (x86_iommu_ir_supported(iommu
)) {
2479 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2482 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2483 dmar
->host_address_width
= intel_iommu
->aw_bits
- 1;
2484 dmar
->flags
= dmar_flags
;
2486 /* DMAR Remapping Hardware Unit Definition structure */
2487 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
2488 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2489 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
2490 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2491 drhd
->pci_segment
= cpu_to_le16(0);
2492 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2494 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2495 * 8.3.1 (version Oct. 2014 or later). */
2496 scope
= &drhd
->scope
[0];
2497 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
2498 scope
->length
= ioapic_scope_size
;
2499 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
2500 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
2501 scope
->path
[0].device
= PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC
);
2502 scope
->path
[0].function
= PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC
);
2504 if (iommu
->dt_supported
) {
2505 atsr
= acpi_data_push(table_data
, sizeof(*atsr
));
2506 atsr
->type
= cpu_to_le16(ACPI_DMAR_TYPE_ATSR
);
2507 atsr
->length
= cpu_to_le16(sizeof(*atsr
));
2508 atsr
->flags
= ACPI_DMAR_ATSR_ALL_PORTS
;
2509 atsr
->pci_segment
= cpu_to_le16(0);
2512 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2513 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2516 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2517 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2519 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2522 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2523 * necessary for the PCI topology.
2526 insert_ivhd(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
2528 GArray
*table_data
= opaque
;
2531 /* "Select" IVHD entry, type 0x2 */
2532 entry
= PCI_BUILD_BDF(pci_bus_num(bus
), dev
->devfn
) << 8 | 0x2;
2533 build_append_int_noprefix(table_data
, entry
, 4);
2535 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_BRIDGE
)) {
2536 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
2537 uint8_t sec
= pci_bus_num(sec_bus
);
2538 uint8_t sub
= dev
->config
[PCI_SUBORDINATE_BUS
];
2540 if (pci_bus_is_express(sec_bus
)) {
2542 * Walk the bus if there are subordinates, otherwise use a range
2543 * to cover an entire leaf bus. We could potentially also use a
2544 * range for traversed buses, but we'd need to take care not to
2545 * create both Select and Range entries covering the same device.
2546 * This is easier and potentially more compact.
2548 * An example bare metal system seems to use Select entries for
2549 * root ports without a slot (ie. built-ins) and Range entries
2550 * when there is a slot. The same system also only hard-codes
2551 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2552 * making no effort to support nested bridges. We attempt to
2553 * be more thorough here.
2555 if (sec
== sub
) { /* leaf bus */
2556 /* "Start of Range" IVHD entry, type 0x3 */
2557 entry
= PCI_BUILD_BDF(sec
, PCI_DEVFN(0, 0)) << 8 | 0x3;
2558 build_append_int_noprefix(table_data
, entry
, 4);
2559 /* "End of Range" IVHD entry, type 0x4 */
2560 entry
= PCI_BUILD_BDF(sub
, PCI_DEVFN(31, 7)) << 8 | 0x4;
2561 build_append_int_noprefix(table_data
, entry
, 4);
2563 pci_for_each_device(sec_bus
, sec
, insert_ivhd
, table_data
);
2567 * If the secondary bus is conventional, then we need to create an
2568 * Alias range for everything downstream. The range covers the
2569 * first devfn on the secondary bus to the last devfn on the
2570 * subordinate bus. The alias target depends on legacy versus
2571 * express bridges, just as in pci_device_iommu_address_space().
2572 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2574 uint16_t dev_id_a
, dev_id_b
;
2576 dev_id_a
= PCI_BUILD_BDF(sec
, PCI_DEVFN(0, 0));
2578 if (pci_is_express(dev
) &&
2579 pcie_cap_get_type(dev
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2580 dev_id_b
= dev_id_a
;
2582 dev_id_b
= PCI_BUILD_BDF(pci_bus_num(bus
), dev
->devfn
);
2585 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2586 build_append_int_noprefix(table_data
, dev_id_a
<< 8 | 0x43, 4);
2587 build_append_int_noprefix(table_data
, dev_id_b
<< 8 | 0x0, 4);
2589 /* "End of Range" IVHD entry, type 0x4 */
2590 entry
= PCI_BUILD_BDF(sub
, PCI_DEVFN(31, 7)) << 8 | 0x4;
2591 build_append_int_noprefix(table_data
, entry
, 4);
2596 /* For all PCI host bridges, walk and insert IVHD entries */
2598 ivrs_host_bridges(Object
*obj
, void *opaque
)
2600 GArray
*ivhd_blob
= opaque
;
2602 if (object_dynamic_cast(obj
, TYPE_PCI_HOST_BRIDGE
)) {
2603 PCIBus
*bus
= PCI_HOST_BRIDGE(obj
)->bus
;
2606 pci_for_each_device(bus
, pci_bus_num(bus
), insert_ivhd
, ivhd_blob
);
2614 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
)
2616 int ivhd_table_len
= 24;
2617 int iommu_start
= table_data
->len
;
2618 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2619 GArray
*ivhd_blob
= g_array_new(false, true, 1);
2622 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2623 /* IVinfo - IO virtualization information common to all
2624 * IOMMU units in a system
2626 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2628 build_append_int_noprefix(table_data
, 0, 8);
2630 /* IVHD definition - type 10h */
2631 build_append_int_noprefix(table_data
, 0x10, 1);
2632 /* virtualization flags */
2633 build_append_int_noprefix(table_data
,
2634 (1UL << 0) | /* HtTunEn */
2635 (1UL << 4) | /* iotblSup */
2636 (1UL << 6) | /* PrefSup */
2637 (1UL << 7), /* PPRSup */
2641 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2642 * complete set of IVHD entries. Do this into a separate blob so that we
2643 * can calculate the total IVRS table length here and then append the new
2644 * blob further below. Fall back to an entry covering all devices, which
2645 * is sufficient when no aliases are present.
2647 object_child_foreach_recursive(object_get_root(),
2648 ivrs_host_bridges
, ivhd_blob
);
2650 if (!ivhd_blob
->len
) {
2652 * Type 1 device entry reporting all devices
2653 * These are 4-byte device entries currently reporting the range of
2654 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2656 build_append_int_noprefix(ivhd_blob
, 0x0000001, 4);
2659 ivhd_table_len
+= ivhd_blob
->len
;
2662 * When interrupt remapping is supported, we add a special IVHD device
2665 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2666 ivhd_table_len
+= 8;
2670 build_append_int_noprefix(table_data
, ivhd_table_len
, 2);
2672 build_append_int_noprefix(table_data
, s
->devid
, 2);
2673 /* Capability offset */
2674 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2675 /* IOMMU base address */
2676 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2677 /* PCI Segment Group */
2678 build_append_int_noprefix(table_data
, 0, 2);
2680 build_append_int_noprefix(table_data
, 0, 2);
2681 /* IOMMU Feature Reporting */
2682 build_append_int_noprefix(table_data
,
2683 (48UL << 30) | /* HATS */
2684 (48UL << 28) | /* GATS */
2685 (1UL << 2) | /* GTSup */
2686 (1UL << 6), /* GASup */
2689 /* IVHD entries as found above */
2690 g_array_append_vals(table_data
, ivhd_blob
->data
, ivhd_blob
->len
);
2691 g_array_free(ivhd_blob
, TRUE
);
2694 * Add a special IVHD device type.
2695 * Refer to spec - Table 95: IVHD device entry type codes
2697 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2698 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2700 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2701 build_append_int_noprefix(table_data
,
2702 (0x1ull
<< 56) | /* type IOAPIC */
2703 (IOAPIC_SB_DEVID
<< 40) | /* IOAPIC devid */
2704 0x48, /* special device */
2708 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2709 "IVRS", table_data
->len
- iommu_start
, 1, NULL
, NULL
);
2713 struct AcpiBuildState
{
2714 /* Copy of table in RAM (for patching). */
2715 MemoryRegion
*table_mr
;
2716 /* Is table patched? */
2719 MemoryRegion
*rsdp_mr
;
2720 MemoryRegion
*linker_mr
;
2723 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2728 pci_host
= acpi_get_i386_pci_host();
2731 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2735 mcfg
->base
= qnum_get_uint(qobject_to(QNum
, o
));
2737 if (mcfg
->base
== PCIE_BASE_ADDR_UNMAPPED
) {
2741 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2743 mcfg
->size
= qnum_get_uint(qobject_to(QNum
, o
));
2749 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2751 PCMachineState
*pcms
= PC_MACHINE(machine
);
2752 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2753 X86MachineState
*x86ms
= X86_MACHINE(machine
);
2754 GArray
*table_offsets
;
2755 unsigned facs
, dsdt
, rsdt
, fadt
;
2759 Range pci_hole
, pci_hole64
;
2762 GArray
*tables_blob
= tables
->table_data
;
2763 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2764 Object
*vmgenid_dev
;
2766 acpi_get_pm_info(machine
, &pm
);
2767 acpi_get_misc_info(&misc
);
2768 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2769 acpi_get_slic_oem(&slic_oem
);
2771 table_offsets
= g_array_new(false, true /* clear */,
2773 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2775 bios_linker_loader_alloc(tables
->linker
,
2776 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2777 64 /* Ensure FACS is aligned */,
2778 false /* high memory */);
2781 * FACS is pointed to by FADT.
2782 * We place it first since it's the only table that has alignment
2785 facs
= tables_blob
->len
;
2786 build_facs(tables_blob
);
2788 /* DSDT is pointed to by FADT */
2789 dsdt
= tables_blob
->len
;
2790 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2791 &pci_hole
, &pci_hole64
, machine
);
2793 /* Count the size of the DSDT and SSDT, we will need it for legacy
2794 * sizing of ACPI tables.
2796 aml_len
+= tables_blob
->len
- dsdt
;
2798 /* ACPI tables pointed to by RSDT */
2799 fadt
= tables_blob
->len
;
2800 acpi_add_table(table_offsets
, tables_blob
);
2801 pm
.fadt
.facs_tbl_offset
= &facs
;
2802 pm
.fadt
.dsdt_tbl_offset
= &dsdt
;
2803 pm
.fadt
.xdsdt_tbl_offset
= &dsdt
;
2804 build_fadt(tables_blob
, tables
->linker
, &pm
.fadt
,
2805 slic_oem
.id
, slic_oem
.table_id
);
2806 aml_len
+= tables_blob
->len
- fadt
;
2808 acpi_add_table(table_offsets
, tables_blob
);
2809 build_madt(tables_blob
, tables
->linker
, pcms
);
2811 vmgenid_dev
= find_vmgenid_dev();
2813 acpi_add_table(table_offsets
, tables_blob
);
2814 vmgenid_build_acpi(VMGENID(vmgenid_dev
), tables_blob
,
2815 tables
->vmgenid
, tables
->linker
);
2818 if (misc
.has_hpet
) {
2819 acpi_add_table(table_offsets
, tables_blob
);
2820 build_hpet(tables_blob
, tables
->linker
);
2822 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2823 acpi_add_table(table_offsets
, tables_blob
);
2824 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2826 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2827 acpi_add_table(table_offsets
, tables_blob
);
2828 build_tpm2(tables_blob
, tables
->linker
, tables
->tcpalog
);
2831 if (pcms
->numa_nodes
) {
2832 acpi_add_table(table_offsets
, tables_blob
);
2833 build_srat(tables_blob
, tables
->linker
, machine
);
2834 if (machine
->numa_state
->have_numa_distance
) {
2835 acpi_add_table(table_offsets
, tables_blob
);
2836 build_slit(tables_blob
, tables
->linker
, machine
);
2839 if (acpi_get_mcfg(&mcfg
)) {
2840 acpi_add_table(table_offsets
, tables_blob
);
2841 build_mcfg(tables_blob
, tables
->linker
, &mcfg
);
2843 if (x86_iommu_get_default()) {
2844 IommuType IOMMUType
= x86_iommu_get_type();
2845 if (IOMMUType
== TYPE_AMD
) {
2846 acpi_add_table(table_offsets
, tables_blob
);
2847 build_amd_iommu(tables_blob
, tables
->linker
);
2848 } else if (IOMMUType
== TYPE_INTEL
) {
2849 acpi_add_table(table_offsets
, tables_blob
);
2850 build_dmar_q35(tables_blob
, tables
->linker
);
2853 if (machine
->nvdimms_state
->is_enabled
) {
2854 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2855 machine
->nvdimms_state
, machine
->ram_slots
);
2858 /* Add tables supplied by user (if any) */
2859 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2860 unsigned len
= acpi_table_len(u
);
2862 acpi_add_table(table_offsets
, tables_blob
);
2863 g_array_append_vals(tables_blob
, u
, len
);
2866 /* RSDT is pointed to by RSDP */
2867 rsdt
= tables_blob
->len
;
2868 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2869 slic_oem
.id
, slic_oem
.table_id
);
2871 /* RSDP is in FSEG memory, so allocate it separately */
2873 AcpiRsdpData rsdp_data
= {
2875 .oem_id
= ACPI_BUILD_APPNAME6
,
2876 .xsdt_tbl_offset
= NULL
,
2877 .rsdt_tbl_offset
= &rsdt
,
2879 build_rsdp(tables
->rsdp
, tables
->linker
, &rsdp_data
);
2880 if (!pcmc
->rsdp_in_ram
) {
2881 /* We used to allocate some extra space for RSDP revision 2 but
2882 * only used the RSDP revision 0 space. The extra bytes were
2883 * zeroed out and not used.
2884 * Here we continue wasting those extra 16 bytes to make sure we
2885 * don't break migration for machine types 2.2 and older due to
2886 * RSDP blob size mismatch.
2888 build_append_int_noprefix(tables
->rsdp
, 0, 16);
2892 /* We'll expose it all to Guest so we want to reduce
2893 * chance of size changes.
2895 * We used to align the tables to 4k, but of course this would
2896 * too simple to be enough. 4k turned out to be too small an
2897 * alignment very soon, and in fact it is almost impossible to
2898 * keep the table size stable for all (max_cpus, max_memory_slots)
2899 * combinations. So the table size is always 64k for pc-i440fx-2.1
2900 * and we give an error if the table grows beyond that limit.
2902 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2903 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2904 * than 2.0 and we can always pad the smaller tables with zeros. We can
2905 * then use the exact size of the 2.0 tables.
2907 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2909 if (pcmc
->legacy_acpi_table_size
) {
2910 /* Subtracting aml_len gives the size of fixed tables. Then add the
2911 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2913 int legacy_aml_len
=
2914 pcmc
->legacy_acpi_table_size
+
2915 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* x86ms
->apic_id_limit
;
2916 int legacy_table_size
=
2917 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2918 ACPI_BUILD_ALIGN_SIZE
);
2919 if (tables_blob
->len
> legacy_table_size
) {
2920 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2921 warn_report("ACPI table size %u exceeds %d bytes,"
2922 " migration may not work",
2923 tables_blob
->len
, legacy_table_size
);
2924 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2925 " or PCI bridges.");
2927 g_array_set_size(tables_blob
, legacy_table_size
);
2929 /* Make sure we have a buffer in case we need to resize the tables. */
2930 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2931 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2932 warn_report("ACPI table size %u exceeds %d bytes,"
2933 " migration may not work",
2934 tables_blob
->len
, ACPI_BUILD_TABLE_SIZE
/ 2);
2935 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2936 " or PCI bridges.");
2938 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2941 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2943 /* Cleanup memory that's no longer used. */
2944 g_array_free(table_offsets
, true);
2947 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2949 uint32_t size
= acpi_data_len(data
);
2951 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2952 memory_region_ram_resize(mr
, size
, &error_abort
);
2954 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2955 memory_region_set_dirty(mr
, 0, size
);
2958 static void acpi_build_update(void *build_opaque
)
2960 AcpiBuildState
*build_state
= build_opaque
;
2961 AcpiBuildTables tables
;
2963 /* No state to update or already patched? Nothing to do. */
2964 if (!build_state
|| build_state
->patched
) {
2967 build_state
->patched
= 1;
2969 acpi_build_tables_init(&tables
);
2971 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2973 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2975 if (build_state
->rsdp
) {
2976 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2978 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2981 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2982 acpi_build_tables_cleanup(&tables
, true);
2985 static void acpi_build_reset(void *build_opaque
)
2987 AcpiBuildState
*build_state
= build_opaque
;
2988 build_state
->patched
= 0;
2991 static const VMStateDescription vmstate_acpi_build
= {
2992 .name
= "acpi_build",
2994 .minimum_version_id
= 1,
2995 .fields
= (VMStateField
[]) {
2996 VMSTATE_UINT8(patched
, AcpiBuildState
),
2997 VMSTATE_END_OF_LIST()
3001 void acpi_setup(void)
3003 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
3004 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
3005 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
3006 AcpiBuildTables tables
;
3007 AcpiBuildState
*build_state
;
3008 Object
*vmgenid_dev
;
3010 static FwCfgTPMConfig tpm_config
;
3012 if (!x86ms
->fw_cfg
) {
3013 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
3017 if (!pcms
->acpi_build_enabled
) {
3018 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
3022 if (!acpi_enabled
) {
3023 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
3027 build_state
= g_malloc0(sizeof *build_state
);
3029 acpi_build_tables_init(&tables
);
3030 acpi_build(&tables
, MACHINE(pcms
));
3032 /* Now expose it all to Guest */
3033 build_state
->table_mr
= acpi_add_rom_blob(acpi_build_update
,
3034 build_state
, tables
.table_data
,
3035 ACPI_BUILD_TABLE_FILE
,
3036 ACPI_BUILD_TABLE_MAX_SIZE
);
3037 assert(build_state
->table_mr
!= NULL
);
3039 build_state
->linker_mr
=
3040 acpi_add_rom_blob(acpi_build_update
, build_state
,
3041 tables
.linker
->cmd_blob
, "etc/table-loader", 0);
3043 fw_cfg_add_file(x86ms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
3044 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
3047 if (tpm
&& object_property_get_bool(OBJECT(tpm
), "ppi", &error_abort
)) {
3048 tpm_config
= (FwCfgTPMConfig
) {
3049 .tpmppi_address
= cpu_to_le32(TPM_PPI_ADDR_BASE
),
3050 .tpm_version
= tpm_get_version(tpm
),
3051 .tpmppi_version
= TPM_PPI_VERSION_1_30
3053 fw_cfg_add_file(x86ms
->fw_cfg
, "etc/tpm/config",
3054 &tpm_config
, sizeof tpm_config
);
3057 vmgenid_dev
= find_vmgenid_dev();
3059 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev
), x86ms
->fw_cfg
,
3063 if (!pcmc
->rsdp_in_ram
) {
3065 * Keep for compatibility with old machine types.
3066 * Though RSDP is small, its contents isn't immutable, so
3067 * we'll update it along with the rest of tables on guest access.
3069 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
3071 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
3072 fw_cfg_add_file_callback(x86ms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
3073 acpi_build_update
, NULL
, build_state
,
3074 build_state
->rsdp
, rsdp_size
, true);
3075 build_state
->rsdp_mr
= NULL
;
3077 build_state
->rsdp
= NULL
;
3078 build_state
->rsdp_mr
= acpi_add_rom_blob(acpi_build_update
,
3079 build_state
, tables
.rsdp
,
3080 ACPI_BUILD_RSDP_FILE
, 0);
3083 qemu_register_reset(acpi_build_reset
, build_state
);
3084 acpi_build_reset(build_state
);
3085 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
3087 /* Cleanup tables but don't free the memory: we track it
3090 acpi_build_tables_cleanup(&tables
, false);