vfio/pci: Cleanup ATI 0x3c3 quirk
[qemu/ar7.git] / target-s390x / cpu.h
blob9aeb0241fb167194823ee6cedeb58b1ca234fe9d
1 /*
2 * S/390 virtual CPU header
4 * Copyright (c) 2009 Ulrich Hecht
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #ifndef CPU_S390X_H
23 #define CPU_S390X_H
25 #include "config.h"
26 #include "qemu-common.h"
28 #define TARGET_LONG_BITS 64
30 #define ELF_MACHINE EM_S390
31 #define ELF_MACHINE_UNAME "S390X"
33 #define CPUArchState struct CPUS390XState
35 #include "exec/cpu-defs.h"
36 #define TARGET_PAGE_BITS 12
38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
41 #include "exec/cpu-all.h"
43 #include "fpu/softfloat.h"
45 #define NB_MMU_MODES 3
47 #define MMU_MODE0_SUFFIX _primary
48 #define MMU_MODE1_SUFFIX _secondary
49 #define MMU_MODE2_SUFFIX _home
51 #define MMU_USER_IDX 0
53 #define MAX_EXT_QUEUE 16
54 #define MAX_IO_QUEUE 16
55 #define MAX_MCHK_QUEUE 16
57 #define PSW_MCHK_MASK 0x0004000000000000
58 #define PSW_IO_MASK 0x0200000000000000
60 typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63 } PSW;
65 typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69 } ExtQueue;
71 typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76 } IOIntQueue;
78 typedef struct MchkQueue {
79 uint16_t type;
80 } MchkQueue;
82 typedef struct CPUS390XState {
83 uint64_t regs[16]; /* GP registers */
85 * The floating point registers are part of the vector registers.
86 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
88 CPU_DoubleU vregs[32][2]; /* vector registers */
89 uint32_t aregs[16]; /* access registers */
91 uint32_t fpc; /* floating-point control register */
92 uint32_t cc_op;
94 float_status fpu_status; /* passed to softfloat lib */
96 /* The low part of a 128-bit return, or remainder of a divide. */
97 uint64_t retxl;
99 PSW psw;
101 uint64_t cc_src;
102 uint64_t cc_dst;
103 uint64_t cc_vr;
105 uint64_t __excp_addr;
106 uint64_t psa;
108 uint32_t int_pgm_code;
109 uint32_t int_pgm_ilen;
111 uint32_t int_svc_code;
112 uint32_t int_svc_ilen;
114 uint64_t per_address;
115 uint16_t per_perc_atmid;
117 uint64_t cregs[16]; /* control registers */
119 ExtQueue ext_queue[MAX_EXT_QUEUE];
120 IOIntQueue io_queue[MAX_IO_QUEUE][8];
121 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
123 int pending_int;
124 int ext_index;
125 int io_index[8];
126 int mchk_index;
128 uint64_t ckc;
129 uint64_t cputm;
130 uint32_t todpr;
132 uint64_t pfault_token;
133 uint64_t pfault_compare;
134 uint64_t pfault_select;
136 uint64_t gbea;
137 uint64_t pp;
139 CPU_COMMON
141 /* reset does memset(0) up to here */
143 uint32_t cpu_num;
144 uint32_t machine_type;
146 uint64_t tod_offset;
147 uint64_t tod_basetime;
148 QEMUTimer *tod_timer;
150 QEMUTimer *cpu_timer;
153 * The cpu state represents the logical state of a cpu. In contrast to other
154 * architectures, there is a difference between a halt and a stop on s390.
155 * If all cpus are either stopped (including check stop) or in the disabled
156 * wait state, the vm can be shut down.
158 #define CPU_STATE_UNINITIALIZED 0x00
159 #define CPU_STATE_STOPPED 0x01
160 #define CPU_STATE_CHECK_STOP 0x02
161 #define CPU_STATE_OPERATING 0x03
162 #define CPU_STATE_LOAD 0x04
163 uint8_t cpu_state;
165 /* currently processed sigp order */
166 uint8_t sigp_order;
168 } CPUS390XState;
170 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
172 return &cs->vregs[nr][0];
175 #include "cpu-qom.h"
176 #include <sysemu/kvm.h>
178 /* distinguish between 24 bit and 31 bit addressing */
179 #define HIGH_ORDER_BIT 0x80000000
181 /* Interrupt Codes */
182 /* Program Interrupts */
183 #define PGM_OPERATION 0x0001
184 #define PGM_PRIVILEGED 0x0002
185 #define PGM_EXECUTE 0x0003
186 #define PGM_PROTECTION 0x0004
187 #define PGM_ADDRESSING 0x0005
188 #define PGM_SPECIFICATION 0x0006
189 #define PGM_DATA 0x0007
190 #define PGM_FIXPT_OVERFLOW 0x0008
191 #define PGM_FIXPT_DIVIDE 0x0009
192 #define PGM_DEC_OVERFLOW 0x000a
193 #define PGM_DEC_DIVIDE 0x000b
194 #define PGM_HFP_EXP_OVERFLOW 0x000c
195 #define PGM_HFP_EXP_UNDERFLOW 0x000d
196 #define PGM_HFP_SIGNIFICANCE 0x000e
197 #define PGM_HFP_DIVIDE 0x000f
198 #define PGM_SEGMENT_TRANS 0x0010
199 #define PGM_PAGE_TRANS 0x0011
200 #define PGM_TRANS_SPEC 0x0012
201 #define PGM_SPECIAL_OP 0x0013
202 #define PGM_OPERAND 0x0015
203 #define PGM_TRACE_TABLE 0x0016
204 #define PGM_SPACE_SWITCH 0x001c
205 #define PGM_HFP_SQRT 0x001d
206 #define PGM_PC_TRANS_SPEC 0x001f
207 #define PGM_AFX_TRANS 0x0020
208 #define PGM_ASX_TRANS 0x0021
209 #define PGM_LX_TRANS 0x0022
210 #define PGM_EX_TRANS 0x0023
211 #define PGM_PRIM_AUTH 0x0024
212 #define PGM_SEC_AUTH 0x0025
213 #define PGM_ALET_SPEC 0x0028
214 #define PGM_ALEN_SPEC 0x0029
215 #define PGM_ALE_SEQ 0x002a
216 #define PGM_ASTE_VALID 0x002b
217 #define PGM_ASTE_SEQ 0x002c
218 #define PGM_EXT_AUTH 0x002d
219 #define PGM_STACK_FULL 0x0030
220 #define PGM_STACK_EMPTY 0x0031
221 #define PGM_STACK_SPEC 0x0032
222 #define PGM_STACK_TYPE 0x0033
223 #define PGM_STACK_OP 0x0034
224 #define PGM_ASCE_TYPE 0x0038
225 #define PGM_REG_FIRST_TRANS 0x0039
226 #define PGM_REG_SEC_TRANS 0x003a
227 #define PGM_REG_THIRD_TRANS 0x003b
228 #define PGM_MONITOR 0x0040
229 #define PGM_PER 0x0080
230 #define PGM_CRYPTO 0x0119
232 /* External Interrupts */
233 #define EXT_INTERRUPT_KEY 0x0040
234 #define EXT_CLOCK_COMP 0x1004
235 #define EXT_CPU_TIMER 0x1005
236 #define EXT_MALFUNCTION 0x1200
237 #define EXT_EMERGENCY 0x1201
238 #define EXT_EXTERNAL_CALL 0x1202
239 #define EXT_ETR 0x1406
240 #define EXT_SERVICE 0x2401
241 #define EXT_VIRTIO 0x2603
243 /* PSW defines */
244 #undef PSW_MASK_PER
245 #undef PSW_MASK_DAT
246 #undef PSW_MASK_IO
247 #undef PSW_MASK_EXT
248 #undef PSW_MASK_KEY
249 #undef PSW_SHIFT_KEY
250 #undef PSW_MASK_MCHECK
251 #undef PSW_MASK_WAIT
252 #undef PSW_MASK_PSTATE
253 #undef PSW_MASK_ASC
254 #undef PSW_MASK_CC
255 #undef PSW_MASK_PM
256 #undef PSW_MASK_64
257 #undef PSW_MASK_32
258 #undef PSW_MASK_ESA_ADDR
260 #define PSW_MASK_PER 0x4000000000000000ULL
261 #define PSW_MASK_DAT 0x0400000000000000ULL
262 #define PSW_MASK_IO 0x0200000000000000ULL
263 #define PSW_MASK_EXT 0x0100000000000000ULL
264 #define PSW_MASK_KEY 0x00F0000000000000ULL
265 #define PSW_SHIFT_KEY 56
266 #define PSW_MASK_MCHECK 0x0004000000000000ULL
267 #define PSW_MASK_WAIT 0x0002000000000000ULL
268 #define PSW_MASK_PSTATE 0x0001000000000000ULL
269 #define PSW_MASK_ASC 0x0000C00000000000ULL
270 #define PSW_MASK_CC 0x0000300000000000ULL
271 #define PSW_MASK_PM 0x00000F0000000000ULL
272 #define PSW_MASK_64 0x0000000100000000ULL
273 #define PSW_MASK_32 0x0000000080000000ULL
274 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
276 #undef PSW_ASC_PRIMARY
277 #undef PSW_ASC_ACCREG
278 #undef PSW_ASC_SECONDARY
279 #undef PSW_ASC_HOME
281 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
282 #define PSW_ASC_ACCREG 0x0000400000000000ULL
283 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
284 #define PSW_ASC_HOME 0x0000C00000000000ULL
286 /* tb flags */
288 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
289 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
290 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
291 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
292 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
293 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
294 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
295 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
296 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
297 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
298 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
299 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
300 #define FLAG_MASK_32 0x00001000
302 /* Control register 0 bits */
303 #define CR0_LOWPROT 0x0000000010000000ULL
304 #define CR0_EDAT 0x0000000000800000ULL
306 /* MMU */
307 #define MMU_PRIMARY_IDX 0
308 #define MMU_SECONDARY_IDX 1
309 #define MMU_HOME_IDX 2
311 static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
313 switch (env->psw.mask & PSW_MASK_ASC) {
314 case PSW_ASC_PRIMARY:
315 return MMU_PRIMARY_IDX;
316 case PSW_ASC_SECONDARY:
317 return MMU_SECONDARY_IDX;
318 case PSW_ASC_HOME:
319 return MMU_HOME_IDX;
320 case PSW_ASC_ACCREG:
321 /* Fallthrough: access register mode is not yet supported */
322 default:
323 abort();
327 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
329 switch (mmu_idx) {
330 case MMU_PRIMARY_IDX:
331 return PSW_ASC_PRIMARY;
332 case MMU_SECONDARY_IDX:
333 return PSW_ASC_SECONDARY;
334 case MMU_HOME_IDX:
335 return PSW_ASC_HOME;
336 default:
337 abort();
341 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
342 target_ulong *cs_base, int *flags)
344 *pc = env->psw.addr;
345 *cs_base = 0;
346 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
347 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
350 /* While the PoO talks about ILC (a number between 1-3) what is actually
351 stored in LowCore is shifted left one bit (an even between 2-6). As
352 this is the actual length of the insn and therefore more useful, that
353 is what we want to pass around and manipulate. To make sure that we
354 have applied this distinction universally, rename the "ILC" to "ILEN". */
355 static inline int get_ilen(uint8_t opc)
357 switch (opc >> 6) {
358 case 0:
359 return 2;
360 case 1:
361 case 2:
362 return 4;
363 default:
364 return 6;
368 /* PER bits from control register 9 */
369 #define PER_CR9_EVENT_BRANCH 0x80000000
370 #define PER_CR9_EVENT_IFETCH 0x40000000
371 #define PER_CR9_EVENT_STORE 0x20000000
372 #define PER_CR9_EVENT_STORE_REAL 0x08000000
373 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
374 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
375 #define PER_CR9_CONTROL_ALTERATION 0x00200000
377 /* PER bits from the PER CODE/ATMID/AI in lowcore */
378 #define PER_CODE_EVENT_BRANCH 0x8000
379 #define PER_CODE_EVENT_IFETCH 0x4000
380 #define PER_CODE_EVENT_STORE 0x2000
381 #define PER_CODE_EVENT_STORE_REAL 0x0800
382 #define PER_CODE_EVENT_NULLIFICATION 0x0100
384 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
385 entry when a PER exception is triggered. */
386 static inline uint8_t get_per_atmid(CPUS390XState *env)
388 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
389 ( (1 << 6) ) |
390 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
391 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
392 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
393 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
396 /* Check if an address is within the PER starting address and the PER
397 ending address. The address range might loop. */
398 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
400 if (env->cregs[10] <= env->cregs[11]) {
401 return env->cregs[10] <= addr && addr <= env->cregs[11];
402 } else {
403 return env->cregs[10] <= addr || addr <= env->cregs[11];
407 #ifndef CONFIG_USER_ONLY
408 /* In several cases of runtime exceptions, we havn't recorded the true
409 instruction length. Use these codes when raising exceptions in order
410 to re-compute the length by examining the insn in memory. */
411 #define ILEN_LATER 0x20
412 #define ILEN_LATER_INC 0x21
413 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
414 #endif
416 S390CPU *cpu_s390x_init(const char *cpu_model);
417 void s390x_translate_init(void);
418 int cpu_s390x_exec(CPUState *cpu);
420 /* you can call this signal handler from your SIGBUS and SIGSEGV
421 signal handlers to inform the virtual CPU of exceptions. non zero
422 is returned if the signal was handled by the virtual CPU. */
423 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
424 void *puc);
425 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
426 int mmu_idx);
428 #include "ioinst.h"
431 #ifndef CONFIG_USER_ONLY
432 void do_restart_interrupt(CPUS390XState *env);
434 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
435 uint8_t *ar)
437 hwaddr addr = 0;
438 uint8_t reg;
440 reg = ipb >> 28;
441 if (reg > 0) {
442 addr = env->regs[reg];
444 addr += (ipb >> 16) & 0xfff;
445 if (ar) {
446 *ar = reg;
449 return addr;
452 /* Base/displacement are at the same locations. */
453 #define decode_basedisp_rs decode_basedisp_s
455 /* helper functions for run_on_cpu() */
456 static inline void s390_do_cpu_reset(void *arg)
458 CPUState *cs = arg;
459 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
461 scc->cpu_reset(cs);
463 static inline void s390_do_cpu_full_reset(void *arg)
465 CPUState *cs = arg;
467 cpu_reset(cs);
470 void s390x_tod_timer(void *opaque);
471 void s390x_cpu_timer(void *opaque);
473 int s390_virtio_hypercall(CPUS390XState *env);
474 void s390_virtio_irq(int config_change, uint64_t token);
476 #ifdef CONFIG_KVM
477 void kvm_s390_virtio_irq(int config_change, uint64_t token);
478 void kvm_s390_service_interrupt(uint32_t parm);
479 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
480 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
481 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
482 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
483 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
484 int len, bool is_write);
485 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
486 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
487 #else
488 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
491 static inline void kvm_s390_service_interrupt(uint32_t parm)
494 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
496 return -ENOSYS;
498 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
500 return -ENOSYS;
502 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
503 void *hostbuf, int len, bool is_write)
505 return -ENOSYS;
507 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
508 uint64_t te_code)
511 #endif
513 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
515 if (kvm_enabled()) {
516 return kvm_s390_get_clock(tod_high, tod_low);
518 /* Fixme TCG */
519 *tod_high = 0;
520 *tod_low = 0;
521 return 0;
524 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
526 if (kvm_enabled()) {
527 return kvm_s390_set_clock(tod_high, tod_low);
529 /* Fixme TCG */
530 return 0;
533 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
534 unsigned int s390_cpu_halt(S390CPU *cpu);
535 void s390_cpu_unhalt(S390CPU *cpu);
536 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
537 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
539 return cpu->env.cpu_state;
542 void gtod_save(QEMUFile *f, void *opaque);
543 int gtod_load(QEMUFile *f, void *opaque, int version_id);
545 /* service interrupts are floating therefore we must not pass an cpustate */
546 void s390_sclp_extint(uint32_t parm);
548 /* from s390-virtio-bus */
549 extern const hwaddr virtio_size;
551 #else
552 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
554 return 0;
557 static inline void s390_cpu_unhalt(S390CPU *cpu)
561 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
563 return 0;
565 #endif
566 void cpu_lock(void);
567 void cpu_unlock(void);
569 typedef struct SubchDev SubchDev;
571 #ifndef CONFIG_USER_ONLY
572 extern void io_subsystem_reset(void);
573 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
574 uint16_t schid);
575 bool css_subch_visible(SubchDev *sch);
576 void css_conditional_io_interrupt(SubchDev *sch);
577 int css_do_stsch(SubchDev *sch, SCHIB *schib);
578 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
579 int css_do_msch(SubchDev *sch, const SCHIB *schib);
580 int css_do_xsch(SubchDev *sch);
581 int css_do_csch(SubchDev *sch);
582 int css_do_hsch(SubchDev *sch);
583 int css_do_ssch(SubchDev *sch, ORB *orb);
584 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
585 void css_do_tsch_update_subch(SubchDev *sch);
586 int css_do_stcrw(CRW *crw);
587 void css_undo_stcrw(CRW *crw);
588 int css_do_tpi(IOIntCode *int_code, int lowcore);
589 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
590 int rfmt, void *buf);
591 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
592 int css_enable_mcsse(void);
593 int css_enable_mss(void);
594 int css_do_rsch(SubchDev *sch);
595 int css_do_rchp(uint8_t cssid, uint8_t chpid);
596 bool css_present(uint8_t cssid);
597 #endif
599 #define cpu_init(model) CPU(cpu_s390x_init(model))
600 #define cpu_exec cpu_s390x_exec
601 #define cpu_gen_code cpu_s390x_gen_code
602 #define cpu_signal_handler cpu_s390x_signal_handler
604 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
605 #define cpu_list s390_cpu_list
607 #include "exec/exec-all.h"
609 #define EXCP_EXT 1 /* external interrupt */
610 #define EXCP_SVC 2 /* supervisor call (syscall) */
611 #define EXCP_PGM 3 /* program interruption */
612 #define EXCP_IO 7 /* I/O interrupt */
613 #define EXCP_MCHK 8 /* machine check */
615 #define INTERRUPT_EXT (1 << 0)
616 #define INTERRUPT_TOD (1 << 1)
617 #define INTERRUPT_CPUTIMER (1 << 2)
618 #define INTERRUPT_IO (1 << 3)
619 #define INTERRUPT_MCHK (1 << 4)
621 /* Program Status Word. */
622 #define S390_PSWM_REGNUM 0
623 #define S390_PSWA_REGNUM 1
624 /* General Purpose Registers. */
625 #define S390_R0_REGNUM 2
626 #define S390_R1_REGNUM 3
627 #define S390_R2_REGNUM 4
628 #define S390_R3_REGNUM 5
629 #define S390_R4_REGNUM 6
630 #define S390_R5_REGNUM 7
631 #define S390_R6_REGNUM 8
632 #define S390_R7_REGNUM 9
633 #define S390_R8_REGNUM 10
634 #define S390_R9_REGNUM 11
635 #define S390_R10_REGNUM 12
636 #define S390_R11_REGNUM 13
637 #define S390_R12_REGNUM 14
638 #define S390_R13_REGNUM 15
639 #define S390_R14_REGNUM 16
640 #define S390_R15_REGNUM 17
641 /* Total Core Registers. */
642 #define S390_NUM_CORE_REGS 18
644 /* CC optimization */
646 enum cc_op {
647 CC_OP_CONST0 = 0, /* CC is 0 */
648 CC_OP_CONST1, /* CC is 1 */
649 CC_OP_CONST2, /* CC is 2 */
650 CC_OP_CONST3, /* CC is 3 */
652 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
653 CC_OP_STATIC, /* CC value is env->cc_op */
655 CC_OP_NZ, /* env->cc_dst != 0 */
656 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
657 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
658 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
659 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
660 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
661 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
663 CC_OP_ADD_64, /* overflow on add (64bit) */
664 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
665 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
666 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
667 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
668 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
669 CC_OP_ABS_64, /* sign eval on abs (64bit) */
670 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
672 CC_OP_ADD_32, /* overflow on add (32bit) */
673 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
674 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
675 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
676 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
677 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
678 CC_OP_ABS_32, /* sign eval on abs (64bit) */
679 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
681 CC_OP_COMP_32, /* complement */
682 CC_OP_COMP_64, /* complement */
684 CC_OP_TM_32, /* test under mask (32bit) */
685 CC_OP_TM_64, /* test under mask (64bit) */
687 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
688 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
689 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
691 CC_OP_ICM, /* insert characters under mask */
692 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
693 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
694 CC_OP_FLOGR, /* find leftmost one */
695 CC_OP_MAX
698 static const char *cc_names[] = {
699 [CC_OP_CONST0] = "CC_OP_CONST0",
700 [CC_OP_CONST1] = "CC_OP_CONST1",
701 [CC_OP_CONST2] = "CC_OP_CONST2",
702 [CC_OP_CONST3] = "CC_OP_CONST3",
703 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
704 [CC_OP_STATIC] = "CC_OP_STATIC",
705 [CC_OP_NZ] = "CC_OP_NZ",
706 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
707 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
708 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
709 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
710 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
711 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
712 [CC_OP_ADD_64] = "CC_OP_ADD_64",
713 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
714 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
715 [CC_OP_SUB_64] = "CC_OP_SUB_64",
716 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
717 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
718 [CC_OP_ABS_64] = "CC_OP_ABS_64",
719 [CC_OP_NABS_64] = "CC_OP_NABS_64",
720 [CC_OP_ADD_32] = "CC_OP_ADD_32",
721 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
722 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
723 [CC_OP_SUB_32] = "CC_OP_SUB_32",
724 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
725 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
726 [CC_OP_ABS_32] = "CC_OP_ABS_32",
727 [CC_OP_NABS_32] = "CC_OP_NABS_32",
728 [CC_OP_COMP_32] = "CC_OP_COMP_32",
729 [CC_OP_COMP_64] = "CC_OP_COMP_64",
730 [CC_OP_TM_32] = "CC_OP_TM_32",
731 [CC_OP_TM_64] = "CC_OP_TM_64",
732 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
733 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
734 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
735 [CC_OP_ICM] = "CC_OP_ICM",
736 [CC_OP_SLA_32] = "CC_OP_SLA_32",
737 [CC_OP_SLA_64] = "CC_OP_SLA_64",
738 [CC_OP_FLOGR] = "CC_OP_FLOGR",
741 static inline const char *cc_name(int cc_op)
743 return cc_names[cc_op];
746 static inline void setcc(S390CPU *cpu, uint64_t cc)
748 CPUS390XState *env = &cpu->env;
750 env->psw.mask &= ~(3ull << 44);
751 env->psw.mask |= (cc & 3) << 44;
752 env->cc_op = cc;
755 typedef struct LowCore
757 /* prefix area: defined by architecture */
758 uint32_t ccw1[2]; /* 0x000 */
759 uint32_t ccw2[4]; /* 0x008 */
760 uint8_t pad1[0x80-0x18]; /* 0x018 */
761 uint32_t ext_params; /* 0x080 */
762 uint16_t cpu_addr; /* 0x084 */
763 uint16_t ext_int_code; /* 0x086 */
764 uint16_t svc_ilen; /* 0x088 */
765 uint16_t svc_code; /* 0x08a */
766 uint16_t pgm_ilen; /* 0x08c */
767 uint16_t pgm_code; /* 0x08e */
768 uint32_t data_exc_code; /* 0x090 */
769 uint16_t mon_class_num; /* 0x094 */
770 uint16_t per_perc_atmid; /* 0x096 */
771 uint64_t per_address; /* 0x098 */
772 uint8_t exc_access_id; /* 0x0a0 */
773 uint8_t per_access_id; /* 0x0a1 */
774 uint8_t op_access_id; /* 0x0a2 */
775 uint8_t ar_access_id; /* 0x0a3 */
776 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
777 uint64_t trans_exc_code; /* 0x0a8 */
778 uint64_t monitor_code; /* 0x0b0 */
779 uint16_t subchannel_id; /* 0x0b8 */
780 uint16_t subchannel_nr; /* 0x0ba */
781 uint32_t io_int_parm; /* 0x0bc */
782 uint32_t io_int_word; /* 0x0c0 */
783 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
784 uint32_t stfl_fac_list; /* 0x0c8 */
785 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
786 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
787 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
788 uint32_t external_damage_code; /* 0x0f4 */
789 uint64_t failing_storage_address; /* 0x0f8 */
790 uint8_t pad6[0x110-0x100]; /* 0x100 */
791 uint64_t per_breaking_event_addr; /* 0x110 */
792 uint8_t pad7[0x120-0x118]; /* 0x118 */
793 PSW restart_old_psw; /* 0x120 */
794 PSW external_old_psw; /* 0x130 */
795 PSW svc_old_psw; /* 0x140 */
796 PSW program_old_psw; /* 0x150 */
797 PSW mcck_old_psw; /* 0x160 */
798 PSW io_old_psw; /* 0x170 */
799 uint8_t pad8[0x1a0-0x180]; /* 0x180 */
800 PSW restart_new_psw; /* 0x1a0 */
801 PSW external_new_psw; /* 0x1b0 */
802 PSW svc_new_psw; /* 0x1c0 */
803 PSW program_new_psw; /* 0x1d0 */
804 PSW mcck_new_psw; /* 0x1e0 */
805 PSW io_new_psw; /* 0x1f0 */
806 PSW return_psw; /* 0x200 */
807 uint8_t irb[64]; /* 0x210 */
808 uint64_t sync_enter_timer; /* 0x250 */
809 uint64_t async_enter_timer; /* 0x258 */
810 uint64_t exit_timer; /* 0x260 */
811 uint64_t last_update_timer; /* 0x268 */
812 uint64_t user_timer; /* 0x270 */
813 uint64_t system_timer; /* 0x278 */
814 uint64_t last_update_clock; /* 0x280 */
815 uint64_t steal_clock; /* 0x288 */
816 PSW return_mcck_psw; /* 0x290 */
817 uint8_t pad9[0xc00-0x2a0]; /* 0x2a0 */
818 /* System info area */
819 uint64_t save_area[16]; /* 0xc00 */
820 uint8_t pad10[0xd40-0xc80]; /* 0xc80 */
821 uint64_t kernel_stack; /* 0xd40 */
822 uint64_t thread_info; /* 0xd48 */
823 uint64_t async_stack; /* 0xd50 */
824 uint64_t kernel_asce; /* 0xd58 */
825 uint64_t user_asce; /* 0xd60 */
826 uint64_t panic_stack; /* 0xd68 */
827 uint64_t user_exec_asce; /* 0xd70 */
828 uint8_t pad11[0xdc0-0xd78]; /* 0xd78 */
830 /* SMP info area: defined by DJB */
831 uint64_t clock_comparator; /* 0xdc0 */
832 uint64_t ext_call_fast; /* 0xdc8 */
833 uint64_t percpu_offset; /* 0xdd0 */
834 uint64_t current_task; /* 0xdd8 */
835 uint32_t softirq_pending; /* 0xde0 */
836 uint32_t pad_0x0de4; /* 0xde4 */
837 uint64_t int_clock; /* 0xde8 */
838 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
840 /* 0xe00 is used as indicator for dump tools */
841 /* whether the kernel died with panic() or not */
842 uint32_t panic_magic; /* 0xe00 */
844 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
846 /* 64 bit extparam used for pfault, diag 250 etc */
847 uint64_t ext_params2; /* 0x11B8 */
849 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
851 /* System info area */
853 uint64_t floating_pt_save_area[16]; /* 0x1200 */
854 uint64_t gpregs_save_area[16]; /* 0x1280 */
855 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
856 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
857 uint32_t prefixreg_save_area; /* 0x1318 */
858 uint32_t fpt_creg_save_area; /* 0x131c */
859 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
860 uint32_t tod_progreg_save_area; /* 0x1324 */
861 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
862 uint32_t clock_comp_save_area[2]; /* 0x1330 */
863 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
864 uint32_t access_regs_save_area[16]; /* 0x1340 */
865 uint64_t cregs_save_area[16]; /* 0x1380 */
867 /* align to the top of the prefix area */
869 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
870 } QEMU_PACKED LowCore;
872 /* STSI */
873 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
874 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
875 #define STSI_LEVEL_1 0x0000000010000000ULL
876 #define STSI_LEVEL_2 0x0000000020000000ULL
877 #define STSI_LEVEL_3 0x0000000030000000ULL
878 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
879 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
880 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
881 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
883 /* Basic Machine Configuration */
884 struct sysib_111 {
885 uint32_t res1[8];
886 uint8_t manuf[16];
887 uint8_t type[4];
888 uint8_t res2[12];
889 uint8_t model[16];
890 uint8_t sequence[16];
891 uint8_t plant[4];
892 uint8_t res3[156];
895 /* Basic Machine CPU */
896 struct sysib_121 {
897 uint32_t res1[80];
898 uint8_t sequence[16];
899 uint8_t plant[4];
900 uint8_t res2[2];
901 uint16_t cpu_addr;
902 uint8_t res3[152];
905 /* Basic Machine CPUs */
906 struct sysib_122 {
907 uint8_t res1[32];
908 uint32_t capability;
909 uint16_t total_cpus;
910 uint16_t active_cpus;
911 uint16_t standby_cpus;
912 uint16_t reserved_cpus;
913 uint16_t adjustments[2026];
916 /* LPAR CPU */
917 struct sysib_221 {
918 uint32_t res1[80];
919 uint8_t sequence[16];
920 uint8_t plant[4];
921 uint16_t cpu_id;
922 uint16_t cpu_addr;
923 uint8_t res3[152];
926 /* LPAR CPUs */
927 struct sysib_222 {
928 uint32_t res1[32];
929 uint16_t lpar_num;
930 uint8_t res2;
931 uint8_t lcpuc;
932 uint16_t total_cpus;
933 uint16_t conf_cpus;
934 uint16_t standby_cpus;
935 uint16_t reserved_cpus;
936 uint8_t name[8];
937 uint32_t caf;
938 uint8_t res3[16];
939 uint16_t dedicated_cpus;
940 uint16_t shared_cpus;
941 uint8_t res4[180];
944 /* VM CPUs */
945 struct sysib_322 {
946 uint8_t res1[31];
947 uint8_t count;
948 struct {
949 uint8_t res2[4];
950 uint16_t total_cpus;
951 uint16_t conf_cpus;
952 uint16_t standby_cpus;
953 uint16_t reserved_cpus;
954 uint8_t name[8];
955 uint32_t caf;
956 uint8_t cpi[16];
957 uint8_t res5[3];
958 uint8_t ext_name_encoding;
959 uint32_t res3;
960 uint8_t uuid[16];
961 } vm[8];
962 uint8_t res4[1504];
963 uint8_t ext_names[8][256];
966 /* MMU defines */
967 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
968 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
969 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
970 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
971 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
972 #define _ASCE_REAL_SPACE 0x20 /* real space control */
973 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
974 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
975 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
976 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
977 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
978 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
980 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
981 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
982 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
983 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
984 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
985 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
986 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
987 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
988 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
990 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
991 #define _SEGMENT_ENTRY_FC 0x400 /* format control */
992 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
993 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
995 #define _PAGE_RO 0x200 /* HW read-only bit */
996 #define _PAGE_INVALID 0x400 /* HW invalid bit */
997 #define _PAGE_RES0 0x800 /* bit must be zero */
999 #define SK_C (0x1 << 1)
1000 #define SK_R (0x1 << 2)
1001 #define SK_F (0x1 << 3)
1002 #define SK_ACC_MASK (0xf << 4)
1004 /* SIGP order codes */
1005 #define SIGP_SENSE 0x01
1006 #define SIGP_EXTERNAL_CALL 0x02
1007 #define SIGP_EMERGENCY 0x03
1008 #define SIGP_START 0x04
1009 #define SIGP_STOP 0x05
1010 #define SIGP_RESTART 0x06
1011 #define SIGP_STOP_STORE_STATUS 0x09
1012 #define SIGP_INITIAL_CPU_RESET 0x0b
1013 #define SIGP_CPU_RESET 0x0c
1014 #define SIGP_SET_PREFIX 0x0d
1015 #define SIGP_STORE_STATUS_ADDR 0x0e
1016 #define SIGP_SET_ARCH 0x12
1017 #define SIGP_STORE_ADTL_STATUS 0x17
1019 /* SIGP condition codes */
1020 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1021 #define SIGP_CC_STATUS_STORED 1
1022 #define SIGP_CC_BUSY 2
1023 #define SIGP_CC_NOT_OPERATIONAL 3
1025 /* SIGP status bits */
1026 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1027 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1028 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1029 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1030 #define SIGP_STAT_STOPPED 0x00000040UL
1031 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1032 #define SIGP_STAT_CHECK_STOP 0x00000010UL
1033 #define SIGP_STAT_INOPERATIVE 0x00000004UL
1034 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
1035 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1037 /* SIGP SET ARCHITECTURE modes */
1038 #define SIGP_MODE_ESA_S390 0
1039 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1040 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1042 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1043 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1044 target_ulong *raddr, int *flags, bool exc);
1045 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1046 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1047 uint64_t vr);
1048 void s390_cpu_recompute_watchpoints(CPUState *cs);
1050 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1051 int len, bool is_write);
1053 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1054 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1055 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1056 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1057 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1058 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1060 /* The value of the TOD clock for 1.1.1970. */
1061 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1063 /* Converts ns to s390's clock format */
1064 static inline uint64_t time2tod(uint64_t ns) {
1065 return (ns << 9) / 125;
1068 /* Converts s390's clock format to ns */
1069 static inline uint64_t tod2time(uint64_t t) {
1070 return (t * 125) >> 9;
1073 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
1074 uint64_t param64)
1076 CPUS390XState *env = &cpu->env;
1078 if (env->ext_index == MAX_EXT_QUEUE - 1) {
1079 /* ugh - can't queue anymore. Let's drop. */
1080 return;
1083 env->ext_index++;
1084 assert(env->ext_index < MAX_EXT_QUEUE);
1086 env->ext_queue[env->ext_index].code = code;
1087 env->ext_queue[env->ext_index].param = param;
1088 env->ext_queue[env->ext_index].param64 = param64;
1090 env->pending_int |= INTERRUPT_EXT;
1091 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1094 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1095 uint16_t subchannel_number,
1096 uint32_t io_int_parm, uint32_t io_int_word)
1098 CPUS390XState *env = &cpu->env;
1099 int isc = IO_INT_WORD_ISC(io_int_word);
1101 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1102 /* ugh - can't queue anymore. Let's drop. */
1103 return;
1106 env->io_index[isc]++;
1107 assert(env->io_index[isc] < MAX_IO_QUEUE);
1109 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1110 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1111 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1112 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1114 env->pending_int |= INTERRUPT_IO;
1115 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1118 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1120 CPUS390XState *env = &cpu->env;
1122 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1123 /* ugh - can't queue anymore. Let's drop. */
1124 return;
1127 env->mchk_index++;
1128 assert(env->mchk_index < MAX_MCHK_QUEUE);
1130 env->mchk_queue[env->mchk_index].type = 1;
1132 env->pending_int |= INTERRUPT_MCHK;
1133 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1136 /* from s390-virtio-ccw */
1137 #define MEM_SECTION_SIZE 0x10000000UL
1138 #define MAX_AVAIL_SLOTS 32
1140 /* fpu_helper.c */
1141 uint32_t set_cc_nz_f32(float32 v);
1142 uint32_t set_cc_nz_f64(float64 v);
1143 uint32_t set_cc_nz_f128(float128 v);
1145 /* misc_helper.c */
1146 #ifndef CONFIG_USER_ONLY
1147 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1148 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1149 #endif
1150 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1151 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1152 uintptr_t retaddr);
1154 #ifdef CONFIG_KVM
1155 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1156 uint16_t subchannel_nr, uint32_t io_int_parm,
1157 uint32_t io_int_word);
1158 void kvm_s390_crw_mchk(void);
1159 void kvm_s390_enable_css_support(S390CPU *cpu);
1160 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1161 int vq, bool assign);
1162 int kvm_s390_cpu_restart(S390CPU *cpu);
1163 int kvm_s390_get_memslot_count(KVMState *s);
1164 void kvm_s390_clear_cmma_callback(void *opaque);
1165 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1166 void kvm_s390_reset_vcpu(S390CPU *cpu);
1167 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1168 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1169 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1170 #else
1171 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1172 uint16_t subchannel_nr,
1173 uint32_t io_int_parm,
1174 uint32_t io_int_word)
1177 static inline void kvm_s390_crw_mchk(void)
1180 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1183 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1184 uint32_t sch, int vq,
1185 bool assign)
1187 return -ENOSYS;
1189 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1191 return -ENOSYS;
1193 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1196 static inline int kvm_s390_get_memslot_count(KVMState *s)
1198 return MAX_AVAIL_SLOTS;
1200 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1202 return -ENOSYS;
1204 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1207 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1208 uint64_t *hw_limit)
1210 return 0;
1212 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1215 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1217 return 0;
1219 #endif
1221 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1223 if (kvm_enabled()) {
1224 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1226 return 0;
1229 static inline void cmma_reset(S390CPU *cpu)
1231 if (kvm_enabled()) {
1232 CPUState *cs = CPU(cpu);
1233 kvm_s390_clear_cmma_callback(cs->kvm_state);
1237 static inline int s390_cpu_restart(S390CPU *cpu)
1239 if (kvm_enabled()) {
1240 return kvm_s390_cpu_restart(cpu);
1242 return -ENOSYS;
1245 static inline int s390_get_memslot_count(KVMState *s)
1247 if (kvm_enabled()) {
1248 return kvm_s390_get_memslot_count(s);
1249 } else {
1250 return MAX_AVAIL_SLOTS;
1254 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1255 uint32_t io_int_parm, uint32_t io_int_word);
1256 void s390_crw_mchk(void);
1258 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1259 uint32_t sch_id, int vq,
1260 bool assign)
1262 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1265 #ifdef CONFIG_KVM
1266 static inline bool vregs_needed(void *opaque)
1268 if (kvm_enabled()) {
1269 return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
1271 return 0;
1273 #else
1274 static inline bool vregs_needed(void *opaque)
1276 return 0;
1278 #endif
1279 #endif