hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10 #include "hw/cpu/core.h"
  11 #include "hw/ppc/spapr_cpu_core.h"
  12 #include "target/ppc/cpu.h"
  13 #include "hw/ppc/spapr.h"
  14 #include "hw/boards.h"
  15 #include "qapi/error.h"
  16 #include "sysemu/cpus.h"
  17 #include "sysemu/kvm.h"
  18 #include "target/ppc/kvm_ppc.h"
  19 #include "hw/ppc/ppc.h"
  20 #include "target/ppc/mmu-hash64.h"
  21 #include "sysemu/numa.h"
  22 #include "sysemu/hw_accel.h"
  23 #include "qemu/error-report.h"
  24
  25 static void spapr_cpu_reset(void *opaque)
  26 {
  27     PowerPCCPU *cpu = opaque;
  28     CPUState *cs = CPU(cpu);
  29     CPUPPCState *env = &cpu->env;
  30     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  31     sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
  32     target_ulong lpcr;
  33
  34     cpu_reset(cs);
  35
  36     /* Set compatibility mode to match the boot CPU, which was either set
  37      * by the machine reset code or by CAS. This should never fail.
  38      */
  39     ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
  40
  41     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  42      * reset code and the rest are explicitly started up by the guest
  43      * using an RTAS call */
  44     cs->halted = 1;
  45
  46     env->spr[SPR_HIOR] = 0;
  47
  48     lpcr = env->spr[SPR_LPCR];
  49
  50     /* Set emulated LPCR to not send interrupts to hypervisor. Note that
  51      * under KVM, the actual HW LPCR will be set differently by KVM itself,
  52      * the settings below ensure proper operations with TCG in absence of
  53      * a real hypervisor.
  54      *
  55      * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
  56      * real mode accesses, which thankfully defaults to 0 and isn't
  57      * accessible in guest mode.
  58      *
  59      * Disable Power-saving mode Exit Cause exceptions for the CPU, so
  60      * we don't get spurious wakups before an RTAS start-cpu call.
  61      */
  62     lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
  63     lpcr |= LPCR_LPES0 | LPCR_LPES1;
  64
  65     /* Set RMLS to the max (ie, 16G) */
  66     lpcr &= ~LPCR_RMLS;
  67     lpcr |= 1ull << LPCR_RMLS_SHIFT;
  68
  69     ppc_store_lpcr(cpu, lpcr);
  70
  71     /* Set a full AMOR so guest can use the AMR as it sees fit */
  72     env->spr[SPR_AMOR] = 0xffffffffffffffffull;
  73
  74     spapr_cpu->vpa_addr = 0;
  75     spapr_cpu->slb_shadow_addr = 0;
  76     spapr_cpu->slb_shadow_size = 0;
  77     spapr_cpu->dtl_addr = 0;
  78     spapr_cpu->dtl_size = 0;
  79 }
  80
  81 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
  82 {
  83     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  84     CPUPPCState *env = &cpu->env;
  85
  86     env->nip = nip;
  87     env->gpr[3] = r3;
  88     CPU(cpu)->halted = 0;
  89     /* Enable Power-saving mode Exit Cause exceptions */
  90     ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
  91 }
  92
  93 /*
  94  * Return the sPAPR CPU core type for @model which essentially is the CPU
  95  * model specified with -cpu cmdline option.
  96  */
  97 const char *spapr_get_cpu_core_type(const char *cpu_type)
  98 {
  99     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
 100     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
 101                                       len, cpu_type);
 102     ObjectClass *oc = object_class_by_name(core_type);
 103
 104     g_free(core_type);
 105     if (!oc) {
 106         return NULL;
 107     }
 108
 109     return object_class_get_name(oc);
 110 }
 111
 112 static void spapr_unrealize_vcpu(PowerPCCPU *cpu)
 113 {
 114     qemu_unregister_reset(spapr_cpu_reset, cpu);
 115     object_unparent(cpu->intc);
 116     cpu_remove_sync(CPU(cpu));
 117     object_unparent(OBJECT(cpu));
 118 }
 119
 120 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
 121 {
 122     sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 123     CPUCore *cc = CPU_CORE(dev);
 124     int i;
 125
 126     for (i = 0; i < cc->nr_threads; i++) {
 127         spapr_unrealize_vcpu(sc->threads[i]);
 128     }
 129     g_free(sc->threads);
 130 }
 131
 132 static const VMStateDescription vmstate_spapr_cpu_state = {
 133     .name = "spapr_cpu",
 134     .version_id = 1,
 135     .minimum_version_id = 1,
 136     .fields = (VMStateField[]) {
 137         VMSTATE_END_OF_LIST()
 138     },
 139 };
 140
 141 static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 142                                Error **errp)
 143 {
 144     CPUPPCState *env = &cpu->env;
 145     Error *local_err = NULL;
 146
 147     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 148     if (local_err) {
 149         goto error;
 150     }
 151
 152     /* Set time-base frequency to 512 MHz */
 153     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
 154
 155     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
 156     kvmppc_set_papr(cpu);
 157
 158     qemu_register_reset(spapr_cpu_reset, cpu);
 159     spapr_cpu_reset(cpu);
 160
 161     cpu->intc = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
 162                            &local_err);
 163     if (local_err) {
 164         goto error_unregister;
 165     }
 166
 167     return;
 168
 169 error_unregister:
 170     qemu_unregister_reset(spapr_cpu_reset, cpu);
 171     cpu_remove_sync(CPU(cpu));
 172 error:
 173     error_propagate(errp, local_err);
 174 }
 175
 176 static PowerPCCPU *spapr_create_vcpu(sPAPRCPUCore *sc, int i, Error **errp)
 177 {
 178     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
 179     CPUCore *cc = CPU_CORE(sc);
 180     Object *obj;
 181     char *id;
 182     CPUState *cs;
 183     PowerPCCPU *cpu;
 184     Error *local_err = NULL;
 185
 186     obj = object_new(scc->cpu_type);
 187
 188     cs = CPU(obj);
 189     cpu = POWERPC_CPU(obj);
 190     cs->cpu_index = cc->core_id + i;
 191     spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
 192     if (local_err) {
 193         goto err;
 194     }
 195
 196     cpu->node_id = sc->node_id;
 197
 198     id = g_strdup_printf("thread[%d]", i);
 199     object_property_add_child(OBJECT(sc), id, obj, &local_err);
 200     g_free(id);
 201     if (local_err) {
 202         goto err;
 203     }
 204
 205     cpu->machine_data = g_new0(sPAPRCPUState, 1);
 206     if (!sc->pre_3_0_migration) {
 207         vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
 208                          cpu->machine_data);
 209     }
 210
 211     object_unref(obj);
 212     return cpu;
 213
 214 err:
 215     object_unref(obj);
 216     error_propagate(errp, local_err);
 217     return NULL;
 218 }
 219
 220 static void spapr_delete_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
 221 {
 222     sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
 223
 224     if (!sc->pre_3_0_migration) {
 225         vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
 226     }
 227     cpu->machine_data = NULL;
 228     g_free(spapr_cpu);
 229     object_unparent(OBJECT(cpu));
 230 }
 231
 232 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 233 {
 234     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 235      * tries to add a sPAPR CPU core to a non-pseries machine.
 236      */
 237     sPAPRMachineState *spapr =
 238         (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
 239                                                   TYPE_SPAPR_MACHINE);
 240     sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 241     CPUCore *cc = CPU_CORE(OBJECT(dev));
 242     Error *local_err = NULL;
 243     int i, j;
 244
 245     if (!spapr) {
 246         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 247         return;
 248     }
 249
 250     sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 251     for (i = 0; i < cc->nr_threads; i++) {
 252         sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
 253         if (local_err) {
 254             goto err;
 255         }
 256     }
 257
 258     for (j = 0; j < cc->nr_threads; j++) {
 259         spapr_realize_vcpu(sc->threads[j], spapr, &local_err);
 260         if (local_err) {
 261             goto err_unrealize;
 262         }
 263     }
 264     return;
 265
 266 err_unrealize:
 267     while (--j >= 0) {
 268         spapr_unrealize_vcpu(sc->threads[j]);
 269     }
 270 err:
 271     while (--i >= 0) {
 272         spapr_delete_vcpu(sc->threads[i], sc);
 273     }
 274     g_free(sc->threads);
 275     error_propagate(errp, local_err);
 276 }
 277
 278 static Property spapr_cpu_core_properties[] = {
 279     DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 280     DEFINE_PROP_BOOL("pre-3.0-migration", sPAPRCPUCore, pre_3_0_migration,
 281                      false),
 282     DEFINE_PROP_END_OF_LIST()
 283 };
 284
 285 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 286 {
 287     DeviceClass *dc = DEVICE_CLASS(oc);
 288     sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 289
 290     dc->realize = spapr_cpu_core_realize;
 291     dc->unrealize = spapr_cpu_core_unrealize;
 292     dc->props = spapr_cpu_core_properties;
 293     scc->cpu_type = data;
 294 }
 295
 296 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 297     {                                                   \
 298         .parent = TYPE_SPAPR_CPU_CORE,                  \
 299         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 300         .class_init = spapr_cpu_core_class_init,        \
 301         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 302     }
 303
 304 static const TypeInfo spapr_cpu_core_type_infos[] = {
 305     {
 306         .name = TYPE_SPAPR_CPU_CORE,
 307         .parent = TYPE_CPU_CORE,
 308         .abstract = true,
 309         .instance_size = sizeof(sPAPRCPUCore),
 310         .class_size = sizeof(sPAPRCPUCoreClass),
 311     },
 312     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 313     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 314     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 315     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 316     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 317     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 318     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 319     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 320     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 321     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 322     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 323 #ifdef CONFIG_KVM
 324     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 325 #endif
 326 };
 327
 328 DEFINE_TYPES(spapr_cpu_core_type_infos)