2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
34 #include "hw/fw-path-provider.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
41 #include "migration/misc.h"
42 #include "migration/global_state.h"
43 #include "migration/register.h"
44 #include "mmu-hash64.h"
45 #include "mmu-book3s-v3.h"
46 #include "cpu-models.h"
49 #include "hw/boards.h"
50 #include "hw/ppc/ppc.h"
51 #include "hw/loader.h"
53 #include "hw/ppc/fdt.h"
54 #include "hw/ppc/spapr.h"
55 #include "hw/ppc/spapr_vio.h"
56 #include "hw/pci-host/spapr.h"
57 #include "hw/ppc/xics.h"
58 #include "hw/pci/msi.h"
60 #include "hw/pci/pci.h"
61 #include "hw/scsi/scsi.h"
62 #include "hw/virtio/virtio-scsi.h"
63 #include "hw/virtio/vhost-scsi-common.h"
65 #include "exec/address-spaces.h"
67 #include "qemu/config-file.h"
68 #include "qemu/error-report.h"
71 #include "hw/intc/intc.h"
73 #include "hw/compat.h"
74 #include "qemu/cutils.h"
75 #include "hw/ppc/spapr_cpu_core.h"
76 #include "hw/mem/memory-device.h"
80 /* SLOF memory layout:
82 * SLOF raw image loaded at 0, copies its romfs right below the flat
83 * device-tree, then position SLOF itself 31M below that
85 * So we set FW_OVERHEAD to 40MB which should account for all of that
88 * We load our kernel at 4M, leaving space for SLOF initial image
90 #define FDT_MAX_SIZE 0x100000
91 #define RTAS_MAX_SIZE 0x10000
92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
93 #define FW_MAX_SIZE 0x400000
94 #define FW_FILE_NAME "slof.bin"
95 #define FW_OVERHEAD 0x2800000
96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
98 #define MIN_RMA_SLOF 128UL
100 #define PHANDLE_XICP 0x00001111
102 /* These two functions implement the VCPU id numbering: one to compute them
103 * all and one to identify thread 0 of a VCORE. Any change to the first one
104 * is likely to have an impact on the second one, so let's keep them close.
106 static int spapr_vcpu_id(sPAPRMachineState
*spapr
, int cpu_index
)
110 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState
*spapr
,
116 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
119 static ICSState
*spapr_ics_create(sPAPRMachineState
*spapr
,
120 const char *type_ics
,
121 int nr_irqs
, Error
**errp
)
123 Error
*local_err
= NULL
;
126 obj
= object_new(type_ics
);
127 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
128 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
130 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &local_err
);
134 object_property_set_bool(obj
, true, "realized", &local_err
);
139 return ICS_SIMPLE(obj
);
142 error_propagate(errp
, local_err
);
146 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
148 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
149 * and newer QEMUs don't even have them. In both cases, we don't want
150 * to send anything on the wire.
155 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
156 .name
= "icp/server",
158 .minimum_version_id
= 1,
159 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
160 .fields
= (VMStateField
[]) {
161 VMSTATE_UNUSED(4), /* uint32_t xirr */
162 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
163 VMSTATE_UNUSED(1), /* uint8_t mfrr */
164 VMSTATE_END_OF_LIST()
168 static void pre_2_10_vmstate_register_dummy_icp(int i
)
170 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
171 (void *)(uintptr_t) i
);
174 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
176 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
177 (void *)(uintptr_t) i
);
180 static int xics_max_server_number(sPAPRMachineState
*spapr
)
183 return DIV_ROUND_UP(max_cpus
* spapr
->vsmt
, smp_threads
);
186 static void xics_system_init(MachineState
*machine
, int nr_irqs
, Error
**errp
)
188 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
189 Error
*local_err
= NULL
;
192 if (machine_kernel_irqchip_allowed(machine
) &&
193 !xics_kvm_init(spapr
, &local_err
)) {
194 spapr
->icp_type
= TYPE_KVM_ICP
;
195 spapr
->ics
= spapr_ics_create(spapr
, TYPE_ICS_KVM
, nr_irqs
,
198 if (machine_kernel_irqchip_required(machine
) && !spapr
->ics
) {
199 error_prepend(&local_err
,
200 "kernel_irqchip requested but unavailable: ");
203 error_free(local_err
);
208 xics_spapr_init(spapr
);
209 spapr
->icp_type
= TYPE_ICP
;
210 spapr
->ics
= spapr_ics_create(spapr
, TYPE_ICS_SIMPLE
, nr_irqs
,
215 error_propagate(errp
, local_err
);
218 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
222 uint32_t servers_prop
[smt_threads
];
223 uint32_t gservers_prop
[smt_threads
* 2];
224 int index
= spapr_get_vcpu_id(cpu
);
226 if (cpu
->compat_pvr
) {
227 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
233 /* Build interrupt servers and gservers properties */
234 for (i
= 0; i
< smt_threads
; i
++) {
235 servers_prop
[i
] = cpu_to_be32(index
+ i
);
236 /* Hack, direct the group queues back to cpu 0 */
237 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
238 gservers_prop
[i
*2 + 1] = 0;
240 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
241 servers_prop
, sizeof(servers_prop
));
245 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
246 gservers_prop
, sizeof(gservers_prop
));
251 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
253 int index
= spapr_get_vcpu_id(cpu
);
254 uint32_t associativity
[] = {cpu_to_be32(0x5),
258 cpu_to_be32(cpu
->node_id
),
261 /* Advertise NUMA via ibm,associativity */
262 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
263 sizeof(associativity
));
266 /* Populate the "ibm,pa-features" property */
267 static void spapr_populate_pa_features(sPAPRMachineState
*spapr
,
269 void *fdt
, int offset
,
272 uint8_t pa_features_206
[] = { 6, 0,
273 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
274 uint8_t pa_features_207
[] = { 24, 0,
275 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
276 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
277 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
278 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
279 uint8_t pa_features_300
[] = { 66, 0,
280 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
281 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
282 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
284 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
286 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
287 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
288 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
289 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
290 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
291 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
292 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
293 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
294 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
295 /* 42: PM, 44: PC RA, 46: SC vec'd */
296 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
297 /* 48: SIMD, 50: QP BFP, 52: String */
298 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
299 /* 54: DecFP, 56: DecI, 58: SHA */
300 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
301 /* 60: NM atomic, 62: RNG */
302 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
304 uint8_t *pa_features
= NULL
;
307 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
308 pa_features
= pa_features_206
;
309 pa_size
= sizeof(pa_features_206
);
311 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
312 pa_features
= pa_features_207
;
313 pa_size
= sizeof(pa_features_207
);
315 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
316 pa_features
= pa_features_300
;
317 pa_size
= sizeof(pa_features_300
);
323 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
325 * Note: we keep CI large pages off by default because a 64K capable
326 * guest provisioned with large pages might otherwise try to map a qemu
327 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
328 * even if that qemu runs on a 4k host.
329 * We dd this bit back here if we are confident this is not an issue
331 pa_features
[3] |= 0x20;
333 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
334 pa_features
[24] |= 0x80; /* Transactional memory support */
336 if (legacy_guest
&& pa_size
> 40) {
337 /* Workaround for broken kernels that attempt (guest) radix
338 * mode when they can't handle it, if they see the radix bit set
339 * in pa-features. So hide it from them. */
340 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
343 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
346 static int spapr_fixup_cpu_dt(void *fdt
, sPAPRMachineState
*spapr
)
348 int ret
= 0, offset
, cpus_offset
;
351 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
354 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
355 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
356 int index
= spapr_get_vcpu_id(cpu
);
357 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
359 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
363 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
365 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
366 if (cpus_offset
< 0) {
367 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
368 if (cpus_offset
< 0) {
372 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
374 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
380 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
381 pft_size_prop
, sizeof(pft_size_prop
));
386 if (nb_numa_nodes
> 1) {
387 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
);
393 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
398 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
,
399 spapr
->cas_legacy_guest_workaround
);
404 static hwaddr
spapr_node0_size(MachineState
*machine
)
408 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
409 if (numa_info
[i
].node_mem
) {
410 return MIN(pow2floor(numa_info
[i
].node_mem
),
415 return machine
->ram_size
;
418 static void add_str(GString
*s
, const gchar
*s1
)
420 g_string_append_len(s
, s1
, strlen(s1
) + 1);
423 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
426 uint32_t associativity
[] = {
427 cpu_to_be32(0x4), /* length */
428 cpu_to_be32(0x0), cpu_to_be32(0x0),
429 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
432 uint64_t mem_reg_property
[2];
435 mem_reg_property
[0] = cpu_to_be64(start
);
436 mem_reg_property
[1] = cpu_to_be64(size
);
438 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
439 off
= fdt_add_subnode(fdt
, 0, mem_name
);
441 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
442 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
443 sizeof(mem_reg_property
))));
444 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
445 sizeof(associativity
))));
449 static int spapr_populate_memory(sPAPRMachineState
*spapr
, void *fdt
)
451 MachineState
*machine
= MACHINE(spapr
);
452 hwaddr mem_start
, node_size
;
453 int i
, nb_nodes
= nb_numa_nodes
;
454 NodeInfo
*nodes
= numa_info
;
457 /* No NUMA nodes, assume there is just one node with whole RAM */
458 if (!nb_numa_nodes
) {
460 ramnode
.node_mem
= machine
->ram_size
;
464 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
465 if (!nodes
[i
].node_mem
) {
468 if (mem_start
>= machine
->ram_size
) {
471 node_size
= nodes
[i
].node_mem
;
472 if (node_size
> machine
->ram_size
- mem_start
) {
473 node_size
= machine
->ram_size
- mem_start
;
477 /* spapr_machine_init() checks for rma_size <= node0_size
479 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
480 mem_start
+= spapr
->rma_size
;
481 node_size
-= spapr
->rma_size
;
483 for ( ; node_size
; ) {
484 hwaddr sizetmp
= pow2floor(node_size
);
486 /* mem_start != 0 here */
487 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
488 sizetmp
= 1ULL << ctzl(mem_start
);
491 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
492 node_size
-= sizetmp
;
493 mem_start
+= sizetmp
;
500 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
501 sPAPRMachineState
*spapr
)
503 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
504 CPUPPCState
*env
= &cpu
->env
;
505 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
506 int index
= spapr_get_vcpu_id(cpu
);
507 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
508 0xffffffff, 0xffffffff};
509 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
510 : SPAPR_TIMEBASE_FREQ
;
511 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
512 uint32_t page_sizes_prop
[64];
513 size_t page_sizes_prop_size
;
514 uint32_t vcpus_per_socket
= smp_threads
* smp_cores
;
515 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
516 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
517 sPAPRDRConnector
*drc
;
519 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
522 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
524 drc_index
= spapr_drc_index(drc
);
525 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
528 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
529 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
531 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
532 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
533 env
->dcache_line_size
)));
534 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
535 env
->dcache_line_size
)));
536 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
537 env
->icache_line_size
)));
538 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
539 env
->icache_line_size
)));
541 if (pcc
->l1_dcache_size
) {
542 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
543 pcc
->l1_dcache_size
)));
545 warn_report("Unknown L1 dcache size for cpu");
547 if (pcc
->l1_icache_size
) {
548 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
549 pcc
->l1_icache_size
)));
551 warn_report("Unknown L1 icache size for cpu");
554 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
555 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
556 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
557 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
558 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
559 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
561 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
562 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
565 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
566 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
567 segs
, sizeof(segs
))));
570 /* Advertise VSX (vector extensions) if available
571 * 1 == VMX / Altivec available
574 * Only CPUs for which we create core types in spapr_cpu_core.c
575 * are possible, and all of those have VMX */
576 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
577 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
579 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
582 /* Advertise DFP (Decimal Floating Point) if available
583 * 0 / no property == no DFP
584 * 1 == DFP available */
585 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
586 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
589 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
590 sizeof(page_sizes_prop
));
591 if (page_sizes_prop_size
) {
592 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
593 page_sizes_prop
, page_sizes_prop_size
)));
596 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
, false);
598 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
599 cs
->cpu_index
/ vcpus_per_socket
)));
601 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
602 pft_size_prop
, sizeof(pft_size_prop
))));
604 if (nb_numa_nodes
> 1) {
605 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
608 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
610 if (pcc
->radix_page_info
) {
611 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
612 radix_AP_encodings
[i
] =
613 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
615 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
617 pcc
->radix_page_info
->count
*
618 sizeof(radix_AP_encodings
[0]))));
622 static void spapr_populate_cpus_dt_node(void *fdt
, sPAPRMachineState
*spapr
)
628 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
630 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
631 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
634 * We walk the CPUs in reverse order to ensure that CPU DT nodes
635 * created by fdt_add_subnode() end up in the right order in FDT
636 * for the guest kernel the enumerate the CPUs correctly.
638 CPU_FOREACH_REVERSE(cs
) {
639 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
640 int index
= spapr_get_vcpu_id(cpu
);
641 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
644 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
648 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
649 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
652 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
657 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
659 MemoryDeviceInfoList
*info
;
661 for (info
= list
; info
; info
= info
->next
) {
662 MemoryDeviceInfo
*value
= info
->value
;
664 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
665 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
667 if (pcdimm_info
->addr
>= addr
&&
668 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
669 return pcdimm_info
->node
;
677 struct sPAPRDrconfCellV2
{
685 typedef struct DrconfCellQueue
{
686 struct sPAPRDrconfCellV2 cell
;
687 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
690 static DrconfCellQueue
*
691 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
692 uint32_t drc_index
, uint32_t aa_index
,
695 DrconfCellQueue
*elem
;
697 elem
= g_malloc0(sizeof(*elem
));
698 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
699 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
700 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
701 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
702 elem
->cell
.flags
= cpu_to_be32(flags
);
707 /* ibm,dynamic-memory-v2 */
708 static int spapr_populate_drmem_v2(sPAPRMachineState
*spapr
, void *fdt
,
709 int offset
, MemoryDeviceInfoList
*dimms
)
711 MachineState
*machine
= MACHINE(spapr
);
712 uint8_t *int_buf
, *cur_index
, buf_len
;
714 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
715 uint64_t addr
, cur_addr
, size
;
716 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
717 uint64_t mem_end
= machine
->device_memory
->base
+
718 memory_region_size(&machine
->device_memory
->mr
);
719 uint32_t node
, nr_entries
= 0;
720 sPAPRDRConnector
*drc
;
721 DrconfCellQueue
*elem
, *next
;
722 MemoryDeviceInfoList
*info
;
723 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
724 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
726 /* Entry to cover RAM and the gap area */
727 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
728 SPAPR_LMB_FLAGS_RESERVED
|
729 SPAPR_LMB_FLAGS_DRC_INVALID
);
730 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
733 cur_addr
= machine
->device_memory
->base
;
734 for (info
= dimms
; info
; info
= info
->next
) {
735 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
741 /* Entry for hot-pluggable area */
742 if (cur_addr
< addr
) {
743 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
745 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
746 cur_addr
, spapr_drc_index(drc
), -1, 0);
747 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
752 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
754 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
755 spapr_drc_index(drc
), node
,
756 SPAPR_LMB_FLAGS_ASSIGNED
);
757 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
759 cur_addr
= addr
+ size
;
762 /* Entry for remaining hotpluggable area */
763 if (cur_addr
< mem_end
) {
764 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
766 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
767 cur_addr
, spapr_drc_index(drc
), -1, 0);
768 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
772 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
773 int_buf
= cur_index
= g_malloc0(buf_len
);
774 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
775 cur_index
+= sizeof(nr_entries
);
777 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
778 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
779 cur_index
+= sizeof(elem
->cell
);
780 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
784 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
792 /* ibm,dynamic-memory */
793 static int spapr_populate_drmem_v1(sPAPRMachineState
*spapr
, void *fdt
,
794 int offset
, MemoryDeviceInfoList
*dimms
)
796 MachineState
*machine
= MACHINE(spapr
);
798 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
799 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
800 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
801 memory_region_size(&machine
->device_memory
->mr
)) /
803 uint32_t *int_buf
, *cur_index
, buf_len
;
806 * Allocate enough buffer size to fit in ibm,dynamic-memory
808 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
809 cur_index
= int_buf
= g_malloc0(buf_len
);
810 int_buf
[0] = cpu_to_be32(nr_lmbs
);
812 for (i
= 0; i
< nr_lmbs
; i
++) {
813 uint64_t addr
= i
* lmb_size
;
814 uint32_t *dynamic_memory
= cur_index
;
816 if (i
>= device_lmb_start
) {
817 sPAPRDRConnector
*drc
;
819 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
822 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
823 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
824 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
825 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
826 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
827 if (memory_region_present(get_system_memory(), addr
)) {
828 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
830 dynamic_memory
[5] = cpu_to_be32(0);
834 * LMB information for RMA, boot time RAM and gap b/n RAM and
835 * device memory region -- all these are marked as reserved
836 * and as having no valid DRC.
838 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
839 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
840 dynamic_memory
[2] = cpu_to_be32(0);
841 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
842 dynamic_memory
[4] = cpu_to_be32(-1);
843 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
844 SPAPR_LMB_FLAGS_DRC_INVALID
);
847 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
849 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
858 * Adds ibm,dynamic-reconfiguration-memory node.
859 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
860 * of this device tree node.
862 static int spapr_populate_drconf_memory(sPAPRMachineState
*spapr
, void *fdt
)
864 MachineState
*machine
= MACHINE(spapr
);
866 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
867 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
868 uint32_t *int_buf
, *cur_index
, buf_len
;
869 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
870 MemoryDeviceInfoList
*dimms
= NULL
;
873 * Don't create the node if there is no device memory
875 if (machine
->ram_size
== machine
->maxram_size
) {
879 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
881 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
882 sizeof(prop_lmb_size
));
887 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
892 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
897 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
898 dimms
= qmp_memory_device_list();
899 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
900 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
902 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
904 qapi_free_MemoryDeviceInfoList(dimms
);
910 /* ibm,associativity-lookup-arrays */
911 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
912 cur_index
= int_buf
= g_malloc0(buf_len
);
915 int_buf
[0] = cpu_to_be32(nr_nodes
);
916 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
918 for (i
= 0; i
< nr_nodes
; i
++) {
919 uint32_t associativity
[] = {
925 memcpy(cur_index
, associativity
, sizeof(associativity
));
928 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
929 (cur_index
- int_buf
) * sizeof(uint32_t));
935 static int spapr_dt_cas_updates(sPAPRMachineState
*spapr
, void *fdt
,
936 sPAPROptionVector
*ov5_updates
)
938 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
941 /* Generate ibm,dynamic-reconfiguration-memory node if required */
942 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
943 g_assert(smc
->dr_lmb_enabled
);
944 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
950 offset
= fdt_path_offset(fdt
, "/chosen");
952 offset
= fdt_add_subnode(fdt
, 0, "chosen");
957 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
958 "ibm,architecture-vec-5");
964 static bool spapr_hotplugged_dev_before_cas(void)
966 Object
*drc_container
, *obj
;
967 ObjectProperty
*prop
;
968 ObjectPropertyIterator iter
;
970 drc_container
= container_get(object_get_root(), "/dr-connector");
971 object_property_iter_init(&iter
, drc_container
);
972 while ((prop
= object_property_iter_next(&iter
))) {
973 if (!strstart(prop
->type
, "link<", NULL
)) {
976 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
977 if (spapr_drc_needed(obj
)) {
984 int spapr_h_cas_compose_response(sPAPRMachineState
*spapr
,
985 target_ulong addr
, target_ulong size
,
986 sPAPROptionVector
*ov5_updates
)
988 void *fdt
, *fdt_skel
;
989 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
991 if (spapr_hotplugged_dev_before_cas()) {
995 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
996 error_report("SLOF provided an unexpected CAS buffer size "
997 TARGET_FMT_lu
" (min: %zu, max: %u)",
998 size
, sizeof(hdr
), FW_MAX_SIZE
);
1002 size
-= sizeof(hdr
);
1004 /* Create skeleton */
1005 fdt_skel
= g_malloc0(size
);
1006 _FDT((fdt_create(fdt_skel
, size
)));
1007 _FDT((fdt_finish_reservemap(fdt_skel
)));
1008 _FDT((fdt_begin_node(fdt_skel
, "")));
1009 _FDT((fdt_end_node(fdt_skel
)));
1010 _FDT((fdt_finish(fdt_skel
)));
1011 fdt
= g_malloc0(size
);
1012 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
1015 /* Fixup cpu nodes */
1016 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
1018 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
1022 /* Pack resulting tree */
1023 _FDT((fdt_pack(fdt
)));
1025 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
1026 trace_spapr_cas_failed(size
);
1030 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
1031 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
1032 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
1038 static void spapr_dt_rtas(sPAPRMachineState
*spapr
, void *fdt
)
1041 GString
*hypertas
= g_string_sized_new(256);
1042 GString
*qemu_hypertas
= g_string_sized_new(256);
1043 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1044 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
1045 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
1046 uint32_t lrdr_capacity
[] = {
1047 cpu_to_be32(max_device_addr
>> 32),
1048 cpu_to_be32(max_device_addr
& 0xffffffff),
1049 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
1050 cpu_to_be32(max_cpus
/ smp_threads
),
1052 uint32_t maxdomains
[] = {
1057 cpu_to_be32(nb_numa_nodes
? nb_numa_nodes
- 1 : 0),
1060 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
1063 add_str(hypertas
, "hcall-pft");
1064 add_str(hypertas
, "hcall-term");
1065 add_str(hypertas
, "hcall-dabr");
1066 add_str(hypertas
, "hcall-interrupt");
1067 add_str(hypertas
, "hcall-tce");
1068 add_str(hypertas
, "hcall-vio");
1069 add_str(hypertas
, "hcall-splpar");
1070 add_str(hypertas
, "hcall-bulk");
1071 add_str(hypertas
, "hcall-set-mode");
1072 add_str(hypertas
, "hcall-sprg0");
1073 add_str(hypertas
, "hcall-copy");
1074 add_str(hypertas
, "hcall-debug");
1075 add_str(qemu_hypertas
, "hcall-memop1");
1077 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1078 add_str(hypertas
, "hcall-multi-tce");
1081 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1082 add_str(hypertas
, "hcall-hpt-resize");
1085 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1086 hypertas
->str
, hypertas
->len
));
1087 g_string_free(hypertas
, TRUE
);
1088 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1089 qemu_hypertas
->str
, qemu_hypertas
->len
));
1090 g_string_free(qemu_hypertas
, TRUE
);
1092 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1093 refpoints
, sizeof(refpoints
)));
1095 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1096 maxdomains
, sizeof(maxdomains
)));
1098 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1099 RTAS_ERROR_LOG_MAX
));
1100 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1101 RTAS_EVENT_SCAN_RATE
));
1103 g_assert(msi_nonbroken
);
1104 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1107 * According to PAPR, rtas ibm,os-term does not guarantee a return
1108 * back to the guest cpu.
1110 * While an additional ibm,extended-os-term property indicates
1111 * that rtas call return will always occur. Set this property.
1113 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1115 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1116 lrdr_capacity
, sizeof(lrdr_capacity
)));
1118 spapr_dt_rtas_tokens(fdt
, rtas
);
1121 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
1122 * that the guest may request and thus the valid values for bytes 24..26 of
1123 * option vector 5: */
1124 static void spapr_dt_ov5_platform_support(void *fdt
, int chosen
)
1126 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1129 23, 0x00, /* Xive mode, filled in below. */
1130 24, 0x00, /* Hash/Radix, filled in below. */
1131 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1132 26, 0x40, /* Radix options: GTSE == yes. */
1135 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1136 first_ppc_cpu
->compat_pvr
)) {
1137 /* If we're in a pre POWER9 compat mode then the guest should do hash */
1138 val
[3] = 0x00; /* Hash */
1139 } else if (kvm_enabled()) {
1140 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1141 val
[3] = 0x80; /* OV5_MMU_BOTH */
1142 } else if (kvmppc_has_cap_mmu_radix()) {
1143 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1145 val
[3] = 0x00; /* Hash */
1148 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1151 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1155 static void spapr_dt_chosen(sPAPRMachineState
*spapr
, void *fdt
)
1157 MachineState
*machine
= MACHINE(spapr
);
1159 const char *boot_device
= machine
->boot_order
;
1160 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1162 char *bootlist
= get_boot_devices_list(&cb
, true);
1164 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1166 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs", machine
->kernel_cmdline
));
1167 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1168 spapr
->initrd_base
));
1169 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1170 spapr
->initrd_base
+ spapr
->initrd_size
));
1172 if (spapr
->kernel_size
) {
1173 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1174 cpu_to_be64(spapr
->kernel_size
) };
1176 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1177 &kprop
, sizeof(kprop
)));
1178 if (spapr
->kernel_le
) {
1179 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1183 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1185 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1186 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1187 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1189 if (cb
&& bootlist
) {
1192 for (i
= 0; i
< cb
; i
++) {
1193 if (bootlist
[i
] == '\n') {
1197 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1200 if (boot_device
&& strlen(boot_device
)) {
1201 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1204 if (!spapr
->has_graphics
&& stdout_path
) {
1206 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1207 * kernel. New platforms should only use the "stdout-path" property. Set
1208 * the new property and continue using older property to remain
1209 * compatible with the existing firmware.
1211 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1212 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1215 spapr_dt_ov5_platform_support(fdt
, chosen
);
1217 g_free(stdout_path
);
1221 static void spapr_dt_hypervisor(sPAPRMachineState
*spapr
, void *fdt
)
1223 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1224 * KVM to work under pHyp with some guest co-operation */
1226 uint8_t hypercall
[16];
1228 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1229 /* indicate KVM hypercall interface */
1230 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1231 if (kvmppc_has_cap_fixup_hcalls()) {
1233 * Older KVM versions with older guest kernels were broken
1234 * with the magic page, don't allow the guest to map it.
1236 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1237 sizeof(hypercall
))) {
1238 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1239 hypercall
, sizeof(hypercall
)));
1244 static void *spapr_build_fdt(sPAPRMachineState
*spapr
,
1248 MachineState
*machine
= MACHINE(spapr
);
1249 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1250 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1256 fdt
= g_malloc0(FDT_MAX_SIZE
);
1257 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1260 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1261 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1262 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1265 * Add info to guest to indentify which host is it being run on
1266 * and what is the uuid of the guest
1268 if (kvmppc_get_host_model(&buf
)) {
1269 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1272 if (kvmppc_get_host_serial(&buf
)) {
1273 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1277 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1279 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1280 if (qemu_uuid_set
) {
1281 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1285 if (qemu_get_vm_name()) {
1286 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1287 qemu_get_vm_name()));
1290 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1291 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1293 /* /interrupt controller */
1294 spapr_dt_xics(xics_max_server_number(spapr
), fdt
, PHANDLE_XICP
);
1296 ret
= spapr_populate_memory(spapr
, fdt
);
1298 error_report("couldn't setup memory nodes in fdt");
1303 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1305 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1306 ret
= spapr_rng_populate_dt(fdt
);
1308 error_report("could not set up rng device in the fdt");
1313 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1314 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
1316 error_report("couldn't setup PCI devices in fdt");
1322 spapr_populate_cpus_dt_node(fdt
, spapr
);
1324 if (smc
->dr_lmb_enabled
) {
1325 _FDT(spapr_drc_populate_dt(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1328 if (mc
->has_hotpluggable_cpus
) {
1329 int offset
= fdt_path_offset(fdt
, "/cpus");
1330 ret
= spapr_drc_populate_dt(fdt
, offset
, NULL
,
1331 SPAPR_DR_CONNECTOR_TYPE_CPU
);
1333 error_report("Couldn't set up CPU DR device tree properties");
1338 /* /event-sources */
1339 spapr_dt_events(spapr
, fdt
);
1342 spapr_dt_rtas(spapr
, fdt
);
1345 spapr_dt_chosen(spapr
, fdt
);
1348 if (kvm_enabled()) {
1349 spapr_dt_hypervisor(spapr
, fdt
);
1352 /* Build memory reserve map */
1353 if (spapr
->kernel_size
) {
1354 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1356 if (spapr
->initrd_size
) {
1357 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1360 /* ibm,client-architecture-support updates */
1361 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1363 error_report("couldn't setup CAS properties fdt");
1370 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1372 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1375 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1378 CPUPPCState
*env
= &cpu
->env
;
1380 /* The TCG path should also be holding the BQL at this point */
1381 g_assert(qemu_mutex_iothread_locked());
1384 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1385 env
->gpr
[3] = H_PRIVILEGE
;
1387 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1391 static uint64_t spapr_get_patbe(PPCVirtualHypervisor
*vhyp
)
1393 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1395 return spapr
->patb_entry
;
1398 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1399 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1400 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1401 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1402 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1405 * Get the fd to access the kernel htab, re-opening it if necessary
1407 static int get_htab_fd(sPAPRMachineState
*spapr
)
1409 Error
*local_err
= NULL
;
1411 if (spapr
->htab_fd
>= 0) {
1412 return spapr
->htab_fd
;
1415 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1416 if (spapr
->htab_fd
< 0) {
1417 error_report_err(local_err
);
1420 return spapr
->htab_fd
;
1423 void close_htab_fd(sPAPRMachineState
*spapr
)
1425 if (spapr
->htab_fd
>= 0) {
1426 close(spapr
->htab_fd
);
1428 spapr
->htab_fd
= -1;
1431 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1433 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1435 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1438 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1440 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1442 assert(kvm_enabled());
1448 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1451 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1454 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1455 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1459 * HTAB is controlled by KVM. Fetch into temporary buffer
1461 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1462 kvmppc_read_hptes(hptes
, ptex
, n
);
1467 * HTAB is controlled by QEMU. Just point to the internally
1470 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1473 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1474 const ppc_hash_pte64_t
*hptes
,
1477 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1480 g_free((void *)hptes
);
1483 /* Nothing to do for qemu managed HPT */
1486 static void spapr_store_hpte(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1487 uint64_t pte0
, uint64_t pte1
)
1489 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1490 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1493 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1495 stq_p(spapr
->htab
+ offset
, pte0
);
1496 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1500 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1504 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1505 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1506 * that's much more than is needed for Linux guests */
1507 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1508 shift
= MAX(shift
, 18); /* Minimum architected size */
1509 shift
= MIN(shift
, 46); /* Maximum architected size */
1513 void spapr_free_hpt(sPAPRMachineState
*spapr
)
1515 g_free(spapr
->htab
);
1517 spapr
->htab_shift
= 0;
1518 close_htab_fd(spapr
);
1521 void spapr_reallocate_hpt(sPAPRMachineState
*spapr
, int shift
,
1526 /* Clean up any HPT info from a previous boot */
1527 spapr_free_hpt(spapr
);
1529 rc
= kvmppc_reset_htab(shift
);
1531 /* kernel-side HPT needed, but couldn't allocate one */
1532 error_setg_errno(errp
, errno
,
1533 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1535 /* This is almost certainly fatal, but if the caller really
1536 * wants to carry on with shift == 0, it's welcome to try */
1537 } else if (rc
> 0) {
1538 /* kernel-side HPT allocated */
1541 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1545 spapr
->htab_shift
= shift
;
1548 /* kernel-side HPT not needed, allocate in userspace instead */
1549 size_t size
= 1ULL << shift
;
1552 spapr
->htab
= qemu_memalign(size
, size
);
1554 error_setg_errno(errp
, errno
,
1555 "Could not allocate HPT of order %d", shift
);
1559 memset(spapr
->htab
, 0, size
);
1560 spapr
->htab_shift
= shift
;
1562 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1563 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1566 /* We're setting up a hash table, so that means we're not radix */
1567 spapr
->patb_entry
= 0;
1570 void spapr_setup_hpt_and_vrma(sPAPRMachineState
*spapr
)
1574 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1575 || (spapr
->cas_reboot
1576 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1577 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1579 uint64_t current_ram_size
;
1581 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1582 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1584 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1586 if (spapr
->vrma_adjust
) {
1587 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1592 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1594 sPAPRDRConnector
*drc
=
1595 (sPAPRDRConnector
*) object_dynamic_cast(child
,
1596 TYPE_SPAPR_DR_CONNECTOR
);
1599 spapr_drc_reset(drc
);
1605 static void spapr_machine_reset(void)
1607 MachineState
*machine
= MACHINE(qdev_get_machine());
1608 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
1609 PowerPCCPU
*first_ppc_cpu
;
1610 uint32_t rtas_limit
;
1611 hwaddr rtas_addr
, fdt_addr
;
1615 spapr_caps_reset(spapr
);
1617 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1618 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1619 ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1620 spapr
->max_compat_pvr
)) {
1621 /* If using KVM with radix mode available, VCPUs can be started
1622 * without a HPT because KVM will start them in radix mode.
1623 * Set the GR bit in PATB so that we know there is no HPT. */
1624 spapr
->patb_entry
= PATBE1_GR
;
1626 spapr_setup_hpt_and_vrma(spapr
);
1629 /* if this reset wasn't generated by CAS, we should reset our
1630 * negotiated options and start from scratch */
1631 if (!spapr
->cas_reboot
) {
1632 spapr_ovec_cleanup(spapr
->ov5_cas
);
1633 spapr
->ov5_cas
= spapr_ovec_new();
1635 ppc_set_compat(first_ppc_cpu
, spapr
->max_compat_pvr
, &error_fatal
);
1638 qemu_devices_reset();
1640 /* DRC reset may cause a device to be unplugged. This will cause troubles
1641 * if this device is used by another device (eg, a running vhost backend
1642 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1643 * situations, we reset DRCs after all devices have been reset.
1645 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1647 spapr_clear_pending_events(spapr
);
1650 * We place the device tree and RTAS just below either the top of the RMA,
1651 * or just below 2GB, whichever is lowere, so that it can be
1652 * processed with 32-bit real mode code if necessary
1654 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1655 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1656 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1658 fdt
= spapr_build_fdt(spapr
, rtas_addr
, spapr
->rtas_size
);
1660 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1664 /* Should only fail if we've built a corrupted tree */
1667 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1668 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1669 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1674 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1675 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1678 /* Set up the entry state */
1679 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1680 first_ppc_cpu
->env
.gpr
[5] = 0;
1682 spapr
->cas_reboot
= false;
1685 static void spapr_create_nvram(sPAPRMachineState
*spapr
)
1687 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1688 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1691 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1695 qdev_init_nofail(dev
);
1697 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
1700 static void spapr_rtc_create(sPAPRMachineState
*spapr
)
1702 object_initialize(&spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
);
1703 object_property_add_child(OBJECT(spapr
), "rtc", OBJECT(&spapr
->rtc
),
1705 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1707 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1708 "date", &error_fatal
);
1711 /* Returns whether we want to use VGA or not */
1712 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1714 switch (vga_interface_type
) {
1721 return pci_vga_init(pci_bus
) != NULL
;
1724 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1729 static int spapr_pre_load(void *opaque
)
1733 rc
= spapr_caps_pre_load(opaque
);
1741 static int spapr_post_load(void *opaque
, int version_id
)
1743 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1746 err
= spapr_caps_post_migration(spapr
);
1751 if (!object_dynamic_cast(OBJECT(spapr
->ics
), TYPE_ICS_KVM
)) {
1754 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1755 icp_resend(ICP(cpu
->intc
));
1759 /* In earlier versions, there was no separate qdev for the PAPR
1760 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1761 * So when migrating from those versions, poke the incoming offset
1762 * value into the RTC device */
1763 if (version_id
< 3) {
1764 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1767 if (kvm_enabled() && spapr
->patb_entry
) {
1768 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1769 bool radix
= !!(spapr
->patb_entry
& PATBE1_GR
);
1770 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1772 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1774 error_report("Process table config unsupported by the host");
1782 static int spapr_pre_save(void *opaque
)
1786 rc
= spapr_caps_pre_save(opaque
);
1794 static bool version_before_3(void *opaque
, int version_id
)
1796 return version_id
< 3;
1799 static bool spapr_pending_events_needed(void *opaque
)
1801 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1802 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1805 static const VMStateDescription vmstate_spapr_event_entry
= {
1806 .name
= "spapr_event_log_entry",
1808 .minimum_version_id
= 1,
1809 .fields
= (VMStateField
[]) {
1810 VMSTATE_UINT32(summary
, sPAPREventLogEntry
),
1811 VMSTATE_UINT32(extended_length
, sPAPREventLogEntry
),
1812 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, sPAPREventLogEntry
, 0,
1813 NULL
, extended_length
),
1814 VMSTATE_END_OF_LIST()
1818 static const VMStateDescription vmstate_spapr_pending_events
= {
1819 .name
= "spapr_pending_events",
1821 .minimum_version_id
= 1,
1822 .needed
= spapr_pending_events_needed
,
1823 .fields
= (VMStateField
[]) {
1824 VMSTATE_QTAILQ_V(pending_events
, sPAPRMachineState
, 1,
1825 vmstate_spapr_event_entry
, sPAPREventLogEntry
, next
),
1826 VMSTATE_END_OF_LIST()
1830 static bool spapr_ov5_cas_needed(void *opaque
)
1832 sPAPRMachineState
*spapr
= opaque
;
1833 sPAPROptionVector
*ov5_mask
= spapr_ovec_new();
1834 sPAPROptionVector
*ov5_legacy
= spapr_ovec_new();
1835 sPAPROptionVector
*ov5_removed
= spapr_ovec_new();
1838 /* Prior to the introduction of sPAPROptionVector, we had two option
1839 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1840 * Both of these options encode machine topology into the device-tree
1841 * in such a way that the now-booted OS should still be able to interact
1842 * appropriately with QEMU regardless of what options were actually
1843 * negotiatied on the source side.
1845 * As such, we can avoid migrating the CAS-negotiated options if these
1846 * are the only options available on the current machine/platform.
1847 * Since these are the only options available for pseries-2.7 and
1848 * earlier, this allows us to maintain old->new/new->old migration
1851 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1852 * via default pseries-2.8 machines and explicit command-line parameters.
1853 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1854 * of the actual CAS-negotiated values to continue working properly. For
1855 * example, availability of memory unplug depends on knowing whether
1856 * OV5_HP_EVT was negotiated via CAS.
1858 * Thus, for any cases where the set of available CAS-negotiatable
1859 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1860 * include the CAS-negotiated options in the migration stream, unless
1861 * if they affect boot time behaviour only.
1863 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1864 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1865 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1867 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1868 * the mask itself since in the future it's possible "legacy" bits may be
1869 * removed via machine options, which could generate a false positive
1870 * that breaks migration.
1872 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
1873 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
1875 spapr_ovec_cleanup(ov5_mask
);
1876 spapr_ovec_cleanup(ov5_legacy
);
1877 spapr_ovec_cleanup(ov5_removed
);
1882 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1883 .name
= "spapr_option_vector_ov5_cas",
1885 .minimum_version_id
= 1,
1886 .needed
= spapr_ov5_cas_needed
,
1887 .fields
= (VMStateField
[]) {
1888 VMSTATE_STRUCT_POINTER_V(ov5_cas
, sPAPRMachineState
, 1,
1889 vmstate_spapr_ovec
, sPAPROptionVector
),
1890 VMSTATE_END_OF_LIST()
1894 static bool spapr_patb_entry_needed(void *opaque
)
1896 sPAPRMachineState
*spapr
= opaque
;
1898 return !!spapr
->patb_entry
;
1901 static const VMStateDescription vmstate_spapr_patb_entry
= {
1902 .name
= "spapr_patb_entry",
1904 .minimum_version_id
= 1,
1905 .needed
= spapr_patb_entry_needed
,
1906 .fields
= (VMStateField
[]) {
1907 VMSTATE_UINT64(patb_entry
, sPAPRMachineState
),
1908 VMSTATE_END_OF_LIST()
1912 static const VMStateDescription vmstate_spapr
= {
1915 .minimum_version_id
= 1,
1916 .pre_load
= spapr_pre_load
,
1917 .post_load
= spapr_post_load
,
1918 .pre_save
= spapr_pre_save
,
1919 .fields
= (VMStateField
[]) {
1920 /* used to be @next_irq */
1921 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
1924 VMSTATE_UINT64_TEST(rtc_offset
, sPAPRMachineState
, version_before_3
),
1926 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPRMachineState
, 2),
1927 VMSTATE_END_OF_LIST()
1929 .subsections
= (const VMStateDescription
*[]) {
1930 &vmstate_spapr_ov5_cas
,
1931 &vmstate_spapr_patb_entry
,
1932 &vmstate_spapr_pending_events
,
1933 &vmstate_spapr_cap_htm
,
1934 &vmstate_spapr_cap_vsx
,
1935 &vmstate_spapr_cap_dfp
,
1936 &vmstate_spapr_cap_cfpc
,
1937 &vmstate_spapr_cap_sbbc
,
1938 &vmstate_spapr_cap_ibs
,
1943 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
1945 sPAPRMachineState
*spapr
= opaque
;
1947 /* "Iteration" header */
1948 if (!spapr
->htab_shift
) {
1949 qemu_put_be32(f
, -1);
1951 qemu_put_be32(f
, spapr
->htab_shift
);
1955 spapr
->htab_save_index
= 0;
1956 spapr
->htab_first_pass
= true;
1958 if (spapr
->htab_shift
) {
1959 assert(kvm_enabled());
1967 static void htab_save_chunk(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1968 int chunkstart
, int n_valid
, int n_invalid
)
1970 qemu_put_be32(f
, chunkstart
);
1971 qemu_put_be16(f
, n_valid
);
1972 qemu_put_be16(f
, n_invalid
);
1973 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1974 HASH_PTE_SIZE_64
* n_valid
);
1977 static void htab_save_end_marker(QEMUFile
*f
)
1979 qemu_put_be32(f
, 0);
1980 qemu_put_be16(f
, 0);
1981 qemu_put_be16(f
, 0);
1984 static void htab_save_first_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1987 bool has_timeout
= max_ns
!= -1;
1988 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1989 int index
= spapr
->htab_save_index
;
1990 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1992 assert(spapr
->htab_first_pass
);
1997 /* Consume invalid HPTEs */
1998 while ((index
< htabslots
)
1999 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2000 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2004 /* Consume valid HPTEs */
2006 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2007 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2008 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2012 if (index
> chunkstart
) {
2013 int n_valid
= index
- chunkstart
;
2015 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2018 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2022 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2024 if (index
>= htabslots
) {
2025 assert(index
== htabslots
);
2027 spapr
->htab_first_pass
= false;
2029 spapr
->htab_save_index
= index
;
2032 static int htab_save_later_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
2035 bool final
= max_ns
< 0;
2036 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2037 int examined
= 0, sent
= 0;
2038 int index
= spapr
->htab_save_index
;
2039 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2041 assert(!spapr
->htab_first_pass
);
2044 int chunkstart
, invalidstart
;
2046 /* Consume non-dirty HPTEs */
2047 while ((index
< htabslots
)
2048 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2054 /* Consume valid dirty HPTEs */
2055 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2056 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2057 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2058 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2063 invalidstart
= index
;
2064 /* Consume invalid dirty HPTEs */
2065 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2066 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2067 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2068 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2073 if (index
> chunkstart
) {
2074 int n_valid
= invalidstart
- chunkstart
;
2075 int n_invalid
= index
- invalidstart
;
2077 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2078 sent
+= index
- chunkstart
;
2080 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2085 if (examined
>= htabslots
) {
2089 if (index
>= htabslots
) {
2090 assert(index
== htabslots
);
2093 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2095 if (index
>= htabslots
) {
2096 assert(index
== htabslots
);
2100 spapr
->htab_save_index
= index
;
2102 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2105 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2106 #define MAX_KVM_BUF_SIZE 2048
2108 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2110 sPAPRMachineState
*spapr
= opaque
;
2114 /* Iteration header */
2115 if (!spapr
->htab_shift
) {
2116 qemu_put_be32(f
, -1);
2119 qemu_put_be32(f
, 0);
2123 assert(kvm_enabled());
2125 fd
= get_htab_fd(spapr
);
2130 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2134 } else if (spapr
->htab_first_pass
) {
2135 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2137 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2140 htab_save_end_marker(f
);
2145 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2147 sPAPRMachineState
*spapr
= opaque
;
2150 /* Iteration header */
2151 if (!spapr
->htab_shift
) {
2152 qemu_put_be32(f
, -1);
2155 qemu_put_be32(f
, 0);
2161 assert(kvm_enabled());
2163 fd
= get_htab_fd(spapr
);
2168 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2173 if (spapr
->htab_first_pass
) {
2174 htab_save_first_pass(f
, spapr
, -1);
2176 htab_save_later_pass(f
, spapr
, -1);
2180 htab_save_end_marker(f
);
2185 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2187 sPAPRMachineState
*spapr
= opaque
;
2188 uint32_t section_hdr
;
2190 Error
*local_err
= NULL
;
2192 if (version_id
< 1 || version_id
> 1) {
2193 error_report("htab_load() bad version");
2197 section_hdr
= qemu_get_be32(f
);
2199 if (section_hdr
== -1) {
2200 spapr_free_hpt(spapr
);
2205 /* First section gives the htab size */
2206 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2208 error_report_err(local_err
);
2215 assert(kvm_enabled());
2217 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2219 error_report_err(local_err
);
2226 uint16_t n_valid
, n_invalid
;
2228 index
= qemu_get_be32(f
);
2229 n_valid
= qemu_get_be16(f
);
2230 n_invalid
= qemu_get_be16(f
);
2232 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2237 if ((index
+ n_valid
+ n_invalid
) >
2238 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2239 /* Bad index in stream */
2241 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2242 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2248 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2249 HASH_PTE_SIZE_64
* n_valid
);
2252 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2253 HASH_PTE_SIZE_64
* n_invalid
);
2260 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2275 static void htab_save_cleanup(void *opaque
)
2277 sPAPRMachineState
*spapr
= opaque
;
2279 close_htab_fd(spapr
);
2282 static SaveVMHandlers savevm_htab_handlers
= {
2283 .save_setup
= htab_save_setup
,
2284 .save_live_iterate
= htab_save_iterate
,
2285 .save_live_complete_precopy
= htab_save_complete
,
2286 .save_cleanup
= htab_save_cleanup
,
2287 .load_state
= htab_load
,
2290 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2293 MachineState
*machine
= MACHINE(opaque
);
2294 machine
->boot_order
= g_strdup(boot_device
);
2297 static void spapr_create_lmb_dr_connectors(sPAPRMachineState
*spapr
)
2299 MachineState
*machine
= MACHINE(spapr
);
2300 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2301 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2304 for (i
= 0; i
< nr_lmbs
; i
++) {
2307 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2308 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2314 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2315 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2316 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2318 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2322 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2323 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2324 " is not aligned to %llu MiB",
2326 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
2330 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2331 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2332 " is not aligned to %llu MiB",
2334 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
2338 for (i
= 0; i
< nb_numa_nodes
; i
++) {
2339 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2341 "Node %d memory size 0x%" PRIx64
2342 " is not aligned to %llu MiB",
2343 i
, numa_info
[i
].node_mem
,
2344 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
2350 /* find cpu slot in machine->possible_cpus by core_id */
2351 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2353 int index
= id
/ smp_threads
;
2355 if (index
>= ms
->possible_cpus
->len
) {
2361 return &ms
->possible_cpus
->cpus
[index
];
2364 static void spapr_set_vsmt_mode(sPAPRMachineState
*spapr
, Error
**errp
)
2366 Error
*local_err
= NULL
;
2367 bool vsmt_user
= !!spapr
->vsmt
;
2368 int kvm_smt
= kvmppc_smt_threads();
2371 if (!kvm_enabled() && (smp_threads
> 1)) {
2372 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2373 "on a pseries machine");
2376 if (!is_power_of_2(smp_threads
)) {
2377 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2378 "machine because it must be a power of 2", smp_threads
);
2382 /* Detemine the VSMT mode to use: */
2384 if (spapr
->vsmt
< smp_threads
) {
2385 error_setg(&local_err
, "Cannot support VSMT mode %d"
2386 " because it must be >= threads/core (%d)",
2387 spapr
->vsmt
, smp_threads
);
2390 /* In this case, spapr->vsmt has been set by the command line */
2393 * Default VSMT value is tricky, because we need it to be as
2394 * consistent as possible (for migration), but this requires
2395 * changing it for at least some existing cases. We pick 8 as
2396 * the value that we'd get with KVM on POWER8, the
2397 * overwhelmingly common case in production systems.
2399 spapr
->vsmt
= MAX(8, smp_threads
);
2402 /* KVM: If necessary, set the SMT mode: */
2403 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2404 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2406 /* Looks like KVM isn't able to change VSMT mode */
2407 error_setg(&local_err
,
2408 "Failed to set KVM's VSMT mode to %d (errno %d)",
2410 /* We can live with that if the default one is big enough
2411 * for the number of threads, and a submultiple of the one
2412 * we want. In this case we'll waste some vcpu ids, but
2413 * behaviour will be correct */
2414 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2415 warn_report_err(local_err
);
2420 error_append_hint(&local_err
,
2421 "On PPC, a VM with %d threads/core"
2422 " on a host with %d threads/core"
2423 " requires the use of VSMT mode %d.\n",
2424 smp_threads
, kvm_smt
, spapr
->vsmt
);
2426 kvmppc_hint_smt_possible(&local_err
);
2431 /* else TCG: nothing to do currently */
2433 error_propagate(errp
, local_err
);
2436 static void spapr_init_cpus(sPAPRMachineState
*spapr
)
2438 MachineState
*machine
= MACHINE(spapr
);
2439 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2440 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2441 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2442 const CPUArchIdList
*possible_cpus
;
2443 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2446 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2447 if (mc
->has_hotpluggable_cpus
) {
2448 if (smp_cpus
% smp_threads
) {
2449 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2450 smp_cpus
, smp_threads
);
2453 if (max_cpus
% smp_threads
) {
2454 error_report("max_cpus (%u) must be multiple of threads (%u)",
2455 max_cpus
, smp_threads
);
2459 if (max_cpus
!= smp_cpus
) {
2460 error_report("This machine version does not support CPU hotplug");
2463 boot_cores_nr
= possible_cpus
->len
;
2466 /* VSMT must be set in order to be able to compute VCPU ids, ie to
2467 * call xics_max_server_number() or spapr_vcpu_id().
2469 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2471 if (smc
->pre_2_10_has_unused_icps
) {
2474 for (i
= 0; i
< xics_max_server_number(spapr
); i
++) {
2475 /* Dummy entries get deregistered when real ICPState objects
2476 * are registered during CPU core hotplug.
2478 pre_2_10_vmstate_register_dummy_icp(i
);
2482 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2483 int core_id
= i
* smp_threads
;
2485 if (mc
->has_hotpluggable_cpus
) {
2486 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2487 spapr_vcpu_id(spapr
, core_id
));
2490 if (i
< boot_cores_nr
) {
2491 Object
*core
= object_new(type
);
2492 int nr_threads
= smp_threads
;
2494 /* Handle the partially filled core for older machine types */
2495 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2496 nr_threads
= smp_cpus
- i
* smp_threads
;
2499 object_property_set_int(core
, nr_threads
, "nr-threads",
2501 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2503 object_property_set_bool(core
, true, "realized", &error_fatal
);
2508 /* pSeries LPAR / sPAPR hardware init */
2509 static void spapr_machine_init(MachineState
*machine
)
2511 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
2512 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2513 const char *kernel_filename
= machine
->kernel_filename
;
2514 const char *initrd_filename
= machine
->initrd_filename
;
2517 MemoryRegion
*sysmem
= get_system_memory();
2518 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2519 hwaddr node0_size
= spapr_node0_size(machine
);
2520 long load_limit
, fw_size
;
2522 Error
*resize_hpt_err
= NULL
;
2523 PowerPCCPU
*first_ppc_cpu
;
2525 msi_nonbroken
= true;
2527 QLIST_INIT(&spapr
->phbs
);
2528 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2530 /* Check HPT resizing availability */
2531 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2532 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2534 * If the user explicitly requested a mode we should either
2535 * supply it, or fail completely (which we do below). But if
2536 * it's not set explicitly, we reset our mode to something
2539 if (resize_hpt_err
) {
2540 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2541 error_free(resize_hpt_err
);
2542 resize_hpt_err
= NULL
;
2544 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2548 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2550 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2552 * User requested HPT resize, but this host can't supply it. Bail out
2554 error_report_err(resize_hpt_err
);
2558 spapr
->rma_size
= node0_size
;
2560 /* With KVM, we don't actually know whether KVM supports an
2561 * unbounded RMA (PR KVM) or is limited by the hash table size
2562 * (HV KVM using VRMA), so we always assume the latter
2564 * In that case, we also limit the initial allocations for RTAS
2565 * etc... to 256M since we have no way to know what the VRMA size
2566 * is going to be as it depends on the size of the hash table
2567 * which isn't determined yet.
2569 if (kvm_enabled()) {
2570 spapr
->vrma_adjust
= 1;
2571 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2574 /* Actually we don't support unbounded RMA anymore since we added
2575 * proper emulation of HV mode. The max we can get is 16G which
2576 * also happens to be what we configure for PAPR mode so make sure
2577 * we don't do anything bigger than that
2579 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2581 if (spapr
->rma_size
> node0_size
) {
2582 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2587 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2588 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2590 /* Set up Interrupt Controller before we create the VCPUs */
2591 xics_system_init(machine
, XICS_IRQS_SPAPR
, &error_fatal
);
2593 /* Set up containers for ibm,client-architecture-support negotiated options
2595 spapr
->ov5
= spapr_ovec_new();
2596 spapr
->ov5_cas
= spapr_ovec_new();
2598 if (smc
->dr_lmb_enabled
) {
2599 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2600 spapr_validate_node_memory(machine
, &error_fatal
);
2603 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2605 /* advertise support for dedicated HP event source to guests */
2606 if (spapr
->use_hotplug_event_source
) {
2607 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2610 /* advertise support for HPT resizing */
2611 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2612 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2615 /* advertise support for ibm,dyamic-memory-v2 */
2616 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2619 spapr_init_cpus(spapr
);
2621 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
2622 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2623 ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
2624 spapr
->max_compat_pvr
)) {
2625 /* KVM and TCG always allow GTSE with radix... */
2626 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2628 /* ... but not with hash (currently). */
2630 if (kvm_enabled()) {
2631 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2632 kvmppc_enable_logical_ci_hcalls();
2633 kvmppc_enable_set_mode_hcall();
2635 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2636 kvmppc_enable_clear_ref_mod_hcalls();
2640 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2642 memory_region_add_subregion(sysmem
, 0, ram
);
2644 /* always allocate the device memory information */
2645 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2647 /* initialize hotplug memory address space */
2648 if (machine
->ram_size
< machine
->maxram_size
) {
2649 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2651 * Limit the number of hotpluggable memory slots to half the number
2652 * slots that KVM supports, leaving the other half for PCI and other
2653 * devices. However ensure that number of slots doesn't drop below 32.
2655 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2656 SPAPR_MAX_RAM_SLOTS
;
2658 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2659 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2661 if (machine
->ram_slots
> max_memslots
) {
2662 error_report("Specified number of memory slots %"
2663 PRIu64
" exceeds max supported %d",
2664 machine
->ram_slots
, max_memslots
);
2668 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2669 SPAPR_DEVICE_MEM_ALIGN
);
2670 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2671 "device-memory", device_mem_size
);
2672 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2673 &machine
->device_memory
->mr
);
2676 if (smc
->dr_lmb_enabled
) {
2677 spapr_create_lmb_dr_connectors(spapr
);
2680 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2682 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2685 spapr
->rtas_size
= get_image_size(filename
);
2686 if (spapr
->rtas_size
< 0) {
2687 error_report("Could not get size of LPAR rtas '%s'", filename
);
2690 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2691 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2692 error_report("Could not load LPAR rtas '%s'", filename
);
2695 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2696 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2697 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2702 /* Set up RTAS event infrastructure */
2703 spapr_events_init(spapr
);
2705 /* Set up the RTC RTAS interfaces */
2706 spapr_rtc_create(spapr
);
2708 /* Set up VIO bus */
2709 spapr
->vio_bus
= spapr_vio_bus_init();
2711 for (i
= 0; i
< serial_max_hds(); i
++) {
2713 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2717 /* We always have at least the nvram device on VIO */
2718 spapr_create_nvram(spapr
);
2721 spapr_pci_rtas_init();
2723 phb
= spapr_create_phb(spapr
, 0);
2725 for (i
= 0; i
< nb_nics
; i
++) {
2726 NICInfo
*nd
= &nd_table
[i
];
2729 nd
->model
= g_strdup("spapr-vlan");
2732 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2733 g_str_equal(nd
->model
, "ibmveth")) {
2734 spapr_vlan_create(spapr
->vio_bus
, nd
);
2736 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2740 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2741 spapr_vscsi_create(spapr
->vio_bus
);
2745 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2746 spapr
->has_graphics
= true;
2747 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2751 if (smc
->use_ohci_by_default
) {
2752 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2754 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2757 if (spapr
->has_graphics
) {
2758 USBBus
*usb_bus
= usb_bus_find(-1);
2760 usb_create_simple(usb_bus
, "usb-kbd");
2761 usb_create_simple(usb_bus
, "usb-mouse");
2765 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
2767 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2772 if (kernel_filename
) {
2773 uint64_t lowaddr
= 0;
2775 spapr
->kernel_size
= load_elf(kernel_filename
, translate_kernel_address
,
2776 NULL
, NULL
, &lowaddr
, NULL
, 1,
2777 PPC_ELF_MACHINE
, 0, 0);
2778 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2779 spapr
->kernel_size
= load_elf(kernel_filename
,
2780 translate_kernel_address
, NULL
, NULL
,
2781 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
2783 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2785 if (spapr
->kernel_size
< 0) {
2786 error_report("error loading %s: %s", kernel_filename
,
2787 load_elf_strerror(spapr
->kernel_size
));
2792 if (initrd_filename
) {
2793 /* Try to locate the initrd in the gap between the kernel
2794 * and the firmware. Add a bit of space just in case
2796 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
2797 + 0x1ffff) & ~0xffff;
2798 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2801 - spapr
->initrd_base
);
2802 if (spapr
->initrd_size
< 0) {
2803 error_report("could not load initial ram disk '%s'",
2810 if (bios_name
== NULL
) {
2811 bios_name
= FW_FILE_NAME
;
2813 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2815 error_report("Could not find LPAR firmware '%s'", bios_name
);
2818 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2820 error_report("Could not load LPAR firmware '%s'", filename
);
2825 /* FIXME: Should register things through the MachineState's qdev
2826 * interface, this is a legacy from the sPAPREnvironment structure
2827 * which predated MachineState but had a similar function */
2828 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
2829 register_savevm_live(NULL
, "spapr/htab", -1, 1,
2830 &savevm_htab_handlers
, spapr
);
2832 qemu_register_boot_set(spapr_boot_set
, spapr
);
2834 if (kvm_enabled()) {
2835 /* to stop and start vmclock */
2836 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
2839 kvmppc_spapr_enable_inkernel_multitce();
2843 static int spapr_kvm_type(const char *vm_type
)
2849 if (!strcmp(vm_type
, "HV")) {
2853 if (!strcmp(vm_type
, "PR")) {
2857 error_report("Unknown kvm-type specified '%s'", vm_type
);
2862 * Implementation of an interface to adjust firmware path
2863 * for the bootindex property handling.
2865 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
2868 #define CAST(type, obj, name) \
2869 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2870 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
2871 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2872 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
2875 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
2876 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
2877 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
2881 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2882 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2883 * in the top 16 bits of the 64-bit LUN
2885 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
2886 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2887 (uint64_t)id
<< 48);
2888 } else if (virtio
) {
2890 * We use SRP luns of the form 01000000 | (target << 8) | lun
2891 * in the top 32 bits of the 64-bit LUN
2892 * Note: the quote above is from SLOF and it is wrong,
2893 * the actual binding is:
2894 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2896 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
2897 if (d
->lun
>= 256) {
2898 /* Use the LUN "flat space addressing method" */
2901 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2902 (uint64_t)id
<< 32);
2905 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2906 * in the top 32 bits of the 64-bit LUN
2908 unsigned usb_port
= atoi(usb
->port
->path
);
2909 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
2910 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2911 (uint64_t)id
<< 32);
2916 * SLOF probes the USB devices, and if it recognizes that the device is a
2917 * storage device, it changes its name to "storage" instead of "usb-host",
2918 * and additionally adds a child node for the SCSI LUN, so the correct
2919 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2921 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
2922 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
2923 if (usb_host_dev_is_scsi_storage(usbdev
)) {
2924 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
2929 /* Replace "pci" with "pci@800000020000000" */
2930 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
2934 /* Same logic as virtio above */
2935 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
2936 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
2939 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
2940 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2941 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
2942 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
2948 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
2950 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2952 return g_strdup(spapr
->kvm_type
);
2955 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
2957 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2959 g_free(spapr
->kvm_type
);
2960 spapr
->kvm_type
= g_strdup(value
);
2963 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
2965 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2967 return spapr
->use_hotplug_event_source
;
2970 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
2973 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2975 spapr
->use_hotplug_event_source
= value
;
2978 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
2983 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
2985 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2987 switch (spapr
->resize_hpt
) {
2988 case SPAPR_RESIZE_HPT_DEFAULT
:
2989 return g_strdup("default");
2990 case SPAPR_RESIZE_HPT_DISABLED
:
2991 return g_strdup("disabled");
2992 case SPAPR_RESIZE_HPT_ENABLED
:
2993 return g_strdup("enabled");
2994 case SPAPR_RESIZE_HPT_REQUIRED
:
2995 return g_strdup("required");
2997 g_assert_not_reached();
3000 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3002 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3004 if (strcmp(value
, "default") == 0) {
3005 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3006 } else if (strcmp(value
, "disabled") == 0) {
3007 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3008 } else if (strcmp(value
, "enabled") == 0) {
3009 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3010 } else if (strcmp(value
, "required") == 0) {
3011 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3013 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3017 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3018 void *opaque
, Error
**errp
)
3020 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3023 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3024 void *opaque
, Error
**errp
)
3026 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3029 static void spapr_instance_init(Object
*obj
)
3031 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3033 spapr
->htab_fd
= -1;
3034 spapr
->use_hotplug_event_source
= true;
3035 object_property_add_str(obj
, "kvm-type",
3036 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3037 object_property_set_description(obj
, "kvm-type",
3038 "Specifies the KVM virtualization mode (HV, PR)",
3040 object_property_add_bool(obj
, "modern-hotplug-events",
3041 spapr_get_modern_hotplug_events
,
3042 spapr_set_modern_hotplug_events
,
3044 object_property_set_description(obj
, "modern-hotplug-events",
3045 "Use dedicated hotplug event mechanism in"
3046 " place of standard EPOW events when possible"
3047 " (required for memory hot-unplug support)",
3049 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3050 "Maximum permitted CPU compatibility mode",
3053 object_property_add_str(obj
, "resize-hpt",
3054 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3055 object_property_set_description(obj
, "resize-hpt",
3056 "Resizing of the Hash Page Table (enabled, disabled, required)",
3058 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3059 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3060 object_property_set_description(obj
, "vsmt",
3061 "Virtual SMT: KVM behaves as if this were"
3062 " the host's SMT mode", &error_abort
);
3063 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3064 spapr_get_msix_emulation
, NULL
, NULL
);
3067 static void spapr_machine_finalizefn(Object
*obj
)
3069 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3071 g_free(spapr
->kvm_type
);
3074 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3076 cpu_synchronize_state(cs
);
3077 ppc_cpu_do_system_reset(cs
);
3080 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3085 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3089 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3090 uint32_t node
, bool dedicated_hp_event_source
,
3093 sPAPRDRConnector
*drc
;
3094 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3095 int i
, fdt_offset
, fdt_size
;
3097 uint64_t addr
= addr_start
;
3098 bool hotplugged
= spapr_drc_hotplugged(dev
);
3099 Error
*local_err
= NULL
;
3101 for (i
= 0; i
< nr_lmbs
; i
++) {
3102 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3103 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3106 fdt
= create_device_tree(&fdt_size
);
3107 fdt_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3108 SPAPR_MEMORY_BLOCK_SIZE
);
3110 spapr_drc_attach(drc
, dev
, fdt
, fdt_offset
, &local_err
);
3112 while (addr
> addr_start
) {
3113 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3114 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3115 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3116 spapr_drc_detach(drc
);
3119 error_propagate(errp
, local_err
);
3123 spapr_drc_reset(drc
);
3125 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3127 /* send hotplug notification to the
3128 * guest only in case of hotplugged memory
3131 if (dedicated_hp_event_source
) {
3132 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3133 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3134 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3136 spapr_drc_index(drc
));
3138 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3144 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3147 Error
*local_err
= NULL
;
3148 sPAPRMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3149 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3150 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
3152 uint64_t align
, size
, addr
;
3155 mr
= ddc
->get_memory_region(dimm
, &local_err
);
3159 align
= memory_region_get_alignment(mr
);
3160 size
= memory_region_size(mr
);
3162 pc_dimm_memory_plug(dev
, MACHINE(ms
), align
, &local_err
);
3167 addr
= object_property_get_uint(OBJECT(dimm
),
3168 PC_DIMM_ADDR_PROP
, &local_err
);
3173 node
= object_property_get_uint(OBJECT(dev
), PC_DIMM_NODE_PROP
,
3175 spapr_add_lmbs(dev
, addr
, size
, node
,
3176 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3185 pc_dimm_memory_unplug(dev
, MACHINE(ms
));
3187 error_propagate(errp
, local_err
);
3190 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3193 const sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3194 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3195 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
3200 if (!smc
->dr_lmb_enabled
) {
3201 error_setg(errp
, "Memory hotplug not supported for this machine");
3205 mr
= ddc
->get_memory_region(dimm
, errp
);
3209 size
= memory_region_size(mr
);
3211 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3212 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3213 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
3217 mem_dev
= object_property_get_str(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
, NULL
);
3218 if (mem_dev
&& !kvmppc_is_mem_backend_page_size_ok(mem_dev
)) {
3219 error_setg(errp
, "Memory backend has bad page size. "
3220 "Use 'memory-backend-file' with correct mem-path.");
3228 struct sPAPRDIMMState
{
3231 QTAILQ_ENTRY(sPAPRDIMMState
) next
;
3234 static sPAPRDIMMState
*spapr_pending_dimm_unplugs_find(sPAPRMachineState
*s
,
3237 sPAPRDIMMState
*dimm_state
= NULL
;
3239 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3240 if (dimm_state
->dimm
== dimm
) {
3247 static sPAPRDIMMState
*spapr_pending_dimm_unplugs_add(sPAPRMachineState
*spapr
,
3251 sPAPRDIMMState
*ds
= NULL
;
3254 * If this request is for a DIMM whose removal had failed earlier
3255 * (due to guest's refusal to remove the LMBs), we would have this
3256 * dimm already in the pending_dimm_unplugs list. In that
3257 * case don't add again.
3259 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3261 ds
= g_malloc0(sizeof(sPAPRDIMMState
));
3262 ds
->nr_lmbs
= nr_lmbs
;
3264 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3269 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState
*spapr
,
3270 sPAPRDIMMState
*dimm_state
)
3272 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3276 static sPAPRDIMMState
*spapr_recover_pending_dimm_state(sPAPRMachineState
*ms
,
3279 sPAPRDRConnector
*drc
;
3280 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
3281 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
, &error_abort
);
3282 uint64_t size
= memory_region_size(mr
);
3283 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3284 uint32_t avail_lmbs
= 0;
3285 uint64_t addr_start
, addr
;
3288 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3292 for (i
= 0; i
< nr_lmbs
; i
++) {
3293 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3294 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3299 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3302 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3305 /* Callback to be called during DRC release. */
3306 void spapr_lmb_release(DeviceState
*dev
)
3308 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3309 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3310 sPAPRDIMMState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3312 /* This information will get lost if a migration occurs
3313 * during the unplug process. In this case recover it. */
3315 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3317 /* The DRC being examined by the caller at least must be counted */
3318 g_assert(ds
->nr_lmbs
);
3321 if (--ds
->nr_lmbs
) {
3326 * Now that all the LMBs have been removed by the guest, call the
3327 * unplug handler chain. This can never fail.
3329 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3332 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3334 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3335 sPAPRDIMMState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3337 pc_dimm_memory_unplug(dev
, MACHINE(hotplug_dev
));
3338 object_unparent(OBJECT(dev
));
3339 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3342 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3343 DeviceState
*dev
, Error
**errp
)
3345 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3346 Error
*local_err
= NULL
;
3347 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3348 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
3351 uint64_t size
, addr_start
, addr
;
3353 sPAPRDRConnector
*drc
;
3355 mr
= ddc
->get_memory_region(dimm
, &local_err
);
3359 size
= memory_region_size(mr
);
3360 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3362 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3369 * An existing pending dimm state for this DIMM means that there is an
3370 * unplug operation in progress, waiting for the spapr_lmb_release
3371 * callback to complete the job (BQL can't cover that far). In this case,
3372 * bail out to avoid detaching DRCs that were already released.
3374 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3375 error_setg(&local_err
,
3376 "Memory unplug already in progress for device %s",
3381 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3384 for (i
= 0; i
< nr_lmbs
; i
++) {
3385 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3386 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3389 spapr_drc_detach(drc
);
3390 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3393 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3394 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3395 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3396 nr_lmbs
, spapr_drc_index(drc
));
3398 error_propagate(errp
, local_err
);
3401 static void *spapr_populate_hotplug_cpu_dt(CPUState
*cs
, int *fdt_offset
,
3402 sPAPRMachineState
*spapr
)
3404 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3405 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3406 int id
= spapr_get_vcpu_id(cpu
);
3408 int offset
, fdt_size
;
3411 fdt
= create_device_tree(&fdt_size
);
3412 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3413 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3415 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3418 *fdt_offset
= offset
;
3422 /* Callback to be called during DRC release. */
3423 void spapr_core_release(DeviceState
*dev
)
3425 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3427 /* Call the unplug handler chain. This can never fail. */
3428 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3431 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3433 MachineState
*ms
= MACHINE(hotplug_dev
);
3434 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3435 CPUCore
*cc
= CPU_CORE(dev
);
3436 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3438 if (smc
->pre_2_10_has_unused_icps
) {
3439 sPAPRCPUCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3442 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3443 CPUState
*cs
= CPU(sc
->threads
[i
]);
3445 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3450 core_slot
->cpu
= NULL
;
3451 object_unparent(OBJECT(dev
));
3455 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3458 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3460 sPAPRDRConnector
*drc
;
3461 CPUCore
*cc
= CPU_CORE(dev
);
3463 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3464 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3469 error_setg(errp
, "Boot CPU core may not be unplugged");
3473 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3474 spapr_vcpu_id(spapr
, cc
->core_id
));
3477 spapr_drc_detach(drc
);
3479 spapr_hotplug_req_remove_by_index(drc
);
3482 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3485 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3486 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3487 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3488 sPAPRCPUCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3489 CPUCore
*cc
= CPU_CORE(dev
);
3490 CPUState
*cs
= CPU(core
->threads
[0]);
3491 sPAPRDRConnector
*drc
;
3492 Error
*local_err
= NULL
;
3493 CPUArchId
*core_slot
;
3495 bool hotplugged
= spapr_drc_hotplugged(dev
);
3497 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3499 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3503 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3504 spapr_vcpu_id(spapr
, cc
->core_id
));
3506 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3512 fdt
= spapr_populate_hotplug_cpu_dt(cs
, &fdt_offset
, spapr
);
3514 spapr_drc_attach(drc
, dev
, fdt
, fdt_offset
, &local_err
);
3517 error_propagate(errp
, local_err
);
3523 * Send hotplug notification interrupt to the guest only
3524 * in case of hotplugged CPUs.
3526 spapr_hotplug_req_add_by_index(drc
);
3528 spapr_drc_reset(drc
);
3532 core_slot
->cpu
= OBJECT(dev
);
3534 if (smc
->pre_2_10_has_unused_icps
) {
3537 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3538 cs
= CPU(core
->threads
[i
]);
3539 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3544 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3547 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3548 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3549 Error
*local_err
= NULL
;
3550 CPUCore
*cc
= CPU_CORE(dev
);
3551 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3552 const char *type
= object_get_typename(OBJECT(dev
));
3553 CPUArchId
*core_slot
;
3556 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3557 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3561 if (strcmp(base_core_type
, type
)) {
3562 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3566 if (cc
->core_id
% smp_threads
) {
3567 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3572 * In general we should have homogeneous threads-per-core, but old
3573 * (pre hotplug support) machine types allow the last core to have
3574 * reduced threads as a compatibility hack for when we allowed
3575 * total vcpus not a multiple of threads-per-core.
3577 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3578 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3579 cc
->nr_threads
, smp_threads
);
3583 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3585 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3589 if (core_slot
->cpu
) {
3590 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3594 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3597 error_propagate(errp
, local_err
);
3600 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
3601 DeviceState
*dev
, Error
**errp
)
3603 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3604 spapr_memory_plug(hotplug_dev
, dev
, errp
);
3605 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3606 spapr_core_plug(hotplug_dev
, dev
, errp
);
3610 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
3611 DeviceState
*dev
, Error
**errp
)
3613 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3614 spapr_memory_unplug(hotplug_dev
, dev
);
3615 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3616 spapr_core_unplug(hotplug_dev
, dev
);
3620 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
3621 DeviceState
*dev
, Error
**errp
)
3623 sPAPRMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3624 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
3626 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3627 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
3628 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
3630 /* NOTE: this means there is a window after guest reset, prior to
3631 * CAS negotiation, where unplug requests will fail due to the
3632 * capability not being detected yet. This is a bit different than
3633 * the case with PCI unplug, where the events will be queued and
3634 * eventually handled by the guest after boot
3636 error_setg(errp
, "Memory hot unplug not supported for this guest");
3638 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3639 if (!mc
->has_hotpluggable_cpus
) {
3640 error_setg(errp
, "CPU hot unplug not supported on this machine");
3643 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
3647 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
3648 DeviceState
*dev
, Error
**errp
)
3650 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3651 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
3652 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3653 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
3657 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
3660 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
3661 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3662 return HOTPLUG_HANDLER(machine
);
3667 static CpuInstanceProperties
3668 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
3670 CPUArchId
*core_slot
;
3671 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3673 /* make sure possible_cpu are intialized */
3674 mc
->possible_cpu_arch_ids(machine
);
3675 /* get CPU core slot containing thread that matches cpu_index */
3676 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
3678 return core_slot
->props
;
3681 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
3683 return idx
/ smp_cores
% nb_numa_nodes
;
3686 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
3689 const char *core_type
;
3690 int spapr_max_cores
= max_cpus
/ smp_threads
;
3691 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3693 if (!mc
->has_hotpluggable_cpus
) {
3694 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
3696 if (machine
->possible_cpus
) {
3697 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
3698 return machine
->possible_cpus
;
3701 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3703 error_report("Unable to find sPAPR CPU Core definition");
3707 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
3708 sizeof(CPUArchId
) * spapr_max_cores
);
3709 machine
->possible_cpus
->len
= spapr_max_cores
;
3710 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
3711 int core_id
= i
* smp_threads
;
3713 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
3714 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
3715 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
3716 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
3717 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
3719 return machine
->possible_cpus
;
3722 static void spapr_phb_placement(sPAPRMachineState
*spapr
, uint32_t index
,
3723 uint64_t *buid
, hwaddr
*pio
,
3724 hwaddr
*mmio32
, hwaddr
*mmio64
,
3725 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
3728 * New-style PHB window placement.
3730 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3731 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3734 * Some guest kernels can't work with MMIO windows above 1<<46
3735 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3737 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3738 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3739 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3740 * 1TiB 64-bit MMIO windows for each PHB.
3742 const uint64_t base_buid
= 0x800000020000000ULL
;
3743 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3744 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3747 /* Sanity check natural alignments */
3748 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3749 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3750 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
3751 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
3752 /* Sanity check bounds */
3753 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
3754 SPAPR_PCI_MEM32_WIN_SIZE
);
3755 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
3756 SPAPR_PCI_MEM64_WIN_SIZE
);
3758 if (index
>= SPAPR_MAX_PHBS
) {
3759 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
3760 SPAPR_MAX_PHBS
- 1);
3764 *buid
= base_buid
+ index
;
3765 for (i
= 0; i
< n_dma
; ++i
) {
3766 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
3769 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
3770 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
3771 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
3774 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
3776 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3778 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
3781 static void spapr_ics_resend(XICSFabric
*dev
)
3783 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3785 ics_resend(spapr
->ics
);
3788 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
3790 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
3792 return cpu
? ICP(cpu
->intc
) : NULL
;
3795 #define ICS_IRQ_FREE(ics, srcno) \
3796 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
3798 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
3802 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
3803 if (num
> (ics
->nr_irqs
- first
)) {
3806 for (i
= first
; i
< first
+ num
; ++i
) {
3807 if (!ICS_IRQ_FREE(ics
, i
)) {
3811 if (i
== (first
+ num
)) {
3820 * Allocate the IRQ number and set the IRQ type, LSI or MSI
3822 static void spapr_irq_set_lsi(sPAPRMachineState
*spapr
, int irq
, bool lsi
)
3824 ics_set_irq_type(spapr
->ics
, irq
- spapr
->ics
->offset
, lsi
);
3827 int spapr_irq_alloc(sPAPRMachineState
*spapr
, int irq_hint
, bool lsi
,
3830 ICSState
*ics
= spapr
->ics
;
3836 if (!ICS_IRQ_FREE(ics
, irq_hint
- ics
->offset
)) {
3837 error_setg(errp
, "can't allocate IRQ %d: already in use", irq_hint
);
3842 irq
= ics_find_free_block(ics
, 1, 1);
3844 error_setg(errp
, "can't allocate IRQ: no IRQ left");
3850 spapr_irq_set_lsi(spapr
, irq
, lsi
);
3851 trace_spapr_irq_alloc(irq
);
3857 * Allocate block of consecutive IRQs, and return the number of the first IRQ in
3858 * the block. If align==true, aligns the first IRQ number to num.
3860 int spapr_irq_alloc_block(sPAPRMachineState
*spapr
, int num
, bool lsi
,
3861 bool align
, Error
**errp
)
3863 ICSState
*ics
= spapr
->ics
;
3869 * MSIMesage::data is used for storing VIRQ so
3870 * it has to be aligned to num to support multiple
3871 * MSI vectors. MSI-X is not affected by this.
3872 * The hint is used for the first IRQ, the rest should
3873 * be allocated continuously.
3876 assert((num
== 1) || (num
== 2) || (num
== 4) ||
3877 (num
== 8) || (num
== 16) || (num
== 32));
3878 first
= ics_find_free_block(ics
, num
, num
);
3880 first
= ics_find_free_block(ics
, num
, 1);
3883 error_setg(errp
, "can't find a free %d-IRQ block", num
);
3887 first
+= ics
->offset
;
3888 for (i
= first
; i
< first
+ num
; ++i
) {
3889 spapr_irq_set_lsi(spapr
, i
, lsi
);
3892 trace_spapr_irq_alloc_block(first
, num
, lsi
, align
);
3897 void spapr_irq_free(sPAPRMachineState
*spapr
, int irq
, int num
)
3899 ICSState
*ics
= spapr
->ics
;
3900 int srcno
= irq
- ics
->offset
;
3903 if (ics_valid_irq(ics
, irq
)) {
3904 trace_spapr_irq_free(0, irq
, num
);
3905 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
3906 if (ICS_IRQ_FREE(ics
, i
)) {
3907 trace_spapr_irq_free_warn(0, i
+ ics
->offset
);
3909 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
3914 qemu_irq
spapr_qirq(sPAPRMachineState
*spapr
, int irq
)
3916 ICSState
*ics
= spapr
->ics
;
3918 if (ics_valid_irq(ics
, irq
)) {
3919 return ics
->qirqs
[irq
- ics
->offset
];
3925 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
3928 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3932 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3934 icp_pic_print_info(ICP(cpu
->intc
), mon
);
3937 ics_pic_print_info(spapr
->ics
, mon
);
3940 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
3942 return cpu
->vcpu_id
;
3945 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
3947 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3950 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
3952 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
3953 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
3954 error_append_hint(errp
, "Adjust the number of cpus to %d "
3955 "or try to raise the number of threads per core\n",
3956 vcpu_id
* smp_threads
/ spapr
->vsmt
);
3960 cpu
->vcpu_id
= vcpu_id
;
3963 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
3968 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3970 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
3978 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
3980 MachineClass
*mc
= MACHINE_CLASS(oc
);
3981 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
3982 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
3983 NMIClass
*nc
= NMI_CLASS(oc
);
3984 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
3985 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
3986 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
3987 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
3989 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
3992 * We set up the default / latest behaviour here. The class_init
3993 * functions for the specific versioned machine types can override
3994 * these details for backwards compatibility
3996 mc
->init
= spapr_machine_init
;
3997 mc
->reset
= spapr_machine_reset
;
3998 mc
->block_default_type
= IF_SCSI
;
3999 mc
->max_cpus
= 1024;
4000 mc
->no_parallel
= 1;
4001 mc
->default_boot_order
= "";
4002 mc
->default_ram_size
= 512 * M_BYTE
;
4003 mc
->kvm_type
= spapr_kvm_type
;
4004 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4005 mc
->pci_allow_0_address
= true;
4006 assert(!mc
->get_hotplug_handler
);
4007 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4008 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4009 hc
->plug
= spapr_machine_device_plug
;
4010 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4011 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4012 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4013 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4014 hc
->unplug
= spapr_machine_device_unplug
;
4016 smc
->dr_lmb_enabled
= true;
4017 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4018 mc
->has_hotpluggable_cpus
= true;
4019 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4020 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4021 nc
->nmi_monitor_handler
= spapr_nmi
;
4022 smc
->phb_placement
= spapr_phb_placement
;
4023 vhc
->hypercall
= emulate_spapr_hypercall
;
4024 vhc
->hpt_mask
= spapr_hpt_mask
;
4025 vhc
->map_hptes
= spapr_map_hptes
;
4026 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4027 vhc
->store_hpte
= spapr_store_hpte
;
4028 vhc
->get_patbe
= spapr_get_patbe
;
4029 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4030 xic
->ics_get
= spapr_ics_get
;
4031 xic
->ics_resend
= spapr_ics_resend
;
4032 xic
->icp_get
= spapr_icp_get
;
4033 ispc
->print_info
= spapr_pic_print_info
;
4034 /* Force NUMA node memory size to be a multiple of
4035 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4036 * in which LMBs are represented and hot-added
4038 mc
->numa_mem_align_shift
= 28;
4040 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4041 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4042 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4043 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4044 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4045 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4046 spapr_caps_add_properties(smc
, &error_abort
);
4049 static const TypeInfo spapr_machine_info
= {
4050 .name
= TYPE_SPAPR_MACHINE
,
4051 .parent
= TYPE_MACHINE
,
4053 .instance_size
= sizeof(sPAPRMachineState
),
4054 .instance_init
= spapr_instance_init
,
4055 .instance_finalize
= spapr_machine_finalizefn
,
4056 .class_size
= sizeof(sPAPRMachineClass
),
4057 .class_init
= spapr_machine_class_init
,
4058 .interfaces
= (InterfaceInfo
[]) {
4059 { TYPE_FW_PATH_PROVIDER
},
4061 { TYPE_HOTPLUG_HANDLER
},
4062 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4063 { TYPE_XICS_FABRIC
},
4064 { TYPE_INTERRUPT_STATS_PROVIDER
},
4069 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4070 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4073 MachineClass *mc = MACHINE_CLASS(oc); \
4074 spapr_machine_##suffix##_class_options(mc); \
4076 mc->alias = "pseries"; \
4077 mc->is_default = 1; \
4080 static void spapr_machine_##suffix##_instance_init(Object *obj) \
4082 MachineState *machine = MACHINE(obj); \
4083 spapr_machine_##suffix##_instance_options(machine); \
4085 static const TypeInfo spapr_machine_##suffix##_info = { \
4086 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4087 .parent = TYPE_SPAPR_MACHINE, \
4088 .class_init = spapr_machine_##suffix##_class_init, \
4089 .instance_init = spapr_machine_##suffix##_instance_init, \
4091 static void spapr_machine_register_##suffix(void) \
4093 type_register(&spapr_machine_##suffix##_info); \
4095 type_init(spapr_machine_register_##suffix)
4100 static void spapr_machine_3_0_instance_options(MachineState
*machine
)
4104 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4106 /* Defaults for the latest behaviour inherited from the base class */
4109 DEFINE_SPAPR_MACHINE(3_0
, "3.0", true);
4114 #define SPAPR_COMPAT_2_12 \
4117 .driver = TYPE_POWERPC_CPU, \
4118 .property = "pre-3.0-migration", \
4122 .driver = TYPE_SPAPR_CPU_CORE, \
4123 .property = "pre-3.0-migration", \
4127 static void spapr_machine_2_12_instance_options(MachineState
*machine
)
4129 spapr_machine_3_0_instance_options(machine
);
4132 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4134 spapr_machine_3_0_class_options(mc
);
4135 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_12
);
4138 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4140 static void spapr_machine_2_12_sxxm_instance_options(MachineState
*machine
)
4142 spapr_machine_2_12_instance_options(machine
);
4145 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4147 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4149 spapr_machine_2_12_class_options(mc
);
4150 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4151 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4152 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4155 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4160 #define SPAPR_COMPAT_2_11 \
4163 static void spapr_machine_2_11_instance_options(MachineState
*machine
)
4165 spapr_machine_2_12_instance_options(machine
);
4168 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4170 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4172 spapr_machine_2_12_class_options(mc
);
4173 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4174 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_11
);
4177 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4182 #define SPAPR_COMPAT_2_10 \
4185 static void spapr_machine_2_10_instance_options(MachineState
*machine
)
4187 spapr_machine_2_11_instance_options(machine
);
4190 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4192 spapr_machine_2_11_class_options(mc
);
4193 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_10
);
4196 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4201 #define SPAPR_COMPAT_2_9 \
4204 .driver = TYPE_POWERPC_CPU, \
4205 .property = "pre-2.10-migration", \
4209 static void spapr_machine_2_9_instance_options(MachineState *machine)
4211 spapr_machine_2_10_instance_options(machine
);
4214 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4216 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4218 spapr_machine_2_10_class_options(mc
);
4219 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_9
);
4220 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4221 smc
->pre_2_10_has_unused_icps
= true;
4222 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4225 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4230 #define SPAPR_COMPAT_2_8 \
4233 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4234 .property = "pcie-extended-configuration-space", \
4238 static void spapr_machine_2_8_instance_options(MachineState
*machine
)
4240 spapr_machine_2_9_instance_options(machine
);
4243 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4245 spapr_machine_2_9_class_options(mc
);
4246 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_8
);
4247 mc
->numa_mem_align_shift
= 23;
4250 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4255 #define SPAPR_COMPAT_2_7 \
4258 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4259 .property = "mem_win_size", \
4260 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4263 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4264 .property = "mem64_win_size", \
4268 .driver = TYPE_POWERPC_CPU, \
4269 .property = "pre-2.8-migration", \
4273 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4274 .property = "pre-2.8-migration", \
4278 static void phb_placement_2_7(sPAPRMachineState
*spapr
, uint32_t index
,
4279 uint64_t *buid
, hwaddr
*pio
,
4280 hwaddr
*mmio32
, hwaddr
*mmio64
,
4281 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
4283 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4284 const uint64_t base_buid
= 0x800000020000000ULL
;
4285 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4286 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4287 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4288 const uint32_t max_index
= 255;
4289 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4291 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4292 hwaddr phb0_base
, phb_base
;
4295 /* Do we have device memory? */
4296 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4297 /* Can't just use maxram_size, because there may be an
4298 * alignment gap between normal and device memory regions
4300 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4301 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4304 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4306 if (index
> max_index
) {
4307 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4312 *buid
= base_buid
+ index
;
4313 for (i
= 0; i
< n_dma
; ++i
) {
4314 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4317 phb_base
= phb0_base
+ index
* phb_spacing
;
4318 *pio
= phb_base
+ pio_offset
;
4319 *mmio32
= phb_base
+ mmio_offset
;
4321 * We don't set the 64-bit MMIO window, relying on the PHB's
4322 * fallback behaviour of automatically splitting a large "32-bit"
4323 * window into contiguous 32-bit and 64-bit windows
4327 static void spapr_machine_2_7_instance_options(MachineState
*machine
)
4329 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
4331 spapr_machine_2_8_instance_options(machine
);
4332 spapr
->use_hotplug_event_source
= false;
4335 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4337 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4339 spapr_machine_2_8_class_options(mc
);
4340 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4341 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_7
);
4342 smc
->phb_placement
= phb_placement_2_7
;
4345 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4350 #define SPAPR_COMPAT_2_6 \
4353 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4355 .value = stringify(off),\
4358 static void spapr_machine_2_6_instance_options(MachineState
*machine
)
4360 spapr_machine_2_7_instance_options(machine
);
4363 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4365 spapr_machine_2_7_class_options(mc
);
4366 mc
->has_hotpluggable_cpus
= false;
4367 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_6
);
4370 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4375 #define SPAPR_COMPAT_2_5 \
4378 .driver = "spapr-vlan", \
4379 .property = "use-rx-buffer-pools", \
4383 static void spapr_machine_2_5_instance_options(MachineState
*machine
)
4385 spapr_machine_2_6_instance_options(machine
);
4388 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4390 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4392 spapr_machine_2_6_class_options(mc
);
4393 smc
->use_ohci_by_default
= true;
4394 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_5
);
4397 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4402 #define SPAPR_COMPAT_2_4 \
4405 static void spapr_machine_2_4_instance_options(MachineState
*machine
)
4407 spapr_machine_2_5_instance_options(machine
);
4410 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4412 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4414 spapr_machine_2_5_class_options(mc
);
4415 smc
->dr_lmb_enabled
= false;
4416 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_4
);
4419 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4424 #define SPAPR_COMPAT_2_3 \
4427 .driver = "spapr-pci-host-bridge",\
4428 .property = "dynamic-reconfiguration",\
4432 static void spapr_machine_2_3_instance_options(MachineState
*machine
)
4434 spapr_machine_2_4_instance_options(machine
);
4437 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4439 spapr_machine_2_4_class_options(mc
);
4440 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_3
);
4442 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4448 #define SPAPR_COMPAT_2_2 \
4451 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4452 .property = "mem_win_size",\
4453 .value = "0x20000000",\
4456 static void spapr_machine_2_2_instance_options(MachineState
*machine
)
4458 spapr_machine_2_3_instance_options(machine
);
4459 machine
->suppress_vmdesc
= true;
4462 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4464 spapr_machine_2_3_class_options(mc
);
4465 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_2
);
4467 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4472 #define SPAPR_COMPAT_2_1 \
4475 static void spapr_machine_2_1_instance_options(MachineState
*machine
)
4477 spapr_machine_2_2_instance_options(machine
);
4480 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4482 spapr_machine_2_2_class_options(mc
);
4483 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_1
);
4485 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4487 static void spapr_machine_register_types(void)
4489 type_register_static(&spapr_machine_info
);
4492 type_init(spapr_machine_register_types
)