target/cris/cpu.c

   1 /*
   2  * QEMU CRIS CPU
   3  *
   4  * Copyright (c) 2008 AXIS Communications AB
   5  * Written by Edgar E. Iglesias.
   6  *
   7  * Copyright (c) 2012 SUSE LINUX Products GmbH
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "cpu.h"
  27 #include "qemu-common.h"
  28 #include "mmu.h"
  29 #include "exec/exec-all.h"
  30
  31
  32 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
  33 {
  34     CRISCPU *cpu = CRIS_CPU(cs);
  35
  36     cpu->env.pc = value;
  37 }
  38
  39 static bool cris_cpu_has_work(CPUState *cs)
  40 {
  41     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  42 }
  43
  44 /* CPUClass::reset() */
  45 static void cris_cpu_reset(CPUState *s)
  46 {
  47     CRISCPU *cpu = CRIS_CPU(s);
  48     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
  49     CPUCRISState *env = &cpu->env;
  50     uint32_t vr;
  51
  52     ccc->parent_reset(s);
  53
  54     vr = env->pregs[PR_VR];
  55     memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
  56     env->pregs[PR_VR] = vr;
  57
  58 #if defined(CONFIG_USER_ONLY)
  59     /* start in user mode with interrupts enabled.  */
  60     env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
  61 #else
  62     cris_mmu_init(env);
  63     env->pregs[PR_CCS] = 0;
  64 #endif
  65 }
  66
  67 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
  68 {
  69     ObjectClass *oc;
  70     char *typename;
  71
  72 #if defined(CONFIG_USER_ONLY)
  73     if (strcasecmp(cpu_model, "any") == 0) {
  74         return object_class_by_name("crisv32-" TYPE_CRIS_CPU);
  75     }
  76 #endif
  77
  78     typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
  79     oc = object_class_by_name(typename);
  80     g_free(typename);
  81     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
  82                        object_class_is_abstract(oc))) {
  83         oc = NULL;
  84     }
  85     return oc;
  86 }
  87
  88 /* Sort alphabetically by VR. */
  89 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
  90 {
  91     CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
  92     CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
  93
  94     /*  */
  95     if (ccc_a->vr > ccc_b->vr) {
  96         return 1;
  97     } else if (ccc_a->vr < ccc_b->vr) {
  98         return -1;
  99     } else {
 100         return 0;
 101     }
 102 }
 103
 104 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
 105 {
 106     ObjectClass *oc = data;
 107     CPUListState *s = user_data;
 108     const char *typename = object_class_get_name(oc);
 109     char *name;
 110
 111     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
 112     (*s->cpu_fprintf)(s->file, "  %s\n", name);
 113     g_free(name);
 114 }
 115
 116 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 117 {
 118     CPUListState s = {
 119         .file = f,
 120         .cpu_fprintf = cpu_fprintf,
 121     };
 122     GSList *list;
 123
 124     list = object_class_get_list(TYPE_CRIS_CPU, false);
 125     list = g_slist_sort(list, cris_cpu_list_compare);
 126     (*cpu_fprintf)(f, "Available CPUs:\n");
 127     g_slist_foreach(list, cris_cpu_list_entry, &s);
 128     g_slist_free(list);
 129 }
 130
 131 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
 132 {
 133     CPUState *cs = CPU(dev);
 134     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
 135     Error *local_err = NULL;
 136
 137     cpu_exec_realizefn(cs, &local_err);
 138     if (local_err != NULL) {
 139         error_propagate(errp, local_err);
 140         return;
 141     }
 142
 143     cpu_reset(cs);
 144     qemu_init_vcpu(cs);
 145
 146     ccc->parent_realize(dev, errp);
 147 }
 148
 149 #ifndef CONFIG_USER_ONLY
 150 static void cris_cpu_set_irq(void *opaque, int irq, int level)
 151 {
 152     CRISCPU *cpu = opaque;
 153     CPUState *cs = CPU(cpu);
 154     int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
 155
 156     if (level) {
 157         cpu_interrupt(cs, type);
 158     } else {
 159         cpu_reset_interrupt(cs, type);
 160     }
 161 }
 162 #endif
 163
 164 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
 165 {
 166     CRISCPU *cc = CRIS_CPU(cpu);
 167     CPUCRISState *env = &cc->env;
 168
 169     if (env->pregs[PR_VR] != 32) {
 170         info->mach = bfd_mach_cris_v0_v10;
 171         info->print_insn = print_insn_crisv10;
 172     } else {
 173         info->mach = bfd_mach_cris_v32;
 174         info->print_insn = print_insn_crisv32;
 175     }
 176 }
 177
 178 static void cris_cpu_initfn(Object *obj)
 179 {
 180     CPUState *cs = CPU(obj);
 181     CRISCPU *cpu = CRIS_CPU(obj);
 182     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
 183     CPUCRISState *env = &cpu->env;
 184     static bool tcg_initialized;
 185
 186     cs->env_ptr = env;
 187
 188     env->pregs[PR_VR] = ccc->vr;
 189
 190 #ifndef CONFIG_USER_ONLY
 191     /* IRQ and NMI lines.  */
 192     qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
 193 #endif
 194
 195     if (tcg_enabled() && !tcg_initialized) {
 196         tcg_initialized = true;
 197         if (env->pregs[PR_VR] < 32) {
 198             cris_initialize_crisv10_tcg();
 199         } else {
 200             cris_initialize_tcg();
 201         }
 202     }
 203 }
 204
 205 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
 206 {
 207     CPUClass *cc = CPU_CLASS(oc);
 208     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 209
 210     ccc->vr = 8;
 211     cc->do_interrupt = crisv10_cpu_do_interrupt;
 212     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 213 }
 214
 215 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
 216 {
 217     CPUClass *cc = CPU_CLASS(oc);
 218     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 219
 220     ccc->vr = 9;
 221     cc->do_interrupt = crisv10_cpu_do_interrupt;
 222     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 223 }
 224
 225 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
 226 {
 227     CPUClass *cc = CPU_CLASS(oc);
 228     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 229
 230     ccc->vr = 10;
 231     cc->do_interrupt = crisv10_cpu_do_interrupt;
 232     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 233 }
 234
 235 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
 236 {
 237     CPUClass *cc = CPU_CLASS(oc);
 238     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 239
 240     ccc->vr = 11;
 241     cc->do_interrupt = crisv10_cpu_do_interrupt;
 242     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 243 }
 244
 245 static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
 246 {
 247     CPUClass *cc = CPU_CLASS(oc);
 248     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 249
 250     ccc->vr = 17;
 251     cc->do_interrupt = crisv10_cpu_do_interrupt;
 252     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 253 }
 254
 255 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
 256 {
 257     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 258
 259     ccc->vr = 32;
 260 }
 261
 262 #define TYPE(model) model "-" TYPE_CRIS_CPU
 263
 264 static const TypeInfo cris_cpu_model_type_infos[] = {
 265     {
 266         .name = TYPE("crisv8"),
 267         .parent = TYPE_CRIS_CPU,
 268         .class_init = crisv8_cpu_class_init,
 269     }, {
 270         .name = TYPE("crisv9"),
 271         .parent = TYPE_CRIS_CPU,
 272         .class_init = crisv9_cpu_class_init,
 273     }, {
 274         .name = TYPE("crisv10"),
 275         .parent = TYPE_CRIS_CPU,
 276         .class_init = crisv10_cpu_class_init,
 277     }, {
 278         .name = TYPE("crisv11"),
 279         .parent = TYPE_CRIS_CPU,
 280         .class_init = crisv11_cpu_class_init,
 281     }, {
 282         .name = TYPE("crisv17"),
 283         .parent = TYPE_CRIS_CPU,
 284         .class_init = crisv17_cpu_class_init,
 285     }, {
 286         .name = TYPE("crisv32"),
 287         .parent = TYPE_CRIS_CPU,
 288         .class_init = crisv32_cpu_class_init,
 289     }
 290 };
 291
 292 #undef TYPE
 293
 294 static void cris_cpu_class_init(ObjectClass *oc, void *data)
 295 {
 296     DeviceClass *dc = DEVICE_CLASS(oc);
 297     CPUClass *cc = CPU_CLASS(oc);
 298     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 299
 300     ccc->parent_realize = dc->realize;
 301     dc->realize = cris_cpu_realizefn;
 302
 303     ccc->parent_reset = cc->reset;
 304     cc->reset = cris_cpu_reset;
 305
 306     cc->class_by_name = cris_cpu_class_by_name;
 307     cc->has_work = cris_cpu_has_work;
 308     cc->do_interrupt = cris_cpu_do_interrupt;
 309     cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
 310     cc->dump_state = cris_cpu_dump_state;
 311     cc->set_pc = cris_cpu_set_pc;
 312     cc->gdb_read_register = cris_cpu_gdb_read_register;
 313     cc->gdb_write_register = cris_cpu_gdb_write_register;
 314 #ifdef CONFIG_USER_ONLY
 315     cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
 316 #else
 317     cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
 318     dc->vmsd = &vmstate_cris_cpu;
 319 #endif
 320
 321     cc->gdb_num_core_regs = 49;
 322     cc->gdb_stop_before_watchpoint = true;
 323
 324     cc->disas_set_info = cris_disas_set_info;
 325 }
 326
 327 static const TypeInfo cris_cpu_type_info = {
 328     .name = TYPE_CRIS_CPU,
 329     .parent = TYPE_CPU,
 330     .instance_size = sizeof(CRISCPU),
 331     .instance_init = cris_cpu_initfn,
 332     .abstract = true,
 333     .class_size = sizeof(CRISCPUClass),
 334     .class_init = cris_cpu_class_init,
 335 };
 336
 337 static void cris_cpu_register_types(void)
 338 {
 339     int i;
 340
 341     type_register_static(&cris_cpu_type_info);
 342     for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
 343         type_register_static(&cris_cpu_model_type_infos[i]);
 344     }
 345 }
 346
 347 type_init(cris_cpu_register_types)